Manufacturing method for glass core wiring board with built-in high frequency filter

Abstract

To provide: a glass core wiring board with a built-in high-frequency filter in which a glass substrate with excellent high-frequency characteristics is used as a core material, and which promotes the efficient placement of a conductor within the glass substrate; a module including the glass core wiring board with a built-in high-frequency filter; and a method for manufacturing a glass core wiring board with a built-in high-frequency filter.SOLUTION: A structure is such that, in forming an electrically conductive layer inside a glass through hole 4 of a glass core substrate 1, there are formed a hollow tubular conductor layer formed on a side wall, and a lid-shaped conductor layer made to cover one of two openings, the hollow tubular conductor layer and the lid-shaped conductor layer being connected. As one means for achieving this structure, a carrier 15 is affixed to one surface of the glass core substrate 1 so as to shield one side of the opening of the glass through hole 4, and after the lamination of a conductor, the carrier 15 is peeled and removed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to high frequency The present invention relates to a method for manufacturing a glass core wiring board with a built-in wave filter. [Background technology]

[0002] As mobile communication devices become more sophisticated, the electronic components they contain are becoming smaller and denser. There is also a demand for circuit boards on which these components are mounted to be able to accommodate a greater number of components.

[0003] In recent years, mobile devices have increasingly adopted Carrier Aggregation (CA) technology, which uses multiple frequency bands simultaneously from the MHz to GHz range to enable high-speed, large-volume data communications. CA technology optimizes circuits by filtering signals within the same module to prevent mutual interference between simultaneously used frequency band signals. Circuit optimization requires an appropriate filter that accurately acquires the frequency band to be used and has the ability to block frequencies in adjacent bands.

[0004] The transmission and reception methods for mobile devices can be broadly divided into frequency division duplex (hereafter abbreviated as FDD) and time division duplex (hereafter abbreviated as TDD), and these methods are sometimes used together in modern front-end modules. Since the FDD method transmits and receives using a set of adjacent frequency bands, surface-mount filters with steep attenuation characteristics that select a narrow band of 20 to 100 MHz, such as BAW filters and SAW filters, are used. On the other hand, the TDD method transmits and receives by time-dividing a single frequency band, and uses a wider band than the FDD method.

[0005] Advances in synchronization technology in 5th generation mobile communications have created a need for TDD filters with a wider passband, such as 500 to 900 MHz. It is considered difficult for BAW and SAW filters to cover the relatively wide 400 to 900 MHz band required for TDD at sub-6 GHz (3.7 / 4.5 GHz) and above. Surface-mount LTCC LC filters are components with the characteristics to filter a wide band, but due to their structure, they tend to be thick and difficult to fit into the housing of a mobile device. For these reasons, there is a demand for LC filters that are smaller and thinner and have characteristics equal to or better than existing LC filters, or for substrates that incorporate such filters.

[0006] In the front-end module mentioned above, many passive components including filters and active components are mounted on the front-end module board. The number of mounted components is expected to increase in the future as high-speed, large-capacity communications will be carried out using a variety of frequency bands.

[0007] In view of this, a proposal has been made to adopt an LC filter consisting of an inductor and a capacitor as a frequency filter and incorporate it into a multilayer wiring board, thereby reducing the number of components occupying the board surface and contributing to a smaller size and lower height. LC filters have a wider transmission area than acoustic wave filters such as BAW filters and SAW filters, and are compatible with the TDD method. In addition, both the inductors and capacitors that are components of the filter have a relatively simple structure, and it is relatively easy to process them in the same way as other wiring and incorporate them inside the board. Furthermore, if an LC filter is incorporated into a multilayer wiring board, it is possible to reduce the height more than with LTCC.

[0008] When incorporating an LC filter into a multilayer wiring board, one example of a structure for the capacitor, which is a component of the filter, is called MIM (Metal / Insulator / Metal), in which a metal layer, a dielectric layer, and a metal layer are layered in parallel with the multilayer structure of the wiring board. Due to the size of the electric capacity required for the LC filter, the dielectric layer of the MIM is at a level of one hundredth of the thickness of the insulator layer of the multilayer wiring board, so it is rare that the laminated structure of the build-up layer can be used as is to construct the MIM, and it is common to laminate the lower electrode as part of the metal layer of the build-up layer, and then create the dielectric layer and upper electrode layer on top of that separately from the build-up layer.

[0009] On the other hand, the inductor, one of the components of an LC filter, can take a variety of forms. For example, it can be processed in the conductor layer of a multilayer wiring board in the same way as other wiring and formed into a spiral shape, or it can be formed as a coil wound in a spiral shape around the insulator layer by providing wiring to each of the two conductor layers sandwiching an insulator layer, forming a through electrode in the insulator layer, and connecting the wiring on both conductor layers to the through electrode. Also, in order to obtain the desired inductance, even one turn may be too many, and in that case, the magnetic field generated around the wiring when current is passed through it is used to address the problem.

[0010] As mentioned above, the frequency bands used in recent mobile devices are becoming higher, and problems specific to high frequencies, such as the skin effect in current, are becoming more apparent. Small irregularities in the cross-sectional shape of wiring can also have a negative effect on the electrical properties of the entire board, and the standards required for materials are becoming stricter in terms of insulation, dielectric constant, dielectric loss tangent, etc.

[0011] In this situation, glass is selected as the material for the core layer of the wiring board disclosed in Patent Document 1. Glass has excellent flatness and smoothness, and is suitable for forming fine wiring similar to silicon substrates, and is superior in insulation to silicon substrates. In addition, glass is not extremely expensive in terms of cost, and can be said to be one of the best core base materials for high-frequency multilayer wiring boards. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] International Publication No. 2019-225698 Summary of the Invention [Problem to be solved by the invention]

[0013] When using glass as a core substrate, the issue of how to achieve electrical continuity between the front and back is an issue. Normally, through-holes are drilled in the glass and a conductive layer is laminated inside the holes to form through-electrodes. However, a general characteristic of glass is that it has relatively poor adhesion to conductors such as metals.

[0014] Therefore, a commonly used method is to use a material that has excellent adhesion to glass for the layer that is in direct contact with the glass, and then form a film of this material by a means that exhibits high adhesion, and then laminate other layers on top of that. One example is forming a film of titanium on the glass by sputtering. Then, as an example of a subsequent process, copper is further sputtered on top of the titanium layer to ensure high conductivity, and then a copper film of the desired thickness is formed by electrolytic plating, which has a high film formation rate.

[0015] In this case, sputtering and electrolytic plating are usually used to form a film on one or both sides of the glass substrate at the same time as on the inner wall of the through hole, and in that case, the thickness of the conductor on the inner wall of the through hole and on the glass surface will be approximately the same. Considering that the inner diameter of the glass through hole is currently 50 μm or more and the glass plate is relatively thick, forming a film to fill the entire inside with a conductor would take too much time and would be excessive, and there is also a risk of defects such as voids occurring in the through hole.

[0016] Therefore, all conductor layers inside the through holes are usually laminated in a conformal shape (along the inner surface) to the hole, and the thickness is selected taking into consideration the thickness required for the conductor layer on the glass surface. The part of the through hole where no conductor is laminated becomes a cavity when the conductor layer is formed, but this cavity is filled with an insulating layer by laminating the insulating layers on the front and back surfaces of the glass later.

[0017] In this way, when a conductor layer is conformally laminated inside the through hole of the glass substrate, a problem occurs. When the glass substrate is viewed in plan, the entrance and exit of the through hole only has a conductor on the edge of the hole. Therefore, when a through electrode provided in an insulating layer to form a so-called stacked via is placed on the glass through hole, it is not possible to establish electrical continuity with the layer built up on the glass substrate.

[0018] In the field of communications, which is the main application field of high frequency filters, miniaturization of communication terminals is always an important issue. Stacked vias are a means of arranging through electrodes for electrical continuity between the layers of a multi-layer board with high spatial efficiency. If this cannot be realized, the superiority of glass as a material for high frequency filters may be weakened.

[0019] The present invention has been made in view of the above problems, and aims to promote efficient arrangement of conductors within a glass substrate, which has excellent high-frequency characteristics, as a core material. high frequency The object of the present invention is to provide a method for manufacturing a glass core wiring board with a built-in wave filter. [Means for solving the problem]

[0021] In order to solve the above problems, the manufacturing method of the high frequency filter built-in glass core wiring board of the present invention comprises the steps of: From the first principal surface to the second principal surface of the glass core substrate The cross-sectional area of ​​the first main surface side is larger than the cross-sectional area of ​​the second main surface side. forming a plurality of glass through holes; applying a carrier material to the second main surface; forming a conductor layer on the first and second main surfaces of the glass core substrate; Along the inner wall of the glass through hole, The layer thickness on the first main surface side is greater than the layer thickness on the second main surface side. forming a hollow cylindrical conductor layer and forming a cover-shaped conductor layer on the carrier material to close an end of the glass through hole on the second main surface side; a step of sequentially connecting the hollow cylindrical conductor layer and the cover-shaped conductor layer of the glass through hole to form an inductor; forming a capacitor using a conductor layer formed on the first principal surface or the second principal surface; filling the inside of the hollow cylindrical conductor layer with an insulating resin; It has the following. Effect of the Invention

[0022] According to the present invention, a glass substrate having excellent high frequency characteristics is used as a core material, and an efficient arrangement of conductors within the glass substrate is promoted. high frequency It is possible to provide a method for manufacturing a glass core wiring board with a built-in wave filter. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a cross-sectional view of a high-frequency filter-embedded glass core wiring board according to this embodiment. [Diagram 2] FIG. 2 is a reference diagram for explaining the structure of the conductive layer in the glass through hole according to this embodiment. [Diagram 3] FIG. 3 is a cross-sectional view of a capacitor included in this embodiment. [Figure 4] FIG. 4 is a perspective view of an inductor included in this embodiment. [Diagram 5] FIG. 5 is a diagram showing a circuit diagram of a bandpass filter included in this embodiment. [Figure 6] FIG. 6 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 7] FIG. 7 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 8] FIG. 8 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 9] FIG. 9 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 10] FIG. 10 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 11] FIG. 11 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 12] FIG. 12 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 13] FIG. 13 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 14] FIG. 14 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 15] FIG. 15 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 16] FIG. 16 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 17] FIG. 17 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 18] FIG. 18 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 19] FIG. 19 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 20] FIG. 20 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 21] FIG. 21 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 22]FIG. 22 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Diagram 23] FIG. 23 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Figure 24] FIG. 24 is a diagram showing a manufacturing process of the wiring board according to this embodiment. [Diagram 25] FIG. 25 is a diagram showing a manufacturing process of the wiring board according to this embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description is merely an example of the present invention, and the present invention is not limited thereto. In addition, in this specification, "upper" refers to a direction away from the glass core, and "lower" refers to a direction toward the glass core.

[0025] <Embodiment> Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the embodiment. In addition, in the description of the drawings, the same parts are denoted by the same reference numerals.

[0026] The high-frequency filter built-in glass core wiring board (hereinafter referred to as wiring board) according to this embodiment is formed using a glass core substrate with a through hole, and has a MIM capacitor structure on the lamination surface. Here, the capacitor structure functions as an electronic component forming an LC resonant circuit or a capacitive passive component used in wireless communication in mobile devices and the like.

[0027] As shown in FIG. 1, the wiring board has a glass core substrate 1 made of glass. One surface of the cross section of the glass core substrate 1 is a first main surface 2, and the other surface is a second main surface 3. A through hole (glass through hole) 4 is formed in the glass core substrate 1 so as to penetrate the first main surface 2 and the second main surface 3 substantially perpendicularly. A conductive layer and an insulating resin layer (insulator layer) are alternately laminated on each of the first main surface 2 and the second main surface 3. The through hole 4 is formed in the glass core substrate 1 as a portion for electrically conducting between adjacent conductor layers, and further an inductor 8 and a capacitor 9 on the glass are provided. A high-frequency module is obtained by mounting electronic components, semiconductor elements, and the like on the wiring substrate shown in FIG. 1. The high-frequency module is formed by providing an electrode portion so as to be exposed from the outermost layer of the wiring substrate, connecting other high-frequency components to the electrode portion, and mounting the components on the wiring substrate.

[0028] A description will now be given of the structure and manufacturing method of the through electrodes of the through holes 4 provided in the glass core substrate 1. Note that the manufacturing method is merely an example and is not intended to be limiting.

[0029] As shown in FIG. 2(a), through holes 4 are formed in the glass core substrate 1, and as shown in FIG. 2(b), a carrier 15 is attached to the second main surface 3 side via an adhesive layer 16.

[0030] 2(c), seed layers 17, 19 are formed from above the first main surface 2 onto the first main surface 2 and within the through holes 4. Since the inner ends of the through holes 4 formed in the glass core substrate 1 are closed by the carrier 15, the seed layers 17, 19 are formed on the carrier 15 (and the adhesive layer 16).

[0031] 2(c), the seed layers 17 and 19 are shown as two layers, but in practice, the materials are often selected so that the bottom layer provides adhesion and the layer above it provides conductivity. In this embodiment, the titanium layers 27 and 30, and the copper layers 28 and 31 are deposited by sputtering in this order from the side closest to the glass core substrate 1, but this is not essential and can be freely selected according to the purpose.

[0032] Next, as shown in FIG. 2(d), main conductive layers 18 and 20 are formed, and finally, as shown in FIG. 2(e), the carrier 15 is peeled off and removed.

[0033] At the time when the carrier 15 is peeled off and removed, the seed layer 19 and the main conductive layer 20 maintain a rigidity sufficient to maintain their shape, and are separated from the carrier 15 in a manner that blocks the inner end of the through hole 4, remaining on the through hole 4 side. For this reason, on the bottom surface on the second main surface 3 side of the through hole 4, the layers are formed in the same order as those formed on the first main surface 2 of the glass core substrate 1, and are connected to the layers formed on the side wall of the through hole 4. Here, the seed layer 19 and the main conductive layer 20 formed on the inner wall of the through hole 4 are referred to as a hollow cylindrical conductor layer, and the seed layer 19 and the main conductive layer 20 formed on the carrier 15 are referred to as a lid-like conductor layer. The hollow cylindrical conductor layer and the lid-like conductor layer constitute a through electrode.

[0034] The inside of the through hole 4 is hollow, and this cavity is filled with an insulating resin layer in a later process, so that the thin-film main conductive layer 20 inside the through hole 4 is reinforced, and it is possible to overlap a conductor on this main conductive layer 20 to provide a stack via.

[0035] The inductor 8 has a shape, for example, as shown in Fig. 4. In Fig. 4, a parallel plate-like glass core substrate 1 having through electrodes arranged in two rows is shown in a transparent state. Wirings 22, 23 are formed to connect the openings of a plurality of through holes 4 penetrating the first and second main surfaces of the glass core substrate, and a main conductive layer is formed on the inner walls of the through holes 4 communicating between the front and back surfaces of the glass plate to form through conductive vias 5 (hereinafter referred to as TGVs).

[0036] Here, the n-th TGV in the first row is called TGV (1, n), and the n-th TGV in the second row is called TGV (2, n). When TGV (1, n) and TGV (2, n) are connected by wiring 23 on the back side, and TGV (1, n) and TGV (2, n+1) are connected by wiring 22 on the front side, an open circuit can be formed in which the conductor goes around (one turn) inside and on the front side of the glass plate with the wiring 23, TGV (1, n), wiring 22, and TGV (1, n+1). By passing a current through this circuit, it can function as an inductor. The characteristics of the inductor can be adjusted, for example, by changing the number of turns.

[0037] The capacitor 9 has an MIM structure in which a dielectric is sandwiched between two conductive plates. As an example of a capacitor, as shown in FIG. 3, a lower electrode 24 is laminated directly on a glass substrate to form a conductive pattern, a dielectric layer 25 is laminated on the conductive pattern, and a conductor 26 serving as an upper electrode is further laminated on the dielectric layer 25. The lower electrode 24 and the upper electrode 26 generally have a multi-layer structure consisting of a seed layer and a main conductive layer. The capacitance of the capacitor 9 is determined by the area of ​​the upper electrode 26 overlapping the lower electrode 24 and the distance between the lower electrode 24 and the upper electrode 26. The capacitor 9 can be provided on either the first main surface 2 or the second main surface 3 of the glass core substrate 1.

[0038] Next, the high frequency LC filter built into the wiring board of this embodiment will be described in detail. An LC filter utilizes the resonance phenomenon between an inductor and a capacitor to pass electrical signals of a specific frequency through a circuit and block other frequencies. However, in reality, the frequency to be passed is not a single point, but has a specified range, and the boundary between passing and blocking is not switched on and off, but the transmittance changes with a finite gradient, and the gradient is usually restricted from the viewpoint of performance.

[0039] For this reason, the inductors and capacitors that make up an LC filter are not a single pair, but are multiplexed, and are designed as a whole to meet precise requirements for transmission and blocking. For example, the circuit diagram of an LC filter intended to pass a frequency band of 3.3GHz to 3.7GHz is shown in Figure 5. In the figure, C1 to C3 are capacitors, and L1 to L3 are inductors. The capacitance and inductance values ​​of each are shown in Tables 1 and 2.

[0040] [Table 1] [Table 2]

[0041] Among the inductances in Table 2, there are some with the number of turns left blank. This indicates that due to the extremely low inductance, even one turn is excessive for wiring on a scale that can be realized using normal processes, and the desired inductance must be realized using the self-inductance of a single wire.

[0042] In this circuit diagram, multiple capacitors and inductors are required, but in the explanatory diagram of this embodiment, in order to avoid complexity, a substrate containing one inductor and one capacitor is used for simplification. Also, for the capacitor, a very small capacitance such as C2 in Table 1 is required, so a thin film capacitor that realizes this is used in the diagram.

[0043] (Manufacturing method) Next, a manufacturing process for the wiring board of this embodiment will be described with reference to the cross-sectional views of FIG. 6 to FIG.

[0044] First, in FIG. 6(a), a through hole 4 is formed in a glass core substrate 1. The type of glass core substrate 1 may be freely selected from alkali-free glass, alkali glass, quartz glass, etc. according to the purpose, but in this embodiment, alkali-free glass with a thickness of 200 μm is used. The processing method of the through hole 4 may be appropriately selected from laser processing, etching processing, electric discharge processing, and combinations thereof, but in this embodiment, laser processing is used. In the figure, the diameter of the through hole 4 is different between the front and back of the core glass. Although this is not essential, here, the larger diameter is referred to as the first main surface 2 of the glass core substrate, and the smaller diameter is referred to as the second main surface 3 of the glass core substrate.

[0045] 6(b), a 500 μm thick carrier glass (glass plate) 15 is attached to the second main surface 3 side of the glass core substrate 1. A weakly adhesive adhesive layer 16 is formed on one side of the carrier glass 15 with a thickness of 10 μm over the entire surface, and attachment can be performed via the adhesive layer 16.

[0046] Next, as shown in Fig. 7(a), titanium layers 27, 30 and copper layers 28, 31 are laminated in this order by sputtering on the surface including the first main surface 2 of the glass core substrate 1 and the inner wall of the through hole 4 from above the first main surface 2 of the glass core substrate 1. The thickness of the titanium layer can be set to 50 nm, and the thickness of the copper layer can be set to 300 nm. By forming the film under processing conditions considered in advance, the side wall of the through hole 4 is consistently covered from the first main surface 2 side to the second main surface 3 side, and the opening of the through hole 4 on the second main surface 3 side is formed approximately uniformly so as to extend onto the glass carrier 15 that shields the through hole 4.

[0047] 7(b), a photoresist layer 44 is provided on the first main surface 2 side of the glass core substrate 1, and the photoresist is patterned so as to expose areas that will later become wiring patterns. The thickness of the photoresist layer is 20 μm.

[0048] Next, as shown in Fig. 8(a), a copper layer 29 is laminated by electrolytic plating on the portion of the pattern of the photoresist layer 44 on the first main surface 2 of the glass core where the photoresist has been removed to expose the base. The conditions can be set in advance with a target thickness of 12 µm for the copper layer 29. Experiments have confirmed that when electrolytic plating is performed under the same conditions, a conformal electrolytic plating layer 32 is formed in the through hole 4 so as to overlap the layer formed by the sputtering.

[0049] Thereafter, as shown in FIG. 8(b), the photoresist layer 44 is removed using a predetermined stripping solution under predetermined stripping conditions.

[0050] Next, as shown in Fig. 9(a), a dielectric layer is formed to be sandwiched between both electrodes of the capacitor built into the multilayer substrate. The procedure is to first form a dielectric layer 25 over the entire top surface of the first main surface 2 side of the glass core substrate 1, with unnecessary portions being removed later. Silicon nitride is selected as the dielectric material, and it is laminated by sputtering, with the thickness set to 200 nm.

[0051] 9(b), a titanium layer 36 is formed on the entire surface of the dielectric layer 25. The titanium layer 36 serves as an adhesive layer for forming the upper electrode of the capacitor in a later process. The thickness of the titanium layer 36 is set to 50 nm, and sputtering is selected as the deposition method.

[0052] 10(a), a copper layer 37 is laminated on the entire surface of the uppermost titanium layer 36 on the first main surface 2 of the glass core substrate 1. The copper layer 37 serves as a conductive seed for electrolytic copper plating in a later process. The copper layer 37 is laminated to a thickness of 300 nm, and sputtering is selected as the lamination method.

[0053] Next, as shown in FIG. 10(b), a photoresist layer 44 is formed on the uppermost copper layer 37 on the first main surface 2 of the glass core substrate 1, and then photolithography is used to pattern the shape of the portion where the photoresist will later be removed from the portion where the upper electrode of the capacitor will be formed by electrolytic copper plating.

[0054] 11(a), electrolytic copper plating is applied to the first main surface 2 of the glass core substrate 1 to form the upper electrode 26 of the capacitor. Here, the plating thickness of the upper electrode 26 is set to 8 μm.

[0055] After the electrolytic plating, the photoresist layer 44 is peeled off as shown in FIG. 11(b). At this stage, the first main surface 2 of the glass core substrate 1 has extra layers laminated thereon except for the portion where the upper electrode 26 of the capacitor is formed. First, in the portion where the wiring pattern is formed on the first main surface 2 of the glass core substrate 1, the dielectric layer 25, the titanium layer 36, and the copper layer 37 are laminated extra thereon, and in the portion where the wiring pattern is not formed on the first main surface 2 of the glass core substrate 1, the extra layers are laminated on the first main surface 2 of the glass core substrate 1 in the order of the titanium layer 27, the copper layer 28, the dielectric layer 25, the titanium layer 36, and the copper layer 37 from the bottom. Therefore, in the next process, these extra layers are sequentially removed.

[0056] First, as shown in FIG. 12, upper electrode 26 constituting capacitor 9 (FIG. 1), the dielectric layer 25 underneath it, and part of copper layer 29 onto which upper electrode 26 is projected (lower electrode 24 shown in FIG. 3) are covered with a photoresist layer 44 to protect them from being removed together in a later step of removing unnecessary layers.

[0057] Next, as shown in FIG. 13(a), the uppermost copper layer 37 formed by sputtering among the unnecessary layers is removed by soft etching.

[0058] 13(b), the titanium layer 36 and the underlying dielectric layer 25 made of silicon nitride are removed. A dry etching method can be selected as the removal method, but this is not limited to this method and can be freely selected as appropriate.

[0059] 14(a), the photoresist layer 44 covering the capacitor is removed. The reason for this is that the copper layer forming the wiring pattern can protect itself and the layers below it in the subsequent process of removing unnecessary layers.

[0060] Next, as shown in FIG. 14(b), the copper layer 28 formed by sputtering, which is deposited in excess on the first main surface 2 of the glass core substrate 1 in an area where no wiring pattern is formed, is removed by a soft etching method.

[0061] 15(a), the titanium layer 27 formed by sputtering, which is deposited in excess on the portion of the first main surface 2 of the glass core substrate 1 where the wiring pattern is not formed, is removed by etching. This leaves the first main surface 2 of the glass core substrate 1 exposed in the portion of the first main surface 2 of the glass core substrate 1 where the wiring pattern is not formed.

[0062] Next, as shown in FIG. 15(b), an insulating resin sheet is laminated on the first main surface 2 side of the glass core substrate 1 to form an insulating resin layer 39. In this embodiment, an insulating resin (product name "ABF-GX-T31R") manufactured by Ajinomoto Fine-Techno Co., Ltd. is used as the insulating resin sheet, and a vacuum press laminator can be used for lamination, but this is not necessarily limited to this and may be selected appropriately. The thickness of the insulating resin sheet can be 25 μm, but in this regard, a thickness that can completely cover the wiring layer and the capacitor on the first main surface 2 of the glass core substrate 1 is required. In this embodiment, when the thickness from the surface of the first main surface 2 of the glass core substrate 1 to the upper electrode 26 of the capacitor is about 21 μm including each base layer, the thickness of the insulating resin sheet is sufficient at 25 μm.

[0063] In the insulating layer forming process, the through hole 4 is also filled with insulating resin 39. Because a vacuum press laminator is used, no voids are formed, and the insulating resin layer 39 conformally completely fills the inside of the through hole 4 where the seed layer 19 and the main conductive layer 20 are laminated in a cylindrical shape, and is integrated with the insulating resin layer 39 on the first main surface 2 of the glass core substrate 1.

[0064] 16(a), a 500 μm-thick carrier glass (glass plate) 14 is attached onto the insulating resin layer 39 on the first main surface 2 side of the glass core substrate 1. A weakly adhesive adhesive layer 16 having a thickness of 10 μm is formed on the entire surface of one side of the carrier glass 14, and attachment is performed via the adhesive layer 16.

[0065] Next, as shown in Fig. 16(b), the carrier glass 15 on the second main surface 3 side of the glass core substrate 1 is peeled off. The peeling is performed manually. After the present inventors actually performed the peeling, they observed the adhesive surface after peeling under an optical microscope (magnification 100 times), but no conductive layer or glass was observed to be taken up by the adhesive surface.

[0066] Next, a wiring layer is formed on the second main surface 3 side of the glass core substrate 1. As shown in Figures 17(a) and (b), first, a titanium layer 33 having high adhesion to the glass core substrate 1 is formed on the second main surface 3 of the glass core substrate 1, and then a copper layer 34 is formed thereon. The film formation is preferably performed continuously by sputtering without opening the chamber of the film formation device between the two types of film formation. Here, the thickness of the titanium film is set to 50 nm, and the thickness of the copper film is set to 300 nm, but the thickness is not limited to this.

[0067] 18(a), a photoresist layer 44 is provided on the second main surface 3 of the glass core substrate 1, and the photoresist layer is patterned so that the area that will later become the wiring pattern is exposed. Here, the thickness of the photoresist layer is set to 20 μm, but is not limited to this.

[0068] 18(b), electrolytic copper plating 35 is applied to the second main surface 3 of the glass core substrate 1 to form a wiring pattern. The plating thickness is preferably set to 8 μm, but is not limited to this.

[0069] After electrolytic plating, the photoresist layer 44 is peeled off, as shown in Fig. 19(a). At this stage, the second main surface 3 of the glass core substrate 1 is in a state in which the sputtered titanium layer 33 and the sputtered copper layer 34 remain as extra layers except for the portion where the wiring pattern is formed. These layers are then removed in sequence.

[0070] First, as shown in Fig. 19(b), the sputtered copper layer 34 is dissolved and removed by soft etching. In this case, part of the copper forming the wiring pattern is also dissolved, but since the thickness of the wiring pattern is much larger than the thickness of the sputtered copper layer, the wiring pattern is relatively hardly affected by this process.

[0071] 20(a), the titanium layer 33 formed by sputtering is dissolved and removed by etching. At this stage, glass is exposed on the second main surface 3 of the glass core substrate 1 in areas where there is no wiring pattern.

[0072] Next, as shown in FIG. 20(b), an insulating resin sheet is laminated on the second main surface 3 side of the glass core substrate 1 to form an insulating resin layer 41. In this embodiment, an insulating resin (product name "ABF-GX-T31R") manufactured by Ajinomoto Fine-Techno Co., Ltd. is used as the insulating resin sheet, and a vacuum press laminator can be used for lamination, but this is not necessarily limited to this and may be selected appropriately. Here, the thickness of the insulating resin sheet can be 25 μm, but in this regard, a thickness that completely covers the wiring layer on the second main surface 3 of the glass core substrate 1 is required. In this embodiment, when the thickness from the surface of the second main surface 3 of the glass core substrate 1 to the upper surface of the wiring layer is about 10 μm including each base layer, a thickness of 25 μm is suitable in terms of balancing with the first main surface 2.

[0073] 21(a), the carrier glass 14 on the first main surface 2 side of the glass core substrate 1 is peeled off. The peeling is performed manually. The present inventors actually performed the peeling and observed the adhesive surface after peeling under an optical microscope (magnification 100 times), but no insulating layer was observed to be removed by the adhesive surface.

[0074] At this stage, there are wiring layers on both sides of the glass core substrate 1, on which insulating resin layers 39, 41 are laminated. At this stage, the glass core substrate 1 has a reasonable degree of rigidity, so there is no need to worry about damage due to handling, and the subsequent processes can be carried out without attaching a carrier glass.

[0075] First, as shown in Fig. 21(b), through holes (insulating layer through holes) 10 for electrical continuity are processed in turn in the insulating resin layers 39, 41 on the first main surface 2 side and the second main surface 3 side of the glass core substrate 1. During processing, a laser processing machine is used, and it is preferable to set the hole diameter to a tapered shape with an inlet side of φ60μm and a bottom side of φ45μm. However, the processing method, hole diameter, and shape are not limited to these and may be selected appropriately according to the purpose.

[0076] Although not shown, it is preferable to perform a desmear process using a solution mainly composed of an aqueous potassium permanganate solution after the laser processing. The purpose of this is to remove the resin dissolved by the laser processing from the bottom of the hole to completely expose the conductor at the bottom of the hole, and to appropriately roughen the resin surface to improve the adhesion of the wiring seed layer described later.

[0077] If the through holes 4 are not covered on the second main surface 3 side of the glass core substrate 1, an insulating resin layer 39 is provided at the opening of the through holes 4 when the through holes 10 are processed. Therefore, when the through holes 10 in the insulating resin layer are formed so as to be continuous with the through holes 4, even if the inside of the through holes 10 is filled with a conductive material, the presence of the insulating resin layer 39 prevents electrical conduction between the conductive material and the conductor layer on the inner wall of the through holes 4.

[0078] In contrast, in this embodiment, the opening of the through hole 4 is covered with a conductor (a lid-like conductor layer) on the second main surface 3 side of the glass core substrate 1. Therefore, by connecting the through holes 10 with a conductive material formed therein to the through holes 4 (here, the two are arranged so as to overlap when viewed in the thickness direction of the glass core substrate 1), electrical conduction is realized between the through electrodes of the through holes 4 and the conductive material in the through holes 10. Through these, the wiring layer on the first main surface 2 side of the glass core substrate 1 and the wiring layer on the surface of the insulating resin layer 41 opposite to the glass core substrate 1 can be connected, so that the design freedom is expanded while ensuring the miniaturization of the high-frequency module using this wiring substrate. In this embodiment, the through holes 10 are also processed in the insulating resin layer 39 above the through holes 4 where necessary.

[0079] As described above, in the wiring board according to this embodiment, since via stacking with the glass core penetrating electrode is possible only on the second main surface 3, it is effective to design the conductive layer, which has dense wiring and requires efficient use of space, to be placed on the second main surface 3 side.

[0080] Next, as shown in FIG. 22(a), copper layers 12, 42 are laminated as conductive seed layers by electroless plating on the surfaces of the insulating resin layer on the first main surface 2 side and the second main surface 3 side of the glass core substrate 1 and on the inner walls of the through holes 10 machined in the insulating resin layer. The thickness of the layer can be set to 500 nm, but is not limited thereto. In this process, the entire substrate is immersed in a chemical bath for processing, and the first main surface 2 and the second main surface 3 are processed simultaneously. Note that the material and processing method for forming the conductive seed layer are not limited to those described above, and may be appropriately selected according to the purpose.

[0081] Next, as shown in FIG. 22(b), a pattern is formed using a photoresist layer 44 on the resin layer laminated on the first main surface 2 side and the second main surface 3 side of the glass core substrate 1, exposing only the areas to be used as the wiring layer.

[0082] Next, as shown in FIG. 23(a), electrolytic copper plating is applied to the portion exposed from the photoresist pattern by electrolytic plating. As a result, an electrolytic plating layer 43 is laminated on the electroless copper plating layer 42 on the insulating resin layer, and an electrolytic plating layer 13 is laminated on the electroless plating layer 12 in the through hole 4. As for the inside of the through hole 4, by adjusting the conditions of electrolytic copper plating in advance, the electrolytic copper layer can be made to have a filled via shape that fills the through hole 4, rather than a conformal one. The copper thickness is preferably set to 12 μm. Note that the copper thickness and lamination method are not limited to these, and may be appropriately selected according to the purpose. Thereafter, the photoresist layer 44 is peeled off and removed, as shown in FIG. 23(b).

[0083] Next, the portions of the electroless copper plating layer on the insulator layer laminated on the first main surface 2 and the second main surface 3 of the glass core substrate 1, on which the electrolytic copper plating layer for wiring is not formed, are removed by a soft etching method, thereby completing the wiring board shown in Figure 24.

[0084] As shown in FIG. 25, if necessary, an insulating layer 7 and a conductive layer 6 may be laminated on one or both sides of the substrate to further increase the number of layers, thereby forming a compact high-frequency module having a high-frequency filter.

[0085] According to this embodiment, in a glass substrate that is highly suitable for high frequencies, in order to realize miniaturization, which is an important need in communication equipment, which is a major application field of the glass substrate, the conductive layer in the through hole 4 of the glass core substrate 1 has a bottom (lid) structure to enable a stacked via structure.

[0086] It is also preferable that the opening area of ​​the through hole 4 in the first main surface 2 is larger than the opening area in the second main surface 3. For example, the through hole 4 having such a shape can be obtained by forming the through hole from the first main surface 2 side with a laser beam.

[0087] It is also preferred that at least one of the seed layers is formed by sputtering.

[0088] In order to realize the structure of this embodiment, it is suitable to use a method such as sputtering, in which the layer to be placed directly on the inner wall of the through hole 4 in the glass core substrate is deposited in a directional manner and the energy of the chemical species (particles such as atoms and molecules) that are deposited is high. In order to deposit a film of sufficient thickness on the side wall of the through hole using a directional deposition method, it is suitable for the through hole 4 to have a tapered shape with the side wall slightly slanted upwards.

[0089] It is also preferred that at least one of the main conductive layers is formed by electroplating.

[0090] In order to realize the structure of this embodiment, it is important to obtain a defect-free seed layer and then laminate a main conductive layer with little variation in thickness on top of it. In addition, electroplating is preferred because it allows film formation at a relatively high speed.

[0091] Moreover, it is preferable that the seed layer on the first main surface has a thickness of 1 μm or less.

[0092] The role of the seed layer is to laminate a layer that has high adhesion to the glass and to obtain a surface condition suitable for depositing the main conductive layer. Naturally, it is not convenient for the film to be too thin, but if it is too thick, it can easily develop cracks and cause problems in terms of cost. Through experimental considerations, it was found that a seed layer thickness of 1 μm is best.

[0093] Moreover, it is preferable that the thickness of the main conductive layer on the first main surface be 1 μm to 30 μm or less.

[0094] The main conductive layer is responsible for transmitting electrical signals that allow the wiring board to realize its performance, so it should be made without short circuits or breaks, with dimensions that do not deviate from the design values ​​as much as possible, and should be made within an economically favorable range without using unnecessary materials or manufacturing time. Consideration through experiments has revealed that the thickness of the main conductive layer should be 1 μm to 30 μm or less.

[0095] In addition, it is preferable that the glass core substrate 1 has an insulating layer laminated on the second main surface and the wiring layer arranged directly above it, and a conductive layer laminated on top of that, and that at least one of the through electrodes that penetrate the insulating layer to establish electrical continuity between the conductive layers above and below it overlaps with the bottom of the through electrode of the glass core substrate 1 on the second main surface side.

[0096] By capping the through-hole with a bottom made of a conductive layer, it becomes possible to stack vias on top of it, thereby optimizing and streamlining the wiring layout of the board and ultimately achieving a smaller board size.

[0097] To make the through hole of the glass core substrate conductive, a seed layer and a main conductive layer can be laminated on the through hole in such a manner that they conformally cover the side wall and the bottom surface on the second main surface side. [Explanation of symbols]

[0098] 1. Glass core substrate 2...First principal surface 3...Second principal surface 4. Through hole 5. Conductive vias 6. Conductive layer 7. Insulation layer 8. Inductor 9. Capacitor 10: Insulation layer through hole 11....Insulating resin layer penetrating electrode 12: Electroless copper plating layer in the through hole of the insulating resin layer 13...Electrolytically plated copper in the through hole of the insulating resin layer 14: Glass carrier (carrier material) to be attached to the first main surface 15: Glass carrier (carrier material) to be attached to the second main surface 16....Adhesive layer of glass carrier 17 - Seed layer on the first main surface 18...Main conductive layer on first main surface 19. Seed layer of through-hole electrode 20...Main conductive layer of through electrode 21... Via stacked area 22...Wiring on the first main surface 23....Wiring on the second main surface 24: Lower electrode of capacitor 25 - Capacitor dielectric layer 26: Upper electrode of capacitor 27...Titanium layer on first principal surface 28... Sputtered copper layer on first major surface 29....Electrolytic copper plating layer on first main surface 30: Titanium layer in through hole 31...Sputtered copper layer in through hole 32...Electrolytic copper plating layer inside the through hole 33...Titanium layer on second major surface 34... Sputtered copper layer on second major surface 35....Electrolytic copper plating layer on the second main surface 36 - Titanium layer on the capacitor dielectric layer 37...Sputtered copper layer on capacitor dielectric layer 38....Electrolytic copper plating layer on the capacitor dielectric layer 39: Insulating resin layer on the first main surface 40: Insulating resin filled in glass through hole 41: Insulating resin layer on second main surface side 42...Electroless copper plating layer on insulating resin layer 43... Electrolytic copper plating layer on insulating resin layer 44...Photoresist layer

Claims

1. forming a plurality of glass through holes from a first main surface to a second main surface of a glass core substrate such that a cross-sectional area on the first main surface side is larger than a cross-sectional area on the second main surface side; applying a carrier material to the second major surface; forming a conductor layer on the first and second main surfaces of the glass core substrate; forming a hollow cylindrical conductor layer along an inner wall of the glass through hole such that the layer thickness on the first main surface side is greater than the layer thickness on the second main surface side, and forming a cover-shaped conductor layer on the carrier material to close an end of the glass through hole on the second main surface side; a step of sequentially connecting the hollow cylindrical conductor layer and the cover-shaped conductor layer of the glass through hole to form an inductor; forming a capacitor using a conductor layer formed on the first main surface or the second main surface; and filling the inside of the hollow tubular conductor layer with insulating resin.

2. 2. The method for manufacturing a high frequency filter built-in glass core wiring substrate according to claim 1, wherein the capacitor is formed by arranging a conductor layer, a dielectric layer, and a conductor layer in this order on the surface of the first main surface or the second main surface.

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