CALIBRATION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Abstract

To provide a semiconductor device and a calibration circuit.SOLUTION: A calibration circuit 200 includes a reference resistance leg 210, and an emphasis circuit 230. The reference resistance leg 210 is connected via a reference resistance node RRN to an external reference resistance RZQ, and is configured to change a voltage level of the reference resistance node RRN on the basis of calibration codes NCAL1, PCAL1. The emphasis circuit 230 is configured to, when the reference resistance leg 210 changes the voltage level of the reference resistance node RRN on the basis of the calibration codes NCAL1, PCAL1, accelerate a change in the voltage level of the reference resistance node RRN.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to integrated circuit technology, and more particularly to semiconductor devices and calibration circuits. [Background technology]

[0002] An electronic device includes many electronic components, and a computer system may include many electronic components made of semiconductors. A semiconductor device constituting a computer system may include a data transfer device to transfer data. While the operating speed of the semiconductor device is improved and power consumption is reduced, distortion of a transferred signal may occur due to the influence of external noise and impedance mismatch between semiconductor devices communicating with each other. Therefore, the semiconductor device may perform an operation of matching the impedance or resistance of the data transfer device.

[0003] Generally, a semiconductor device includes an on-die termination circuit that performs impedance matching for accurate signal transfer. Also, the semiconductor device must perform a termination resistor correction according to a PVT change so that accurate impedance matching can be achieved. Generally, a memory device can correct the impedance value of the termination resistor by connecting to an external reference resistor and performing a calibration operation using the external reference resistor. This is generally called a ZQ calibration operation. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiment of the present invention provides a calibration circuit that can quickly stabilize the level of a calibration voltage that changes depending on a calibration code.

[0005] Also, embodiments of the present invention provide a semiconductor device in which multiple dies can share an external reference resistor to perform a calibration operation. [Means for solving the problem]

[0006] A calibration circuit according to an embodiment of the present invention may include a reference resistor leg connected to the external reference resistor via a reference resistor node and changing a voltage level of the reference resistor node based on a calibration code; and an emphasis circuit changing a voltage level of the reference resistor node based on the calibration code.

[0007] A calibration circuit according to an embodiment of the present invention may include a reference resistor leg connected to an external reference resistor via a reference resistor node and changing a voltage level of the reference resistor node based on a calibration code; an emphasis control signal generator generating an emphasis control signal based on the calibration code; and an emphasis driver changing the voltage level of the reference resistor node based on the emphasis control signal.

[0008] A semiconductor device according to an embodiment of the present invention includes a plurality of dies commonly connected to an external reference resistor and sequentially performing calibration operations, at least one of the plurality of dies including a calibration circuit connected to the external reference resistor via a reference resistor pad and generating a first calibration code and a second calibration code; and a data output circuit configured to set an impedance based on the first and second calibration codes and output data, the calibration circuit including a reference resistor leg connected to a reference resistor node connected to the reference resistor pad and changing a voltage level of the reference resistor node based on the first calibration code; and an emphasis circuit configured to change a voltage level of the reference resistor node based on the voltage sensing signal and the first calibration code. Effect of the Invention

[0009] The present invention can improve the operational reliability of a semiconductor device by performing an accurate calibration operation even if the capacitance of a node connected to a calibration resistor increases. [Brief description of the drawings]

[0010] [Figure 1] 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a diagram showing a configuration of a calibration circuit according to an embodiment of the present invention. [Diagram 3] 3 is a diagram illustrating the operation of the emphasis control signal generator shown in FIG. 2. [Figure 4] FIG. 4a is a diagram showing changes in the voltage level of the reference resistance node, and FIG. 4b is a diagram showing changes in the voltage level of the reference resistance node. [Diagram 5] 5A and 5B are diagrams illustrating the operation of a calibration circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] FIG. 1 is a diagram showing a configuration of a semiconductor device 100 according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 may include a plurality of dies. The semiconductor device 100 may be a stacked semiconductor device in which a plurality of dies are stacked on one substrate 101 and packaged into a single package. As shown in FIG. 1, the semiconductor device 100 includes four dies, but is not limited thereto, and the number of stacked dies may be less than four or more than four. The first die 110, the second die 120, the third die 130, and the fourth die 140 are stacked on the substrate 101 in a plane, but this is merely a conceptual illustration, and some and / or all of the first to fourth dies 110, 120, 130, and 140 may be stacked vertically. The first to fourth dies 110, 120, 130, and 140 may be designed to have the same structure as each other, or may be designed to have different structures and / or functions in whole or in part. Any one of the first to fourth dies 110, 120, 130, and 140 may function as a master die that can communicate preferentially with an external device (not shown) of the semiconductor device 100, and the rest may function as slave dies that communicate with the external device via the master die. However, the present invention is not limited thereto, and the first to fourth dies 110, 120, 130, and 140 may communicate with an external device independently of each other.

[0012] The semiconductor device 100 may include an external reference resistor RZQ disposed on the substrate 101. The first to fourth dies 110, 120, 130, and 140 may be commonly connected to the external reference resistor RZQ. The first to fourth dies 110, 120, 130, and 140 may each be connected to the external reference resistor RZQ to perform a calibration operation. The first to fourth dies 110, 120, 130, and 140 may be commonly connected to the external reference resistor RZQ to perform a calibration operation sequentially. For example, the first die 110 may perform a calibration operation preferentially. The first die 110 may perform a calibration operation by receiving a command signal instructing to perform a calibration operation from the external device. When the calibration operation of the first die 110 is completed, the second die 120 may perform a calibration operation. When the calibration operation of the second die 120 is completed, the third die 130 can perform a calibration operation, and when the calibration operation of the third die 130 is completed, the fourth die 140 can perform a calibration operation. When the calibration operation of the fourth die 140 is completed, the fourth die 140 can transmit a signal notifying the first die 110 that the calibration operation has been completed. When the calibration operations of all dies are completed, the first die 110 can output a signal notifying the external device that the calibration operation of the semiconductor device 100 has been completed.

[0013] The first to fourth dies 110, 120, 130, 140 may include reference resistor pads 111, 121, 131, 141, calibration circuits 112, 122, 132, 142, and data output circuits 113, 123, 133, 143, respectively. In the first die 110, the calibration circuit 112 is connected to the external reference resistor RZQ through the reference resistor pad 111, and may perform a calibration operation using the external reference resistor RZQ. The calibration circuit 112 may generate a first calibration code NCAL1 and a second calibration code PCAL1 through the calibration operation. The first and second calibration codes NCAL1 and PCAL1 may set an impedance of the data output circuit 113. The data output circuit 113 may output data to the external device based on internal data of the first die 110. The data output circuit 113 may be connected to a data bus and may include a pull-up driver and a pull-down driver for driving the data bus to transfer the data. The pull-up driver may include a plurality of pull-up resistor legs, and the pull-down driver may include a plurality of pull-down resistor legs. The pull-down resistor legs of the data output circuit 113 may have a resistance value set based on the first calibration code NCAL1. The pull-up resistor legs of the data output circuit 113 may have a resistance value set based on the second calibration code PCAL1.

[0014] In the second die 120, the calibration circuit 122 is connected to the external reference resistor RZQ through the reference resistor pad 121, and may perform a calibration operation using the external reference resistor RZQ. The calibration circuit 122 may generate a first calibration code NCAL2 and a second calibration code PCAL2 through the calibration operation. The first and second calibration codes NCAL2 and PCAL2 may set an impedance of the data output circuit 123. The data output circuit 123 may output data to the external device based on internal data of the second die 120. The data output circuit 123 may be connected to a data bus and may include a pull-up driver and a pull-down driver that drive the data bus to transfer the data. The pull-up driver may include a plurality of pull-up resistor legs, and the pull-down driver may include a plurality of pull-down resistor legs. The pull-down resistor legs may have a resistance value set based on the first calibration code NCAL2. The pull-up resistor legs may have a resistance value set based on the second calibration code PCAL2.

[0015] In the third die 130, the calibration circuit 132 is connected to the external reference resistor RZQ through the reference resistor pad 131, and may perform a calibration operation using the external reference resistor RZQ. The calibration circuit 132 may generate a first calibration code NCAL3 and a second calibration code PCAL3 through the calibration operation. The first and second calibration codes NCAL3 and PCAL3 may set an impedance of the data output circuit 133. The data output circuit 133 may output data to the external device based on internal data of the third die 130. The data output circuit 133 may be connected to a data bus and may include a pull-up driver and a pull-down driver that drive the data bus to transfer the data. The pull-up driver may include a plurality of pull-up resistor legs, and the pull-down driver may include a plurality of pull-down resistor legs. The pull-down resistor legs may have a resistance value set based on the first calibration code NCAL3. The pull-up resistor legs may have a resistance value set based on the second calibration code PCAL3.

[0016] In the fourth die 140, the calibration circuit 142 is connected to the external reference resistor RZQ through the reference resistor pad 141, and may perform a calibration operation using the external reference resistor RZQ. The calibration circuit 142 may generate a first calibration code NCAL4 and a second calibration code PCAL4 through the calibration operation. The first and second calibration codes NCAL4 and PCAL4 may set an impedance of the data output circuit 143. The data output circuit 143 may output data to the external device based on internal data of the fourth die 140. The data output circuit 143 may be connected to a data bus and may include a pull-up driver and a pull-down driver that drive the data bus to transfer the data. The pull-up driver may include a plurality of pull-up resistor legs, and the pull-down driver may include a plurality of pull-down resistor legs. The pull-down resistor legs may have a resistance value set based on the first calibration code NCAL4. The pull-up resistor legs may have a resistance value set based on the second calibration code PCAL4.

[0017] The external reference resistor RZQ may have one end connected to a voltage terminal and the other end commonly connected to the reference resistor pads 111, 121, 131, 141 of the first to fourth dies 110, 120, 130, 140. The voltage terminal may be a power supply voltage terminal to which a power supply voltage is supplied. The power supply voltage may have a level higher than a ground voltage and may be an operating power supply voltage of the semiconductor device 100 applied from an external power supply of the semiconductor device 100. When the external reference resistor RZQ is connected to a power supply voltage terminal, the calibration circuits 112, 122, 132, 142 of the first to fourth dies 110, 120, 130, 140 may preferentially generate the first calibration codes NCAL1, NCAL2, NCAL3, NCAL4, and generate the second calibration codes PCAL1, PCAL2, PCAL3, PCAL4 based on the first calibration codes NCAL1, NCAL2, NCAL3, NCAL4. In one embodiment, the voltage terminal may be a ground voltage terminal connected to a ground voltage. When the external reference resistor RZQ is connected to a ground voltage terminal, the calibration circuits 112, 122, 132, and 142 of the first to fourth dies 110, 120, 130, and 140 may preferentially generate the second calibration codes PCAL1, PCAL2, PCAL3, and PCAL4, and generate the first calibration codes NCAL1, NCAL2, NCAL3, and NCAL4 based on the second calibration codes PCAL1, PCAL2, PCAL3, and PCAL4.

[0018] FIG. 2 is a diagram showing a configuration of a calibration circuit 200 according to an embodiment of the present invention. The calibration circuit 200 can be applied to some or all of the calibration circuits 112, 122, 132, and 142 shown in FIG. 1. As shown in FIG. 2, the calibration circuit 200 can be connected to an external reference resistor RZQ through a reference resistor pad 211. The reference resistor pad 211 can be connected to a reference resistor node RRN. The calibration circuit 200 can include a reference resistor leg 210, a first calibration code generation circuit 220, and an emphasis circuit (emphasizer) 230. The reference resistor leg 210 can be connected to the external reference resistor RZQ through the reference resistor node RRN and the reference resistor pad 211. The reference resistor leg 210 can receive a first calibration code NCAL<1:n> and can set a resistance value based on the first calibration code NCAL<1:n>. The resistance value of the reference resistor leg 210 can be changed based on the first calibration code NCAL<1:n>. One end of the external reference resistor RZQ may be connected to a first power supply voltage VDDQ terminal, and the other end may be connected to the reference resistor node RRN via the reference resistor pad 211. One end of the reference resistor leg 210 may be connected to the reference resistor node RRN, and the other end may be connected to a ground voltage (VSS) terminal. The voltage level of the reference resistor node RRN may be determined between the first power supply voltage VDDQ and the ground voltage VSS according to a resistance ratio of the external reference resistor RZQ and the reference resistor leg 210. Therefore, the reference resistor leg 210 may change the voltage level of the reference resistor node RRN based on the first calibration code NCAL<1:n>.

[0019] The first calibration code generation circuit 220 may be connected to the reference resistor node RRN. The first calibration code generation circuit 220 may compare a voltage level of the reference resistor node RRN with a voltage level of a reference voltage VREF. The reference voltage VREF may have a voltage level corresponding to a middle voltage between the first power supply voltage VDDQ and the ground voltage VSS. The first calibration code generation circuit 220 may compare a voltage level of the reference resistor node RRN with a voltage level of the reference voltage VREF to generate a voltage detection signal VD and the first calibration code NCAL<1:n>. The first calibration code generation circuit 220 may generate the voltage detection signal VD and the first calibration code NCAL<1:n> based on a comparison result between the voltage level of the reference resistor node RRN and the voltage level of the reference voltage VREF. For example, the first calibration code generation circuit 220 may transition the level of the voltage sensing signal VD to a logic high level when the voltage level of the reference resistor node RRN is higher than the voltage level of the reference voltage VREF. The first calibration code generation circuit 220 may transition the level of the voltage sensing signal VD to a logic low level when the voltage level of the reference resistor node RRN is lower than the voltage level of the reference voltage VREF. The first calibration code generation circuit 220 may change the code value of the first calibration code NCAL<1:n> to decrease the resistance value of the reference resistor leg 210 when the voltage level of the reference resistor node RRN is higher than the voltage level of the reference voltage VREF. For example, the first calibration code generation circuit 220 may increase the code value of the first calibration code NCAL<1:n>. The first calibration code generation circuit 220 can change the code value of the first calibration code NCAL<1:n> so as to increase the resistance value of the reference resistor leg 210 when the voltage level of the reference resistor node RRN is lower than the voltage level of the reference voltage VREF.For example, the first calibration code generation circuit 220 can decrease the code value of the first calibration code NCAL<1:n>.

[0020] The emphasis circuit 230 may change a voltage level of the reference resistor node RRN based on the first calibration code NCAL<1:n> and the voltage detection signal VD. The emphasis circuit 230 may further change the voltage level of the reference resistor node RRN when the voltage level of the reference resistor node RRN changes due to a change in the resistance value of the reference resistor leg 210. The emphasis circuit 230 may perform an emphasis operation to boost the change in the voltage level of the reference resistor node RRN. The emphasis circuit 230 may also increase the voltage level of the reference resistor node RRN when the reference resistor leg 210 increases the voltage level of the reference resistor node RRN based on the first calibration code NCAL<1:n>. The emphasis circuit 230 can lower the voltage level of the reference resistor node RRN when the reference resistor leg 210 lowers the voltage level of the reference resistor node RRN based on the first calibration code NCAL<1:n>. The emphasis circuit 230 can change the voltage level of the reference resistor node RRN by detecting a change in the code value of the first calibration code NCAL<1:n>. The emphasis circuit 230 can change the voltage level of the reference resistor node RRN based on at least a part of the first calibration code NCAL<1:n>. This will be described in detail later.

[0021] The first calibration code generating circuit 220 may include a first comparator 221 and a first control signal generator 222. The first comparator 221 may be connected to the reference resistor node RRN to receive the reference voltage VREF. The first comparator 221 may compare a voltage level of the reference resistor node RRN with a voltage level of the reference voltage VREF. For example, the first comparator 221 may output a signal having a logic high level when the voltage level of the reference resistor node RRN is higher than the voltage level of the reference voltage VREF. The first comparator 221 may output a signal having a logic low level when the voltage level of the reference resistor node RRN is lower than the voltage level of the reference voltage VREF. The first comparator 221 may further receive a clock signal CLK. The first comparator 221 may perform a voltage comparison operation in synchronization with the clock signal CLK. For example, the first comparator 221 may perform an operation of comparing a voltage level of the reference resistor node RRN with a voltage level of the reference voltage VREF in synchronization with an edge of the clock signal. The first comparator 221 may perform a voltage comparison operation in synchronization with a rising edge of the clock signal CLK. In one embodiment, the first comparator 221 may perform a voltage comparison operation in synchronization with both the rising edge and the falling edge of the clock signal CLK.

[0022] The first control signal generator 222 may receive a signal output from the first comparator 221 and generate the voltage sensing signal VD and the first calibration code NCAL<1:n>. The first control signal generator 222 may transition a logic level of the voltage sensing signal VD based on the output of the first comparator 221 to increase or decrease a code value of the first calibration code NCAL<1:n>. For example, when a signal having a logic high level is output from the first comparator 221, the first control signal generator 222 may transition the voltage sensing signal VD to a logic high level to increase a code value of the first calibration code NCAL<1:n>. When a signal having a logic low level is output from the first comparator 221, the first control signal generator 222 may transition the voltage sensing signal VD to a logic low level to decrease a code value of the first calibration code NCAL<1:n>.

[0023] The emphasis circuit 230 may include an emphasis control signal generator 231 and an emphasis driver 232. The emphasis control signal generator 231 may receive the first calibration code NCAL<1:n> from the first control signal generator 222 of the first calibration code generation circuit 220. The emphasis control signal generator 231 may generate an emphasis control signal PS based on the first calibration code NCAL<1:n>. The emphasis control signal generator 231 may generate a complementary signal PSB together with the emphasis control signal PS. The emphasis control signal generator 231 may generate the emphasis control signal PS based on at least a part of the first calibration code NCAL<1:n>. For example, the emphasis control signal generator 231 may detect a transition of a least significant bit (LSB) in the first calibration code NCAL<1:n> to generate the emphasis control signal PS. The emphasis control signal generator 231 can enable the emphasis control signal PS and the complementary signal PSB every time the logic level of the least significant bit of the first calibration code NCAL<1:n> transitions.

[0024] The emphasis driver 232 may receive the voltage sensing signal VD and the emphasis control signal PS. The emphasis driver 232 may change a voltage level of the reference resistor node RRN based on the voltage sensing signal VD and the emphasis control signal PS. The emphasis driver 232 may increase a voltage level of the reference resistor node RRN based on the voltage sensing signal VD and the emphasis control signal PS when the voltage level of the reference resistor node RRN is lower than the voltage level of the reference voltage VREF. The emphasis driver 232 may decrease a voltage level of the reference resistor node RRN based on the voltage sensing signal VD and the emphasis control signal PS when the voltage level of the reference resistor node RRN is higher than the voltage level of the reference voltage VREF.

[0025] The emphasis driver 232 may include a pull-up emphasis driver 232-1 and a pull-down emphasis driver 232-2. The pull-up emphasis driver 232-1 may receive the voltage detection signal VD and the complementary signal PSB of the emphasis control signal. The pull-up emphasis driver 232-1 may increase a voltage level of the reference resistor node RRN based on the voltage detection signal VD and the complementary signal PSB of the emphasis control signal. The pull-down emphasis driver 232-2 may receive the voltage detection signal VD and the emphasis control signal PS. The pull-down emphasis driver 232-2 may decrease a voltage level of the reference resistor node RRN based on the voltage detection signal VD and the emphasis control signal PS. The pull-up emphasis driver 232-1 may be connected between a second power supply voltage (VDD) terminal and the reference resistor node RRN to pull up the reference resistor node RRN. The pull-down emphasis driver 232-2 is connected between the reference resistor node RRN and the ground voltage (VSS) terminal and can pull down the reference resistor node RRN.

[0026] In one embodiment, the second power supply voltage VDD may have the same voltage level as the first power supply voltage VDDQ. When the first power supply voltage VDDQ and the second power supply voltage VDD have the same voltage level, the terminal supplying the first power supply voltage VDDQ and the terminal supplying the second power supply voltage VDD may be electrically isolated from each other. In one embodiment, the second power supply voltage VDD may have a different voltage level from the first power supply voltage VDDQ, and the second power supply voltage VDD may have a higher voltage level than the first power supply voltage VDDQ. In one embodiment, the ground voltage terminal to which the reference resistor leg 210 is connected may be a first ground voltage (VSSQ) terminal, and the ground voltage terminal to which the pull-down emphasis driver 232-2 is connected may be a second ground voltage (VSS) terminal. The first ground voltage (VSSQ) terminal and the second ground voltage (VSS) terminal may be electrically isolated from each other.

[0027] The pull-up emphasis driver 232-1 may include a first transistor T1 and a second transistor T2. The first and second transistors T1 and T2 may be P-channel MOS transistors. The gate of the first transistor T1 may receive the voltage detection signal VD and the source may be connected to the second power supply voltage (VDD) terminal. The gate of the second transistor T2 may receive the complementary signal PSB of the emphasis control signal, the source may be connected to the drain of the first transistor T1, and the drain may be connected to the reference resistor node RRN. The pull-up emphasis driver 232-1 may pull up the reference resistor node RRN to the second power supply voltage VDD when the voltage detection signal VD has a logic low level and the complementary signal PSB of the emphasis control signal is enabled to a logic low level.

[0028] The pull-down emphasis driver 232-2 may include a third transistor T3 and a fourth transistor T4. The third and fourth transistors T3 and T4 may be N-channel MOS transistors. The gate of the third transistor T3 may receive the voltage detection signal VD and the source may be connected to the ground voltage (VSS) terminal. The gate of the fourth transistor T4 may receive the emphasis control signal PS, the drain may be connected to the reference resistor node RRN, and the source may be connected to the drain of the third transistor T3. The pull-down emphasis driver 232-2 may pull down the reference resistor node RRN to the ground voltage VSS when the voltage detection signal VD has a logic high level and the emphasis control signal PS is enabled to a logic high level.

[0029] 3 is a diagram illustrating an operation of the emphasis control signal generator 231 shown in FIG. 2. As shown in FIG. 3, the emphasis control signal generator 231 can enable the emphasis control signal PS to a logic high level and enable the complementary signal PSB of the emphasis control signal to a logic low level every time the logic level of the least significant bit LSB of the first calibration code NCAL<1:n> transitions. The least significant bit LSB of the first calibration code NCAL<1:n> can change logic level most frequently among the bits of the first calibration code NCAL<1:n> according to the voltage comparison result of the first comparator 221. Therefore, the emphasis control signal generator 231 can detect the least significant bit LSB of the first calibration code NCAL<1:n> and generate the emphasis control signal PS and the complementary signal PSB every time the voltage level of the reference resistor node RRN changes based on the first calibration code NCAL<1:n>. In one embodiment, the emphasis control signal generator 231 may detect a logic level transition of a bit other than the least significant bit (LSB) and generate the emphasis control signal PS and its complementary signal PSB.

[0030] 4a and 4b are diagrams illustrating changes in the voltage level of the reference resistor node RRN. FIG. 4a illustrates that the resistance value of the reference resistor leg 210 increases based on the first calibration code NCAL<1:n>, and the voltage level of the reference resistor node RRN increases. As shown in FIG. 1, when multiple dies are commonly connected to one external reference resistor RZQ, the load and / or capacitance of each of the reference resistor pads of the multiple dies may be increased compared to when one die is connected to the external reference resistor RZQ. Therefore, in the case where the emphasis circuit 230 shown in FIG. 2 is not provided, when the resistance value of the reference resistor leg 210 increases and the voltage level of the reference resistor node RRN increases, the slope of the voltage level increase may decrease as shown by the dotted curve (A). In the case where the emphasis circuit 230 is provided, when the voltage level of the reference resistor node RRN increases, the emphasis circuit 230 can further boost the voltage level of the reference resistor node RRN. Therefore, the slope of the voltage level rise can be increased as shown by the solid line curve (B), and the voltage level of the reference resistor node RRN can be quickly increased and quickly stabilized at the target voltage level.

[0031] 4b is a diagram showing that the resistance value of the reference resistor leg 210 decreases based on the first calibration code NCAL<1:n>, and the voltage level of the reference resistor node RRN decreases. In the case where the emphasis circuit 230 shown in FIG. 2 is not provided, when the resistance value of the reference resistor leg 210 increases and the voltage level of the reference resistor node RRN decreases, the slope of the voltage level decrease may decrease as shown by the dotted curve (C). In the case where the emphasis circuit 230 is provided, when the voltage level of the reference resistor node RRN decreases, the emphasis circuit 230 can further boost the voltage level of the reference resistor node RRN. Therefore, the slope of the voltage level decrease may increase as shown by the solid curve (D), and the voltage level of the reference resistor node RRN may decrease quickly and be stabilized to the target voltage level quickly.

[0032] 2, the calibration circuit 200 may further include a pull-down resistor leg 240, a pull-up resistor leg 250, and a second calibration code generation circuit 260. The pull-down resistor leg 240 may receive the first calibration code NCAL<1:n>. The pull-down resistor leg 240 may have a resistance value set based on the first calibration code NCAL<1:n>. The resistance value of the pull-down resistor leg 240 may be changed based on the first calibration code NCAL<1:n>. The pull-down resistor leg 240 may be connected between a node ND and the ground voltage (VSS) terminal. The pull-down resistor leg 240 may be set to have the same resistance value as the reference resistor leg 210 based on the first calibration code NCAL<1:n>. The pull-up resistor leg 250 may receive the second calibration code PCAL<1:n>. The resistance value of the pull-up resistor leg 250 may be set based on the second calibration code PCAL<1:n>. The resistance value of the pull-up resistor leg 250 may be changed based on the second calibration code PCAL<1:n>. The pull-up resistor leg 250 may be connected between the first power supply voltage (VDDQ) terminal and the node ND.

[0033] The second calibration code generation circuit 260 may detect a voltage level that changes according to a resistance ratio between the pull-up resistor leg 250 and the pull-down resistor leg 240 to generate the second calibration code PCAL<1:n>. The second calibration code generation circuit 260 may be connected to the node ND and may generate the second calibration code PCAL<1:n> by comparing a voltage level of the node ND with a voltage level of the reference voltage VREF. When the voltage level of the node ND is higher than the voltage level of the reference voltage VREF, the second calibration code generation circuit 260 may change the code value of the second calibration code PCAL<1:n> so that the resistance value of the pull-up resistor leg 250 increases. For example, the second calibration code generation circuit 260 may decrease the code value of the second calibration code PCAL<1:n>. When the voltage level of the node ND is lower than the voltage level of the reference voltage VREF, the second calibration code generation circuit 260 may change the code value of the second calibration code PCAL<1:n> so that the resistance value of the pull-up resistor leg decreases. For example, the second calibration code generation circuit 260 may increase the code value of the second calibration code PCAL<1:n>.

[0034] The second calibration code generating circuit 260 may include a second comparator 261 and a second control signal generator 262. The second comparator 261 may be connected to the node ND to receive the reference voltage VREF. The second comparator 261 may compare a voltage level of the node ND with a voltage level of the reference voltage VREF. For example, the second comparator 261 may output a signal having a logic high level when the voltage level of the node ND is higher than the voltage level of the reference voltage VREF, and may output a signal having a logic low level when the voltage level of the node ND is lower than the voltage level of the reference voltage VREF. The second comparator 261 may further receive the clock signal CLK. The second comparator 261 may perform a voltage comparison operation in synchronization with the clock signal CLK. For example, the second comparator 261 may perform an operation of comparing a voltage level of the node ND with a voltage level of the reference voltage VREF in synchronization with a rising edge of the clock signal CLK.

[0035] The second control signal generator 262 may generate the second calibration code PCAL<1:n> by receiving a signal output from the second comparator 261. The second control signal generator 262 may decrease a code value of the second calibration code PCAL<1:n> when a signal having a logic high level is output from the second comparator 261. The second control signal generator 262 may increase a code value of the second calibration code PCAL<1:n> when a signal having a logic low level is output from the second comparator 261.

[0036] FIG. 5 is a diagram illustrating an operation of the calibration circuit 200 according to an embodiment of the present invention. The operation of the calibration circuit 200 and the semiconductor device 100 according to an embodiment of the present invention will be described below with reference to all of FIGS. 1, 2, and 5. When a rising edge of the clock signal CLK occurs to perform a calibration operation of the semiconductor device 100, the first comparator 221 can compare the voltage level of the reference resistor node RRN with the voltage level of the reference voltage VREF. When the voltage level of the reference resistor node RRN is lower than the voltage level of the reference voltage VREF, the first control signal generator 222 can transition the voltage sensing signal VD to a logic low level and decrease the code value of the first calibration code NCAL<1:n> to increase the resistance value of the reference resistor leg 210. When the code value of the first calibration code NCAL<1:n> decreases, the logic level of the least significant bit LSB of the first calibration code NCAL<1:n> can be transitioned. If the logic level of the least significant bit LSB transitions from a low level to a high level, the emphasis control signal generator 231 detects the logic level transition of the least significant bit of the first calibration code, and enables the emphasis control signal PS to a logic high level and the complementary signal PSB to a logic low level. The resistance value of the reference resistor leg 210 may increase according to the decreased code value of the first calibration code NCAL<1:n>, and the voltage level of the reference resistor node RRN may increase. Since the voltage detection signal VD has a logic low level, the pull-up emphasis driver 232-1 may pull up the reference resistor node RRN to accelerate the rise of the voltage level of the reference resistor node RRN, and the voltage level of the reference resistor node RRN may be quickly stabilized to a target voltage level.

[0037] When the next rising edge of the clock signal CLK occurs, the first comparator 221 compares the voltage level of the reference resistor node RRN with the voltage level of the reference voltage VREF again. At this time, if the emphasis circuit 230 is not provided, the voltage level of the reference resistor node RRN cannot reach the target voltage level, but if the emphasis circuit 230 is provided, the voltage level of the reference resistor node RRN can reach the target voltage level. Therefore, the embodiment of the present invention can perform a calibration operation by comparing the voltage level of the reference resistor node RRN that has reached the target voltage level with the voltage level of the reference voltage VREF, thereby enabling an accurate calibration operation to be performed. In addition, the voltage level of the reference resistor node can be quickly stabilized to the target voltage level, and the period of the voltage comparison operation can be reduced. Therefore, the time required for performing the calibration operation can be shortened. When the comparison result of the first comparator 221 indicates that the voltage level of the reference resistor node RRN is lower than the voltage level of the reference voltage VREF, the first control signal generator 222 may maintain the logic level of the voltage detection signal VD at a logic low level and decrease the code value of the first calibration code NCAL<1:n>. Due to the decrease in the code value of the first calibration code NCAL<1:n>, the logic level of the least significant bit LSB may transition from a logic high level to a logic low level. The emphasis control signal generator 231 may detect the transition of the least significant bit LSB and enable the emphasis control signal PS to a logic high level and the complementary signal PSB to a logic low level. The resistance value of the reference resistor leg 210 may increase due to the decreased code value of the first calibration code NCAL<1:n>, and the voltage level of the reference resistor node RRN may rise. At this time, the pull-up emphasis driver 232-1 can accelerate the rise in the voltage level of the reference resistor node RRN by pulling up the reference resistor node RRN, so that the voltage level of the reference resistor node RRN can be quickly stabilized to a new target voltage level.

[0038] Once the generation of the first calibration code NCAL<1:n> is completed, the resistance value of the pull-down resistor leg 240 can be set based on the first calibration code NCAL<1:n>. The second calibration code generation circuit 260 can increase or decrease the code value of the second calibration code PCAL<1:n> by comparing the voltage level of the node ND, which changes depending on the resistance ratio of the pull-up resistor leg 250 and the pull-down resistor leg 240, with the voltage level of the reference voltage VREF. Once the generation of the second calibration code PCAL<1:n> is completed, the calibration operation can be completed.

[0039] Those skilled in the art to which the present invention pertains should understand that the present invention can be embodied in other specific forms without departing from the technical spirit and essential features thereof, and that the above-described embodiments are illustrative and not limiting in all respects. The scope of the present invention is defined by the claims below rather than the above detailed description, and all modifications and variations derived from the meaning and scope of the claims and their equivalent concepts should be understood to be included in the scope of the present invention.

Claims

1. a reference resistor leg coupled to an external reference resistor via a reference resistor node, the reference resistor leg changing a voltage level of the reference resistor node according to a calibration code; a calibration code generating circuit that compares a voltage level of the reference resistor node with a voltage level of a reference voltage to generate a voltage sensing signal and the calibration code; and a calibration circuit comprising: an emphasis circuit for changing a voltage level of the reference resistance node based on the calibration code and the voltage sensing signal when the reference resistance leg changes a voltage level of the reference resistance node.

2. 2. The calibration circuit of claim 1, wherein the calibration code generation circuit transitions a logic level of the voltage sensing signal based on a comparison result between a voltage level of the reference resistor node and a voltage level of the reference voltage, thereby increasing or decreasing a code value of the calibration code.

3. the emphasis circuit includes an emphasis control signal generator that generates an emphasis control signal based on the calibration code; and 2. The calibration circuit of claim 1, further comprising an emphasis driver that changes a voltage level of the reference resistor node based on the voltage sense signal and the emphasis control signal.

4. 4. The calibration circuit according to claim 3, wherein the emphasis control signal generator senses a transition of at least a portion of the calibration code and enables the emphasis control signal.

5. the emphasis driver increases a voltage level of the reference resistor node based on the voltage sensing signal and the emphasis control signal when a voltage level of the reference resistor node is lower than a voltage level of the reference voltage; 4. The calibration circuit of claim 3, wherein when the voltage level of the reference resistor node is higher than the voltage level of the reference voltage, the voltage level of the reference resistor node is decreased based on the voltage sensing signal and the emphasis control signal.

6. the emphasis driver being a pull-up emphasis driver that raises a voltage level of the reference resistor node based on the voltage sensing signal and a complement of the emphasis control signal; and 4. The calibration circuit according to claim 3, further comprising a pull-down emphasis driver that lowers a voltage level of the reference resistor node based on the voltage sensing signal and the emphasis control signal.

7. the external reference resistor is connected between a terminal for supplying a first power supply voltage and the reference resistor node, and the reference resistor leg is connected between the reference resistor node and a ground voltage terminal; 7. The calibration circuit of claim 6, wherein the pull-up emphasis driver is connected between a terminal for supplying a second power supply voltage and the reference resistor node, and the pull-down emphasis driver is connected between the reference resistor node and the ground voltage terminal.

8. 8. The calibration circuit according to claim 7, wherein the second power supply voltage has a higher voltage level than the first power supply voltage.

9. A plurality of dies are commonly connected to an external reference resistor and sequentially perform a calibration operation; At least one of the plurality of dies includes a calibration circuit coupled to the external reference resistor via a reference resistor pad and configured to generate a first calibration code and a second calibration code; and a data output circuit having an impedance set based on the first and second calibration codes and outputting data; the calibration circuit includes a reference resistor leg coupled to a reference resistor node coupled to the reference resistor pad, the reference resistor leg changing a voltage level of the reference resistor node based on the first calibration code; a first calibration code generating circuit for comparing a voltage level of the reference resistor node with a voltage level of a reference voltage to generate a voltage sensing signal and the first calibration code; and a voltage detection signal and a first calibration code for detecting a voltage level of the reference resistor node when the reference resistor leg changes the voltage level of the reference resistor node, the voltage detection signal being detected by the first calibration code and the first calibration code being detected by the first calibration code.

10. the emphasis circuit increases a voltage level of the reference resistor node based on the voltage sensing signal and the first calibration code when the reference resistor leg increases a voltage level of the reference resistor node based on the first calibration code; 10. The semiconductor device of claim 9, wherein when the reference resistor leg lowers a voltage level of the reference resistor node based on the first calibration code, the voltage level of the reference resistor node is lowered based on the voltage sensing signal and the first calibration code.

11. the emphasis circuit includes an emphasis control signal generator that generates an emphasis control signal based on the calibration code; and 10. The semiconductor device according to claim 9, further comprising an emphasis driver that changes a voltage level of the reference resistor node based on the voltage detection signal and the emphasis control signal.

12. 12. The semiconductor device of claim 11, wherein the emphasis control signal generator detects a transition of a part of bits of the calibration code and enables the emphasis control signal.

13. the emphasis driver being a pull-up emphasis driver that raises a voltage level of the reference resistor node based on the voltage sensing signal and a complement of the emphasis control signal; and 12. The semiconductor device according to claim 11, further comprising a pull-down emphasis driver that lowers a voltage level of the reference resistor node based on the voltage detection signal and the emphasis control signal.

14. the external reference resistor is connected between a terminal for supplying a first power supply voltage and the reference resistor node, and the reference resistor leg is connected between the reference resistor node and a ground voltage terminal; 14. The semiconductor device of claim 13, wherein the pull-up emphasis driver is connected between a terminal for supplying a second power supply voltage and the reference resistor node, and the pull-down emphasis driver is connected between the reference resistor node and the ground voltage terminal.

15. 15. The semiconductor device according to claim 14, wherein the second power supply voltage has a higher voltage level than the first power supply voltage.

16. the calibration circuit includes a pull-down resistor leg whose resistance value is set based on the first calibration code; a pull-up resistor leg whose resistance value is set based on the second calibration code; and 10. The semiconductor device according to claim 9, further comprising a second calibration code generation circuit that generates the second calibration code by comparing a voltage level based on a resistance ratio of the pull-up resistor leg and the pull-down resistor leg with a voltage level of the reference voltage.

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