Switch circuit and imaging device

Abstract

To provide a switching circuit with high reliability, and an imaging apparatus having the switching circuit.SOLUTION: A switching circuit 100 includes: a first input terminal 401; an output terminal 400; and a first circuit 110 that switches over whether to output a first voltage to be input to the first input terminal 401 to the output terminal 400. The first circuit 110 includes a first transistor 1 and a second transistor 2 that are connected to each other in series between the first input terminal 401 and the output terminal 400; and a first voltage-division circuit 12 that divides a first voltage and supplies the same to a common node N1 between the first transistor 1 and the second transistor 2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a switch circuit and an imaging device including the switch circuit, and more particularly to a switch circuit including a plurality of transistors connected in series. [Background technology]

[0002] 2. Description of the Related Art Conventionally, as a switch circuit that uses low-voltage transistors to handle high voltages, a circuit configuration in which transistors are connected in series in multiple stages is known.

[0003] For example, in Patent Document 1 (see FIG. 3), a switch circuit connected between two terminals where a potential difference exceeding the transistor breakdown voltage occurs has a configuration in which NMOS transistors are connected in series in three stages. Furthermore, the following voltages are input to the gate voltages of these NMOS transistors. That is, two intermediate voltages are generated by resistively dividing a high voltage applied between the gate of the NMOS transistor in the first stage and the drain of the NMOS transistor in the third stage, and the first intermediate voltage, GND voltage Vg1, is input to the gate of the NMOS transistor in the first stage, intermediate voltage Vg2, which is the second highest after GND voltage Vg1, is input to the gate of the NMOS transistor in the second stage, and intermediate voltage Vg3, which is the third highest after GND voltage Vg1, is input to the gate of the NMOS transistor in the third stage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-207700 A Summary of the Invention [Problem to be solved by the invention]

[0005] There is a demand for improved reliability in a switch circuit including a plurality of transistors connected in series.

[0006] An object of the present disclosure is to provide a highly reliable switch circuit and an imaging device including the switch circuit. [Means for solving the problem]

[0007] According to certain non-limiting exemplary embodiments of the present disclosure, for example, the following is provided:

[0008] A switch circuit according to an embodiment of the present disclosure includes a first input terminal, an output terminal, and a first circuit configured to switch whether or not a first voltage input to the first input terminal is to be output to the output terminal, the first circuit including a first transistor and a second transistor connected in series between the first input terminal and the output terminal, and a first transistor configured to switch whether or not the first voltage is to be output to the output terminal. and a reference voltage that is maintained at a given potential. and a first voltage divider circuit that divides the voltage of the first input terminal and supplies the divided voltage to a first node between the first transistor and the second transistor, and when the first transistor and the second transistor are in an off state, the first input terminal is electrically insulated from the output terminal.

[0009] An imaging device according to one embodiment of the present disclosure comprises a semiconductor substrate, a pixel array including a plurality of pixels arranged on the semiconductor substrate, and the switch circuit located on the semiconductor substrate, each of the plurality of pixels having a photoelectric conversion unit including a first electrode layer, a second electrode layer, and a photoelectric conversion layer sandwiched between the first electrode layer and the second electrode layer, the first electrode layers of each of the plurality of pixels being electrically connected to each other, and the output terminal of the switch circuit being connected to the first electrode layer. Effect of the Invention

[0010] According to an embodiment of the present disclosure, the reliability of a switch circuit including a plurality of transistors connected in series and an imaging device including the switch circuit is improved. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of a switch circuit according to the first embodiment. [Diagram 2] FIG. 2 is a diagram showing a specific circuit example of the switch circuit according to the first embodiment. In FIG. [Diagram 3] FIG. 3 is a diagram illustrating a configuration example of a switch circuit according to the second embodiment. [Figure 4] FIG. 4 is a diagram showing a table illustrating the states of the switch circuit in the second embodiment. [Diagram 5] FIG. 5 is a diagram showing a specific circuit example of the switch circuit according to the second embodiment. In FIG. [Figure 6] FIG. 6 is a diagram showing a specific circuit example of the switch circuit according to the third embodiment. In FIG. [Figure 7] FIG. 7 is a diagram showing a configuration example of an image sensor according to a fourth embodiment, in which the switch circuit according to any one of the first to third embodiments is mounted. [Figure 8] FIG. 8 is a timing chart showing an example of the operation of the image sensor shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] (Findings that have led to one aspect of the present disclosure) In the switch circuit disclosed in Patent Document 1, three transistors are connected in series, and voltages Vg2 and Vg3 obtained by dividing the high voltage between a high-voltage node nd1 and a low-voltage node nd3 by resistors are applied to the gates of two of the three transistors. This switch circuit is configured to be in an on state when the voltage of node nd2=the voltage of node nd1<0 (i.e., negative potential), and to be in an off state when the voltage of node nd2<the voltage of node nd1, or when the voltage of node nd2=the voltage of node nd1=GND level. In this switch circuit, the three transistors are connected in series so that the transistors can maintain their reliability without being damaged even when a voltage exceeding the withstand voltage of the transistor is applied to node nd1. The withstand voltage is the maximum allowable voltage that can be applied to a transistor, and is also called the maximum rating. In addition, when simply written as "transistor", it refers to the transistor that constitutes the switch circuit. In addition, "high voltage" as an input voltage is a relative term and means a voltage exceeding the withstand voltage of the transistor.

[0013] However, when the switch circuit is in the off state, the voltages of the source terminal and drain terminal of each transistor converge to a certain value due to the off-leak current of the transistor after the gate voltage of each transistor is divided by resistors. The time it takes to converge and the voltage value at which it converges also vary depending on the threshold voltage (Vth) of each transistor, the potential difference between node nd1 and node nd2, the size of each transistor (gate width, gate length), the off-leak current value, the power supply voltage, the junction temperature, and other factors. For this reason, it is difficult to frequently switch the on / off state of the switch circuit while reliably controlling the voltages between the gate-source, gate-drain, drain-source, and gate-backgate terminals to below the withstand voltage.

[0014] Furthermore, in the conventional switch circuit, it is assumed that the nodes nd1 and nd2 are at the same potential when the switch circuit is in the off state. For this reason, when a switch circuit is constructed using two or more switch circuit elements and has the same number of input terminals and one common output terminal as the number of the switch circuit elements, when any one of the switch circuit elements is in the on state and the other switch circuit element is in the off state and a potential difference occurs between the input terminal and the common output terminal of the switch circuit element in the off state, it is difficult to maintain the switch circuit element in the off state while ensuring the reliability of the transistor constituting the switch circuit element in the off state. Note that the switch circuit is a circuit as a whole having a switch function. The switch circuit element is one of the elements constituting the switch circuit and is a circuit having a switch function. The switch circuit is composed of one or more switch circuit elements.

[0015] Therefore, an object of the present disclosure is to provide a switch circuit that can speed up the on / off switching time and reliably control the inter-terminal voltage of each transistor to be equal to or lower than the withstand voltage when configuring a switch circuit with a high withstand voltage using low withstand voltage transistors.Furthermore, an object of the present disclosure is to ensure the reliability of transistors in the off state in a switch circuit that uses two or more switch circuit elements and has the same number of input terminals as the number of the switch circuit elements and one common output terminal.

[0016] In order to achieve the above object, in an embodiment of the present disclosure, a desired voltage generated by resistive voltage division is applied to the drain voltage terminal of the first transistor (i.e., the source voltage of the second transistor), thereby making the drain voltage of the first transistor (i.e., the source voltage of the second transistor) follow the response characteristics when controlling the gate voltage while reliably keeping the voltage between the terminals of each transistor below the withstand voltage. As a result, in a switch circuit that uses low-voltage transistors to turn on and off a high voltage, it becomes possible to switch the on / off state faster than with conventional technology while maintaining the reliability of the low-voltage transistors.

[0017] The following embodiments will be described with reference to the drawings. Each of the embodiments described below shows a specific example of the present disclosure. The numerical values, shapes, components, the arrangement and connection of the components, operation timing, and the like shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, each figure is not necessarily a strict illustration. In each figure, substantially the same configuration is given the same reference numeral, and duplicated explanations may be omitted or simplified.

[0018] (Embodiment 1) FIG. 1 is a diagram showing a configuration example of a switch circuit 100 in the first embodiment. In FIG. 1, the switch circuit 100 includes a first input terminal 401 to which a high voltage, which is an example of a first voltage, is input, an output terminal 400 to which the high voltage input to the first input terminal 401 is output, and a first circuit 110 which is a switch circuit element for switching whether or not the high voltage input to the first input terminal 401 is output to the output terminal 400. The first circuit 110 includes a first transistor 1 and a second transistor 2 connected in series, a first gate voltage control unit 10 which controls the on / off of the first transistor 1, a second gate voltage control unit 11 which controls the on / off of the second transistor 2, and a first voltage dividing circuit 12 which divides the high voltage input to the first input terminal 401. A voltage VN1 obtained by the voltage division in the first voltage dividing circuit 12 is supplied to a common node N1 which is an example of a first node between the first transistor 1 and the second transistor 2. It should be noted that the first gate voltage control section 10 and the second gate voltage control section 11 do not necessarily have to be provided in the first circuit 110, and may be provided outside the switch circuit 100, for example.

[0019] In this embodiment, both the first transistor 1 and the second transistor 2 are PMOS transistors. When the switch circuit 100 is turned on, the first gate voltage control unit 10 and the second gate voltage control unit 11 turn on the first transistor 1 and the second transistor 2, respectively, while when the switch circuit 100 is turned off, the first gate voltage control unit 10 and the second gate voltage control unit 11 turn off the first transistor 1 and the second transistor 2, respectively.

[0020] In the switch circuit 100 of this embodiment, two low-voltage transistors, the first transistor 1 and the second transistor 2, are connected in series, and therefore, when the switch circuit 100 is in an off state, the terminal voltage between any two terminals (between the gate terminal and the source terminal, between the gate terminal and the drain terminal, between the drain terminal and the source terminal, between the gate terminal and the backgate terminal, between the source terminal and the backgate terminal, and between the drain terminal and the backgate terminal) of the first transistor 1 and the second transistor 2 is controlled so as not to exceed the withstand voltage of the transistor. Note that when the switch circuit 100 is in an off state, the output terminal 400 is in a floating state, so that another voltage may be applied to the output terminal 400 via another switch circuit.

[0021] For example, an example is shown of the gate voltage of the transistor and the voltage VN1 of the common node N1 between the two series-connected first transistor 1 and second transistor 2 in a state in which the withstand voltage Vhv of the transistor is 4 V, the high voltage VIN1 = 7 V input to the first input terminal 401, and the output voltage VOUT = 0 V is applied to the output terminal 400 when the switch circuit 100 is in the off state.

[0022] The first gate voltage control unit 10 applies a gate voltage Vg1=7V to the gate of the first transistor 1. As a result, the gate-source voltage of the first transistor 1 becomes Vg1-VIN=0V, and the first transistor 1 is turned off. The second gate voltage control unit 11 applies a gate voltage Vg2 determined as follows to the gate of the second transistor 2. That is, the gate voltage Vg2 of the second transistor 2 is determined so as to satisfy (Vg2-VOUT)<4V, which is the potential difference between the gate of the second transistor 2 and the output terminal 400, and (Vg2-VN1)>Vth and Vg1-VN1<4V. For example, if Vg2=3.5V and VN1=3.5V, then Vg1-VN1=3.5V and Vg2-VN1=0V, and therefore the above-mentioned conditions can be satisfied. Note that Vth is the threshold voltage of the first transistor 1 and the second transistor 2.

[0023] In the switch circuit 100 of this embodiment, when the switch circuit 100 is in the off state, even if the output voltage VOUT changes from 7 V to 0 V, a potential difference of 3.5 V or more is not generated between any two terminals of the first transistor 1 and the second transistor 2 of the switch circuit 100, and the reliability of the transistors can be ensured.

[0024] Fig. 2 is a diagram showing a specific circuit example of the switch circuit 100 in the first embodiment. In this circuit example, the switch circuit 100 includes a bias voltage generating circuit 500 and a control circuit 501 in addition to the elements shown in Fig. 1. However, the bias voltage generating circuit 500 and the control circuit 501 do not necessarily need to be included in the switch circuit 100, and may be provided outside the switch circuit 100.

[0025] The first gate voltage control unit 10 outputs, as the gate voltage Vg1, to the gate of the first transistor 1, either a voltage obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 or a high voltage input to the first input terminal 401. For this purpose, the first gate voltage control unit 10 includes a control transistor 301 that controls whether to output a divided voltage obtained by dividing the high voltage VIN1 input to the first input terminal 401 by voltage dividing resistors R10 and R11, or to output a high voltage input to the first input terminal 401. Since the high voltage VIN1 input to the first input terminal 401 exceeds the withstand voltage of the transistor used in the first gate voltage control unit 10, the control transistor 300 is connected in series with the control transistor 301, and a configuration is adopted in which the potential difference between each terminal of the control transistors 300 and 301 does not exceed the withstand voltage of the transistor.

[0026] The control circuit 501 operates by receiving a power supply voltage (e.g., 3.3 V) supplied to an SoC (System on Chip) on which the switch circuit 100 is mounted. The bias voltage generation circuit 500 outputs a divided voltage (e.g., 4 V) obtained by resistively dividing the voltage between the first input terminal 401 and the reference voltage terminal 600. The reference voltage terminal 600 is maintained at the same potential as the ground potential of the SoC, for example.

[0027] The second gate voltage control section 11 outputs, as the gate voltage Vg2, either a voltage obtained by dividing the voltage between the common node N1 and the reference voltage terminal 600 or the voltage of the common node N1 to the gate of the second transistor 2. For this purpose, the second gate voltage control section 11 includes a control transistor 303 that controls whether to output a divided voltage obtained by dividing the voltage VN1 of the common node N1 by voltage dividing resistors R20 and R21 or to output the voltage VN1 of the common node N1. Since the voltage VN1 of the common node N1 may exceed the withstand voltage of the transistor used in the second gate voltage control section 11, the control transistor 302 is connected in series with the control transistor 303, and a configuration is adopted in which the potential difference between the terminals of the control transistors 302 and 303 does not exceed the withstand voltage of the transistor.

[0028] The first voltage divider circuit 12 is connected between the first input terminal 401 and the reference voltage terminal 600, and is composed of two voltage dividing resistors R1 and R2 connected in series. The voltage dividing resistors R1 and R2 are an example of a first resistive element and a second resistive element, respectively. The connection point of the voltage dividing resistors R1 and R2 is connected to a common node N1. The first voltage divider circuit 12 divides the high voltage VIN1 input to the first input terminal 401 by the voltage dividing resistors R1 and R2, and supplies the divided voltage to the common node N1 between the first transistor 1 and the second transistor 2.

[0029] Assuming that the input high voltage is 7V, the SoC power supply voltage is 3.3V, the voltage of the reference voltage terminal 600 is the SoC ground terminal 0V, and the transistor withstand voltage is 4V, the operating state of the switch circuit 100 will be described below.

[0030] When turning on the first transistor 1 and the second transistor 2, the control circuit 501 outputs an H level (e.g., 3.3 V). As a result, the control transistors 301 and 303 are turned on, and the voltage dividing resistors R10 and R11 and R20 and R21 of the first gate voltage control unit 10 and the second gate voltage control unit 11 are connected to the reference voltage terminal 600. Therefore, the first gate voltage control unit 10 outputs, as the gate voltage Vg1, the voltage obtained by dividing the high voltage input to the first input terminal 401 with the voltage dividing resistors R10 and R11 to the gate of the first transistor 1. As a result, the first transistor 1 is turned on. At this time, Vg1 = VIN1 × {R11 / (R10 + R11)}. Note that the voltage dividing resistors R10 and R11 are set to resistance values such that (Vg1 - VIN1) < Vth and |Vg1 - VIN1| < 4V. Similarly, the second gate voltage control unit 11 outputs, as the gate voltage Vg2, the voltage obtained by dividing the voltage VN1 of the common node N1 with the voltage dividing resistors R20 and R21 to the gate of the second transistor 2. As a result, the second transistor 2 is turned on. At this time, Vg2 = VN1 × {R21 / (R20 + R21)}. Note that the voltage dividing resistors R20 and R21 are set to resistance values such that (Vg2 - VN1) < Vth and |Vg2 - VN1| < 4V.

[0031] Also, by setting the resistance values of the voltage dividing resistors R1 and R2 to 1000 times or more the on-resistance values of the first transistor 1 and the second transistor 2, when the first transistor 1 is in the on state, the voltage of the common node N1 (VN1) becomes almost equal to the high voltage VIN1 of the first input terminal 401.

[0032] On the other hand, when turning off the first transistor 1 and the second transistor 2, the control circuit 501 outputs an L level, that is, a voltage equal to the voltage of the reference voltage terminal 600 (for example, the ground voltage 0V of the SoC). As a result, the control transistors 301 and 303 are turned off, and the voltage dividing resistors R10 and R11 and R20 and R21 of the first gate voltage control unit 10 and the second gate voltage control unit 11 are not connected to the reference voltage terminal 600. Therefore, the first gate voltage control unit 10 outputs, as the gate voltage Vg1, a voltage having the same potential as the high voltage VIN1 input to the first input terminal 401 to the gate of the first transistor 1. As a result, the first transistor 1 is turned off.

[0033] The first voltage dividing circuit 12 is always connected between the first input terminal 401 and the reference voltage terminal 600 regardless of the output state of the control circuit 501, and when the first transistor 1 is in the off state, the divided voltage VN1 by the voltage dividing resistors R1 and R2 is a voltage obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 by the voltage dividing resistors R1 and R2. The second gate voltage control unit 11 is connected between the output terminal (i.e., the common node N1) of the first voltage dividing circuit 12 and the reference voltage terminal 600, and when the control transistor 303 is in the off state, it outputs VN1=VIN1×{R2 / (R1+R2)} as the gate voltage Vg2 to the gate of the second transistor 2. In other words, the output voltage Vg2 of the second gate voltage control unit 11 is Vg2=VN1. Therefore, the voltage at the source terminal of the second transistor 2 (i.e., the voltage VN1 at the common node N1) - the gate voltage of the second transistor 2 (Vg2 voltage) ≈ 0 V, and the second transistor 2 is turned off. Note that the resistance values ​​of the voltage-dividing resistors R1 and R2 are set so that |VN1-VOUT|<4 V when the second transistor 2 is in the off state.

[0034] As described above, according to the switch circuit 100 of the first embodiment, the first voltage divider circuit 12 enables the voltage of the common node N1 between the first transistor 1 and the second transistor 2 to converge to a desired voltage accurately and quickly when the switch circuit 100 is in an off state. In addition, it becomes possible to perform control so as not to exceed the withstand voltage of the transistor without being affected by variations in Vth of the transistor due to temperature changes or manufacturing variations.

[0035] As described above, the switch circuit 100 in this embodiment includes the first input terminal 401, the output terminal 400, and the first circuit 110 that switches whether or not the first voltage input to the first input terminal 401 is output to the output terminal 400. The first circuit 110 includes a first transistor 1 and a second transistor 2 connected in series between the first input terminal 401 and the output terminal 400, and a first voltage divider circuit 12 that divides the first voltage and supplies it to a common node N1 between the first transistor 1 and the second transistor 2.

[0036] As a result, a divided voltage obtained by dividing the first voltage input to the first input terminal 401 by the first voltage divider circuit 12 is supplied to the common node N1 between the first transistor 1 and the second transistor 2. Therefore, unlike the conventional technology of dividing the power supply voltage, it is possible to accurately and quickly converge the voltage of the common node N1 between the first transistor 1 and the second transistor 2 to a desired voltage. In addition, it is possible to perform control so that the withstand voltage of the transistor is not exceeded without being affected by the Vth variation of the transistor due to temperature change or manufacturing variation. As a result, the reliability of the switch circuit including a plurality of transistors connected in series is improved.

[0037] The first voltage dividing circuit 12 includes a first resistor element (R1) and a second resistor element (R2) connected in series between the first input terminal 401 and a reference voltage, and the connection point between the first resistor element (R1) and the second resistor element (R2) is connected to a common node N1. This makes it possible to accurately and quickly converge the voltage of the common node N1 to a desired voltage by simple resistive voltage division.

[0038] (Embodiment 2) FIG. 3 is a diagram showing a configuration example of the switch circuit 200 in the second embodiment. In FIG. 3, the switch circuit 200 includes a first input terminal 401 to which a high voltage, which is an example of a first voltage, is input, a second input terminal 402 to which a low voltage, which is an example of a second voltage, is input, an output terminal 400 to selectively output a high voltage input to the first input terminal 401 or a low voltage input to the second input terminal 402, a first circuit 110 which is a switch circuit element that receives a high voltage, which is an example of a first voltage, and controls on / off of whether to output the input high voltage, and a second circuit 120 which is a switch circuit element that receives a low voltage, which is an example of a second voltage, and controls on / off of whether to output the input low voltage. In this embodiment, the low voltage input to the second input terminal 402 is a voltage that does not exceed the withstand voltage of either the third transistor 3 or the fourth transistor 4. The same components as those in the first embodiment are denoted by the same reference numerals, and their description will be omitted.

[0039] The second circuit 120 includes a third transistor 3 and a fourth transistor 4 connected in series, a third gate voltage control unit 13 that controls the on / off of the third transistor 3, a fourth gate voltage control unit 14 that controls the on / off of the fourth transistor 4, and a second voltage dividing circuit 15 that divides the voltage of the output terminal 400. The voltage obtained by the voltage division in the second voltage dividing circuit 15 is supplied to a common node N2, which is an example of a second node between the third transistor 3 and the fourth transistor 4. The third gate voltage control unit 13 and the fourth gate voltage control unit 14 do not necessarily need to be included in the second circuit 120, and may be provided outside the switch circuit 200, for example.

[0040] Fig. 4 is a diagram showing a table illustrating the states of the switch circuit 200 in Fig. 3. Shown are the output voltage VOUT of the switch circuit 200, the on / off state of the first circuit 110, and the on / off state of the second circuit 120 in each of three states of the switch circuit 200 ("State 1", "State 2", and "State 3"). In "State 3", the output terminal 400 of the switch circuit 200 is in a floating state, and the output voltage VOUT of the switch circuit 200 is undefined ("-" in the diagram).

[0041] FIG. 5 is a diagram showing a specific circuit example of the switch circuit 200 according to the second embodiment.

[0042] In the switch circuit 200, the first circuit 110 has the same configuration as the circuit shown in Fig. 2. In the switch circuit 200, the second circuit 120 includes a bias voltage generating circuit 502, a control circuit 503, and voltage dividing resistors R31 and R32 in addition to the elements shown in Fig. 3. However, the bias voltage generating circuit 502, the control circuit 503, and the voltage dividing resistors R31 and R32 do not necessarily need to be included in the switch circuit 200, and may be provided outside the switch circuit 200.

[0043] The second circuit 120 has an input terminal connected to a second input terminal 402 to which a low voltage (a voltage not exceeding a transistor withstand voltage) is input, and an output terminal connected to the same node as the output terminal 400 of the first circuit 110.

[0044] The third gate voltage control unit 13 has a control circuit 504 that receives a power supply voltage (e.g., 3.3 V) of the SoC and outputs a gate voltage Vg3 to the gate of the third transistor 3. The fourth gate voltage control unit 14 outputs a voltage obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 as a gate voltage Vg4 to the gate of the fourth transistor 4.

[0045] The second voltage dividing circuit 15 is connected between the output terminal 400 and the reference voltage terminal 600, and is composed of two voltage dividing resistors R3 and R4 connected in series. The voltage dividing resistors R3 and R4 are an example of a third resistor element and a fourth resistor element, respectively. The connection point of the voltage dividing resistors R3 and R4 is connected to a common node N2. The second voltage dividing circuit 15 divides the voltage between the output terminal 400 and the reference voltage terminal 600 by the voltage dividing resistors R3 and R4, and supplies the obtained divided voltage VN2 to the common node N2 between the third transistor 3 and the fourth transistor 4.

[0046] 4, the switch circuit 200 can be in three states depending on a combination of the on / off states of the first circuit 110 and the second circuit 120. Below, the circuit operation in each of the three states 1 to 3 shown in FIG 4 will be described assuming that the high voltage VIN1 input to the first input terminal 401 is 7V, the low voltage VIN2 input to the second input terminal 402 is 0.5V, the SoC power supply voltage is 3.3V, the voltage of the reference voltage terminal 600 is SoC ground terminal is 0V, and the transistor withstand voltage is 4V.

[0047] In state 1 shown in FIG. 4, the first circuit 110 is on (i.e., the first transistor 1 and the second transistor 2 are on) and the second circuit 120 is off (i.e., the third transistor 3 and the fourth transistor 4 are off).

[0048] The on state of the first transistor 1 and the second transistor 2 is the same as the on state of the first transistor 1 and the second transistor 2 of the switch circuit 100 in FIG. 2, so a detailed description of the operation will be omitted.

[0049] To turn off the third transistor 3 and the fourth transistor 4, the control circuits 503 and 504 output the same voltage as the reference voltage terminal 600 (for example, the ground voltage 0V of the SoC). Note that when the voltage input to the third transistor 3 is equal to or lower than the breakdown voltage, it may be controlled at the same potential as the power supply voltage of the SoC. Since the control circuit 504 outputs the same voltage as the reference voltage terminal 600 to the gate of the third transistor 3, (Vg3 - VIN2) < Vth, and the third transistor 3 is turned off. Note that Vth in the present embodiment is the threshold voltage of the third transistor 3 and the fourth transistor 4.

[0050] Next, the output voltage of the fourth gate voltage control unit 14 (i.e., the gate voltage Vg4 of the fourth transistor 4) will be described. When the first circuit 110 is in the on state, the output voltage VOUT = VIN1, and since the high voltage VIN1 input to the first input terminal 401 is output as the output voltage VOUT, the off state of the fourth transistor 4 must be maintained with the high voltage VIN1 applied to the drain terminal of the fourth transistor 4. Therefore, the fourth gate voltage control unit 14 generates the gate voltage Vg4 using the high voltage VIN1 input to the first input terminal 401. Specifically, since the control transistor 305 is in the off state, the fourth gate voltage control unit 14 outputs, as the gate voltage Vg4, the voltage obtained by dividing the high voltage VIN1 input to the first input terminal 401 with the voltage dividing resistors R31 and R32. At this time, VIN2, Vg3, Vg4, the voltage VN2 at the common node N2, and VOUT must satisfy the relationships |VOUT - Vg4| < 4V, (Vg4 - VN2) < Vth, |VOUT - VN2| < 4V, |VN2 - Vg3| < 4V, and |VN2 - VIN2| < 4V, respectively. Note that the voltages of VN2 and Vg4 can be calculated as VN2 = VOUT × {R4 / (R3 + R4)} and Vg4 = VIN1 × {R32 / (R31 + R32)}, respectively. For example, if designed such that VN2 = 3.0V and Vg4 = 3.0V, the five relational expressions are satisfied, and the fourth transistor 4 can be turned off. In this way, by generating the gate voltage Vg4 of the fourth transistor 4 and the voltage VN2 of the common node N2 between the third transistor 3 and the fourth transistor 4 from the high voltage VIN1 input to the first input terminal 401 and the output voltage VOUT, respectively, reliable control that does not exceed the breakdown voltage of the transistor connected to the boundary between the high voltage and the low voltage becomes possible, and the reliability of the switch circuit can be ensured.

[0051] In the state 2 shown in FIG. 4, the first circuit 110 is in the off state (i.e., the first transistor 1 and the second transistor 2 are in the off state), and the second circuit 120 is in the on state (i.e., the third transistor 3 and the fourth transistor 4 are in the on state).

[0052] The off state of the first transistor 1 and the second transistor 2 is the same as the off state of the first transistor 1 and the second transistor 2 of the switch circuit 100 in FIG. 2, so a detailed description of the operation will be omitted.

[0053] To turn on the third transistor 3 and the fourth transistor 4, the control circuits 503 and 504 output an H level, that is, a voltage the same as the SoC power supply voltage (e.g., 3.3 V). As a result, (Vg3-VIN2)>Vth, and the third transistor 3 is turned on.

[0054] Next, the output voltage of the fourth gate voltage control unit 14 (i.e., the gate voltage Vg4 of the fourth transistor 4) will be described. Since the control transistor 305 is in the ON state, the fourth gate voltage control unit 14 outputs Vg4=VIN1×{(R32 / / R33) / {R31+(R32 / / R33)}} (note that R32 / / R33=R32×R33 / (R32+R33)) as the gate voltage Vg4 to the gate of the fourth transistor 4. At this time, if (Vg4-VIN2)>Vth and |Vg4-VIN2|<4V, the fourth transistor is in the ON state and the output voltage VOUT=VIN2. In addition, by setting the resistance values ​​of the voltage-dividing resistors R3 and R4 of the second voltage-dividing circuit 15 to be 1000 times or more the on-resistance values ​​of the third transistor 3 and the fourth transistor 4, when the fourth transistor 4 is in the on state, the voltage VN2 of the common node N2 becomes approximately equal to the voltage of the second input terminal 402.

[0055] 4, the first circuit 110 is in the off state (i.e., the first transistor 1 and the second transistor 2 are in the off state), and the second circuit 120 is in the off state (i.e., the third transistor 3 and the fourth transistor 4 are in the off state). In this state 3, the output terminal 400 of the switch circuit 200 is in a floating state.

[0056] Details of the off state of the first circuit 110 are the same as those of the off states of the first transistor 1 and the second transistor 2 of the switch circuit 100 in Fig. 2. Meanwhile, details of the off state of the second circuit 120 are the same as those of the off state of the second circuit 120 in state 1 of the switch circuit 200 (i.e., the off states of the third transistor 3 and the fourth transistor 4). Therefore, detailed explanations of the operations of the first circuit 110 and the second circuit 120 will be omitted.

[0057] As described above, according to the switch circuit 200 in the second embodiment, even when a switch circuit that outputs a high voltage and a low voltage from the same terminal is constructed, it is possible to accurately and quickly converge the voltage of the common node N1 between the first transistor 1 and the second transistor 2 and the voltage of the common node N2 between the third transistor 3 and the fourth transistor 4 to a desired voltage when the switch circuit element is in the off state. Furthermore, it is possible to reliably control so as not to exceed the withstand voltage of the transistor without being affected by the Vth variations of the transistor due to temperature changes and manufacturing variations, and it is possible to provide a switch circuit that can switch between high voltage and low voltage while satisfying the reliability of the transistor.

[0058] As described above, the switch circuit 200 in this embodiment further comprises, in comparison with the switch circuit 100 in the first embodiment, the second input terminal 402 and the second circuit 120 that switches whether or not the second voltage input to the second input terminal 402 is to be output to the output terminal 400. The second circuit 120 includes a third transistor 3 and a fourth transistor 4 connected in series between the second input terminal 402 and the output terminal 400, and a second voltage divider circuit 15 that divides the voltage of the output terminal 400 and supplies it to a common node N2 between the third transistor 3 and the fourth transistor 4.

[0059] This makes it possible to selectively output from the output terminal 400 either the first voltage input to the first input terminal 401 or the second voltage input to the second input terminal 402. Also, a divided voltage obtained by dividing the voltage of the output terminal 400 by the second voltage divider circuit 15 is supplied to the common node N2 between the third transistor 3 and the fourth transistor 4. Therefore, unlike the conventional technology of dividing the power supply voltage, it becomes possible to accurately and quickly converge the voltage of the common node N2 between the third transistor 3 and the fourth transistor 4 to a desired voltage. Also, it becomes possible to perform control so as not to exceed the withstand voltage of the transistor without being affected by the Vth variation of the transistor due to temperature change or manufacturing variation. As a result, a switch circuit with improved reliability is realized, which includes a plurality of switch circuit elements and selectively outputs one of two or more types of input voltages.

[0060] The second voltage dividing circuit 15 also includes a third resistor element (R3) and a fourth resistor element (R4) connected in series between the output terminal 400 and the reference voltage, and the connection point between the third resistor element (R3) and the fourth resistor element (R4) is connected to the common node N2. This makes it possible to accurately and quickly converge the voltage of the common node N2 to a desired voltage by simple resistance voltage division.

[0061] In addition, a high voltage exceeding the maximum rating of at least one of the first transistor 1 and the second transistor 2 is input to the first input terminal 401, and a low voltage not exceeding the maximum rating of either the third transistor 3 or the fourth transistor 4 is input to the second input terminal 402, and the output terminal 400 outputs the high voltage input to the first input terminal 401 during a first period, and outputs the low voltage input to the second input terminal 402 during a second period different from the first period.

[0062] As a result, even if a high voltage exceeding the maximum rating of the transistor is input, the potential difference between any two terminals of the transistor is equal to or less than the maximum rating, and a switch circuit is realized that selectively outputs the high voltage input to the first input terminal 401 and the low voltage input to the second input terminal 402.

[0063] (Embodiment 3) Fig. 6 is a diagram showing a specific circuit example of the switch circuit 210 in the third embodiment. This switch circuit 210 corresponds to a modified example of the switch circuit 200 in the second embodiment shown in Fig. 5. More specifically, the switch circuit 210 has a configuration in which two transistors connected in series (a first transistor 1 and a second transistor 2) in the switch circuit 200 are replaced with three transistors connected in series, and two transistors connected in series (a third transistor 3 and a fourth transistor 4) are replaced with three transistors connected in series.

[0064] Specifically, switch circuit 210 includes a first input terminal 401 to which a high voltage is input, a second input terminal 402 to which a low voltage is input, an output terminal 400 which outputs the high voltage input to first input terminal 401 or the low voltage input to second input terminal 402, a first circuit 110a which is a switch circuit element that receives a high voltage as an input and controls on / off of whether or not to output the input high voltage, and a second circuit 120a which is a switch circuit element that receives a low voltage as an input and controls on / off of whether or not to output the input low voltage. The same components as those in the second embodiment are denoted by the same reference numerals, and their description will be omitted.

[0065] The first circuit 110a includes a first transistor 1, a second transistor 2, and a fifth transistor 5 connected in series, a first gate voltage control unit 10a that controls the on / off of the first transistor 1, a second gate voltage control unit 11a that controls the on / off of the second transistor 2, a fifth gate voltage control unit 16 that controls the on / off of the fifth transistor 5, a first voltage dividing circuit 12a that divides a high voltage input to a first input terminal 401 and supplies the two obtained divided voltages to a common node N3 and a common node N1, which are an example of a third node between the second transistor 2 and the fifth transistor 5, respectively, bias voltage generating circuits 500 and 500a, and a control circuit 501.

[0066] The first circuit 110a in the present embodiment has a configuration in which a fifth transistor 5 is added to the rear stage of the first transistor 1 and the second transistor 2 of the first circuit 110 in the second embodiment. However, the fifth transistor 5 may be connected to the front stage of the first transistor 1 and the second transistor 2, or between them. In other words, the first circuit 110a in the present embodiment has a configuration in which three transistors are connected in series, unlike the second embodiment in which two transistors are connected in series.

[0067] Like the first transistor 1 and the second transistor 2, the fifth transistor 5 is a PMOS transistor in this embodiment.

[0068] The bias voltage generating circuit 500 outputs a divided voltage (e.g., a divided voltage that is ⅔ of the high voltage) obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 by resistor division. The bias voltage generating circuit 500a outputs a divided voltage (e.g., a divided voltage that is ⅓ of the high voltage) obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 by resistor division.

[0069] The first gate voltage control unit 10a is a circuit that controls the on / off of the first transistor 1, and has a configuration in which the two control transistors 300 and 301 connected in series in the first gate voltage control unit 10 of the second embodiment are replaced with three control transistors 300, 306 and 301 connected in series.

[0070] The second gate voltage control section 11a is a circuit that controls the on / off of the second transistor 2, and has a configuration in which the two control transistors 302 and 303 connected in series in the second gate voltage control section 11 of the second embodiment are replaced with three control transistors 302, 307 and 303 connected in series.

[0071] The fifth gate voltage controller 16 basically has the same configuration as the second gate voltage controller 11a. That is, the fifth gate voltage controller 16 is connected between the common node N3 and the reference voltage terminal 600, and is composed of voltage dividing resistors R20a and R20b, and control transistors 302a, 308, and 303a, which are connected in series.

[0072] The first voltage dividing circuit 12a is connected between the first input terminal 401 and the reference voltage terminal 600, and is composed of three voltage dividing resistors R1a, R2a, and R2b connected in series. The connection point between the voltage dividing resistors R1a and R2a is connected to a common node N1 and one end of the second gate voltage control unit 11a (i.e., one end of the voltage dividing resistor R20). The connection point between the voltage dividing resistors R2a and R2b is connected to a common node N3 and one end of the fifth gate voltage control unit 16 (i.e., one end of the voltage dividing resistor R20a).

[0073] The second circuit 120a includes a third transistor 3, a sixth transistor 6, and a fourth transistor 4 connected in series, a third gate voltage control unit 13 that controls the on / off of the third transistor 3, a fourth gate voltage control unit 14a that controls the on / off of the sixth transistor 6 and the fourth transistor 4, a second voltage dividing circuit 15a that divides the voltage output to the output terminal 400 and supplies the two obtained divided voltages to a common node N4 and a common node N2, which are an example of a fourth node between the third transistor 3 and the sixth transistor 6, respectively, a bias voltage generating circuit 502, and a control circuit 503.

[0074] The second circuit 120a in the present embodiment has a configuration in which a sixth transistor 6 is added between the third transistor 3 and the fourth transistor 4 of the second circuit 120 in the second embodiment. However, the sixth transistor 6 may be connected in front of the third transistor 3 and the fourth transistor 4, or in the rear of them. That is, the second circuit 120a in the present embodiment has a configuration in which three transistors are connected in series, unlike the second embodiment in which two transistors are connected in series.

[0075] Like the third transistor 3 and the fourth transistor 4, the sixth transistor 6 is an NMOS transistor in this embodiment.

[0076] The fourth gate voltage control unit 14a is a circuit that controls the on / off of the fourth transistor 4 and the sixth transistor 6, and basically has the same configuration as the fourth gate voltage control unit 14 in the second embodiment. However, in addition to the function of the fourth gate voltage control unit 14 in the second embodiment, the fourth gate voltage control unit 14a also has a function of applying the voltage applied to the gate of the control transistor 304 as the gate voltage Vg6 to the gate of the sixth transistor 6 as it is. Note that in this embodiment, the gate voltage Vg6 happens to be the same voltage regardless of whether the second circuit 120a is on or off, and is the same voltage as the bias voltage applied to the gate of the control transistor 304, so the voltage applied to the gate of the control transistor 304 is applied to the gate of the sixth transistor 6 as the gate voltage Vg6 as it is. However, if the number of transistors connected in series in the second circuit 120a is not three as in this embodiment but is a different number such as four or five, or if the voltages of the high voltage VIN1 and the low voltage VIN2 are different from those in this embodiment, the voltage applied to the gate of the control transistor 304 is not necessarily applied as is as the gate voltage Vg6 to the gate of the sixth transistor 6. In such a case, a gate control unit is provided that outputs, as the gate voltage, an appropriate voltage required to turn on and off each of the transistors connected in series.

[0077] The second voltage dividing circuit 15a is connected between the output terminal 400 and the reference voltage terminal 600, and is composed of three voltage dividing resistors R3a, R4a, and R4b connected in series. The connection point between the voltage dividing resistors R3a and R4a is connected to a common node N1, and the connection point between the voltage dividing resistors R4a and R4b is connected to a common node N4.

[0078] The operation of the switch circuit 210 in the present embodiment configured as above is as follows. The switch circuit 210 in the present embodiment takes the same state as that of the second embodiment shown in FIG. 4. That is, when the first circuit 110a is in the on state and the second circuit 120a is in the off state, the switch circuit 210 goes to state 1 and outputs the high voltage input to the first input terminal 401 from the output terminal 400. On the other hand, when the first circuit 110a is in the off state and the second circuit 120a is in the on state, the switch circuit 210 goes to state 2 and outputs the low voltage input to the second input terminal 402 from the output terminal 400. Furthermore, when the first circuit 110a is in the off state and the second circuit 120a is in the off state, the switch circuit 210 goes to state 3 and makes the output terminal 400 float.

[0079] In the first circuit 110a, the control circuit 501 outputs an H level when the first circuit 110a is turned on, and outputs an L level when the first circuit 110a is turned off, as in the second embodiment. When the first circuit 110a is turned off, which is a case in which the breakdown voltage of the transistors can be a problem, the voltages at the terminals of the transistors constituting the first circuit 110a are as follows:

[0080] That is, a high voltage (e.g., 7.5 V) input to the first input terminal 401 is applied to the source of the first transistor 1, a gate voltage Vg1 (e.g., 7.5 V) is applied to the gate of the first transistor 1 from the first gate voltage control unit 10a, and a divided voltage VN1 (e.g., 5 V) is applied to the drain of the first transistor 1 from the first voltage dividing circuit 12a. As a result, the first transistor 1 is maintained in an off state, and a potential difference between any of the terminals does not exceed a withstand voltage (e.g., 3 V).

[0081] Moreover, a divided voltage VN1 (e.g., 5 V) from the first voltage dividing circuit 12a is applied to the source of the second transistor 2, a gate voltage Vg2 (e.g., 5 V) from the second gate voltage control unit 11a is applied to the gate of the second transistor 2, and a divided voltage VN3 (e.g., 2.5 V) from the first voltage dividing circuit 12a is applied to the drain of the second transistor 2. As a result, the second transistor 2 is maintained in an off state, and a potential difference between any of the terminals does not exceed a withstand voltage (e.g., 3 V).

[0082] Moreover, the divided voltage VN3 (e.g., 2.5 V) is applied to the source of the fifth transistor 5 from the first voltage divider circuit 12a, the gate voltage Vg5 (e.g., 2.5 V) is applied to the gate of the fifth transistor 5 from the fifth gate voltage control unit 16, and the drain of the fifth transistor 5 is in a floating state or the output voltage (e.g., 0.5 V) of the second circuit 120a is applied to it. As a result, the fifth transistor 5 is maintained in an off state, and a potential difference between any of the terminals does not exceed a withstand voltage (e.g., 3 V).

[0083] The three control transistors constituting the first gate voltage control unit 10a, the second gate voltage control unit 11a and the fifth gate voltage control unit 16 are also configured to be connected in series between the high voltage (e.g., 7.5 V) input to the first input terminal 401 and the reference voltage terminal 600, so that for each control transistor, the potential difference between any of the terminals does not exceed the withstand voltage (e.g., 3 V).

[0084] In the second circuit 120a, the control circuits 503 and 504 output an H level when the second circuit 120a is turned on, and output an L level when the second circuit 120a is turned off, as in the second embodiment. When the second circuit 120a is in the off state and the first circuit 110a is in the on state, which is a case in which the breakdown voltage of the transistors may be a problem, the voltages at the terminals of the transistors constituting the second circuit 120a are as follows:

[0085] That is, the voltage (e.g., 7.5 V) of the output terminal 400 is applied to the drain of the fourth transistor 4, the gate voltage Vg4 (e.g., 5 V) is applied from the fourth gate voltage control unit 14a to the gate of the fourth transistor 4, and the divided voltage VN2 (e.g., 5 V) is applied from the second voltage dividing circuit 15a to the source of the fourth transistor 4. As a result, the fourth transistor 4 is maintained in the off state, and a potential difference between any of the terminals does not exceed a withstand voltage (e.g., 3 V).

[0086] Moreover, a divided voltage VN2 (e.g., 5 V) is applied to the drain of the sixth transistor 6 from the second voltage divider circuit 15a, a gate voltage Vg6 (e.g., 2.5 V) is applied to the gate of the sixth transistor 6 from the fourth gate voltage control unit 14a, and a divided voltage VN4 (e.g., 2.5 V) is applied to the source of the sixth transistor 6 from the second voltage divider circuit 15a. As a result, the sixth transistor 6 is maintained in an off state, and a potential difference between any of the terminals does not exceed a withstand voltage (e.g., 3 V).

[0087] Moreover, a divided voltage VN4 (e.g., 2.5 V) is applied from the second voltage divider circuit 15a to the drain of the third transistor 3, a gate voltage Vg3 (e.g., 0 V) ​​is applied from the third gate voltage control unit 13 to the gate of the third transistor 3, and a low voltage (e.g., 0.5 V) input to the second input terminal 402 is applied to the source of the third transistor 3. As a result, the third transistor 3 is maintained in an off state, and a potential difference between any of the terminals does not exceed a withstand voltage (e.g., 3 V).

[0088] As described above, in the switch circuit 210 of the present embodiment, compared to the switch circuit 200 of the second embodiment, the first circuit 110a further includes a fifth transistor 5 connected in series with the first transistor 1 and the second transistor 2 between the first input terminal 401 and the output terminal 400, and the first voltage divider circuit 12a further divides the first voltage and supplies it to a common node N3 between the fifth transistor 5 and the first transistor 1 or the second transistor 2.

[0089] As a result, three transistors are connected in series between the first input terminal 401 and the output terminal 400, thereby realizing a switch circuit that can withstand higher voltages and reliably switch between on and off states.

[0090] The second circuit 120a further includes a sixth transistor 6 connected in series with the third transistor 3 and the fourth transistor 4 between the second input terminal 402 and the output terminal 400, and the second voltage divider circuit 15a further divides the voltage of the output terminal 400 and supplies it to a common node N4 between the sixth transistor 6 and the third transistor 3 or the fourth transistor 4.

[0091] As a result, three transistors are connected in series between the second input terminal 402 and the output terminal 400, thereby realizing a switch circuit that has a higher withstand voltage and can reliably selectively output two input voltages.

[0092] In this embodiment, the first circuit 110a is provided with three transistors connected in series between the first input terminal 401 and the output terminal 400, and each of the gate voltage control sections (10a, 11a, 16) is provided with three transistors connected in series, but the number of transistors connected in series is not limited to this and may be four or more. The number may be appropriately determined in consideration of the maximum voltage input to the switch circuit and the withstand voltage of the transistors so that the voltage applied between the terminals of each transistor does not exceed the withstand voltage.

[0093] (Embodiment 4) 7 is a diagram showing a configuration example of an image sensor 70, which is an imaging device according to embodiment 4, equipped with a switch circuit according to any one of embodiments 1 to 3 (in this embodiment, switch circuit 200 according to embodiment 2). Image sensor 70 is a one-chip (i.e., image sensor chip) semiconductor integrated circuit including a semiconductor substrate 71 and circuits located on the semiconductor substrate 71 (i.e., a pixel array 50a including a plurality of pixels 50, two horizontal readout circuits 59a and 59b, a vertical scanning circuit 57, and four switch circuits 200).

[0094] Each pixel 50 is composed of a photoelectric conversion unit 60 and a readout circuit (a circuit composed of a selection transistor 61, a detection transistor 62, and a reset transistor 63). The photoelectric conversion unit 60 is an element capable of varying sensitivity depending on an externally applied voltage, and is, for example, an organic imaging element. The photoelectric conversion unit 60 has a layer structure in which a photoelectric conversion layer is sandwiched between two electrodes (i.e., an upper electrode which is an example of a first electrode layer and a lower electrode which is an example of a second electrode layer) facing each other. The upper electrodes of each pixel 50 are electrically connected to each other and are connected to a sensitivity control voltage line 56. The lower electrodes of each pixel 50 are connected to a charge accumulation node 64 of each pixel. In each pixel 50, the signal charge generated by the photoelectric conversion unit 60 is accumulated in the charge accumulation node 64, and in a pixel in which the selection transistor 61 is in an on state, the charge signal is read out by the detection transistor 62 whose drain is connected to the power line 52. The charge signal read out from the pixel is read out to the outside via a vertical signal line 58 and a horizontal readout circuit 59a or 59b. The sensitivity control voltage line 56 is connected to an output terminal 400 of the switch circuit 200 via a terminal 51. A first input terminal 401 and a second input terminal 402 of the switch circuit 200 are provided as external connection terminals of the image sensor chip, and are connected to a voltage generating circuit outside the image sensor chip.

[0095] The selection transistor 61 is turned on and off by a control signal for each row output from the vertical scanning circuit 57 via the address control line 54. The reset transistor 63 has a drain connected to a reset voltage line 53, and is turned on and off by a control signal for each row output from the vertical scanning circuit 57 via a reset control line 55, thereby resetting the charge storage node 64.

[0096] As shown in Fig. 7, in this embodiment, the image sensor 70 includes four switch circuits 200 according to the second embodiment, and the switch circuits 200 are located at the four corners of the image sensor chip. That is, the semiconductor substrate 71 has a rectangular shape in a plan view. The four switch circuits 200 are located near the four corners of the semiconductor substrate 71 in a plan view. Note that near the four corners means an area close to each of the four corners of the rectangle, and more specifically, a position closer to the corner than the center of each of the four sides constituting the rectangle.

[0097] The required number of switch circuits 200 is not limited to four and may be determined appropriately depending on the pixel array area of ​​the image sensor chip. The switch circuits included in the image sensor 70 are not limited to the switch circuits 200 in the second embodiment and may be the switch circuits 100 in the first embodiment, the switch circuits 210 in the third embodiment, or a mixture of the switch circuits in the first to third embodiments.

[0098] FIG. 8 is a timing chart showing an example of operation of the image sensor 70 shown in FIG. 7. Here, a timing chart showing the relationship between switch control using the switch circuit 200 and exposure and readout of the image sensor chip is shown. In this figure, Vss represents the timing of the fall (or rise) of the vertical synchronization signal, and Hss represents the timing of the fall (or rise) of the horizontal synchronization signal. A waveform indicated by H level V1 and L level V2 represents the voltage applied from the switch circuit 200 to the upper electrode of the photoelectric conversion unit 60. A band-shaped chart shows the exposure state in each row of the pixel array 50a. For simplicity, an example of operation will be described in the case where the pixel array 50a is composed of eight rows (R0 to R7) of pixels 50.

[0099] For example, looking at row R0 in Fig. 8, the white rectangles represent the exposure period, the gray (dotted) rectangles represent the non-exposure period, and the shaded rectangles represent the pixel readout period. It is assumed that the photoelectric conversion unit 60 has a characteristic that the photoelectric conversion sensitivity is high when a high voltage is applied to the upper electrode, and that the photoelectric conversion sensitivity is low when a low voltage is applied. Specifically, it is assumed that photoelectric conversion occurs when V1 = 7V, and that the photoelectric conversion sensitivity is low and almost no photoelectric conversion occurs when V2 = 0.5V.

[0100] The period from time t0 to t1 is called a 1H period, which indicates the period from when a row is selected to when the next row is selected, and the period from t0 to t15 from when a row is selected to when the row is read out again is called a 1V period. In the example of FIG. 8, the 1V period corresponds to one frame. During the 1V period, the image sensor 70 performs exposure and pixel signal readout. For example, during the period from t0 to t7, a high voltage V1 is applied to the photoelectric conversion unit 60. At this time, the photoelectric conversion unit 60 outputs a signal charge proportional to the amount of light incident on the pixel. Next, during the period from t7 to t15, a low voltage V2 is applied to the photoelectric conversion unit 60. At this time, the photoelectric conversion unit 60 hardly performs photoelectric conversion, so the voltage of the charge storage node 64 of each pixel 50 does not change. In other words, t0 to t7 is an exposure period, and t7 to t15 is an exposure stop period, and the exposure of the entire pixel array 50a covered by the photoelectric conversion unit 60 can be controlled. During the exposure stop period, it is possible to sequentially read out the rows R0 to R7, which is a function equivalent to a global shutter. By using the switch circuit 200 of the present disclosure, it is possible to realize an image sensor 70 that switches the sensitivity characteristics of the photoelectric conversion unit 60 without providing an external switch circuit or using high-voltage transistors in the image sensor chip.

[0101] As described above, the image sensor 70 in embodiment 4 includes a semiconductor substrate 71, a pixel array 50a including a plurality of pixels 50 arranged on the semiconductor substrate 71, and a switch circuit 200 located on the semiconductor substrate 71, and each of the plurality of pixels 50 has a photoelectric conversion unit 60 including a first electrode layer, a second electrode layer, and a photoelectric conversion layer sandwiched between the first electrode layer and the second electrode layer, the first electrode layers of each of the plurality of pixels 50 are electrically connected to each other, and the output terminal 400 of the switch circuit 200 is connected to the first electrode layer.

[0102] As a result, a highly reliable switch circuit that uses low-voltage transistors to output a high voltage applies an output voltage to the first electrode layer, thereby realizing a highly reliable image sensor 70 that can change the sensitivity of photoelectric conversion depending on the voltage applied to the photoelectric conversion unit 60.

[0103] Moreover, the image sensor 70 includes a plurality of switch circuits 200, and the output terminal 400 of each of the plurality of switch circuits 200 is connected to the first electrode layer. For example, the image sensor 70 includes four switch circuits 200, the semiconductor substrate 71 has a rectangular shape in a plan view, and the four switch circuits 200 are located near the four corners of the semiconductor substrate 71 in a plan view.

[0104] As a result, voltage is supplied from the switch circuit to four locations on the first electrode layer, thereby suppressing voltage drop in the first electrode layer and suppressing variations in the value and timing of the voltage applied to the photoelectric conversion unit 60 of each pixel 50, resulting in a highly reliable image sensor 70.

[0105] Although the switch circuit and the imaging device according to the present disclosure have been described above based on the first to fourth embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to each embodiment and other forms constructed by combining some of the components in each embodiment are also included within the scope of the present disclosure.

[0106] In the above first to third embodiments, a configuration in which a resistive element is used to generate a divided potential has been exemplified, but a configuration in which a divided potential is generated by control other than that of a resistive element may also be used.

[0107] In the above first to third embodiments, the first circuits 110 and 110a are configured with two or more PMOS transistors connected in series, and the second circuits 120 and 120a are configured with two or more NMOS transistors connected in series, but depending on the input voltage, they may be configured with CMOS type switches using both PMOS and NMOS.

[0108] Moreover, the bias voltage generating circuits 500, 500a, and 502 may output a voltage obtained by dividing the voltage input to the first input terminal 401, or may output a separate voltage inside or outside the SoC.

[0109] Furthermore, all of the numbers used in the description of the above embodiments 1 to 4 are merely examples for specifically explaining the present disclosure, and the present disclosure is not limited to the exemplified numbers.

[0110] In addition, the elements of each of the components shown above are all exemplified to specifically explain the disclosure, and are not limited to the elements exemplified in the present disclosure. In addition, the connection relationships between the components are exemplified to specifically explain the disclosure, and the connection relationships that realize the functions of the present disclosure are not limited to these. [Industrial Applicability]

[0111] The switch circuit according to the present disclosure has the feature of controlling high voltage while ensuring reliability by using low-voltage transistors, and is useful as a switch circuit that selects and outputs multiple voltages. It can also be applied to a voltage-controlled switch of an image sensor that requires high-voltage control such as applying a potential to a photoelectric conversion layer to change the sensitivity. The imaging device according to the present disclosure can be used as a highly reliable image sensor that can change the sensitivity of photoelectric conversion depending on the voltage applied to the photoelectric conversion unit, for example, as an organic image sensor. [Explanation of symbols]

[0112] 1 First transistor 2 Second transistor 3. Third transistor 4 Fourth transistor 5 Fifth transistor 6 6th transistor 10, 10a First gate voltage control section 11, 11a Second gate voltage control section 12, 12a 1st voltage divider circuit 13 Third gate voltage control section 14, 14a Fourth gate voltage control section 15, 15a Second voltage divider circuit 16 5th gate voltage control section N1, N2, N3, N4 common nodes R1, R1a, R2, R2a, R2b, R3, R3a, R4, R4a, R4b, R10, R11, R20, R20a, R20b, R21, R31, R32, R33 Voltage divider resistors 50 pixels 50a Pixel Array 51 Terminal 52 Power line 53 Reset voltage line 54 Address control line 55 Reset control line 56 Sensitivity control voltage line 57 Vertical scanning circuit 58 Vertical signal line 59a, 59b Horizontal readout circuit 60 Photoelectric conversion unit 61 Select transistor 62 Detection transistor 63 Reset Transistor 64 Charge Storage Node 70 Image Sensor 71 Semiconductor Substrate 100, 200, 210 Switch circuit 110, 110a 1st circuit 120, 120a Second Circuit 300, 301, 302, 302a, 303, 303a, 304, 305, 306, 307, 308 control transistor 400 Output terminal 401 First input terminal 402 Second input terminal 500, 500a, 502 Bias voltage generating circuit 501, 503, 504 Control circuit 600 Reference voltage terminal

Claims

1. A first input terminal; An output terminal; a first circuit that switches whether or not a first voltage input to the first input terminal is to be output to the output terminal, The first circuit is a first transistor and a second transistor connected in series between the first input terminal and the output terminal; a first voltage divider circuit that divides a voltage between the first voltage and a reference voltage that is maintained at a predetermined potential and supplies the divided voltage to a first node between the first transistor and the second transistor; Including, When the first transistor and the second transistor are in an off state, the first input terminal is electrically isolated from the output terminal.

2. A second input terminal; a second circuit that switches whether or not a second voltage input to the second input terminal is to be output to the output terminal, The second circuit is a third transistor and a fourth transistor connected in series between the second input terminal and the output terminal; a second voltage dividing circuit that divides the voltage of the output terminal and supplies the divided voltage to a second node between the third transistor and the fourth transistor; The switch circuit of claim 1 , comprising:

3. the first voltage divider circuit includes a first resistor element and a second resistor element connected in series between the first input terminal and the reference voltage; 3. The switch circuit according to claim 1, wherein a connection point between said first resistance element and said second resistance element is connected to said first node.

4. the second voltage dividing circuit includes a third resistor element and a fourth resistor element connected in series between the output terminal and the reference voltage; 3. The switch circuit according to claim 2, wherein a connection point between said third resistor element and said fourth resistor element is connected to said second node.

5. the first voltage exceeding a maximum rating of at least one of the first transistor and the second transistor is input to the first input terminal; the second input terminal is supplied with the second voltage that does not exceed a maximum rating of either the third transistor or the fourth transistor; 5. The switch circuit according to claim 2, wherein the output terminal outputs the first voltage in a first period and outputs the second voltage in a second period different from the first period.

6. the first circuit further includes a fifth transistor connected in series with the first transistor and the second transistor between the first input terminal and the output terminal; the first voltage dividing circuit further divides the first voltage and supplies the divided voltage to a third node between the fifth transistor and the first transistor or the second transistor. The switch circuit according to any one of claims 1 to 5.

7. the second circuit further includes a sixth transistor connected in series with the third transistor and the fourth transistor between the second input terminal and the output terminal; the second voltage dividing circuit further divides the voltage of the output terminal and supplies the divided voltage to a fourth node between the sixth transistor and the third transistor or the fourth transistor.

6. A switch circuit according to claim 2, 4 or 5.

8. A semiconductor substrate; a pixel array including a plurality of pixels arranged on the semiconductor substrate; A switch circuit according to any one of claims 1 to 7 located on the semiconductor substrate, Each of the plurality of pixels has a photoelectric conversion unit including a first electrode layer, a second electrode layer, and a photoelectric conversion layer sandwiched between the first electrode layer and the second electrode layer, the first electrode layers of the plurality of pixels are electrically connected to each other; the output terminal of the switch circuit is connected to the first electrode layer; Imaging device.

9. A plurality of the switch circuits are provided, the output terminal of each of the plurality of switch circuits is connected to the first electrode layer; 9. The imaging device according to claim 8.

10. The switch circuit includes four of the switch circuits, The semiconductor substrate has a rectangular shape in a plan view, the four switch circuits are located near four corners of the semiconductor substrate in the plan view, 10. The imaging device according to claim 8.

Images