Gate drive circuit and semiconductor circuit breaker

Abstract

A gate drive circuit (1) is provided with: an input terminal (T1); a first circuit path (5) inserted into wiring connecting the input terminal (T1) and the gate of a power transistor (2); a second circuit path (6) connected in parallel to the first circuit path (5); and a third circuit path (7) connected in parallel to the second circuit path (6). The first circuit path (5) includes a gate resistor (Rgon). The second circuit path (6) includes a first capacitor (C1) and a first resistor (R1) which are connected in series. The third circuit path (7) includes a second capacitor (C2) and a second resistor (R2) which are connected in series. The capacitance value of the second capacitor (C2) is greater than that of the first capacitor (C1). The resistor value of the second resistor (R2) is greater than that of the first resistor (R1). The resistor value of the gate resistor (Rgon) is greater than that of the second resistor (R2).

Description

[Technical field]

[0001] The present disclosure relates to a gate drive circuit for driving a power transistor and a semiconductor circuit breaker. [Background technology]

[0002] Data centers and communication stations require highly reliable and high-quality systems. In the DC power supply systems used in such systems, power supplied from a host power supply is branched by a current distribution device, and the power is supplied to a large number of loads. This current distribution device is equipped with a protection device for short circuits. Types of protection devices include fuses, MCCBs (Molded-Case Circuit Breakers), and protection devices using semiconductor power transistors (hereinafter referred to as semiconductor circuit breakers). For example, when a semiconductor circuit breaker detects an overcurrent, it controls the gate voltage of the semiconductor power transistor and turns off the semiconductor power transistor to limit the overcurrent.

[0003] A semiconductor power transistor is controlled by a gate drive circuit that supplies a signal to the gate to drive a switching operation. Examples of the gate drive circuit include those disclosed in Patent Documents 1 to 7 and Non-Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 3964833 [Patent Document 2] Patent No. 5925434 [Patent Document 3] Japanese Patent Application Publication No. 10-327059 [Patent Document 4] JP 2010-220325 A [Patent Document 5] JP 2003-284318 A [Patent Document 6] JP 2000-232347 A [Patent Document 7] Japanese Patent Application Publication No. 1-183214 [Non-patent literature]

[0005] [Non-Patent Document 1] "Double-stage Gate Drive Circuit for Parallel Connected IGBT Modules" D. Bortis, P. Steiner, J. Biela and JW Kolar, Published in: IEEE Transactions on Dielectrics and Electrical Insulation ( Volume: 16 , Issue: 4 , August 2009) Summary of the Invention [Problem to be solved by the invention]

[0006] However, when a semiconductor circuit breaker interrupts current at high speed, a surge voltage due to energy stored in the parasitic inductance of the load circuit is applied to the device. If the surge voltage exceeds the withstand voltage, it may destroy the semiconductor circuit breaker. Thus, high-speed current interruption poses the problem of compromising the reliability of the semiconductor circuit breaker.

[0007] Conversely, if the current is interrupted slowly, the mirror period during which the gate voltage of the semiconductor power transistor becomes flat becomes longer. During the mirror period, the drain-source current is not interrupted, so there is a possibility that an overcurrent may damage the semiconductor circuit breaker. Thus, slow current interruption also poses the problem of impairing the reliability of the semiconductor circuit breaker.

[0008] Therefore, an object of the present disclosure is to provide a gate drive circuit and a semiconductor circuit breaker that enhance reliability by suppressing surge voltage and shortening the Miller period. [Means for solving the problem]

[0009] In order to solve the above problems, a gate drive circuit according to one embodiment of the present disclosure includes an input terminal, a first circuit path inserted in a wiring connecting the input terminal and a gate of a power transistor, a second circuit path connected in parallel to the first circuit path, and a third circuit path connected in parallel to the second circuit path, wherein the first circuit path has a gate resistor, the second circuit path has a first capacitance and a first resistance connected in series, and the third circuit path has a second capacitance and a second resistance connected in series, a capacitance value of the second capacitance is larger than the first capacitance, a resistance value of the second resistance is larger than the first resistance, and a resistance value of the gate resistance is larger than the second resistance.

[0010] A semiconductor circuit breaker according to one aspect of the present disclosure includes the above gate drive circuit and the power transistor. Effect of the Invention

[0011] According to the gate drive circuit and semiconductor circuit breaker of the present disclosure, it is possible to improve reliability by suppressing surge voltage and shortening the Miller period. [Brief description of the drawings]

[0012] [Figure 1A] FIG. 1A is a circuit diagram showing a power switching system including a gate drive circuit in a comparative example. [Figure 1B] FIG. 1B is a diagram showing waveforms of a gate-source voltage, a drain-source voltage, and a drain-source current in a gate drive circuit in a comparative example. [Figure 1C] FIG. 1C is a diagram showing characteristics of gate-source voltage and drain-source current versus gate resistance in a comparative example. [Figure 2A] FIG. 2A is a diagram showing a configuration example of a power switching system including a gate drive circuit according to an embodiment. [Figure 2B]FIG. 2B is a waveform diagram showing the gate voltage, the gate current, and the source current in the gate drive circuits according to the comparative example and the embodiment. [Diagram 3] FIG. 3 is a diagram showing an example of the gate charge characteristics of a power transistor when it is turned off. [Figure 4] FIG. 4 is an explanatory diagram showing the state of the gate current in the gate drive circuit according to the embodiment. [Diagram 5] FIG. 5 is a diagram showing experimental results of the gate drive circuits according to the comparative example and the embodiment. [Figure 6] FIG. 6 is a diagram showing other experimental results of the gate drive circuits according to the comparative example and the embodiment. [Figure 7A] FIG. 7A is a diagram showing an example of the configuration of a power switching system including a first modified example of a gate drive circuit according to an embodiment. [Figure 7B] FIG. 7B is a diagram illustrating the operation of the gate drive circuit in the first modified example and the comparative example. [Figure 8A] FIG. 8A is a diagram showing an example of the configuration of a power switching system including a second modified example of a gate drive circuit according to an embodiment. [Figure 8B] FIG. 8B is an explanatory diagram of the operation of a comparative example including a FET as a power transistor. [Figure 8C] FIG. 8C is a diagram illustrating the operation of the gate drive circuit including a FET as a power transistor according to the embodiment. [Figure 9A] FIG. 9A is a diagram showing an example of the configuration of a power switching system including a third modified example of a gate drive circuit according to an embodiment. [Figure 9B] FIG. 9B is an operation explanatory diagram of the third modified example of the gate drive circuit according to the embodiment. [Figure 10] FIG. 10 is a diagram showing an example of the configuration of a power switching system including a fourth modified example of a gate drive circuit according to an embodiment. [Figure 11A] FIG. 11A is a diagram showing an example of the configuration of a power switching system including a fifth modified example of a gate drive circuit according to an embodiment. [Figure 11B] FIG. 11B is an explanatory diagram of the operation of the fifth modified example of the gate drive circuit according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] (How one aspect of the present disclosure was achieved) The present inventors have found that the above problem occurs in the gate drive circuit described in the "Background Art" section. This problem will be described below with reference to Figures 1A to 1C.

[0014] 1A is a circuit diagram showing a power switching system including a gate drive circuit according to a comparative example. The power switching system in the figure includes a load circuit 13, a power transistor 12, and a gate drive circuit 11.

[0015] The load circuit 13 is a schematic equivalent circuit including a diode D0 and a parasitic inductor Ls.

[0016] The power transistor 12 is a power device for power control.

[0017] The gate drive circuit 11 includes a control circuit 14 and a gate resistor Rg.

[0018] The control circuit 14 generates a gate signal, which is a square wave signal for switching the power transistor 12, and supplies the gate of the power transistor 12 via a gate resistor Rg.

[0019] The gate resistor Rg reduces the steep changes in the gate signal. The gate resistor Rg increases the rise time and fall time. In other words, it is a resistor that adjusts the slew rate of the rising edge and the falling edge to be larger.

[0020] FIG. 1B is a diagram showing waveforms of the gate-source voltage Vgs, the drain-source voltage Vds, and the drain-source current Ids in the gate drive circuit in the comparative example. The horizontal axis in the upper and lower parts of the figure is the time axis. The vertical axis in the upper part indicates the gate-source voltage when the power transistor 12 is turned off. Hereinafter, the gate-source voltage Vgs may be simply referred to as the gate voltage Vgs. The vertical axis in the lower part indicates the drain-source voltage Vds and the drain-source current Ids. Hereinafter, the drain-source voltage Vds may be simply referred to as the drain voltage Vds, and the drain-source current Ids may be simply referred to as the drain current Ids. Vth indicates the threshold voltage of the power transistor 12.

[0021] Time t1 is the start point of the fall of the gate signal from the control circuit 14, that is, the start point of turning off the power transistor 12. Time t4 is the end point of turning off. From time t1 to time t4, the gate voltage Vgs does not change monotonically, but a mirror period occurs during which the gate voltage Vgs becomes flat.

[0022] Here, the mirror period will be explained. When the gate voltage Vgs approaches the threshold voltage Vth when the power transistor 12 is turned on or off, a period occurs in which the gate voltage Vgs becomes flat in order to charge and discharge the parasitic capacitance Cgd between the gate and drain (which has an effect larger than the actual capacitance value due to the mirror effect). This is the mirror period. The mirror voltage Vgm is the gate voltage Vgs during this mirror period. The mirror period is the period in which the drain-source voltage Vds changes, and ends when the drain-source voltage Vds reaches its final value.

[0023] As shown in Figure 1B, if the change in current from the end of the Miller period is called the current interruption speed di / dt, the surge voltage caused by the parasitic inductor Ls is proportional to Ls(di / dt). In other words, the magnitude of the surge voltage is proportional to the inductance of the parasitic inductor Ls and to the current interruption speed di / dt. If the surge voltage exceeds the withstand voltage, it may damage the semiconductor circuit breaker, so it is necessary to reduce the current interruption speed di / dt.

[0024] FIG. 1C is a diagram showing the characteristics of the gate-source voltage Vgs and the drain-source current Ids with respect to the magnitude of the gate resistance Rg in the comparative example. The two-dot chain line, dotted line, one-dot chain line, dashed line, and solid line in the diagram correspond to the magnitude of the resistance value of the gate resistance Rg, in that order. As shown in FIG. 1C, when the resistance value of the gate resistance Rg is small, the mirror period is short, and when the resistance value of the gate resistance Rg is large, the mirror period is long. Since the drain current Ids is not cut off during the mirror period, there is a possibility that the semiconductor circuit breaker will be damaged by an overcurrent, so the mirror period needs to be short.

[0025] However, as shown in FIG. 1C, when the resistance value of the gate resistor Rg is small, the current cutoff speed di / dt increases, so there is a trade-off between suppressing the surge voltage and shortening the Miller period.

[0026] Therefore, the present disclosure provides a gate drive circuit and a semiconductor circuit breaker that achieve both suppression of surge voltage and shortening of the Miller period, thereby improving reliability.

[0027] In order to solve this problem, a gate drive circuit according to one embodiment of the present disclosure includes an input terminal, a first circuit path inserted in a wiring connecting the input terminal and a gate of a power transistor, a second circuit path connected in parallel to the first circuit path, and a third circuit path connected in parallel to the second circuit path, wherein the first circuit path has a gate resistor, the second circuit path has a first capacitance and a first resistance connected in series, the third circuit path has a second capacitance and a second resistance connected in series, a capacitance value of the second capacitance is larger than the first capacitance, a resistance value of the second resistance is larger than the first resistance, and a resistance value of the gate resistance is larger than the second resistance.

[0028] This makes it possible to shorten the mirror period and suppress the surge voltage (i.e., reduce the current cutoff speed di / dt), thereby improving the reliability of the power transistor.

[0029] For example, in the process of turning off the power transistor, the second circuit path first quickly discharges a portion of the charge from the gate capacitance of the power transistor 2. This makes it possible to shorten the mirror period.

[0030] For example, following the discharge of the second circuit path, the third circuit path discharges another part of the charge from the gate capacitance at a slower rate than the second circuit path, thereby reducing the current interruption speed and suppressing the surge voltage.

[0031] Incidentally, since the resistance value of the gate resistor of the first circuit path is larger than that of the second resistor, it hardly contributes to the discharge of the power transistor when it is turned off.

[0032] A semiconductor circuit breaker according to one aspect of the present disclosure includes the above gate drive circuit and the power transistor.

[0033] This makes it possible to shorten the mirror period and suppress the surge voltage, thereby improving the reliability of the power transistor.

[0034] Hereinafter, the embodiment will be specifically described with reference to the drawings.

[0035] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection of components, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept are described as optional components.

[0036] (Embodiment) [1. Configuration] 2A is a diagram showing a configuration example of a power switching system including a gate drive circuit according to an embodiment. The power switching system in the figure is, for example, a semiconductor circuit breaker. The power switching system in FIG. 2A includes a load circuit 3, a power transistor 2, and a gate drive circuit 1.

[0037] The load circuit 3 is a schematic equivalent circuit including a diode D0 and a parasitic inductor Ls.

[0038] The power transistor 2 is a power device for power control, and is, for example, a semiconductor switching element having a withstand voltage of several hundred volts. For example, the power transistor 2 may be an IGBT (Insulated Gate Bipolar Transistor), a SiC FET (Field Effect Transistor), or a Gallium Nitride (GaN) transistor. The power transistor 2 may have a P-type gate structure, may be a GaN bidirectional switch with a P-type dual gate structure, or may be a MOSFET.

[0039] The gate drive circuit 1 drives the power transistor 2 by charging and discharging the gate capacitance of the power transistor 2. To this end, the gate drive circuit 1 includes an input terminal T1, a control circuit 4, a first circuit path 5, a second circuit path 6, and a third circuit path 7. The gate capacitance of the power transistor 2 also includes parasitic capacitance such as a gate-drain parasitic capacitance.

[0040] The control circuit 4 generates a gate signal, which is a rectangular wave signal for switching the power transistor 2, and supplies the gate signal to the gate of the power transistor 2 via an input terminal T1 and a parallel circuit of a first circuit path 5, a second circuit path 6, and a third circuit path 7.

[0041] The first circuit path 5 is inserted into the wiring that connects the input terminal T1 and the gate of the power transistor 2. The first circuit path 5 has a diode D1 and a gate resistor Rgon that are connected in series. The first circuit path 5 mainly contributes to turning on and turning on the power transistor 2, and hardly contributes to turning off the power transistor 2.

[0042] The second circuit path 6 is connected in parallel to the first circuit path 5. The second circuit path 6 has a first capacitance C1 and a first resistance R1 connected in series. The second circuit path 6 has a lower capacitance and a lower resistance than the third circuit path 7. Since the first resistance R1 is low resistance, the second circuit path 6 first discharges a part of the charge from the gate capacitance of the power transistor 2 faster than the third circuit path 7 in the process of turning off the power transistor 2. The high-speed discharge of the second circuit path 6 can shorten the mirror period. In addition, the amount of charge of the high-speed discharge can be limited by appropriately setting the capacitance value of the first capacitance C1. For example, the second circuit path 6 discharges a first amount of charge from the gate capacitance of the power transistor 2 in the process of turning off the power transistor 2. This first amount of charge is set to be smaller than a second amount of charge discharged from the gate capacitance of the power transistor 2 from the start of turning off the power transistor 2 until the mirror period of the power transistor 2 is completed.

[0043] The third circuit path 7 is connected in parallel to the second circuit path 6. The third circuit path 7 has a second capacitance C2 and a second resistance R2 connected in series. Here, the capacitance value of the second capacitance C2 is larger than the first capacitance C1. The resistance value of the second resistance R2 is larger than the first resistance R1. Also, the resistance value of the gate resistance Rgon is larger than the second resistance R2. In the process of turning off the power transistor 2, the third circuit path 7 discharges another part of the charge from the gate capacitance, following the discharge of the second circuit path 6, at a slower speed than the second circuit path 6. This reduces the current interruption speed di / dt, thereby suppressing the surge voltage.

[0044] Next, a signal waveform during the process of turning off the power transistor 2 will be described.

[0045] 2B is a waveform diagram showing the gate voltage Vgs, the gate current iG, and the source current Ids in the gate drive circuits according to the comparative example and the embodiment. The comparative example column (a) in FIG. 2B corresponds to the gate drive circuit 11 in FIG. 1A. The embodiment column (b) in FIG. 2B corresponds to the gate drive circuit 1 in FIG. 2A.

[0046] 2B(a) and (b), time t1 indicates the start point of turn-off, and time t5 indicates the end point of turn-off. The period from time t2 to time t3 indicates the Miller period. Time t4 indicates the time when the gate voltage Vgs reaches the threshold voltage Vth. In other words, the power transistor 2 is turned off after time t4.

[0047] As shown in Fig. 2B(b), the gate drive circuit 1 according to this embodiment has a shorter mirror period and a smaller current interruption speed di / dt than the gate drive circuit 11 of the comparative example in Fig. 1A. The smaller current interruption speed di / dt means that surge voltage is suppressed.

[0048] The second circuit path 6 contributes to the shortening of the mirror period. For example, the capacitance value of the first capacitance C1 of the second circuit path 6 is set to a value that absorbs the charge discharged by the gate capacitance from the start of turn-off at time t1 until the end of the mirror period at time t3. In addition, the first resistor R1 is set to a relatively small resistance value that allows high-speed movement of charge. As a result, the second circuit path 6 quickly discharges the gate capacitance from the start of turn-off at time t1 until the end of the mirror period. In this way, the mirror period is shortened.

[0049] The above "before the mirror period is completed" may be "before time t3 when the gate voltage Vgs reaches the threshold voltage Vth".

[0050] Furthermore, at time t3 or after the second circuit path 6 has finished discharging, the third circuit path 7 discharges the gate capacitance at a low speed. At time t4, when the gate voltage Vgs falls below the threshold voltage within the period from time t3 to time t5, the gate capacitance is discharged at a low speed, and the change in the drain current Ids is mitigated. This reduces the current interruption speed di / dt, making it possible to suppress the surge voltage.

[0051] 3 is a diagram showing an example of the gate charge characteristic of the power transistor 2 at the time of turning off. The horizontal axis of the diagram represents time, and the vertical axis represents the gate voltage Vg.

[0052] The amount of charge Qg(ON) stored in the gate capacitance when the power transistor 2 is in the ON state is expressed by the following equation. Qg(ON) = Qgs1 + Qgd + Qgs2

[0053] Here, Qgs1 denotes the parasitic capacitance between the gate and source corresponding to a gate voltage smaller than the threshold, Qgd denotes the parasitic capacitance between the gate and drain, and Qgs2 denotes the parasitic capacitance between the gate and source corresponding to a gate voltage larger than the threshold.

[0054] The capacitance value of the first capacitor C1 is set to satisfy the following formula. C1<(Qgs2+Qgd)

[0055] More precisely, the first capacitance C1 is set to satisfy the following equation: C1(Vg(t1)-Vg(t2))<(Qgs2+Qgd)

[0056] Here, Vg(t1) indicates the gate voltage at time t1 in FIG. 3. Vg(t2) indicates the gate voltage at time t2 in FIG. 3. The left side of this equation indicates the charge amount indicated by the product of the difference between the gate voltage Vg at time t1 and the gate voltage Vg at time t2 and the first charge amount C1. The first capacitance C1 is set so that the charge amount indicated on the left side is smaller than (Qgs2+Qgd) on the right side. This allows the high-speed discharge by the first capacitance C1 and the first resistor R1 to end before the mirror period ends.

[0057] That is, the amount of charge stored in the first capacitance C1 when the power transistor 2 is in the on state is set to be equal to or less than (Qgs2+Qgd) of the amount of charge Qg of the gate capacitance of the power transistor 2. As a result, after the start of turn-off, the gate charge of the power transistor 2 can be discharged at high speed by the low-resistance second circuit path 6 until the middle of the mirror period, and the mirror period can be shortened.

[0058] The amount of charge Q(C1_ON) stored in the first capacitance C1 when the power transistor 2 is in the on state is defined by the following equation. Q(C1_ON) = Capacitance value of C1 × (Vdd-Vgs(ON))

[0059] Here, Vdd is the gate drive power supply voltage, and Vgs(ON) is the gate-source voltage when the power transistor 2 is on.

[0060] The capacitance value of the second capacitor C2 is set to satisfy the following formula. C2>(Qgs1+Qgd+Qgs2)

[0061] That is, the capacitance value of the second capacitor C2 is set to be larger than the charge amount Qg(ON) = Qgs1 + Qgd + Qgs2 of the gate capacitance when the power transistor 2 is in the on state.

[0062] More precisely, the second capacitor C2 is set to satisfy the following equation. C2(Vg(t1) - Vg(t5)) < (Qgs1 + Qgd + Qgs2)

[0063] Here, Vg(t1) represents the gate voltage at time t1 in FIG. 3. Vg(t5) represents the gate voltage at time t5 in FIG. 3.

[0064] After the first capacitor C1 absorbs the charge amount of Q(C1_ON) during the turn-off process, the voltage across the first capacitor C1 becomes smaller, and the current flowing through the first capacitor C1 becomes smaller than the current flowing through the second capacitor C2. The current flowing through the second capacitor C2 can be adjusted by the magnitude of the second resistor R2, and the current cut-off speed di / dt can be adjusted.

[0065] Also, the gate resistor Rgon is necessary to determine the gate voltage during on-state when the power transistor 2 has a p-type gate. However, the gate resistor Rgon needs to be larger than the second resistor R2. This is because if the gate resistor Rgon is smaller than the second resistor R2, it becomes complicated or difficult to adjust the current cut-off speed di / dt according to the resistance value of the second resistor R2.

[0066] Also, when the power transistor 2 is off, the diode D1 can make the gate resistor Rgon non-conductive, and the current cut-off speed di / dt can be easily adjusted by the second resistor R2.

[0067] In addition, in FIG. 2A, instead of satisfying C1 < C2 and R1 < R2, it may be set to satisfy C1×R1 < C2×R2. Here, C1×R1 is the time constant of the second circuit path 6, and C2×R2 is the time constant of the third circuit path 7.

[0068] [2. Operation] Next, the operation of the gate drive circuit 1 will be described.

[0069] FIG. 4 is an explanatory diagram showing the gate current in the gate drive circuit 1 according to the embodiment. FIG. 4(a) shows the gate current immediately after the power transistor 2 starts to turn on. The thick arrows in the figure show the main gate current paths. The dotted arrows show the gate current paths with smaller current amounts than the thick arrows. Immediately after the start of turn on, most of the gate current passes through the second circuit path 6 to charge the gate capacitance of the power transistor 2. At the same time, a part of the gate current passes through the first circuit path 5 and the third circuit path 7 to charge the gate capacitance of the power transistor 2.

[0070] 4(b) shows the steady on-state of the power transistor 2. When the power transistor 2 is in the on-state, the main gate current can be supplied to the gate through the first circuit path 5. At this time, the second circuit path 6 and the third circuit path 7 do not pass DC gate current.

[0071] FIG. 4(c) shows the gate current immediately after the power transistor 2 starts turning off, for example, from time t1 to time t3 in FIG. 2B(b). Immediately after the power transistor 2 starts turning off, most of the gate current flows through the first resistor R1 and the first capacitor C1 in the second circuit path 6, and a small part of the gate current flows through the second resistor R2 and the second capacitor C2 in the third circuit path 7. This is because the resistance value of the first resistor R1 is smaller than that of the second resistor R2. The gate current indicated by the thick arrow discharges the gate capacitance at high speed, so that the mirror period can be shortened. In addition, the gate current indicated by the thick arrow stops flowing when the first capacitor C1 becomes full. The capacitance value of the first capacitor C1 is set to be full before time t3 in FIG. 2B(b), that is, at the completion or midway point of the mirror period.

[0072] FIG. 4(d) shows the gate current in the period following (c). In FIG. 4(d), the mirror period is completed, so the gate voltage decreases as the gate capacitance is discharged. At this time, the first capacitance C1 is full, so no gate current flows through the second circuit path 6. The main gate current flows through the second resistor R2 and second capacitance C2 in the third circuit path 7. Since the resistance value of the second resistor R2 is larger than the first resistor R1, the gate current flowing through the third circuit path 7 is limited compared to (c). This reduces the current interruption speed di / dt and suppresses the surge voltage.

[0073] [3. Experimental Results] Next, the results of an experiment simulating the operation of the gate drive circuit 1 according to the embodiment will be described.

[0074] Fig. 5 shows experimental results of the gate drive circuit 1 according to the comparative example and the embodiment. Fig. 5(b) shows the gate drive circuit 1 shown in Fig. 2A. In contrast, Fig. 5(a) shows, as a comparative example, a configuration in which the second circuit path 6 is deleted from the gate drive circuit 1 of Fig. 5(b). The deleted second circuit path 6 is made up of a first capacitance C1 and a first resistance R1, and is a circuit for quickly discharging the gate capacitance of the power transistor 2 in the process of turning off the power transistor 2.

[0075] The constants of each circuit element in (a) and (b) of Figure 5 are set as follows: The gate resistance Rgon in the first circuit path 5 is set to 330 Ω. The first capacitance C1 in the second circuit path 6 is set to 2 nF, and the first resistance R1 is set to 10 Ω. The second capacitance C2 in the third circuit path 7 is set to 4.7 nF, and the second resistance R2 is set to 4.7 kΩ. The power transistor 2 in the experiment of Figure 5 is a GaN bidirectional switch with a P-type dual gate structure.

[0076] The waveforms on the right side of FIGS. 5(a) and (b) show the gate voltage Vg1, the drain-source current Is, and the drain-source voltage Vs2s1 as simulated experimental results.

[0077] The mirror period from the start of turn-off at time t1 to time t2a in the comparative example of Fig. 5(a) is 20 μs, whereas the mirror period from the start of turn-off at time t1 to time t2b in the gate drive circuit 1 of the embodiment of Fig. 5(b) is 5 μs.

[0078] It was confirmed that the second circuit path 6 in Fig. 5(b) has the effect of shortening the mirror period to 1 / 4 compared to Fig. 5(a). In addition, as shown in the waveform in Fig. 5(b), shortening the mirror period suppresses the amount of drain-source current Is during the mirror period, and also suppresses the drain-source voltage Vs2s1. In other words, it suppresses the possibility that an overcurrent of the drain-source current Is during the mirror period will destroy the power transistor 2.

[0079] Further, the results of other experiments simulating the operation of the gate drive circuit 1 according to the embodiment will be described.

[0080] FIG. 6 is a diagram showing other experimental results of the gate drive circuit according to the comparative example and the embodiment. The circuit configurations in (b) and (a) of FIG. 6 are the same as those in (b) and (a) of FIG. 5. However, the constants of each circuit element in FIG. 6 are different from those in FIG. 5. The constants of each circuit element in (a) and (b) of FIG. 6 are set as follows. The gate resistance Rgon in the first circuit path 5 is set to 330 Ω. The first capacitance C1 in the second circuit path 6 is set to 1.5 nF, and the first resistance R1 is set to 7.5 Ω. The second capacitance C2 in the third circuit path 7 is set to 4.7 nF, and the second resistance R2 is set to 2.2 kΩ. The power transistor 2 in the experiment in FIG. 6 is a GaN bidirectional switch with a P-type dual gate structure, as in FIG. 5.

[0081] The mirror period in FIG. 6(b) is shortened to about 1 / 4 of that in FIG. 6(a).

[0082] Also, the drain-source current Is is 8 A at the start of the mirror period in FIG. 6(a) and increases to 18 A at the end of the mirror period. In contrast, the drain-source current Is is 8 A at the start of the mirror period in FIG. 6(b) and 9 A at the end of the mirror period, so the increase is small. Thus, in FIG. 6(b), the shortening of the mirror period significantly reduces the amount of drain-source current Is during the mirror period. In other words, the possibility that an overcurrent of the drain-source current Is during the mirror period will destroy the power transistor 2 is significantly reduced.

[0083] [First Modification] Next, a first modified example of the gate drive circuit 1 will be described.

[0084] Fig. 7A is a diagram showing a configuration example of a power switching system including a first modified example of a gate drive circuit according to an embodiment. Fig. 7A is different from Fig. 2A in that the diode D1 in the first circuit path 5 is deleted. Below, the following description will focus on the differences, avoiding duplication of explanation of the same points.

[0085] Since the diode D1 is deleted, the first circuit path 5 passes a gate current due to the discharge of the gate capacitance of the power transistor 2 in the turn-off process. However, since the resistance value of the gate resistor Rgon is sufficiently larger than the second resistor R2, the gate current flowing in the first circuit path 5 may be ignored compared to the gate current flowing in the second circuit path 6. Therefore, the gate drive circuit 1 in the first modification of FIG. 7A can also obtain the same action and effect as that of FIG. 2A.

[0086] Furthermore, an example of the operation of the gate drive circuit 1 in one modified example will be described.

[0087] FIG. 7B is an explanatory diagram of the operation of the gate drive circuit in the first modified example and the comparative example. FIG. 7B (a) shows the gate voltage Vg and gate current Ig at the start of turning off the gate drive circuit 1 in the first modified example (i.e., at the end of the on-state). FIG. 7B (b) and (c) correspond to the period of slow gate capacitance discharge by the third circuit path 7. That is, FIG. 7B (b) shows the gate voltage Vg and gate current Ig immediately after the high-speed discharge by the second circuit path 6 is completed. FIG. 7B (c) shows the gate voltage Vg and gate current Ig during the period of slow discharge by the third circuit path 7. Note that Ig@R2 in FIG. 7B means the gate current Ig flowing through the second resistor R2.

[0088] Moreover, the comparative example of FIG. 7B is premised on a circuit example in which the second capacitance C2 is deleted from the gate drive circuit 1 in the first modified example of FIG. 7A. (a1) of FIG. 7B shows the gate voltage Vg and gate current Ig at the start of turn-off of the gate drive circuit in the comparative example (i.e., at the end of the on-state). (b1) and (c1) of FIG. 7B correspond to the period of slow discharge of the gate capacitance by the second resistor R2. That is, (b1) of FIG. 7B shows the gate voltage Vg and gate current Ig immediately after the completion of fast discharge by the second circuit path 6. (c1) of FIG. 7B shows the gate voltage Vg and gate current Ig during the period of slow discharge by the third circuit path 7.

[0089] In the slow discharge period (period from (b) to (c)) of the first modified example, the gate current Ig@R2 changes from 11V / R2 to 10V / R2. That is, the rate of change of Ig is about 9 percent. That is, the current interruption speed di / dt is relatively small. This makes it possible to suppress the surge voltage and the possibility of destruction of the power transistor 2.

[0090] In contrast, in the comparative example, during the slow discharge period (the period from (b1) to (c1)), the gate current Ig@R2 changes from 2V / R2 to 1V / R2. In other words, the rate of change of Ig is about 50 percent. In other words, the current cutoff speed di / dt is relatively large. As a result, the effect of suppressing the surge voltage is small, and the effect of suppressing the possibility of destruction of the power transistor 2 is also small.

[0091] [Second modified example] Next, a second modification of the gate drive circuit 1 will be described.

[0092] Fig. 8A is a diagram showing a configuration example of a power switching system including a second modified example of a gate drive circuit according to an embodiment. Fig. 8A is different from Fig. 7A in that the power transistor 2 is a MOSFET. That is, the power transistor 2 in Fig. 8A is not a GIT (Gate Insulated Transistor) whose gate portion is a diode, but an insulated gate MOSFET. In this case, the gate voltage when the power transistor 2 is in an on state rises to the voltage of the input terminal T1 in Fig. 8A because there is a gate resistor Rgon.

[0093] If the gate resistor Rgon does not exist as in Fig. 8B, the gate voltage of the power transistor 2 in the on state becomes a voltage value obtained by dividing the voltage of the input terminal T1 depending on the capacitance ratio between the first capacitance C1, the second capacitance C2 and the gate capacitance. Fig. 8B shows an example in which the gate voltage is 6V as a result of dividing 12V of the input terminal T1.

[0094] If the diode D1 is connected in series to the gate resistor Rgon as in Figure 8C, there is no discharge path for the charge stored in the gate capacitance, so the gate voltage Vg of the MOSFET cannot reach zero. However, if there is no second capacitance C2 in Figure 8C, the charge of the gate capacitance can be discharged.

[0095] Therefore, when the power transistor 2 is a MOSFET, the configuration of FIG. 8A and the configuration of FIG. 8C without the second capacitor C2 are suitable.

[0096] In the case of a p-type gate such as bidirectional GaN, the gate itself is a pn diode, and the gate charge can naturally be discharged through the on diode, so the configuration of FIG. 8C is also suitable.

[0097] [Third Modification] Next, a third modification of the gate drive circuit 1 will be described.

[0098] 9A is a diagram showing a configuration example of a power switching system including a third modified example of a gate drive circuit according to an embodiment. Compared to FIG. 2A, FIG. 9A is different in that a diode D2 is provided instead of the first resistor R1. The following mainly describes the difference.

[0099] The diode D2 is provided in place of the low resistance first resistor R1 for fast discharge and, like the first resistor R1, enables fast discharge at turn-off.

[0100] Furthermore, according to the third modification, ringing of the source current and gate voltage occurring at the time of turn-on can be suppressed. Also, in the third modification, by providing the diode D2, almost no current flows from the first capacitance C1 to charge the gate capacitance during the turn-on process, and the gate current during the turn-on process flows through the diode D1 and the gate resistor Rgon. By setting the resistance value of the gate resistor Rgon, the turn-on speed can be adjusted independently of the current cut-off speed di / dt at the time of turn-off.

[0101] In addition, the main path of the gate current during the turn-on process is the one with the smaller resistance between the second resistor R2 and the gate resistor Rgon. Note that the diode D2 itself has a capacitance, so a current flows through it momentarily, but this capacitance is usually small compared to the first capacitor C1 and can be ignored.

[0102] FIG. 9B is an explanatory diagram of the operation of a third modified example of the gate drive circuit according to the embodiment. FIG. 9B shows the waveforms of the gate voltage Vgs, the drain voltage Vds, and the drain current Ids during the turn-on process of the power transistor 2. In the third modified example, a diode D2 is provided instead of the first resistor R1, so that high-speed charging of the gate capacitance by the first capacitance C1 and the first resistor R1 at the time of turn-on is prohibited. This makes it easy to adjust the turn-on speed by setting the resistance value of the gate resistor Rgon.

[0103] [Fourth Variation] Next, a fourth modification of the gate drive circuit 1 will be described.

[0104] Fig. 10 is a diagram showing a configuration example of a power switching system including a fourth modified example of a gate drive circuit according to an embodiment. Fig. 10 is different from Fig. 2A in that the second capacitor C2 is deleted. The following mainly describes the differences.

[0105] The third circuit path 7 does not have the second capacitance C2 and is composed of the second resistor R2. The gate current can be constantly conducted between the input terminal T1 and the gate without being subjected to the DC blocking action of the second capacitance C2. The third circuit path 7 can discharge the gate charge without leaving it in the off state of the power transistor 2. Therefore, the gate drive circuit 1 of FIG. 10 is suitable for the case where the power transistor 2 is, for example, a MOSFET having an insulated gate. As in FIG. 10, even without the second capacitance C2, it is possible to shorten the mirror period and reduce the current blocking speed di / dt in the same way as in FIG. 2A.

[0106] [Fifth Modification] Next, a fifth modification of the gate drive circuit 1 will be described.

[0107] Fig. 11A is a diagram showing a configuration example of a power switching system including a fifth modified example of a gate drive circuit according to an embodiment, and Fig. 11B is a diagram illustrating the operation of the fifth modified example of a gate drive circuit according to an embodiment.

[0108] FIG. 11A is different from FIG. 2A in that the fourth circuit path 8 is added. Hereinafter, the description will focus on the differences.

[0109] The fourth circuit path 8 is connected in parallel with the third circuit path 7. The fourth circuit path 8 has a third capacitor C3 and a third resistor R3 connected in series. Here, the capacitance value of the third capacitor C3 is larger than that of the second capacitor C2. The resistance value of the third resistor R3 is larger than that of the second resistor R2.

[0110] In the operation example of FIG. 11B, the second circuit path 6 mainly discharges the gate capacitance at the highest speed from the start of turn-off to the beginning of the mirror period. The third circuit path 7 mainly discharges the gate capacitance at high speed during the mirror period. The fourth circuit path 8 mainly discharges the gate capacitance at low speed from the end of the mirror period to the completion of turn-off. Therefore, the capacitance value and the resistance value only need to satisfy the following formula.

[0111] C1 < C2 < C3 R1 < R2 < R3 < Rgon

[0112] Thereby, in the process of turn-off, the main gate current flows through the first capacitor C1, the second capacitor C2, and the third capacitor C3 in this order, and is cut off in this order when it becomes full. Even when the mirror period cannot be sufficiently shortened only by the first capacitor C1, it can be sufficiently shortened or adjusted by the second capacitor C2. The current cut-off rate di / dt after the mirror period can be easily adjusted by the third capacitor C3.

[0113] Note that in FIG. 11A, instead of satisfying C1 < C2 < C3 and R1 < R2 < R3, it may be made to satisfy C1×R1 < C2×R2 < C3×R3. Here, C1×R1 is the time constant of the second circuit path 6, C2×R2 is the time constant of the third circuit path 7, and C3×R3 is the time constant of the fourth circuit path 8.

[0114] As described above, the gate drive circuit 1 according to one aspect of the embodiment includes an input terminal T1, a first circuit path 5 inserted in a wiring connecting the input terminal T1 and the gate of the power transistor 2, a second circuit path 6 connected in parallel to the first circuit path 5, and a third circuit path 7 connected in parallel to the second circuit path 6, where the first circuit path 5 has a gate resistance Rgon, the second circuit path 6 has a first capacitance C1 and a first resistance R1 connected in series, and the third circuit path 7 has a second capacitance C2 and a second resistance R2 connected in series, where the capacitance value of the second capacitance C2 is larger than the first capacitance C1, the resistance value of the second resistance R2 is larger than the first resistance R1, and the resistance value of the gate resistance Rgon is larger than the second resistance R2.

[0115] This makes it possible to shorten the mirror period and suppress the surge voltage (that is, to reduce the current cutoff speed di / dt), thereby improving the reliability of the power transistor 2.

[0116] Here, the second circuit path 6 may discharge a portion of the charge from the gate capacitance of the power transistor 2 in the process of turning off the power transistor 2, and the third circuit path 7 may discharge another portion of the charge from the gate capacitance following the discharge by the second circuit path 6 at a slower speed than the second circuit path 6.

[0117] According to this, the mirror period can be shortened by high-speed discharge through the second circuit path 6. The current interruption speed di / dt is reduced by low-speed discharge through the third circuit path 7, so that the surge voltage can be suppressed.

[0118] Here, the second circuit path 6 discharges a first amount of charge from the gate capacitance of the power transistor 2 in the process of turning off the power transistor 2, and the first amount of charge may be set to be smaller than a second amount of charge discharged from the gate capacitance of the power transistor 2 from the start of turning off the power transistor 2 to the completion of the mirror period of the power transistor 2.

[0119] This makes it possible to set the period during which high-speed discharge by the second circuit path 6 is performed within the range of the mirror period.

[0120] Here, the first circuit path 5 includes a diode D1 connected in series to the gate resistor Rgon, and the forward direction of the diode D1 may be from the input terminal toward the gate of the power transistor.

[0121] According to this, since the resistance value of the gate resistor Rgon of the first circuit path 5 is larger than that of the second resistor R2, it hardly contributes to the discharge at the turn-off of the power transistor 2. Therefore, the operation setting or adjustment at the turn-off can be performed exclusively in the second circuit path 6 and the third circuit path 7.

[0122] Here, the circuit further includes a fourth circuit path 8 connected in parallel to the third circuit path 7, and the fourth circuit path 8 has a third capacitance C3 and a third resistor R3 connected in series, and the capacitance value of the third capacitance C3 may be greater than the second capacitance C2, and the resistance value of the third resistor R3 may be greater than the second resistor R2.

[0123] According to this, for example, the shortening of the mirror period can be easily adjusted by the third circuit path 7, and the current interruption speed di / dt can be easily adjusted by the fourth circuit path 8.

[0124] Here, the power transistor 2 may have a P-type gate structure.

[0125] Here, the power transistor 2 may be a GaN bidirectional switch with a P-type dual gate structure.

[0126] Here, the power transistor 2 may be a MOSFET.

[0127] Moreover, a gate drive circuit 1 according to one aspect of the embodiment includes an input terminal T1, a first circuit path 5 inserted in a wiring connecting the input terminal T1 and the gate of the power transistor 2, a second circuit path 6 connected in parallel to the first circuit path 5, and a third circuit path 7 connected in parallel to the second circuit path 6, where the first circuit path 5 has a gate resistance Rgon, the second circuit path 6 has a first capacitance C1 and a diode D2 connected in series, and the third circuit path 7 has a second capacitance C2 and a second resistance R2 connected in series, where the capacitance value of the second capacitance C2 is larger than the first capacitance C1 and the resistance value of the gate resistance Rgon is larger than the second resistance R2.

[0128] This makes it possible to shorten the mirror period and suppress the surge voltage (that is, to reduce the current cutoff speed di / dt), thereby improving the reliability of the power transistor 2.

[0129] Here, the second circuit path 6 may be set to discharge a first amount of charge from the gate capacitance of the power transistor 2 during the process of turning off the power transistor 2, and the first amount of charge may be set to be smaller than a second amount of charge discharged from the gate capacitance of the power transistor 2 from the start of turning off the power transistor 2 to the completion of the mirror period of the power transistor 2.

[0130] This makes it possible to set the period during which high-speed discharge by the second circuit path 6 is performed within the range of the mirror period.

[0131] Here, the first circuit path 5 may comprise a diode D1 connected in series with a gate resistor Rgon.

[0132] According to this, since the resistance value of the gate resistor Rgon of the first circuit path 5 is larger than that of the second resistor R2, it hardly contributes to the discharge at the turn-off of the power transistor 2. Therefore, the operation setting or adjustment at the turn-off can be performed exclusively in the second circuit path 6 and the third circuit path 7.

[0133] Here, the forward direction of the diode D1 in the first circuit path 5 may be the direction from the input terminal T1 to the gate of the power transistor, and the forward direction of the diode D2 in the second circuit path 6 may be the direction from the gate of the power transistor to the input terminal T1.

[0134] Moreover, a gate drive circuit 1 according to one aspect of the embodiment includes an input terminal T1, a first circuit path 5 inserted in a wiring connecting the input terminal T1 and the gate of the power transistor 2, a second circuit path 6 connected in parallel to the first circuit path 5, and a third circuit path 7 connected in parallel to the second circuit path 6, where the first circuit path 5 has a diode D1 and a gate resistor Rgon connected in series, the second circuit path 6 has a first capacitance C1 and a first resistor R1 connected in series, and the third circuit path 7 has a second resistor R2, where the resistance value of the second resistor R2 is larger than the first resistor R1, and the resistance value of the gate resistor Rgon is larger than the second resistor R2.

[0135] This makes it possible to shorten the mirror period and suppress the surge voltage (that is, to reduce the current cutoff speed di / dt), thereby improving the reliability of the power transistor 2.

[0136] Here, the second circuit path 6 discharges a first amount of charge from the gate capacitance of the power transistor 2 in the process of turning off the power transistor 2, and the first amount of charge may be set to be smaller than a second amount of charge discharged from the gate capacitance of the power transistor 2 from the start of turning off the power transistor 2 to the completion of the mirror period of the power transistor 2.

[0137] This makes it possible to set the period during which high-speed discharge by the second circuit path 6 is performed within the range of the mirror period.

[0138] Moreover, a semiconductor circuit breaker according to an aspect of the embodiment includes the above-mentioned gate drive circuit 1 and a power transistor 2.

[0139] This makes it possible to shorten the mirror period and suppress the surge voltage (that is, to reduce the current cutoff speed di / dt), thereby improving the reliability of the power transistor 2.

[0140] Although the gate drive circuit according to one or more aspects has been described based on the embodiment, the present disclosure is not limited to this embodiment. As long as it does not deviate from the gist of the present disclosure, various modifications conceived by a person skilled in the art to this embodiment and forms constructed by combining components in different embodiments may also be included within the scope of one or more aspects. [Industrial Applicability]

[0141] The gate drive circuit and semiconductor circuit breaker according to the present disclosure can be used, for example, in a power switching system. [Explanation of symbols]

[0142] 1 Gate drive circuit 2. Power transistor 3 Load circuit 4 Control circuit 5 First Circuit Path 6 Second Circuit Path 7. 3rd Circuit Pass 8 4th Circuit Pass C1 1st capacity C2 2nd capacity C3 3rd capacity D1, D2 Diodes R1 First resistor R2 2nd resistor R3 3rd resistor Rgon Gate resistance T1 input terminal

Claims

1. An input terminal; a first circuit path inserted in a wiring that connects the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; a third circuit path connected in parallel to the second circuit path, the first circuit path includes a gate resistor; the second circuit path includes a first capacitance and a first resistance connected in series; the third circuit path includes a second capacitance and a second resistance connected in series; the capacitance value of the second capacitance is greater than the capacitance of the first capacitance; the second resistor has a resistance greater than that of the first resistor; The resistance value of the gate resistor is greater than the second resistor. Gate drive circuit.

2. the second circuit path discharges a portion of charge from a gate capacitance of the power transistor during a process of turning off the power transistor; The third circuit path discharges another part of the charge from the gate capacitance at a slower rate than the second circuit path following the discharge of the second circuit path.

2. The gate drive circuit of claim 1.

3. the second circuit path discharges a first amount of charge from a gate capacitance of the power transistor during a turn-off process of the power transistor; The first charge amount is set to be smaller than a second charge amount discharged from the gate capacitance of the power transistor from the start of turn-off of the power transistor until the completion of the mirror period of the power transistor.

3. The gate drive circuit according to claim 1 or 2.

4. the first circuit path comprises a diode connected in series with the gate resistor; The forward direction of the diode is from the input terminal to the gate of the power transistor.

4. A gate drive circuit according to claim 1.

5. further comprising a fourth circuit path connected in parallel to the third circuit path; the fourth circuit path includes a third capacitance and a third resistance connected in series; the capacitance value of the third capacitance is greater than the capacitance of the second capacitance; The resistance value of the third resistor is greater than the resistance value of the second resistor.

5. A gate drive circuit according to claim 1.

6. The power transistor has a P-type gate structure.

6. A gate drive circuit according to claim 1.

7. The power transistor is a GaN bidirectional switch with a P-type dual gate structure.

6. A gate drive circuit according to claim 1.

8. The power transistor is a MOSFET.

6. A gate drive circuit according to claim 1.

9. An input terminal; a first circuit path inserted in a wiring that connects the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; a third circuit path connected in parallel to the second circuit path, the first circuit path includes a gate resistor; the second circuit path includes a first capacitance and a diode connected in series; the third circuit path includes a second capacitance and a second resistance connected in series; the capacitance value of the second capacitance is greater than the capacitance of the first capacitance; the resistance value of the gate resistor is greater than the second resistance; The forward direction of the diode in the second circuit path is from the gate of the power transistor to the input terminal. Gate drive circuit.

10. the second circuit path discharges a first amount of charge from a gate capacitance of the power transistor during a turn-off process of the power transistor; The first charge amount is set to be smaller than a second charge amount discharged from the gate capacitance of the power transistor from the start of turn-off of the power transistor until the completion of the mirror period of the power transistor.

10. The gate drive circuit of claim 9.

11. the first circuit path comprises a diode connected in series with the gate resistor; The forward direction of the diode in the first circuit path is from the input terminal to the gate of the power transistor.

11. The gate drive circuit according to claim 9 or 10.

12. An input terminal; a first circuit path inserted in a wiring that connects the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; a third circuit path connected in parallel to the second circuit path, the first circuit path includes a series connected diode and a gate resistor; the second circuit path includes a first capacitance and a first resistance connected in series; the third circuit path having a second resistor; the second resistor has a resistance greater than that of the first resistor; the resistance value of the gate resistor is greater than the second resistance; The forward direction of the diode in the first circuit path is from the input terminal to the gate of the power transistor. Gate drive circuit.

13. the second circuit path discharges a first amount of charge from a gate capacitance of the power transistor during a turn-off process of the power transistor; The first charge amount is set to be smaller than a second charge amount discharged from the gate capacitance of the power transistor from the start of turn-off of the power transistor until the completion of the mirror period of the power transistor.

13. The gate drive circuit of claim 12.

14. A gate drive circuit according to any one of claims 1 to 13; The power transistor. Semiconductor circuit breaker.

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