Graphene Diffusion Barrier

Abstract

Graphene barrier layers are disclosed. Some embodiments relate to graphene barrier layers that can prevent diffusion from a filler layer to a substrate surface and / or vice versa. Some embodiments relate to graphene barrier layers that prevent fluorine diffusion from a tungsten layer to an underlying substrate. Further embodiments relate to electronic devices that include graphene barrier layers. [Selected Figure] Figure 1

Description

[Technical field]

[0001]

[0001] Embodiments of the present disclosure generally relate to the use of graphene diffusion barriers to prevent diffusion of elements across boundaries. Further embodiments of the present disclosure relate to electronic devices that include graphene diffusion barriers. [Background technology]

[0002]

[0002] Preventing the migration of elements from one material to another within electronic devices is a long-recognized problem in the semiconductor technology field. Diffusion barriers have been developed to prevent the diffusion of large atoms such as metals.

[0003]

[0003] As the semiconductor field advances, many manufacturing techniques utilize processes that rely on materials containing smaller elements, such as boron and fluorine. These atoms can easily diffuse from one material to another, potentially damaging or adversely changing the properties of the materials they diffuse into.

[0004]

[0004] Therefore, there is a need for new diffusion barriers that impede the diffusion of smaller atoms. Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to a method of forming an electronic device. The method includes forming a graphene barrier layer on a substrate surface. A filler layer is deposited on the graphene barrier layer. The graphene barrier layer prevents diffusion of at least one element between the filler layer and the substrate surface.

[0006]

[0006] A further embodiment of the present disclosure is directed to a method of forming an electronic device. The method includes forming a graphene barrier layer on a substrate surface comprising Al2O3. The graphene barrier layer has a thickness ranging from about 15 Å to about 100 Å. An amorphous silicon layer is formed on the graphene barrier layer. The amorphous silicon layer is exposed to a tungsten precursor to form a tungsten layer by atomic substitution. The tungsten precursor includes WF6. The graphene barrier layer prevents diffusion of fluorine to the substrate surface.

[0007] Further embodiments of the present disclosure are directed to an electronic device comprising a graphene barrier layer between a first material and a second material, the graphene barrier layer preventing diffusion of at least one element between the first material and the second material.

[0008]

[0008] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure is open to other equally effective embodiments, and therefore the accompanying drawings merely illustrate typical embodiments of the present disclosure, and should not be considered as limiting the scope of the present disclosure. [Brief description of the drawings]

[0009] [Figure 1]

[0009] FIG. 1 illustrates a cross-sectional view of a substrate during processing according to one or more embodiments described herein. [Diagram 2]

[0010] 1 illustrates a system that can be used to process a substrate in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0011] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0011]

[0012] As used herein and in the appended claims, the term "substrate" refers to a surface or a portion of a surface on which a process acts. Those skilled in the art will also understand that a reference to a substrate may also refer to only a portion of the substrate, unless the context clearly indicates otherwise. Additionally, a reference to depositing on a substrate can refer to both the exposed substrate and the substrate having one or more films or features deposited or formed thereon.

[0012]

[0013] As used herein, "substrate surface" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, in this disclosure, any of the disclosed film treatment steps may be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0013]

[0014] Some embodiments of the present disclosure relate to the use of graphene as a barrier layer. Further embodiments of the present disclosure relate to methods of forming electronic devices that include a graphene barrier layer. Further embodiments of the present disclosure relate to electronic devices that include a graphene barrier layer. Some embodiments of the present disclosure advantageously provide barrier layers that can block the diffusion of small atoms such as boron and fluorine. Some embodiments of the present disclosure advantageously provide thinner barrier layers with equal or superior blocking capabilities. Some embodiments of the present disclosure advantageously provide thinner barrier layers that allow for a greater amount of fill material with lower resistance.

[0014]

[0015] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0015]

[0016] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit layers of material on a substrate surface. The substrate or a portion of the substrate is separately exposed to two or more reactive compounds that are introduced into a reaction zone of a processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay so that each compound can deposit and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface are exposed to two or more reactive compounds simultaneously, so that a given point on the substrate is not exposed to two or more reactive compounds simultaneously. As used herein and in the appended claims, the term "substantially" as used in this respect means that a small portion of the substrate may be exposed to multiple reactive gases at the same time by diffusion, as would be understood by one skilled in the art, and simultaneous exposure is not intended.

[0016]

[0017] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone followed by a first time delay. Then, a second reactive gas (i.e., a second precursor or compound B) is pulsed into the reaction zone followed by a second delay. During each time delay, a purge gas, such as argon or helium, is introduced into the process chamber to purge the reaction zone or otherwise remove residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process such that only the purge gas flows during the time delay between pulses of reactive compounds. The reactive gas is alternatively pulsed until a desired film or film thickness is formed on the substrate surface. In either overview, the ALD process in which compound A, purge gas, compound B, and purge gas are pulsed is referred to as a cycle. The cycle may start with either compound A or compound B and continue with each sequence of cycles until a film having a predetermined thickness is obtained.

[0017]

[0018] As used herein, "pulse" or "dose" is intended to refer to an amount of source gas that is intermittently or non-continuously introduced into a process chamber. The amount of a particular compound in each pulse may vary over time, depending on the duration of the pulse. A particular process gas may include a single compound or a mixture / combination of two or more compounds, such as the process gases described below.

[0018]

[0019] The duration of each pulse / dose is variable and can be adjusted, for example, to accommodate the volume capacity of the process chamber and the capacity of the vacuum system coupled thereto. In addition, the dose time of the process gas can vary depending on the flow rate of the process gas, the temperature of the process gas, the type of control valve, the type of process chamber used, and the ability of the components of the process gas to adsorb on the substrate surface. The dose time can also vary based on the type of layer being formed and the geometry of the device being formed. The dose time should be long enough to provide a sufficient amount of compound to adsorb / chemisorb on substantially the entire surface of the substrate and form a layer of the process gas components thereon.

[0019]

[0020] 1 , some embodiments of the present disclosure relate to a method 100 of forming an electronic device. The method includes forming a graphene barrier layer 20 on a substrate surface 10 and depositing a filler layer 30 on the graphene barrier layer 20. In some embodiments, the graphene barrier layer 20 prevents diffusion of at least one element between the filler layer 30 and the substrate surface 10.

[0020]

[0021] As used herein and in the appended claims, the phrase "prevents diffusion" means that the graphene barrier layer removes or reduces the concentration of at least one element in a destination material compared to the concentration in the absence of the barrier layer. A "destination material" is a material into which at least one element has diffused. Diffusion may occur as a result of storage and / or use of the electronic device, or may occur during subsequent processing steps.

[0021]

[0022] In some embodiments, the substrate surface comprises a dielectric material. In some embodiments, the dielectric material is a low-k dielectric material. In some embodiments, the dielectric material is a high-k dielectric material. In some embodiments, the dielectric material comprises a metal oxide. In some embodiments, the dielectric material comprises aluminum oxide (e.g., Al2O3) or consists essentially of aluminum oxide.

[0022]

[0023] As used herein and in the appended claims, phrases such as "consisting essentially of" mean that the subject film or composition is greater than about 95%, 98%, 99%, or 99.5% of the recited active material. For gas compositions (e.g., reactive gases), the phrase "consisting essentially of" refers to the active ingredients of the composition without diluents, carriers, or inert gases.

[0023]

[0024] In some embodiments, the graphene barrier layer 20 is formed by a plasma-enhanced atomic layer deposition (PEALD) process. Without being bound by theory, it is believed that the PEALD process provides greater control over the thickness of the graphene barrier layer 20. The thickness of the graphene barrier layer 20 may be measured as a number of atomic layers or as an absolute thickness. In some embodiments, the graphene barrier layer 20 has a thickness in the range of about 2 to about 50 atomic layers, or in the range of about 4 to about 30 atomic layers. In some embodiments, the graphene barrier layer 20 has a thickness of about 50 atomic layers or less, about 40 atomic layers or less, about 30 atomic layers or less, about 25 atomic layers or less, about 20 atomic layers or less, about 10 atomic layers or less, about 5 atomic layers or less, or about 3 atomic layers or less.

[0024]

[0025] In some embodiments, the graphene barrier layer has a thickness in the range of about 5 Å to about 150 Å, or in the range of about 15 Å to about 100 Å. In some embodiments, the graphene barrier layer has a thickness of about 150 Å or less, about 125 Å or less, about 100 Å or less, about 75 Å or less, about 50 Å or less, about 25 Å or less, or about 10 Å or less.

[0025]

[0026] The fill layer 30 can be any suitable material. In some embodiments, the fill layer 30 comprises at least one element that is prevented from diffusing into the substrate surface 10 by the graphene barrier layer 20. In some implementations, the fill layer 30 comprises or consists essentially of one or more metal elements. In some embodiments, the fill layer 30 comprises or consists essentially of one or more of tungsten, ruthenium, copper, or cobalt.

[0026]

[0027] In some embodiments, the at least one element is present in the fill layer 30 as a dopant. In some embodiments, the at least one element is present in the fill layer 30 as a by-product of the deposition of the fill layer 30. In some embodiments, the at least one element comprises or consists essentially of one or more of a halogen, oxygen, or boron. In some embodiments, the at least one element comprises or consists essentially of fluorine.

[0027]

[0028] The fill layer 30 may be deposited by any suitable method. In some embodiments, the fill material 30 may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). In some embodiments, the fill layer 30 comprises a bulk metal material.

[0028]

[0029] In some embodiments, the fill layer 30 comprises tungsten, and the fill layer 30 is deposited by a method that includes forming an amorphous silicon layer on the graphene barrier layer 20 and exposing the amorphous silicon layer to a tungsten precursor to form a tungsten layer by atomic substitution. In some embodiments, forming the amorphous silicon layer on the graphene barrier layer 20 includes exposing the graphene barrier layer to a silane, polysilane, or halogenated derivatives thereof. In some embodiments, the tungsten precursor comprises or consists essentially of tungsten and halogen atoms. In some embodiments, the tungsten precursor comprises or consists essentially of WF6, WCI6, and / or WCI5. In some implementations, the tungsten precursor comprises WF6, and at least one element comprises fluorine.

[0029]

[0030] In some embodiments, the fill layer 30 comprises tungsten, and the fill layer 30 is deposited by a method that includes sequentially exposing the graphene barrier layer to a tungsten precursor and a reactant. As used in this respect, sequentially exposing refers to an atomic layer deposition process as generally described herein. In some embodiments, the tungsten precursor comprises or consists essentially of tungsten atoms and halogen atoms. In some embodiments, the tungsten precursor comprises or consists essentially of WF6, WCI6, and / or WCI5. In some embodiments, the reactant comprises or consists essentially of hydrogen gas (H2) or silane (SiH4).

[0030]

[0031] Although some embodiments of the present disclosure have been described in connection with a graphene barrier layer that prevents diffusion of at least one element from the filler layer 30 to the substrate surface 10, it is also envisioned that a graphene barrier layer is useful for preventing diffusion of at least one element from the substrate surface 10 to the filler layer 30.

[0031]

[0032] Further embodiments of the present disclosure relate to electronic devices that include a graphene barrier layer. In some embodiments, the electronic device includes a graphene barrier layer between a first material and a second material. In some embodiments, the graphene barrier layer prevents diffusion of at least one element between the first material and the second material.

[0032]

[0033] As specified herein, the graphene barrier layer may be formed by any suitable process. The graphene barrier layer may be limited to any of the thicknesses disclosed herein. Specifically, in some embodiments, the graphene barrier layer has a thickness in the range of about 15 Å to about 100 Å.

[0033]

[0034] The at least one element can be any element as discussed elsewhere herein. In some embodiments, the at least one element comprises or consists essentially of one or more of a halogen, oxygen, or boron. In some embodiments, the at least one element comprises or consists essentially of fluorine.

[0034]

[0035] The first material and the second material can be any suitable material. The meaning of first and second is arbitrary, as long as diffusion between the first and second materials is prevented. In some embodiments, the first material and the second material comprise the same material. In some embodiments, the first material comprises or consists essentially of a metal, and the second material comprises or consists essentially of a dielectric material. In some embodiments, the metal comprises or consists essentially of one or more of tungsten, ruthenium, copper, or cobalt. In some embodiments, the dielectric material comprises or consists essentially of a metal oxide. In some embodiments, the metal oxide is aluminum oxide (e.g., Al2O3).

[0035]

[0036] In some embodiments, the electronic device comprising the graphene barrier layer is a 3D NAND device comprising multiple alternating layers of a first material and a second material. In some embodiments, the first material is a gate material and the second material is an oxide. In some embodiments, the first material is a nitride and the second material is an oxide.

[0036]

[0037] With reference to FIG. 2, a further embodiment of the present disclosure is directed to a system 900 for performing the methods described herein. FIG. 2 illustrates a system 900 that can be used to process substrates according to one or more embodiments of the present disclosure. The system 900 may be referred to as a cluster tool. The system 900 includes a central transfer station 910 with a robot 912 therein. The robot 912 is illustrated as a single blade robot, but one of ordinary skill in the art will recognize that other robot 912 configurations are within the scope of the disclosure. The robot 912 is configured to move one or more substrates between chambers coupled to the central transfer station 910.

[0037]

[0038] At least one pre-clean / buffer chamber 920 is coupled to the central transfer station 910. The pre-clean / buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-clean / buffer chamber 920 may be used as a holding area for individual semiconductor substrates or for cassettes of wafers for processing. The pre-clean / buffer chamber 920 may perform a pre-clean process or pre-heat the substrate for processing or simply be a staging area for a process sequence. In some embodiments, there are two pre-clean / buffer chambers 920 coupled to the central transfer station 910.

[0038]

[0039] 9, the pre-clean chamber 920 may function as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 may include one or more robots 906 for moving substrates from a cassette to the pre-clean / buffer chamber 920. A robot 912 may then move the substrate from the pre-clean / buffer chamber 920 to other chambers in the system 900.

[0039]

[0040] A first processing chamber 930 may be coupled to the central transfer station 910. The first processing chamber 930 may be configured as an anisotropic etch chamber and may be fluidly coupled to one or more reactive gas sources to provide one or more flows of reactive gas to the first processing chamber 930. Substrates may be moved to and from the processing chamber 930 by a robot 912 passing through an isolation valve 914.

[0040]

[0041] Processing chambers 940 may also be coupled to the central transfer station 910. In some embodiments, the processing chambers 940 comprise isotropic etch chambers and are fluidly coupled to one or more reactive gas sources to provide a flow of reactive gas to the processing chambers 940 to perform an isotropic etch process. Substrates may be moved to and from the processing chambers 940 by a robot 912 passing through an isolation valve 914.

[0041]

[0042] Processing chamber 945 may also be coupled to the central transfer station 910. In some embodiments, processing chamber 945 is the same type of processing chamber 940 configured to perform the same process as processing chamber 940. This configuration may be useful when the process to be performed in processing chamber 940 takes much longer than the process in processing chamber 930.

[0042]

[0043] In some embodiments, a processing chamber 960 is coupled to the central transfer station 910 and configured to function as a selective epitaxial growth chamber. The processing chamber 960 can be configured to perform one or more different epitaxial growth processes.

[0043]

[0044] In some embodiments, the anisotropic etching process is performed in the same processing chamber as the isotropic etching process. In such embodiments, processing chamber 930 and processing chamber 960 may be configured to perform an etching process on two substrates simultaneously, and processing chamber 940 and processing chamber 945 may be configured to perform a selective epitaxial growth process.

[0044]

[0045] In some embodiments, each of the processing chambers 930, 940, 945, and 960 is configured to perform a different portion of a processing method. For example, processing chamber 930 may be configured to perform an anisotropic etching process, processing chamber 940 may be configured to perform an isotropic etching process, processing chamber 945 may be configured as a metrology station or to perform a first selective epitaxial growth process, and processing chamber 960 may be configured to perform a second epitaxial growth process. One skilled in the art will appreciate that the number and arrangement of individual processing chambers on a tool may vary, and that the embodiment shown in FIG. 9 represents only one possible configuration.

[0045]

[0046] In some embodiments, system 900 includes one or more metrology stations. For example, the metrology station can be located in the pre-clean / buffer chamber 920, in the central transfer station 910, or within any of the individual processing chambers. The metrology station can be located anywhere in system 900 that allows the recessed distance to be measured without exposing the substrate to an oxidizing environment.

[0046]

[0047] At least one controller 950 is coupled to one or more of the central transfer station 910, the pre-clean / buffer chamber 920, the processing chambers 930, 940, 945, or 960. In some embodiments, there is more than one controller 950 coupled to individual chambers or stations, with a main control processor coupled to each of the separate processors to control the system 900. The controller 950 can be one of any form of general purpose computer processor, microcontroller, microprocessor, etc. that can be used in an industrial environment to control the various chambers and sub-processors.

[0047]

[0048] At least one controller 950 may include a processor 952, a memory 954 coupled to the processor 952, input / output devices 956 coupled to the processor 952, and support circuits 958 for communication between different electronic components. The memory 954 may include one or more of a temporary memory (e.g., random access memory) and a non-transitory memory (e.g., storage).

[0048]

[0049] The processor's memory 954 or computer readable medium may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage, local or remote. The memory 954 may hold a set of instructions operable by the processor 952 to control parameters and components of the system 900. The support circuits 958 are coupled to the processor 952 for supporting the processor in a conventional manner. The circuits may include, for example, cache, power supplies, clock circuits, input / output circuits, subsystems, etc.

[0049]

[0050] The processes may generally be stored in memory as software routines that, when executed by a processor, cause the processing chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed using a computer system, for example in hardware as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a specific-purpose computer (controller) that controls the chamber operation so that the processes are performed.

[0050]

[0051] In some embodiments, the controller 950 has one or more configurations for executing individual processes or sub-processes to perform a method. The controller 950 may be coupled to and configured to operate intermediate components to perform the functions of a method. For example, the controller 950 may be connected to and configured to control one or more of gas valves, actuators, motors, slit valves, vacuum controls, etc.

[0051]

[0052] The controller 950 in some embodiments has one or more configurations selected from: moving a substrate on a robot between multiple processing chambers and a metrology station; transferring a substrate into and / or out of the system; forming a graphene barrier layer on a substrate surface; and depositing a filler layer on the graphene barrier layer.

[0052]

[0053] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0053]

[0054] Although the disclosure of this specification has been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Thus, the present disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming an electronic device, the method comprising: forming a graphene barrier layer on a substrate surface; depositing a filler layer over the graphene barrier layer, the filler layer comprising tungsten, the filler layer comprising: forming an amorphous silicon layer on the graphene barrier layer; exposing the amorphous silicon layer to a tungsten precursor to form a tungsten layer by atomic substitution; depositing a filler layer on the graphene barrier layer formed by Including, The method of claim 1, wherein the graphene barrier layer prevents diffusion of at least one element between the fill layer and the substrate surface.

2. The method of claim 1 , wherein the substrate surface comprises a dielectric material.

3. The method of claim 2 , wherein the dielectric material comprises a metal oxide.

4. The dielectric material is essentially Al ２ 0 ３ The method of claim 2, comprising:

5. 10. The method of claim 1, wherein the graphene barrier layer is formed by a method comprising plasma-enhanced atomic layer deposition.

6. 10. The method of claim 1, wherein the graphene barrier layer has a thickness in the range of about 15 Å to about 100 Å.

7. The method of claim 1 , wherein the fill layer comprises one or more of tungsten, ruthenium, copper, or cobalt.

8. The method of claim 1 , wherein the at least one element comprises one or more of a halogen, oxygen, or boron.

9. The method of claim 8 , wherein the at least one element consists essentially of fluorine.

10. The tungsten precursor is WF ６ 2. The method of claim 1 , comprising:

11. The filling layer is formed by dissolving the graphene barrier layer in a solvent such as WF ６ 13. The method of claim 1 , wherein the tungsten is deposited by a process comprising sequentially exposing the tungsten to a tungsten precursor and a reactant comprising:

12. 1. A method of forming an electronic device, the method comprising: A ２ 0 ３ forming a graphene barrier layer having a thickness in a range of about 15 Å to about 100 Å on a substrate surface comprising: forming an amorphous silicon layer on the graphene barrier layer; The amorphous silicon layer is formed by ６ forming a tungsten layer by atomic replacement; wherein the graphene barrier layer prevents diffusion of fluorine to the substrate surface.

13. An electronic device having a graphene barrier layer, comprising: The electronic device is a 3D NAND device comprising multiple alternating layers of a first material and a second material.

Images