Memory Devices

Abstract

To provide a memory device such as a three-dimensional AND flash memory or a three-dimensional NOR flash memory.SOLUTION: A memory device 500 includes a first chip 510 and a second chip 520. The first chip includes a plurality of source line switches SLT1, SLT2, a plurality of bit line switches BLT1, BLT2, a plurality of page buffers PB1, PB2, and a plurality of sensing amplifiers SA1, SA2. The first chip includes a plurality of first pads. The second chip includes a plurality of memory cells, and forming a plurality of memory cell blocks 521, 522. The plurality of second pads are on a first surface of the second chip, and are respectively connected to a plurality of local bit lines LBL0 to LBL3 and a plurality of local source lines LSL0 to LSL3 of the memory cell blocks. Each of the first pads is connected to a corresponding one of the second pads.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to memory devices, and more particularly to memory devices formed by stacking multiple chips. [Background technology]

[0002] In a 3D-AND flash memory, some memory blocks may share a sense amplifier to save circuit layout area, but this will affect the number of sense amplifiers on the memory access bandwidth.

[0003] In the prior art, the design of a small-sized memory cell block can increase the access speed of the memory cell. However, by sharing one sense amplifier with multiple memory cell blocks, the length of the global bit line is increased, and the signal transmission impedance is excessively high. The excessively high signal transmission impedance is often the bottleneck of the data sensing speed of the memory, which is the reason why the read efficiency cannot be effectively improved. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a memory device that can effectively reduce the transfer impedance of a sense amplifier connected to a global bit line between memory cells. [Means for solving the problem]

[0005] The memory device of the present disclosure includes a first chip and a second chip. The first chip has a plurality of source line switches, a plurality of bit line switches, a plurality of page buffers, and a plurality of sense amplifiers. The first chip has a plurality of first pads. The second chip has a plurality of memory cells and forms a plurality of memory cell blocks. A first surface of the second chip has a plurality of second pads respectively connected to a plurality of local bit lines and a plurality of local source lines of the memory cell blocks. Each of the first pads is connected to a corresponding second pad. Effect of the Invention

[0006] Based on the above, the memory device of the present disclosure is formed by combining two different chips. The source line switch, the bit line switch, the page buffer, and the sense amplifier are disposed in the first chip, and the memory cell block is disposed in the second chip. A whole circuit loop of the memory device may be completed by connecting a plurality of first pads on the first chip to a plurality of second pads on the second chip. In addition, the sense amplifier may be electrically connected to the global bit line of the corresponding memory cell block through the first pad and the second pad, which reduces the length and transmission impedance of the global bit line and improves the operation efficiency of the memory device. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 shows a schematic diagram of a memory device according to one embodiment of the present disclosure.

[0008] [Diagram 2] 1 shows a schematic diagram of a three-dimensional structure of a memory device according to an embodiment of the present disclosure.

[0009] [Diagram 3] 1 shows a three-dimensional schematic diagram of the structure of a pad of a memory device according to an embodiment of the present disclosure.

[0010] [Figure 4]FIG. 2 shows a schematic top view of a pad of a memory device according to one embodiment of the present disclosure.

[0011] [Diagram 5] 1 shows a schematic diagram of a circuit of a memory device according to one embodiment of the present disclosure.

[0012] [Figure 6] 1 shows a schematic diagram of a cross-sectional structure of a memory device according to one embodiment of the present disclosure.

[0013] [Figure 7] 1 shows a schematic diagram of the structure of a peripheral circuit connection method of a memory device according to an embodiment of the present disclosure; [Figure 8] 1 shows a schematic diagram of the structure of a peripheral circuit connection method of a memory device according to an embodiment of the present disclosure; [Figure 9] 1 shows a schematic diagram of the structure of a peripheral circuit connection method of a memory device according to an embodiment of the present disclosure;

[0014] [Figure 10] 1 shows a schematic diagram of a three-dimensional structure of a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Please refer to FIG. 1. FIG. 1 shows a schematic diagram of a memory device according to an embodiment of the present disclosure. The memory device 100 includes a first chip 110 and a second chip 120. The first chip 110 has a plurality of source line switches, a plurality of bit line switches, a plurality of page buffers, and a plurality of sense amplifiers. The plurality of source line switches may be divided into a plurality of source line switch groups. The plurality of bit line switches may be divided into a plurality of bit line switch groups. Each of the sense amplifiers corresponds to each of the source line switch groups, each of the bit line switch groups, and each of the page buffers. In terms of the connection relationship, each of the sense amplifiers is connected to a corresponding page buffer and is connected to a corresponding bit line switch via a corresponding global bit line.

[0016] In this embodiment, a plurality of pads PD1 may be formed on the first chip 110. A portion of the pads PD1 may be connected to, for example, a first end of a corresponding bit line switch, and another portion of the pads PD1 may be connected to, for example, a first end of a corresponding source line switch. A second end of the bit line switch may be connected to a corresponding global bit line. The second end of the source line switch may receive a reference voltage, such as a reference ground voltage.

[0017] Meanwhile, the second chip 120 has a plurality of memory cells and forms a plurality of memory cell blocks. Each of the memory cell blocks may correspond to each of the sense amplifiers on the first chip 110. A plurality of pads PD2 may be formed on the first surface S1 of the second chip 120. A portion of the pad PD2 may be connected to a local bit line of each of the memory cell blocks, and another portion of the pad PD2 may be connected to a local source line of each of the memory cell blocks.

[0018] In this embodiment, each of the sense amplifiers on the first chip 110 may be connected to a corresponding one of the memory cell blocks on the second chip 120 via a corresponding group of source line switches and a corresponding group of bit line switches by correspondingly electrically connecting each of the pads PD1 to the pads PD2. The construction of the entire circuit loop of the memory device 100 may be completed.

[0019] The circuitry of the memory device 100 will be described in more detail in the following embodiments.

[0020] It should be noted that the memory device 100 of the present disclosure divides the circuit elements disposed on the first chip 110 and the second chip 120, respectively. This can effectively reduce the density of the circuit elements on the first chip 110 and the second chip 120. This can reduce the complexity of the circuit layout of the first chip 110 and the second chip 120, and can also reduce unexpected parasitic effects occurring between the circuit elements, effectively improving the operation efficiency of the memory device 100.

[0021] Please refer to FIG. 2 below. FIG. 2 shows a schematic diagram of a three-dimensional structure of a memory device according to an embodiment of the present disclosure. The memory device 200 includes a first chip 210 and a second chip 220. The first chip 210 includes circuit blocks 211-1 to 211-N and circuit blocks 212-1 to 212-N. The second chip 220 includes circuit blocks 221-1 to 221-N and circuit blocks 222-1 to 222-N. In the first chip 210, each of the circuit blocks 212-1 to 212-N is configured to accommodate a sense amplifier and a corresponding page buffer. Each of the circuit blocks 211-1 to 211-N is configured to accommodate a corresponding bit line switch group and source line switch group. In the second chip 220, each of the circuit blocks 221-1 to 221-N is configured to arrange an X-address sensor, and each of the circuit blocks 222-1 to 222-N is configured to arrange a memory cell block corresponding to the X-address sensor. In this embodiment, the circuit blocks 222-1 to 222-N in which the memory cell blocks are arranged are stacked above the circuit blocks 221-1 to 221-N configured to arrange the X-address sensors.

[0022] On the other hand, taking the circuit block 222-1 as an example, a plurality of local bit lines LBL and a plurality of local source lines LSL are on the memory cell block in the circuit block 222-1. The local bit lines LBL and the local source lines LSL are alternately arranged, and the local bit lines LBL and the local source lines LSL are parallel to each other. A plurality of pads may be formed on each of the local bit lines LBL and each of the local source lines LSL. The second chip 220 may be electrically connected to a plurality of pads on the first chip 210 through a plurality of pads, enabling the local bit lines LBL and the local source lines LSL on the memory cell block to be electrically connected to the corresponding bit line switch groups and source line switch groups, respectively.

[0023] In this embodiment, the first chip 210 and the second chip 220 are attached to each other in the vertical direction to complete the electrical connection. In this state, the sense amplifiers and corresponding page buffers in each of the circuit blocks 212-1 to 212-N may be stacked above the corresponding memory cell blocks in each of the circuit blocks 221-1 to 221-N, and the bit line switch groups and source line switch groups in each of the circuit blocks 211-1 to 211-N may also be stacked correspondingly above the memory cell blocks in each of the circuit blocks 221-1 to 221-N.

[0024] In this embodiment, each of the memory cell blocks has a corresponding sense amplifier and is stacked vertically, which can effectively shorten the length of the global bit line completing the electrical connection between the memory cell block and the corresponding sense amplifier, greatly reduce the signal transmission resistance between the memory cell block and the corresponding sense amplifier, and improve the operation efficiency of the memory device 200.

[0025] Please refer to FIG. 3 below. FIG. 3 shows a three-dimensional schematic diagram of a pad structure of a memory device according to an embodiment of the present disclosure. FIG. 3 takes a second chip as an example. In the second chip, a plurality of local bit lines LBL0-LBL3 and a plurality of local source lines LSL0-LSL3 may be arranged on a memory cell block 310. The local bit lines LBL0-LBL3 and the local source lines LSL0-LSL3 are arranged alternately. The local bit lines LBL0-LBL3 and the local source lines LSL0-LSL3 may have the same size, and each of the adjacent local bit lines LBL0-LBL3 and each of the local source lines LSL0-LSL3 may have the same interval. As a result, the parasitic capacitances (such as capacitances C1, C2, etc.) formed between each of the local bit lines LBL0-LBL3 and each of the local source lines LSL0-LSL3 may have substantially the same capacitance value (there may still be some difference between the parasitic capacitances based on the manufacturing process error). This makes it possible to maintain the quality of data transmission on the local bit lines LBL0 to LBL3 and the local source lines LSL0 to LSL3.

[0026] In this embodiment, the local bit lines LBL0 to LBL3 and the local source lines LSL0 to LSL3 may be formed via the first layer (TM1) of the upper metal layer.

[0027] On the other hand, the pads PD may be arranged above the corresponding local bit lines LBL0-LBL3 and local source lines LSL0-LSL3. The pads PD are electrically connected to the corresponding local bit lines LBL0-LBL3 and local source lines LSL0-LSL3 through the conductive vias TV1. The pads PD may be regularly arranged above the local bit lines LBL0-LBL3 and local source lines LSL0-LSL3, and the horizontal and vertical distances between two pads PD corresponding to adjacent local bit lines LBL0-LBL3 and the local source lines LSL0-LSL3 may be fixed.

[0028] In this embodiment, the pad PD may be formed, for example, via the second layer (TM2) of the upper metal layer.

[0029] It is worth mentioning that the arrangement of the pads on the first chip may also be arranged according to the mounting method shown in FIG. 3, but it will not be repeated here.

[0030] Please refer to FIG. 4 below. FIG. 4 shows a schematic top view of a pad of a memory device according to an embodiment of the present disclosure. In FIG. 4, a plurality of local bit lines LBL0-LBLN and a plurality of local source lines LSL0-LSLN may be arranged alternately in parallel and cover a memory cell block (not shown). The local bit lines LBL0-LBLN and the local source lines LSL0-LSLN may be of the same size, and each of the adjacent local bit lines LBL0-LBLN and each of the local source lines LSL0-LSLN have the same interval and form a parasitic capacitance having substantially the same capacitance value.

[0031] The pads PD are disposed above the local bit lines LBL0 to LBLN and the local source lines LSL0 to LSLN, respectively, and are electrically connected to the local bit lines LBL0 to LBLN and the local source lines LSL0 to LSLN, respectively, through conductive vias.

[0032] Please refer to FIG. 5 below. FIG. 5 shows a schematic diagram of a circuit of a memory device according to an embodiment of the present disclosure. In FIG. 5, the memory device 500 includes a first chip 510 and a second chip 520. The first chip 510 includes sense amplifiers SA1, SA2, page buffers PB1, PB2, a plurality of bit line switches BLT1, BLT2, and a plurality of source line switches SLT1, SLT2. The sense amplifier SA1 is connected to the page buffer PB1 and is connected to the bit line switch BLT1. The sense amplifier SA2 is connected to the page buffer PB2 and is connected to the bit line switch BLT2. The plurality of source line switches SLT1, SLT2 may not be connected to the end of the first chip 510, but may be connected to a ground end to receive a reference ground voltage GND.

[0033] The second chip 520 includes a plurality of memory cell blocks 521 and 522. Taking the memory cell block 521 as an example, the memory cell block 521 has a plurality of local bit lines LBL0-LBL3 and a plurality of local source lines LSL0-LSL3. In this embodiment, the local bit lines LBL0-LBL3 are respectively connected to different bit line switches BLT1 via a plurality of connection structures PDA, and the local source lines LSL0-LSL3 are also respectively connected to different source line switches SLT1 via a plurality of connection structures PDA. Each of the connection structures PDA is two pads connected to each other on the first chip 510 and the second chip 520.

[0034] The memory cell blocks 521 and 522 may each include a three-dimensionally stacked AND flash memory cell array or a NOR flash memory cell array.

[0035] In this embodiment, the sense amplifiers SA1, SA2 may be implemented using any sense amplifier circuit known to those skilled in the art and applied to memories, and the page buffers PB1, PB2 may be digital circuits and may be implemented by any page buffer circuit known to those skilled in the art and applied to memories without limitation.

[0036] Please refer to FIG. 6. FIG. 6 shows a schematic diagram of a cross-sectional structure of a memory device according to an embodiment of the present disclosure. The memory device 600 includes a first chip 610 and a second chip 620. The first chip 610 has a plurality of sense amplifiers, a plurality of bit line switches, a plurality of source line switches, and a plurality of page buffers. In FIG. 6, the first chip 610 has transistors T1 and T2. The transistors T1 and T2 are configured to build a bit line switch, a source line switch, or other control circuit. An end (source or drain) of the transistor T1 may be connected to a pad PD11, and an end (source or drain) of the transistor T2 may be connected to a pad PD12.

[0037] On the other hand, the second chip 620 has a memory cell region 621. The memory cell region 621 may have a plurality of memory cell blocks. A local bit line or a local source line of the memory cell block may be connected to a pad PD21. The pad PD21 may be electrically connected to an opposing pad PD11, and a transistor T1 used as a source line switch or a bit line switch in the first chip 610 may be connected to a local source line or a local bit line in the second chip 620.

[0038] In addition, the second chip 620 may further include a through silicon via TAV1. An end of the through silicon via TAV1 is connected to the bottom metal layer BM4 of the second chip 620, and passes through the word line region of the second chip 620 to connect to a pad PD22. The pad PD22 may be electrically connected to an opposing pad PD12, allowing the transistor T2 in the first chip 610 to perform a signal transmission operation with the second chip 620.

[0039] It should be noted that in this embodiment, the X-address decoder may be disposed below the bottom metal layer BM4. The X-address decoder may perform a position decoding operation and provide access address information to the memory cell region 621.

[0040] Please refer to Figures 7 to 9 below. Figures 7 to 9 show schematic diagrams of the structure of a connection method for peripheral circuits of a memory device according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the first chip of the memory device further includes a peripheral circuit. The peripheral circuit may perform signal transmission operations between an external electronic device and perform a number of control operations related to the access operation of the memory device.

[0041] In this embodiment, the peripheral circuitry may be connected to a plurality of through silicon vias, and may transmit and receive a plurality of control signals and power signals to and from an external electronic device through the plurality of through silicon vias, which are formed in the second chip and electrically connect to the peripheral circuitry in the first chip through the second chip.

[0042] In the three-dimensional view of Figure 7, the ground poly layer 710 may generate multiple split islands 711 by an etching operation on the ground poly layer 710 in the peripheral area of ​​the second chip. The multiple split islands 711 are physically separated from each other. In addition, in the second chip, multiple through silicon via TSVs may be generated on the split islands 711. Because the split islands 711 are physically separated from each other and from the ground poly layer 710, electrical isolation effects may occur between the through silicon via TSVs.

[0043] In the cross-sectional view of FIG. 8, the through silicon via TSV penetrates the divided island 711 and is connected between the pad PD2 and the conductive bump MB. The conductive bump MB is formed on the second surface S2 of the second chip, and the pad PD2 is formed on the first surface S1 of the second chip, and the first surface S1 faces the second surface S2. It is worth noting that when penetrating the second chip, the through silicon via TSV penetrates the non-circuit area Z1 of the second chip to avoid the occurrence of signal transmission contention between the internal circuit of the second chip.

[0044] In addition, the pad PD2 is configured to be electrically connected to the pad PD1 on the first chip. The pad PD1 on the first chip may be electrically connected to a peripheral circuit in the first chip. Thus, an external electronic device may perform a signal transmission operation between the peripheral circuit of the first chip and the pad PD2, PD1 using a signal transmission path formed by the through silicon via TSV and the pads PD2, PD1 via the conductive bump MB.

[0045] According to the schematic cross-sectional view of the memory device in FIG. 9, it can be seen that in the memory device 900, the first chip 910 has a peripheral circuit region 911 and a non-peripheral circuit region. The peripheral circuit region 911 is configured to arrange peripheral circuits, and the non-peripheral circuit region is configured to arrange sense amplifiers, page buffers, source line switches, and bit line switches. The first chip 910 has pads PD11, PD12, and PD13. The second chip 920 has a memory cell region 921. The memory cell region 921 has a plurality of memory cell blocks. The pads PD21, PD22, and PD23 are on a surface of the second chip 920 facing the first chip 910. The pads PD21, PD22, and PD23 on the second chip 920 are electrically connected to the pads PD11, PD12, and PD13 on the first chip 910, respectively.

[0046] The pad PD11 is configured to connect to a bit line switch or a source line switch in the first chip 910, and the pad PD21 is configured to connect to a local bit line or a local source line of a memory cell block in the second chip 920. The pad PD12 may be connected to any transistor in the first chip 910, and the pad PD22 may be connected to any metal layer in the second chip 920. The pad PD13 may be connected to a peripheral circuit in the first chip 910, and the pad PD23 may be connected to a through silicon via TSV formed in the second chip 920. The through silicon via TSV penetrates the second chip 920 and is connected to a conductive bump MB formed on another surface of the second chip 920.

[0047] Please refer to FIG. 10. FIG. 10 shows a schematic diagram of a three-dimensional structure of a memory device according to an embodiment of the present disclosure. The memory device 1000 includes a first chip 1110 and a second chip 1120. The first chip 1110 covers the second chip 1120. The first chip 1110 has a peripheral circuit area 1111 and non-peripheral circuit areas 1112-1115. The peripheral circuit area 1111 is configured to arrange peripheral circuits. The non-peripheral circuit areas 1112-1115 are configured to arrange sense amplifiers, page buffers, source line switches, and bit line switches.

[0048] The first chip 1110 covers an area of ​​the memory cell region 1121 and is electrically connected to a plurality of pads on the second chip 1120 via a plurality of pads. The peripheral circuitry is electrically connected to a plurality of through silicon vias TSV in the second chip 1120 via pads PDP. The through silicon vias TSV may pass through a plurality of split islands 1123 formed on a ground poly layer in the second chip 1120. [Industrial Applicability]

[0049] In short, in the memory device of the present disclosure, the sense amplifiers, the page buffer, the source line switch and the bit line switch are disposed in a first chip, and the memory cell block is disposed in a second chip. A plurality of pads are formed on the first chip and on the second chip, respectively, and the entire memory device is formed by electrically connecting the plurality of pads on the first chip and on the second chip to each other. Thus, in the memory device, each of the memory cell blocks has a corresponding sense amplifier. Furthermore, the sense amplifiers may be connected to the corresponding memory cell blocks through pads, which can effectively shorten the length of the transmission wire therebetween, reduce the signal transmission impedance, and improve the operation efficiency of the memory device. [Explanation of symbols]

[0050] 100, 200, 500, 600, 900, 1000: Memory devices 110, 210, 510, 610, 910, 1110: 1st chip 1112~1115: Non-peripheral circuit area 1121: Memory cell area 120, 220, 520, 620, 920, 1120: 2nd chip 211-1~222-N: Circuit block 310: Memory cell block 621: Memory cell area 710: Ground poly layer 711, 1123: Split Island 911, 1111: Peripheral circuit area BLT1, BLT2: bit line switches BM4: Bottom metal layer C1, C2: Capacity GND: Reference ground voltage LBL, LBL0 to LBL3: local bit lines LSL, LSL0~LSL3: Local source lines MB: Conductive bump PB1, PB2: Page buffer PD1, PD2, PD11 to PD23, PDP: Pads PDA: Connection structure S1, S2: Surface SA1, SA2: Sense amplifiers SLT1, SLT2: Source line switches T1, T2: transistors TAV1, TSV: Through Silicon Via TM2:Top metal layer Z1: No circuit area

Claims

1. 1. A memory device comprising: a first chip having a plurality of source line switches, a plurality of bit line switches, a plurality of page buffers, and a plurality of sense amplifiers, the first chip having a plurality of first pads; a second chip having a plurality of memory cells for forming a plurality of memory cell blocks, a first surface of the second chip having a plurality of second pads respectively connected to a plurality of local bit lines and a plurality of local source lines of the plurality of memory cell blocks; Each of the first pads is connected to a corresponding one of the second pads; A memory device, wherein each of the local bit lines and each of the local source lines are arranged in alternating parallel fashion above a corresponding one of the memory cell blocks, and each of the sense amplifiers and corresponding one of the page buffers are arranged above each of the local bit lines and each of the local source lines of the corresponding one of the memory cell blocks.

2. 2. The memory device according to claim 1, wherein the second chip has a plurality of X-address decoders respectively corresponding to the plurality of memory cell blocks.

3. 3. The memory device of claim 2, wherein the plurality of source line switches are divided into a plurality of source line switch groups, the plurality of bit line switches are divided into a plurality of bit line switch groups, and each of the plurality of source line switch groups and each of the plurality of bit line switch groups corresponds to each of the memory cell blocks.

4. 4. The memory device of claim 3, wherein each of said memory cell blocks corresponds to a respective one of said X address decoders.

5. 5. The memory device of claim 4, wherein each of said memory cell blocks is stacked with a corresponding group of said source line switches, a corresponding group of said bit line switches, a corresponding group of said sense amplifiers, and a corresponding group of said X-address decoders.

6. 4. The memory device of claim 3, wherein each of said sense amplifiers is connected to a corresponding one of said page buffers and to a corresponding one of said bit line switches.

7. 2. The memory device of claim 1, wherein the plurality of local bit lines and the plurality of local source lines have the same size, and each of the local bit lines and adjacent local source lines has substantially the same parasitic capacitance value.

8. 2. The memory device of claim 1, wherein the second pads are formed above the local bit lines and the local source lines, respectively, and are electrically connected to the local bit lines and the local source lines through conductive vias.

9. 2. The memory device of claim 1, further comprising a peripheral circuit disposed within the first chip, connected to a plurality of through silicon vias, and configured to transmit and receive a plurality of control signals and power signals to and from an external electronic device via the plurality of through silicon vias.

10. 10. The memory device of claim 9, wherein the plurality of through silicon vias extend through non-circuitry areas of the second chip.

11. 10. The memory device of claim 9, wherein a plurality of split islands are formed by a ground poly layer of the second chip, and the plurality of through silicon vias extend through each of the plurality of split islands.

12. 10. The memory device of claim 9, wherein a second surface of the second chip has a plurality of conductive bumps, the plurality of conductive bumps being respectively connected to the plurality of through silicon vias.

13. 10. The memory device of claim 9, wherein the peripheral circuitry is arranged in a center of the first chip, the peripheral circuitry divides the first chip into a plurality of regions, and each of the source line switches, the corresponding bit line switches, each of the page buffers, and each of the sense amplifiers are arranged in one of the plurality of regions.

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