Semiconductor device and semiconductor memory device

Abstract

To provide a semiconductor device with high heat resistance.SOLUTION: A semiconductor device according to an embodiment includes an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region, a gate electrode, a gate insulating layer provided between the third region and the gate electrode, a first electrode electrically connected to the first region, a second electrode electrically connected to the second region, a first conductive layer provided in at least one of a position between the first region and the first electrode and a position between the second region and the second electrode and containing at least one element of oxygen (O) and nitrogen (N) and a first metal element, and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer, containing at least one element selected from the group consisting of oxygen (O), indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and having larger thickness than the first conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a semiconductor memory device. [Background technology]

[0002] An oxide semiconductor transistor having a channel formed in an oxide semiconductor layer has an excellent characteristic of having an extremely small channel leakage current during off-state operation. For this reason, the use of oxide semiconductor transistors as switching transistors in memory cells of dynamic random access memories (DRAMs), for example, has been considered.

[0003] For example, when an oxide semiconductor transistor is used as a switching transistor of a memory cell, the oxide semiconductor transistor undergoes heat treatment associated with the formation of the memory cell and wirings, and therefore it is expected to realize an oxide semiconductor transistor with high heat resistance and with little change in characteristics even after heat treatment. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-239216 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device having high heat resistance. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment includes an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region, a gate electrode, a gate insulating layer provided between the third region and the gate electrode, a first electrode electrically connected to the first region, a second electrode electrically connected to the second region, and a gate insulating layer provided at least one position between the first region and the first electrode and between the second region and the second electrode, Oxygen (O) and Nitrogen (N) and a first conductive layer containing a first metal element; and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer, containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O), and having a thickness greater than that of the first conductive layer. The first metal element is titanium (Ti). . [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Diagram 3] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 4] FIG. 13 is a block diagram of a semiconductor memory device according to a third embodiment. [Diagram 5] FIG. 13 is a schematic cross-sectional view of a memory cell array in a semiconductor memory device according to a third embodiment. [Figure 6] FIG. 13 is a schematic cross-sectional view of a memory cell array in a semiconductor memory device according to a third embodiment. [Figure 7] FIG. 11 is a schematic cross-sectional view of a first memory cell of a semiconductor memory device according to a third embodiment. [Figure 8] FIG. 11 is a schematic cross-sectional view of a second memory cell in the semiconductor memory device according to the third embodiment. [Figure 9] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described will be omitted as appropriate.

[0009] In addition, in this specification, the terms "upper" and "lower" may be used for convenience. "Upper" and "lower" are terms that indicate a relative positional relationship in the drawing, and are not terms that define a positional relationship with respect to gravity.

[0010] Qualitative and quantitative analysis of the chemical composition of the members constituting the semiconductor device and semiconductor memory device in this specification can be performed by, for example, secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). In addition, for example, a transmission electron microscope (TEM) can be used to measure the thickness of the members constituting the semiconductor device, the distance between the members, the crystal grain size, and the like.

[0011] (First embodiment) The semiconductor device of the first embodiment includes an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region, a gate electrode, a gate insulating layer provided between the third region and the gate electrode, a first electrode electrically connected to the first region, a second electrode electrically connected to the second region, a first conductive layer provided at least at one of a position between the first region and the first electrode and a position between the second region and the second electrode, the first conductive layer including at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), the second conductive layer having a thickness greater than that of the first conductive layer, and oxygen (O).

[0012] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment.

[0013] The semiconductor device of the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer. The transistor 100 is a so-called bottom-gate transistor in which a gate electrode is provided below the oxide semiconductor layer in which the channel is formed, and a source electrode and a drain electrode are provided above the oxide semiconductor layer. The transistor 100 is an n-channel transistor that uses electrons as carriers.

[0014] The transistor 100 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, a contact layer 22, a first insulating layer 24, and a second insulating layer 26.

[0015] The source electrode 16 is an example of a first electrode. The drain electrode 18 is an example of a second electrode. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer.

[0016] In the oxide semiconductor layer 10, a channel that serves as a current path is formed when the transistor 100 is in an on-state. The direction in which electrons flow in the channel is referred to as the channel length direction. In FIG. 1, the channel length direction is indicated by a double-headed arrow.

[0017] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.

[0018] The oxide semiconductor layer 10 contains, for example, at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn). The ratio of the sum of the atomic concentrations of indium, gallium, aluminum, and zinc to the sum of the atomic concentrations of metal elements contained in the oxide semiconductor layer 10 is, for example, 90% or more. In addition, the ratio of the sum of the atomic concentrations of indium, gallium, aluminum, and zinc to the sum of the atomic concentrations of elements other than oxygen contained in the oxide semiconductor layer 10 is, for example, 90% or more. For example, in the oxide semiconductor layer 10, there is no element other than oxygen that has an atomic concentration higher than any one of indium, gallium, aluminum, and zinc.

[0019] The atomic concentration of zinc (Zn) contained in the oxide semiconductor layer 10 is, for example, not less than 5 atomic % and not more than 20 atomic %.

[0020] The oxide semiconductor layer 10 has a first region 10a, a second region 10b, and a third region 10c. The third region 10c is a region between the first region 10a and the second region 10b.

[0021] The oxide semiconductor layer 10 includes, for example, oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 10 function as donors.

[0022] The oxide semiconductor layer 10 has a thickness of, for example, not less than 10 nm and not more than 100 nm.

[0023] The oxide semiconductor layer 10 is formed by, for example, an atomic layer deposition (ALD) method.

[0024] The gate electrode 12 is provided below the oxide semiconductor layer 10. The gate electrode 12 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 12 is, for example, titanium nitride (TiN) or tungsten (W). The gate length of the gate electrode 12 is, for example, 20 nm or more and 100 nm or less. The gate length of the gate electrode 12 is the length of the gate electrode 12 in the channel length direction.

[0025] The gate insulating layer 14 is provided between the oxide semiconductor layer 10 and the gate electrode 12. The gate insulating layer 14 is provided between the third region 10c and the gate electrode 12.

[0026] The gate insulating layer 14 is, for example, an oxide or an oxynitride. The gate insulating layer 14 is, for example, a silicon oxide or an aluminum oxide. The thickness of the gate insulating layer 14 is, for example, 2 nm or more and 10 nm or less.

[0027] It is also possible to provide an oxide layer (not shown) made of a material different from that of the gate insulating layer 14 between the oxide semiconductor layer 10 and the gate insulating layer 14 .

[0028] The source electrode 16 is provided on the upper side of the oxide semiconductor layer 10. The oxide semiconductor layer 10 is sandwiched between the gate electrode 12 and the source electrode 16.

[0029] The source electrode 16 is provided on the upper side of the first region 10a. The source electrode 16 is electrically connected to the first region 10a.

[0030] The source electrode 16 is, for example, a metal or a metal compound. The source electrode 16 is, for example, a metal having a different chemical composition than the barrier layer 20.

[0031] The source electrode 16 includes, for example, a second metal element. For example, among the atomic concentrations of the metal elements included in the source electrode 16, the atomic concentration of the second metal element is the highest.

[0032] The second metal element is, for example, at least one element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0033] The source electrode 16 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, molybdenum, or molybdenum nitride.

[0034] The second metal element contained in the source electrode 16 is, for example, the same as the first metal element contained in the barrier layer 20. In addition, the second metal element contained in the source electrode 16 is, for example, different from the first metal element contained in the barrier layer 20.

[0035] The thickness of the source electrode 16 is, for example, greater than the thickness of the contact layer 22. The thicknesses of the source electrode 16 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0036] The drain electrode 18 is provided on the upper side of the oxide semiconductor layer 10. The oxide semiconductor layer 10 is sandwiched between the gate electrode 12 and the drain electrode 18.

[0037] The drain electrode 18 is provided on the upper side of the second region 10b and is electrically connected to the second region 10b.

[0038] The drain electrode 18 includes, for example, a second metal element. For example, among the atomic concentrations of the metal elements included in the drain electrode 18, the atomic concentration of the second metal element is the highest.

[0039] The second metal element is, for example, at least one metal element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0040] Drain electrode 18 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, molybdenum, or molybdenum nitride.

[0041] The second metal element contained in the drain electrode 18 is, for example, the same as the first metal element contained in the barrier layer 20. In addition, the second metal element contained in the drain electrode 18 is, for example, different from the first metal element contained in the barrier layer 20.

[0042] The thickness of the drain electrode 18 is, for example, thicker than the thickness of the contact layer 22. The thicknesses of the drain electrode 18 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the drain electrode 18.

[0043] The barrier layer 20 is provided between the oxide semiconductor layer 10 and the source electrode 16. The barrier layer 20 is provided between the first region 10a and the source electrode 16. The barrier layer 20 is in contact with, for example, the source electrode 16. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 to the source electrode 16 side.

[0044] The barrier layer 20 is provided between the oxide semiconductor layer 10 and the drain electrode 18. The barrier layer 20 is provided between the second region 10b and the drain electrode 18. The barrier layer 20 is in contact with, for example, the drain electrode 18. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 to the drain electrode 18 side.

[0045] The barrier layer 20 contains a first metal element and at least one of oxygen (O) and nitrogen (N). For example, among the atomic concentrations of elements contained in the barrier layer 20 other than oxygen (O) and nitrogen (N), the atomic concentration of the first metal element is the highest.

[0046] The first metal element is, for example, at least one element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0047] Barrier layer 20 may be, for example, an oxide, nitride, or oxynitride.

[0048] The barrier layer 20 includes, for example, titanium (Ti) as a first metal element. The barrier layer 20 includes, for example, oxygen (O) and nitrogen (N). The barrier layer 20 is, for example, titanium oxide or titanium oxynitride.

[0049] The thickness of the barrier layer 20 is, for example, thinner than the thickness of the contact layer 22. The thicknesses of the barrier layer 20 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0050] The thickness of the barrier layer 20 is, for example, equal to or less than half the thickness of the contact layer 22. The thickness of the barrier layer 20 is, for example, equal to or more than 1 nm and equal to or less than 10 nm.

[0051] The barrier layer 20 is, for example, crystalline. The crystal grain size of the barrier layer 20 is, for example, smaller than the crystal grain size of the contact layer 22. The crystal grain sizes of the barrier layer 20 and the contact layer 22 are represented by, for example, the median value of the major axis of the crystal grain.

[0052] The barrier layer 20 is, for example, amorphous.

[0053] The barrier layer 20 is formed by, for example, a sputtering method or an ALD method, and is formed by, for example, oxidizing, nitriding, or oxynitriding a part of the source electrode 16 or the drain electrode 18.

[0054] The contact layer 22 is provided between the oxide semiconductor layer 10 and the barrier layer 20. The contact layer 22 is provided between the first region 10a and the source electrode 16. The contact layer 22 is also provided between the second region 10b and the drain electrode 18.

[0055] The contact layer 22 is in contact with, for example, the barrier layer 20. The contact layer 22 is in contact with, for example, the oxide semiconductor layer 10. The contact layer 22 is in contact with, for example, the first region 10a. The contact layer 22 is in contact with, for example, the second region 10b.

[0056] The contact layer 22 has a function of reducing the electrical resistance between the first region 10a and the source electrode 16. The contact layer 22 has a function of reducing the electrical resistance between the second region 10b and the drain electrode 18.

[0057] The contact layer 22 contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). The contact layer 22 is an oxide.

[0058] The contact layer 22 includes, for example, indium (In) and tin (Sn) The contact layer 22 is, for example, an oxide including indium (In) and tin (Sn).

[0059] The contact layer 22 is, for example, thicker than the barrier layer 20. The thicknesses of the contact layer 22 and the barrier layer 20 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0060] The thickness of the contact layer 22 is, for example, twice or more the thickness of the barrier layer 20. The thickness of the contact layer 22 is, for example, 5 nm or more and 30 nm or less.

[0061] The contact layer 22 is, for example, crystalline.

[0062] The contact layer 22 is formed by, for example, a sputtering method or an ALD method.

[0063] The first insulating layer 24 is provided under the oxide semiconductor layer 10. The first insulating layer 24 is, for example, an oxide, a nitride, or an oxynitride. The first insulating layer 24 is, for example, a silicon oxide, a silicon nitride, or a silicon oxynitride.

[0064] The second insulating layer 26 is provided on the upper side of the oxide semiconductor layer 10. The second insulating layer 26 is provided between the source electrode 16 and the drain electrode 18.

[0065] The second insulating layer 26 electrically separates the source electrode 16 from the drain electrode 18. The second insulating layer 26 is, for example, an oxide, a nitride, or an oxynitride. The second insulating layer 26 is, for example, a silicon oxide, a silicon nitride, or a silicon oxynitride.

[0066] The operation and effects of the semiconductor device of the first embodiment will be described below.

[0067] For example, when an oxide semiconductor transistor is used as a switching transistor of a memory cell, the oxide semiconductor transistor undergoes heat treatment associated with the formation of the memory cell and wirings, and the threshold voltage of the oxide semiconductor transistor may vary due to the heat treatment.

[0068] The threshold voltage of an oxide semiconductor transistor fluctuates when oxygen in an oxide semiconductor layer where a channel is formed escapes to the source electrode or drain electrode side, causing oxygen vacancies in the oxide semiconductor layer.

[0069] The oxygen vacancies function as donors in the oxide semiconductor layer. Therefore, for example, when the oxide semiconductor transistor is an n-channel transistor, the occurrence of oxygen vacancies reduces the threshold voltage of the oxide semiconductor transistor.

[0070] The transistor 100 of the first embodiment includes a barrier layer 20 that suppresses diffusion of oxygen between the oxide semiconductor layer 10 and the source electrode 16 and between the oxide semiconductor layer 10 and the drain electrode 18. The provision of the barrier layer 20 suppresses oxygen in the oxide semiconductor layer 10 from escaping to the side of the source electrode 16 or the drain electrode 18. Therefore, fluctuations in the threshold voltage of the transistor 100 are suppressed.

[0071] From the viewpoint of suppressing oxygen diffusion and reducing the electrical resistivity of the barrier layer 20, the barrier layer 20 preferably contains at least one first metal element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo), and at least one element of oxygen (O) and nitrogen (N). Of the atomic concentrations of elements contained in the barrier layer 20 other than oxygen (O) and nitrogen (N), the atomic concentration of the first metal element is the highest.

[0072] The barrier layer 20 is preferably titanium oxynitride from the viewpoint of suppressing oxygen diffusion and reducing the electrical resistivity of the barrier layer 20. The barrier layer 20 preferably contains titanium (Ti), oxygen (O), and nitrogen (N). The first metal element is preferably titanium (Ti).

[0073] From the viewpoint of suppressing oxygen diffusion, it is preferable that the crystal grain size of the barrier layer 20 is small. From the viewpoint of suppressing oxygen diffusion, it is preferable that the crystal grain size of the barrier layer 20 is smaller than the crystal grain size of the contact layer 22. Furthermore, from the viewpoint of suppressing oxygen diffusion, it is preferable that the barrier layer 20 is amorphous.

[0074] The thickness of the barrier layer 20 is preferably 1 nm or more and 10 nm or less, and more preferably 2 nm or more and 8 nm or less. By exceeding the lower limit, the effect of suppressing oxygen diffusion is improved. By being below the upper limit, the resistance of the barrier layer 20 is reduced, and the electrical resistance between the source electrode 16 and the oxide semiconductor layer 10 can be reduced. In addition, the electrical resistance between the drain electrode 18 and the oxide semiconductor layer 10 can be reduced.

[0075] The transistor 100 of the first embodiment includes a contact layer 22 between the oxide semiconductor layer 10 and the barrier layer 20. By including the contact layer 22, the contact resistance is reduced compared to, for example, a case where the barrier layer 20 is in direct contact with the oxide semiconductor layer 10 without providing the contact layer 22.

[0076] The contact layer 22 of the transistor 100 is an oxide containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). Since the contact layer 22 is an oxide containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O), it is possible to suppress the formation of a high-resistance reaction product due to heat treatment between the oxide semiconductor layer 10 and the contact layer 22. Therefore, the contact resistance between the oxide semiconductor layer 10 and the contact layer 22 can be reduced.

[0077] From the viewpoint of reducing the contact resistance between the oxide semiconductor layer 10 and the contact layer 22, the contact layer 22 is preferably an oxide containing indium (In) and tin (Sn).

[0078] The thickness of the barrier layer 20 is preferably thinner than the thickness of the contact layer 22. The thickness of the barrier layer 20 is preferably equal to or less than half the thickness of the contact layer 22, and more preferably equal to or less than one-third the thickness of the contact layer 22.

[0079] The thickness of the contact layer 22 is preferably greater than the thickness of the barrier layer 20. The thickness of the contact layer 22 is preferably at least twice as thick as the barrier layer 20, and more preferably at least three times as thick.

[0080] The electrical resistivity of the barrier layer 20 is higher than that of the contact layer 22. By making the thickness of the barrier layer 20 thinner than that of the contact layer 22, in other words, by making the thickness of the contact layer 22 thicker than that of the barrier layer 20, for example, the electrical resistance between the source electrode 16 and the oxide semiconductor layer 10 can be reduced. Also, the electrical resistance between the drain electrode 18 and the oxide semiconductor layer 10 can be reduced.

[0081] The thickness of the source electrode 16 is preferably greater than the thickness of the contact layer 22. The thickness of the drain electrode 18 is preferably greater than the thickness of the contact layer 22. The electrical resistivities of the source electrode 16 and the drain electrode 18 are lower than the electrical resistivity of the contact layer 22.

[0082] By making the source electrode 16 thicker than the contact layer 22, the wiring resistance can be reduced when the source electrode 16 is used as wiring. By making the drain electrode 18 thicker than the contact layer 22, the wiring resistance can be reduced when the drain electrode 18 is used as wiring.

[0083] From the viewpoints of heat resistance, resistance, and manufacturing, the source electrode 16 or the drain electrode 18 preferably contains at least one second metal element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo). Among the atomic concentrations of the metal elements contained in the source electrode 16 or the drain electrode 18, the atomic concentration of the second metal element is the highest.

[0084] From the viewpoints of heat resistance, resistance, and manufacturing, the source electrode 16 or the drain electrode 18 more preferably contains titanium (Ti) or tungsten (W). The second metal element is more preferably titanium (Ti) or tungsten (W). The source electrode 16 or the drain electrode 18 is more preferably titanium nitride or tungsten.

[0085] The second metal element contained in the source electrode 16 or the drain electrode 18 is preferably the same as the first metal element contained in the barrier layer 20. By making the second metal element contained in the source electrode 16 or the drain electrode 18 the same as the first metal element contained in the barrier layer 20, it is possible to form the barrier layer 20 by oxidizing, nitriding, or oxynitriding the source electrode 16 or the drain electrode 18.

[0086] It is preferable that the source electrode 16 or the drain electrode 18 is titanium nitride, and the barrier layer 20 is titanium oxynitride. In this case, the first metal element and the second metal element are titanium (Ti). In this case, the barrier layer 20 can be formed by oxidizing the source electrode 16 or the drain electrode 18.

[0087] The second metal element contained in the source electrode 16 or the drain electrode 18 is preferably different from the first metal element contained in the barrier layer 20. By making the second metal element contained in the source electrode 16 or the drain electrode 18 a metal element different from the first metal element contained in the barrier layer 20, it is possible to form the source electrode 16 or the drain electrode 18 and the barrier layer 20 independently.

[0088] It is preferable that the source electrode 16 or the drain electrode 18 is tungsten, and the barrier layer 20 is titanium oxynitride. In this case, the first metal element is titanium (Ti) and the second metal element is tungsten (W).

[0089] As described above, according to the first embodiment, the variation in threshold voltage after heat treatment is suppressed, and an oxide semiconductor transistor having high heat resistance is realized.

[0090] Second Embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the gate electrode surrounds the oxide semiconductor layer. In the following, some of the contents that overlap with the first embodiment may be omitted.

[0091] Figures 2 and 3 are schematic cross-sectional views of a semiconductor device according to a second embodiment. Figure 3 is a cross-sectional view taken along line AA' in Figure 2. In Figure 2, the horizontal direction is referred to as a first direction, the depth direction as a second direction, and the up-down direction as a third direction.

[0092] The semiconductor device of the second embodiment is a transistor 200. The transistor 200 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The transistor 200 is a so-called surrounding gate transistor (SGT) in which a gate electrode is provided to surround an oxide semiconductor layer in which a channel is formed. The transistor 200 is a so-called vertical transistor.

[0093] The transistor 200 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, a contact layer 22, and an interlayer insulating layer 32. The source electrode 16 is an example of a first electrode. The drain electrode 18 is an example of a second electrode. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer.

[0094] The oxide semiconductor layer 10 is provided between the source electrode 16 and the drain electrode 18. A channel that serves as a current path is formed in the oxide semiconductor layer 10 when the transistor 200 is in an on-operation state. The oxide semiconductor layer 10 extends in a third direction. The oxide semiconductor layer 10 has a columnar shape extending in the third direction. The oxide semiconductor layer 10 has, for example, a cylindrical shape.

[0095] The direction in which electrons flow in the channel is called the channel length direction. The third direction is the channel length direction of the transistor 200.

[0096] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.

[0097] The oxide semiconductor layer 10 contains, for example, at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn). The ratio of the sum of the atomic concentrations of indium, gallium, aluminum, and zinc to the sum of the atomic concentrations of metal elements contained in the oxide semiconductor layer 10 is, for example, 90% or more. In addition, the ratio of the sum of the atomic concentrations of indium, gallium, aluminum, and zinc to the sum of the atomic concentrations of elements other than oxygen contained in the oxide semiconductor layer 10 is, for example, 90% or more. For example, in the oxide semiconductor layer 10, there is no element other than oxygen that has an atomic concentration higher than any one of indium, gallium, aluminum, and zinc.

[0098] The atomic concentration of zinc (Zn) contained in the oxide semiconductor layer 10 is, for example, not less than 5 atomic % and not more than 20 atomic %.

[0099] The oxide semiconductor layer 10 has a first region 10a, a second region 10b, and a third region 10c. The third region 10c is a region between the first region 10a and the second region 10b.

[0100] The oxide semiconductor layer 10 includes, for example, oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 10 function as donors.

[0101] The width of the oxide semiconductor layer 10 in the first direction is, for example, not less than 20 nm and not more than 100 nm, and the length of the oxide semiconductor layer 10 in the third direction is, for example, not less than 80 nm and not more than 200 nm.

[0102] The oxide semiconductor layer 10 is formed by, for example, an ALD method.

[0103] The gate electrode 12 is provided to surround the oxide semiconductor layer 10. The gate electrode 12 is provided around the oxide semiconductor layer 10.

[0104] The gate electrode 12 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 12 is, for example, titanium nitride (TiN) or tungsten (W). The gate length of the gate electrode 12 is, for example, 20 nm or more and 100 nm or less. The gate length of the gate electrode 12 is the length of the gate electrode 12 in the third direction.

[0105] The gate insulating layer 14 is provided between the oxide semiconductor layer 10 and the gate electrode 12. The gate insulating layer 14 is provided to surround the oxide semiconductor layer 10. The gate insulating layer 14 is provided between the third region 10c and the gate electrode 12.

[0106] The gate insulating layer 14 is, for example, an oxide or an oxynitride. The gate insulating layer 14 is, for example, a silicon oxide or an aluminum oxide. The thickness of the gate insulating layer 14 is, for example, 2 nm or more and 10 nm or less.

[0107] It is also possible to provide an oxide layer (not shown) made of a material different from that of the gate insulating layer 14 between the oxide semiconductor layer 10 and the gate insulating layer 14 .

[0108] The source electrode 16 is provided below the oxide semiconductor layer 10. The source electrode 16 is provided below the first region 10a. The source electrode 16 is electrically connected to the first region 10a.

[0109] The source electrode 16 is, for example, a metal or a metal compound. The source electrode 16 is, for example, a metal having a different chemical composition than the barrier layer 20.

[0110] The source electrode 16 includes, for example, a second metal element. For example, among the atomic concentrations of the metal elements included in the source electrode 16, the atomic concentration of the second metal element is the highest.

[0111] The second metal element is, for example, at least one element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0112] The source electrode 16 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, molybdenum, or molybdenum nitride.

[0113] The second metal element contained in the source electrode 16 is, for example, the same as the first metal element contained in the barrier layer 20. In addition, the second metal element contained in the source electrode 16 is, for example, different from the first metal element contained in the barrier layer 20.

[0114] The thickness of the source electrode 16 is, for example, greater than the thickness of the contact layer 22. The thicknesses of the source electrode 16 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0115] The drain electrode 18 is provided on the upper side of the oxide semiconductor layer 10. The drain electrode 18 is provided on the upper side of the second region 10b. The drain electrode 18 is electrically connected to the second region 10b.

[0116] The drain electrode 18 includes, for example, a second metal element. For example, among the atomic concentrations of the metal elements included in the drain electrode 18, the atomic concentration of the second metal element is the highest.

[0117] The second metal element is, for example, at least one metal element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0118] Drain electrode 18 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, molybdenum, or molybdenum nitride.

[0119] The second metal element contained in the drain electrode 18 is, for example, the same as the first metal element contained in the barrier layer 20. In addition, the second metal element contained in the drain electrode 18 is, for example, different from the first metal element contained in the barrier layer 20.

[0120] The thickness of the drain electrode 18 is, for example, thicker than the thickness of the contact layer 22. The thicknesses of the drain electrode 18 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the drain electrode 18.

[0121] The barrier layer 20 is provided between the oxide semiconductor layer 10 and the source electrode 16. The barrier layer 20 is provided between the first region 10a and the source electrode 16. The barrier layer 20 is in contact with, for example, the source electrode 16. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 to the source electrode 16 side.

[0122] The barrier layer 20 is provided between the oxide semiconductor layer 10 and the drain electrode 18. The barrier layer 20 is provided between the second region 10b and the drain electrode 18. The barrier layer 20 is in contact with, for example, the drain electrode 18. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 to the drain electrode 18 side.

[0123] The barrier layer 20 contains a first metal element and at least one of oxygen (O) and nitrogen (N). For example, among the atomic concentrations of elements contained in the barrier layer 20 other than oxygen (O) and nitrogen (N), the atomic concentration of the first metal element is the highest.

[0124] The first metal element is, for example, at least one element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0125] Barrier layer 20 may be, for example, an oxide, nitride, or oxynitride.

[0126] The barrier layer 20 includes, for example, titanium (Ti) as a first metal element. The barrier layer 20 includes, for example, oxygen (O) and nitrogen (N). The barrier layer 20 is, for example, titanium oxide or titanium oxynitride.

[0127] The thickness of the barrier layer 20 is, for example, thinner than the thickness of the contact layer 22. The thicknesses of the barrier layer 20 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0128] The thickness of the barrier layer 20 is, for example, equal to or less than half the thickness of the contact layer 22. The thickness of the barrier layer 20 is, for example, equal to or more than 1 nm and equal to or less than 10 nm.

[0129] The barrier layer 20 is, for example, crystalline. The crystal grain size of the barrier layer 20 is, for example, smaller than the crystal grain size of the contact layer 22. The crystal grain sizes of the barrier layer 20 and the contact layer 22 are represented by, for example, the median value of the major axis of the crystal grain.

[0130] The barrier layer 20 is, for example, amorphous.

[0131] The contact layer 22 is provided between the oxide semiconductor layer 10 and the barrier layer 20. The contact layer 22 is provided between the first region 10a and the source electrode 16. The contact layer 22 is also provided between the second region 10b and the drain electrode 18.

[0132] The contact layer 22 is in contact with, for example, the barrier layer 20. The contact layer 22 is in contact with, for example, the oxide semiconductor layer 10. The contact layer 22 is in contact with, for example, the first region 10a. The contact layer 22 is in contact with, for example, the second region 10b.

[0133] The contact layer 22 has a function of reducing the resistance between the first region 10a and the source electrode 16. The contact layer 22 has a function of reducing the resistance between the second region 10b and the drain electrode .

[0134] The contact layer 22 contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). The contact layer 22 is an oxide.

[0135] The contact layer 22 includes, for example, indium (In) and tin (Sn) The contact layer 22 is, for example, an oxide including indium (In) and tin (Sn).

[0136] The contact layer 22 is, for example, thicker than the barrier layer 20. The thicknesses of the contact layer 22 and the barrier layer 20 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0137] The thickness of the contact layer 22 is, for example, twice or more the thickness of the barrier layer 20. The thickness of the contact layer 22 is, for example, 5 nm or more and 30 nm or less.

[0138] The contact layer 22 is, for example, crystalline.

[0139] The contact layer 22 is formed by, for example, a sputtering method or an ALD method.

[0140] The interlayer insulating layer 32 is provided around the gate electrode 12, the source electrode 16, and the drain electrode 18. The interlayer insulating layer 32 is, for example, an oxide, a nitride, or an oxynitride. The interlayer insulating layer 32 is, for example, a silicon oxide, a silicon nitride, or a silicon oxynitride.

[0141] As described above, according to the second embodiment, as in the first embodiment, the variation in threshold voltage after heat treatment is suppressed, and an oxide semiconductor transistor having high heat resistance is realized. In addition, according to the second embodiment, the use of SGT makes it possible to arrange transistors at a high density per unit area.

[0142] (Third embodiment) The semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction intersecting the first direction, and a memory cell, the memory cell including a first region, a second region, and a third region between the first region and the second region, the first region being electrically connected to the first wiring, an oxide semiconductor layer in which the third region is surrounded by a part of the second wiring, a gate insulating layer provided between the third region and a part of the second wiring, a first electrode electrically connected to the second region, a second electrode, and a gate insulating layer between the first electrode and the second electrode. and an insulating layer between the first region and the first wiring, a first conductive layer provided at least at one of positions between the second region and the first electrode and between the first region and the first electrode, the first conductive layer including at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O), and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer and including at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd). Hereinafter, some of the contents that overlap with the first or second embodiment may be omitted.

[0143] The semiconductor memory device of the third embodiment is a semiconductor memory 300. The semiconductor memory device of the third embodiment is a dynamic random access memory (DRAM). The semiconductor memory 300 uses the transistor 200 of the second embodiment as a switching transistor of a memory cell of the DRAM.

[0144] FIG. 4 is a block diagram of a semiconductor memory device according to the third embodiment.

[0145] As shown in FIG. 4, the semiconductor memory 300 includes a memory cell array 210, a word line driver circuit 212, a row decoder circuit 214, a sense amplifier circuit 215, a column decoder circuit 217, and a control circuit 221.

[0146] 5 and 6 are schematic cross-sectional views of a memory cell array of a semiconductor memory device according to a third embodiment. FIG. 5 is a cross-sectional view of a plane including a first direction and a third direction, and FIG. 6 is a cross-sectional view of a plane including a second direction and a third direction. The first direction and the second direction intersect. The first direction and the second direction are, for example, perpendicular. The third direction is a direction perpendicular to the first direction and the second direction. The third direction is, for example, a direction perpendicular to a substrate.

[0147] The memory cell array 210 of the third embodiment has a three-dimensional structure in which memory cells are arranged three-dimensionally. Each of the areas surrounded by dashed lines in Figures 5 and 6 represents one memory cell.

[0148] The memory cell array 210 includes a silicon substrate 250 .

[0149] The memory cell array 210 includes, for example, a plurality of bit lines BL and a plurality of word lines WL on a silicon substrate 250. The bit lines BL extend in a first direction. The word lines WL extend in a second direction.

[0150] The bit lines BL and the word lines WL intersect, for example, perpendicularly. Memory cells are arranged in the regions where the bit lines BL and the word lines WL intersect. The memory cells include a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 and the second memory cell MC2 are examples of memory cells.

[0151] The bit line BL connected to the first memory cell MC1 and the second memory cell MC2 is the bit line BLx. The bit line BLx is an example of a first wiring. The word line WL connected to the first memory cell MC1 is the word line WLx. The word line WLx is an example of a second wiring.

[0152] The word line WL connected to the second memory cell MC2 is the word line WLy. The word line WLx is provided on one side of the bit line BLx. The word line WLy is provided on the other side of the bit line BLx.

[0153] The memory cell array 210 has a plurality of plate electrode lines PL. The plate electrode lines PL are connected to the plate electrodes 72 of the respective memory cells.

[0154] The memory cell array 210 includes an interlayer insulating layer 260 for electrical isolation of each wiring and each electrode.

[0155] The word lines WL are electrically connected to a row decoder circuit 214. The bit lines BL are electrically connected to a sense amplifier circuit 215.

[0156] The row decoder circuit 214 has a function of selecting a word line WL in accordance with an input row address signal, and the word line driver circuit 212 has a function of applying a predetermined voltage to the word line WL selected by the row decoder circuit 214.

[0157] The column decoder circuit 217 has a function of selecting a bit line BL according to an input column address signal. The sense amplifier circuit 215 has a function of applying a predetermined voltage to the bit line BL selected by the column decoder circuit 217. The sense amplifier circuit 215 also has a function of detecting and amplifying the potential of the bit line BL.

[0158] The control circuit 221 has a function of controlling the word line driver circuit 212, the row decoder circuit 214, the sense amplifier circuit 215, the column decoder circuit 217, and other circuits (not shown).

[0159] Circuits such as the word line driver circuit 212, the row decoder circuit 214, the sense amplifier circuit 215, the column decoder circuit 217, and the control circuit 221 are configured by, for example, transistors and wiring layers (not shown). The transistors are formed by using, for example, a silicon substrate 250.

[0160] The bit lines BL and the word lines WL are, for example, made of metal, or have a laminated structure of titanium nitride, tungsten, or titanium nitride and tungsten.

[0161] Fig. 7 is a schematic cross-sectional view of a first memory cell of the semiconductor memory device of the third embodiment. Fig. 8 is a schematic cross-sectional view of a second memory cell of the semiconductor memory device of the third embodiment.

[0162] The first memory cell MC1 is provided between the silicon substrate 250 and the bit line BLx. The bit line BLx is provided between the silicon substrate 250 and the second memory cell MC2.

[0163] The first memory cell MC1 is provided below the bit line BLx, and the second memory cell MC2 is provided above the bit line BLx.

[0164] The first memory cell MC1 is provided on one side of the bit line BLx, and the second memory cell MC2 is provided on the other side of the bit line BLx.

[0165] The second memory cell MC2 has a structure obtained by inverting the first memory cell MC1 upside down. Each of the first memory cell MC1 and the second memory cell MC2 includes a transistor 200 and a capacitor 201.

[0166] The transistor 200 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, and a contact layer 22. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer. The transistor 200 has a similar configuration to the transistor 200 of the second embodiment.

[0167] The oxide semiconductor layer 10 has a first region 10a, a second region 10b, and a third region 10c. The third region 10c is a region between the first region 10a and the second region 10b.

[0168] The capacitor 201 includes a cell electrode 71, a plate electrode 72, and a capacitor insulating film 73. The cell electrode 71 and the plate electrode 72 are made of, for example, titanium nitride. The capacitor insulating film 73 has a laminated structure of, for example, zirconium oxide, aluminum oxide, and zirconium oxide.

[0169] The cell electrode 71 is an example of a first electrode. The plate electrode 72 is an example of a second electrode. The capacitor insulating film 73 is an example of an insulating layer.

[0170] The capacitor 201 is electrically connected to one end of the oxide semiconductor layer 10 of the first memory cell MC1 and the second memory cell MC2. The cell electrode 71 of the capacitor 201 is connected to the drain electrode 18. The plate electrode 72 is connected to the plate electrode line PL. The drain electrode 18 can be considered as a part of the cell electrode 71.

[0171] The source electrode 16 is connected to a bit line BL. The gate electrode 12 is connected to a word line WL. The source electrode 16 can be considered as a part of the bit line BL.

[0172] 5, 6, 7, and 8 show an example in which the bit line BL and the source electrode 16, and the word line WL and the gate electrode 12 are simultaneously formed of the same material. The bit line BL and the source electrode 16, and the word line WL and the gate electrode 12 may be separately formed of different materials.

[0173] The bit line BLx includes, for example, a second metal element, and for example, the atomic concentration of the second metal element is the highest among the atomic concentrations of the metal elements included in the bit line BLx.

[0174] The second metal element is, for example, at least one element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0175] The bit lines BLx are made of, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, molybdenum, or molybdenum nitride.

[0176] The second metal element contained in the bit line BLx is, for example, the same as the first metal element contained in the barrier layer 20. In addition, the second metal element contained in the bit line BLx is, for example, different from the first metal element contained in the barrier layer 20.

[0177] The cell electrode 71 contains, for example, a second metal element. For example, among the atomic concentrations of the metal elements contained in the cell electrode 71, the atomic concentration of the second metal element is the highest.

[0178] The second metal element is, for example, at least one metal element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0179] The cell electrodes 71 are, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, molybdenum, or molybdenum nitride.

[0180] The second metal element contained in the cell electrode 71 is, for example, the same as the first metal element contained in the barrier layer 20. In addition, the second metal element contained in the drain electrode 18 is, for example, different from the first metal element contained in the barrier layer 20.

[0181] The bit line BLx is electrically connected to the end (other end) of the oxide semiconductor layer 10 of the first memory cell MC1 opposite to the end to which the capacitor 201 is connected. The bit line BLx is electrically connected to the end (other end) of the oxide semiconductor layer 10 of the second memory cell MC2 opposite to the end to which the capacitor 201 is connected.

[0182] A word line WLx is electrically connected to the gate electrode 12 of the first memory cell MC1, and a word line WLy is electrically connected to the gate electrode 12 of the second memory cell MC2.

[0183] The transistor 200 includes a barrier layer 20 between the oxide semiconductor layer 10 and the source electrode 16 and the drain electrode 18. In addition, a contact layer 22 is included between the oxide semiconductor layer 10 and the barrier layer 20.

[0184] When an oxide semiconductor transistor is used as a switching transistor of a memory cell of a DRAM, the transistor is subjected to a high-temperature and long-time heat treatment after the transistor is formed. The heat treatment is, for example, a heat treatment for forming a capacitor. The high-temperature and long-time heat treatment is likely to cause a fluctuation in the threshold voltage of the oxide semiconductor transistor.

[0185] The transistor 200 includes a barrier layer 20 between the oxide semiconductor layer 10 and the source electrode 16 and drain electrode 18. Therefore, even if a high-temperature, long-time heat treatment is performed after the transistor is formed, the fluctuation of the threshold voltage is suppressed.

[0186] Furthermore, the transistor 200 includes a contact layer 22 between the oxide semiconductor layer 10 and the barrier layer 20. This reduces the contact resistance, thereby increasing the on-current of the transistor 200.

[0187] The thickness of the bit line BLx is preferably thicker than the thickness of the contact layer 22. The thickness of the bit line BLx and the thickness of the contact layer 22 are thicknesses in the third direction.

[0188] The electrical resistivity of the bit line BLx is lower than that of the contact layer 22. By making the thickness of the bit line BLx thicker than the thickness of the contact layer 22, the wiring resistance of the bit line BLx can be reduced.

[0189] The thickness of the cell electrode 71 is preferably greater than the thickness of the contact layer 22. The thickness of the cell electrode 71 and the thickness of the contact layer 22 are the thicknesses in the third direction.

[0190] According to the third embodiment, by using the transistor 200 of the second embodiment as a switching transistor of a DRAM, the fluctuation of the threshold voltage after heat treatment is suppressed, and a semiconductor memory with high heat resistance is realized.

[0191] (Fourth embodiment) The semiconductor device of the fourth embodiment includes an oxide semiconductor layer, an electrode, a first conductive layer provided between the oxide semiconductor layer and the electrode and containing a first metal element, and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer and containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). Hereinafter, some of the contents that overlap with the first embodiment may be omitted.

[0192] FIG. 9 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment.

[0193] The semiconductor device of the fourth embodiment includes a contact structure 400. The contact structure 400 includes an oxide semiconductor layer 10, a barrier layer 20, a contact layer 22, a wiring layer 40, a contact plug 42, and an interlayer insulating layer 44. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer. The contact plug 42 is an example of an electrode.

[0194] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.

[0195] The oxide semiconductor layer 10 contains, for example, at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn). The ratio of the sum of the atomic concentrations of indium, gallium, aluminum, and zinc to the sum of the atomic concentrations of metal elements contained in the oxide semiconductor layer 10 is, for example, 90% or more. In addition, the ratio of the sum of the atomic concentrations of indium, gallium, aluminum, and zinc to the sum of the atomic concentrations of elements other than oxygen contained in the oxide semiconductor layer 10 is, for example, 90% or more. For example, in the oxide semiconductor layer 10, there is no element other than oxygen that has an atomic concentration higher than any one of indium, gallium, aluminum, and zinc.

[0196] The wiring layer 40 is, for example, a metal or a metal compound.

[0197] The contact plug 42 is provided between the oxide semiconductor layer 10 and the wiring layer 40 .

[0198] The contact plug 42 is, for example, a metal or a metal compound. The contact plug 42 is, for example, a metal having a different chemical composition from the barrier layer 20.

[0199] The contact plug 42 includes, for example, a second metal element. For example, among the atomic concentrations of the metal elements included in the contact plug 42, the atomic concentration of the second metal element is the highest.

[0200] The second metal element is, for example, at least one element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0201] The contact plug 42 is made of, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, molybdenum, or molybdenum nitride.

[0202] The second metal element contained in the contact plug 42 is, for example, the same as the first metal element contained in the barrier layer 20. In addition, the second metal element contained in the contact plug 42 is, for example, different from the first metal element contained in the barrier layer 20.

[0203] The thickness of the contact plug 42 is, for example, thicker than the thickness of the contact plug 42. The thickness of the contact plug 42 and the thickness of the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the contact plug 42.

[0204] The barrier layer 20 is provided between the oxide semiconductor layer 10 and the contact plug 42. The barrier layer 20 is in contact with, for example, the contact plug 42. The barrier layer 20 functions as a diffusion barrier for oxygen diffusing from the oxide semiconductor layer 10 toward the contact plug 42 side.

[0205] The barrier layer 20 contains a first metal element and at least one of oxygen (O) and nitrogen (N). For example, among the atomic concentrations of elements contained in the barrier layer 20 other than oxygen (O) and nitrogen (N), the atomic concentration of the first metal element is the highest.

[0206] The first metal element is, for example, at least one metal element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo).

[0207] Barrier layer 20 may be, for example, an oxide, nitride, or oxynitride.

[0208] The barrier layer 20 contains, for example, titanium (Ti) as a first metal element. The barrier layer 20 contains, for example, oxygen (O) and nitrogen (N). The barrier layer 20 is titanium oxide or titanium oxynitride.

[0209] The thickness of the barrier layer 20 is, for example, thinner than the thickness of the contact layer 22. The thicknesses of the barrier layer 20 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the contact plug 42.

[0210] The thickness of the barrier layer 20 is, for example, equal to or less than half the thickness of the contact layer 22. The thickness of the barrier layer 20 is, for example, equal to or more than 1 nm and equal to or less than 10 nm.

[0211] The barrier layer 20 is, for example, crystalline. The crystal grain size of the barrier layer 20 is, for example, smaller than the crystal grain size of the contact layer 22. The crystal grain sizes of the barrier layer 20 and the contact layer 22 are represented by, for example, the median value of the major axis of the crystal grain.

[0212] The barrier layer 20 is, for example, amorphous.

[0213] The barrier layer 20 is formed by, for example, a sputtering method or an ALD method, and is formed by, for example, oxidizing, nitriding, or oxynitriding a part of the contact plug 42.

[0214] The contact layer 22 is provided between the oxide semiconductor layer 10 and the barrier layer 20. The contact layer 22 is in contact with, for example, the barrier layer 20. The contact layer 22 is in contact with, for example, the oxide semiconductor layer 10.

[0215] The contact layer 22 has a function of reducing the electrical resistance between the oxide semiconductor layer 10 and the contact plug 42 .

[0216] The contact layer 22 contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). The contact layer 22 is an oxide.

[0217] The contact layer 22 includes, for example, indium (In) and tin (Sn) The contact layer 22 is, for example, an oxide including indium (In) and tin (Sn).

[0218] The contact layer 22 is, for example, thicker than the barrier layer 20. The thicknesses of the contact layer 22 and the barrier layer 20 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the contact plug 42.

[0219] The thickness of the contact layer 22 is, for example, twice or more the thickness of the barrier layer 20. The thickness of the contact layer 22 is, for example, 5 nm or more and 30 nm or less.

[0220] The contact layer 22 is, for example, crystalline.

[0221] The contact layer 22 is formed by, for example, a sputtering method or an ALD method.

[0222] The interlayer insulating layer 44 is provided between the oxide semiconductor layer 10 and the wiring layer 40. The interlayer insulating layer 44 is made of, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0223] If the contact structure 400 does not include the barrier layer 20, oxygen in the oxide semiconductor layer escapes to the contact plug 42 side due to heat treatment applied after the formation of the contact structure 400. The escape of oxygen in the oxide semiconductor layer causes oxygen vacancies in the oxide semiconductor layer. The oxygen vacancies function as donors in the oxide semiconductor layer.

[0224] When the concentration of donors in the oxide semiconductor layer 10 under the contact plug 42 changes, the contact resistance between the oxide semiconductor layer 10 and the contact plug 42 fluctuates. The contact resistance between the oxide semiconductor layer 10 and the contact plug 42 becomes unstable.

[0225] The contact structure 400 includes a barrier layer 20 between the oxide semiconductor layer 10 and the contact plug 42. The provision of the barrier layer 20 suppresses changes in the concentration of donors in the oxide semiconductor layer 10. Therefore, the contact resistance between the oxide semiconductor layer 10 and the contact plug 42 is stabilized.

[0226] Furthermore, the contact structure 400 includes the contact layer 22 between the oxide semiconductor layer 10 and the barrier layer 20. Therefore, the contact resistance between the oxide semiconductor layer 10 and the contact plug 42 is reduced.

[0227] As described above, according to the fourth embodiment, the variation in contact resistance after heat treatment is suppressed, and a semiconductor device with high heat resistance is realized.

[0228] In the first to fourth embodiments, a transistor in which the barrier layer 20 and the contact layer 22 are provided both between the first region 10a and the source electrode 16 and between the second region 10b and the drain electrode 18 has been described as an example. However, it is also possible to provide a transistor in which the barrier layer 20 and the contact layer 22 are provided only in one of the positions between the first region 10a and the source electrode 16 and between the second region 10b and the drain electrode 18.

[0229] In the first to fourth embodiments, the oxide semiconductor layer 10 is a metal oxide containing at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn), but other metal oxides may also be used for the oxide semiconductor layer 10.

[0230] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0231] 10 Oxide semiconductor layer 10a First Area 10b The second area 10c The third area 12 Gate electrode 14 Gate insulating layer 16 Source electrode (first electrode) 18 Drain electrode (second electrode) 20 Barrier layer (first conductive layer) 22 Contact layer (second conductive layer) 71 Cell electrode (first electrode) 72 Plate electrode (second electrode) 73 Capacitor insulating film (insulating layer) 100 Transistor (semiconductor device) 200 Transistors (semiconductor devices) 201 Capacitor 300 Semiconductor memory (semiconductor storage device) BLx bit line (first wiring) MC1 First memory cell (memory cell) WLx Word line (second wiring)

Claims

1. an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; A gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; a first conductive layer provided at least one of a position between the first region and the first electrode and a position between the second region and the second electrode, the first conductive layer including oxygen (O), nitrogen (N) and a first metal element; a second conductive layer provided between the oxide semiconductor layer and the first conductive layer, containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O), and having a thickness greater than that of the first conductive layer; Equipped with The semiconductor device, wherein the first metal element is titanium (Ti).

2. 2. The semiconductor device according to claim 1, wherein a thickness of the first electrode having the first conductive layer provided between it and the oxide semiconductor layer, or a thickness of the second electrode having the first conductive layer provided between it and the oxide semiconductor layer, is thicker than a thickness of the second conductive layer.

3. 3. The semiconductor device according to claim 1, wherein the first conductive layer has a thickness of 1 nm or more and 10 nm or less.

4. 4. The semiconductor device according to claim 1, wherein the atomic concentration of the first metal element is the highest among atomic concentrations of elements other than oxygen (O) and nitrogen (N) contained in the first conductive layer.

5. at least one of the first electrode having the first conductive layer provided between it and the oxide semiconductor layer and the second electrode having the first conductive layer provided between it and the oxide semiconductor layer contains a second metal element; the atomic concentration of the second metal element is the highest among the atomic concentrations of the metal elements contained in the at least one of the electrodes; 5. The semiconductor device according to claim 1, wherein the second metal element is the same as the first metal element.

6. at least one of the first electrode having the first conductive layer provided between it and the oxide semiconductor layer and the second electrode having the first conductive layer provided between it and the oxide semiconductor layer contains a second metal element; the atomic concentration of the second metal element is the highest among the atomic concentrations of the metal elements contained in the at least one of the electrodes; 5. The semiconductor device according to claim 1, wherein the second metal element is different from the first metal element.

7. an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; A gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; a first conductive layer provided at least at one of the positions between the first region and the first electrode and between the second region and the second electrode, the first conductive layer including at least one first metal element selected from the group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo), oxygen (O), and nitrogen (N), and the atomic concentration of the first metal element is the highest among atomic concentrations of elements other than oxygen (O) and nitrogen (N) contained in the first conductive layer; a second conductive layer provided between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O); Equipped with The semiconductor device, wherein the first metal element is titanium (Ti).

8. an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; A gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; a first conductive layer provided at least one of a position between the first region and the first electrode and a position between the second region and the second electrode, the first conductive layer including oxygen (O), nitrogen (N) and a first metal element; a second conductive layer provided between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O); at least one of the first electrode having the first conductive layer provided between it and the oxide semiconductor layer and the second electrode having the first conductive layer provided between it and the oxide semiconductor layer contains a second metal element; the atomic concentration of the second metal element is the highest among the atomic concentrations of the metal elements contained in the at least one of the electrodes; the second metal element is the same as the first metal element; The semiconductor device, wherein the first metal element is titanium (Ti).

9. 9. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn).

10. The semiconductor device according to claim 1 , wherein the gate electrode surrounds the oxide semiconductor layer.

11. A first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; A memory cell, The memory cell includes: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region, the first region being electrically connected to the first wiring, and the third region being surrounded by a part of the second wiring; a gate insulating layer provided between the third region and a portion of the second wiring; a capacitor including a first electrode electrically connected to the second region, a second electrode, and an insulating layer between the first electrode and the second electrode; a first conductive layer provided at least one of a position between the first region and the first wiring and a position between the second region and the first electrode, the first conductive layer including oxygen (O), nitrogen (N) and a first metal element; a second conductive layer provided between the oxide semiconductor layer and the first conductive layer, containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O), and having a thickness greater than that of the first conductive layer; Equipped with The first metal element is titanium (Ti).

12. 12. The semiconductor memory device according to claim 11, wherein a thickness of the first wiring having the first conductive layer provided between it and the oxide semiconductor layer, or a thickness of the first electrode having the first conductive layer provided between it and the oxide semiconductor layer is thicker than a thickness of the second conductive layer.

13. 13. The semiconductor memory device according to claim 11, wherein the first conductive layer has a thickness of 1 nm to 10 nm.

14. 14. The semiconductor memory device according to claim 11, wherein the atomic concentration of the first metal element is the highest among atomic concentrations of elements other than oxygen (O) and nitrogen (N) contained in the first conductive layer.

15. at least one of the first wiring having the first conductive layer provided between it and the oxide semiconductor layer and the first electrode having the first conductive layer provided between it and the oxide semiconductor layer contains a second metal element; Among the atomic concentrations of metal elements contained in at least one of the first and second metal elements, the atomic concentration of the second metal element is the highest, 15. The semiconductor memory device according to claim 11, wherein the second metal element is the same as the first metal element.

16. at least one of the first wiring having the first conductive layer provided between it and the oxide semiconductor layer and the first electrode having the first conductive layer provided between it and the oxide semiconductor layer contains a second metal element; Among the atomic concentrations of metal elements contained in at least one of the first and second metal elements, the atomic concentration of the second metal element is the highest, 15. The semiconductor memory device according to claim 11, wherein the second metal element is different from the first metal element.

17. A first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; A memory cell, The memory cell includes: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region, the first region being electrically connected to the first wiring, and the third region being surrounded by a part of the second wiring; a gate insulating layer provided between the third region and a portion of the second wiring; a capacitor electrically connected to the second region; a first conductive layer provided at least at one of a position between the first region and the first wiring and a position between the second region and the capacitor, the first conductive layer including at least one first metal element selected from a group consisting of titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), and molybdenum (Mo), oxygen (O), and nitrogen (N), and the atomic concentration of the first metal element is the highest among atomic concentrations of elements other than oxygen (O) and nitrogen (N) contained in the first conductive layer; a second conductive layer provided between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O); Equipped with The first metal element is titanium (Ti).

18. A first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; A memory cell, The memory cell includes: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region, the first region being electrically connected to the first wiring, and the third region being surrounded by a part of the second wiring; a gate insulating layer provided between the third region and a portion of the second wiring; a capacitor including a first electrode electrically connected to the second region, a second electrode, and an insulating layer between the first electrode and the second electrode; a first conductive layer provided at least one of a position between the first region and the first wiring and a position between the second region and the first electrode, the first conductive layer including oxygen (O), nitrogen (N) and a first metal element; a second conductive layer provided between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O); at least one of the first wiring having the first conductive layer provided between it and the oxide semiconductor layer and the first electrode having the first conductive layer provided between it and the oxide semiconductor layer contains a second metal element; Among the atomic concentrations of metal elements contained in at least one of the first and second metal elements, the atomic concentration of the second metal element is the highest, the second metal element is the same as the first metal element; The first metal element is titanium (Ti).

19. 19. The semiconductor memory device according to claim 11, wherein the oxide semiconductor layer contains at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn).

Images