Plasma processing apparatus and method for manufacturing semiconductor device

Abstract

To suppress the variation in processing characteristics between the center and outer edge portions of a substrate.SOLUTION: A plasma processing device includes a processing container for processing a substrate, an upper electrode installed inside the processing container, a substrate placing table, having a lower electrode opposing the upper electrode, on which the substrate is placed, a perimeter ring arranged on the outer edge of the substrate placing table and surrounding the substrate periphery, and a power supply for supplying power to at least one of the upper electrode and the lower electrode to generate plasma in the processing container. The perimeter ring has a pattern on its outermost surface including a component of a deposited film generated by plasma reaction.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] An embodiment of the present invention relates to a plasma processing apparatus and a method for manufacturing a semiconductor device. [Background technology]

[0002] In the manufacturing process of a semiconductor device, a substrate may be subjected to plasma processing. In this case, the concentration of a predetermined product of a plasma reaction may differ between the center and the outer edge of the substrate. In this case, the processing characteristics may differ between the center and the outer edge of the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5671843 [Patent Document 2] Special Publication No. 2004-311972 [Patent Document 3] Special Publication No. 2004-311972 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a plasma processing apparatus and a method for manufacturing a semiconductor device that can suppress variations in processing characteristics between the center and the outer edge of a substrate. [Means for solving the problem]

[0005] The plasma processing apparatus of the embodiment includes a processing vessel for processing a substrate, an upper electrode installed in the processing vessel, a substrate supporting table having a lower electrode facing the upper electrode and on which the substrate is supported, an outer peripheral ring disposed on the outer edge of the substrate supporting table and surrounding the periphery of the substrate, and a power supply that supplies power to at least one of the upper electrode and the lower electrode to generate plasma in the processing vessel, and the outer peripheral ring has a pattern on its outermost surface containing components of a deposition film generated by a plasma reaction. [Brief description of the drawings]

[0006] [Figure 1] 1 is a perspective top view illustrating an example of an overall configuration of a plasma processing apparatus according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view illustrating an example of a configuration of a processing chamber included in the plasma processing apparatus in the embodiment. [Diagram 3] FIG. 4 is a diagram showing an example of a detailed configuration of an outer circumferential ring according to the embodiment. [Figure 4] 5A to 5C are cross-sectional views showing an example of a procedure of imprint processing and plasma processing on a wafer in the embodiment. [Diagram 5] 1A to 1C are top views showing an example of a detailed procedure of an imprint process on a wafer according to an embodiment. [Figure 6] 10A to 10C are top views showing an example of a process for forming a pattern on the upper surface of the upper ring in the embodiment. [Figure 7] FIG. 4 is a flow diagram showing an example of a usage cycle of the outer ring according to the embodiment. [Figure 8] FIG. 4 is a flow diagram showing an example of a procedure for plasma processing using an outer ring according to an embodiment. [Figure 9] FIG. 11 is a top view showing an example of the configuration of an outer circumferential ring included in the plasma processing apparatus according to the first modified example of the embodiment. [Figure 10] FIG. 11 is a top view showing an example of the configuration of an outer circumferential ring included in a plasma processing apparatus according to Modification 2 of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following embodiments. In addition, the components in the following embodiments include those that a person skilled in the art can easily imagine or are substantially the same.

[0008] (Configuration example of plasma processing apparatus) 1 is a perspective top view showing an example of an overall configuration of a plasma processing apparatus 1 according to an embodiment. As shown in FIG. 1, the plasma processing apparatus 1 includes a processing chamber 11, a transfer chamber 71, load locks 81, 82, 91, and 92, and a controller 50.

[0009] The processing chamber 11 as a processing container is a container for performing plasma processing on the wafer 100, and is connected in an airtight sealed state to the transfer chamber 71. The wafer 100 accommodated in the processing chamber 11 is processed by plasma with an outer periphery ring 20 disposed on the outer periphery.

[0010] The load lock 81 is a container for storing wafers 100 to be processed, and is hermetically sealed and connected to the transfer chamber 71. The load lock 81 is configured to be capable of storing a plurality of wafers 100, for example, one lot of wafers 100.

[0011] The load lock 82 is a container for collecting processed wafers 100, and is hermetically sealed and connected to the transfer chamber 71. The load lock 82 is configured to be capable of accommodating a plurality of wafers 100, for example, one lot of wafers 100.

[0012] The load lock 91 as a storage container is a container for storing the outer ring 20 arranged on the outer periphery of the wafer 100 during plasma processing, and is connected in an airtight sealed state to the transfer chamber 71. The load lock 91 is configured to be able to store the same number of outer rings 20 as the number of wafers 100 stored in the load lock 81, for example.

[0013] The load lock 92 as a recovery container is a container for recovering the outer ring 20 used in the plasma processing, and is hermetically sealed and connected to the transfer chamber 71. The load lock 92 is configured to be able to accommodate the same number of outer rings 20 as the number of wafers 100 stored in the load lock 81, that is, the same number of outer rings 20 as the number of outer rings 20 stored in the load lock 91.

[0014] As described later, the outer circumferential ring 20 is composed of several parts. Therefore, the plasma processing apparatus 1 may include a plurality of sets of load locks 91, 93 for each of the parts of the outer circumferential ring 20.

[0015] The transfer chamber 71 is a container for transferring the wafer 100 and the periphery ring 20 under reduced pressure, and is configured to be airtightly sealed. The transfer chamber 71 includes a transfer arm 72 for transferring the wafer 100 and the periphery ring 20.

[0016] The transfer arm 72 transfers the wafer 100 from the load lock 81 to the processing chamber 11, and also transfers the wafer 100 from the processing chamber 11 to the load lock 82. The transfer arm 72 also transfers the outer circumferential ring 20 from the load lock 91 to the processing chamber 11, and also transfers the outer circumferential ring 20 from the processing chamber 11 to the load lock 92. However, the plasma processing apparatus 1 may also include a transfer arm that transfers the wafer 100 and a transfer arm that transfers the outer circumferential ring 20.

[0017] The control unit 50 controls each part of the plasma processing apparatus 1, including the transfer arm 72. The control unit 50 is configured as a computer including a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like (not shown).

[0018] However, the control unit 50 may be configured as an ASIC (Application Specific Integrated Circuit) having functions for use with the plasma processing apparatus 1 or the like.

[0019] 2 is a cross-sectional view showing a schematic configuration example of a processing chamber 11 included in the plasma processing apparatus 1 according to the embodiment. The processing chamber 11 is configured to be capable of performing an etching process using plasma, for example, and the plasma processing apparatus 1 is configured as an etching apparatus, for example.

[0020] 2, the plasma processing apparatus 1 includes a processing chamber 11 for processing a wafer 100. The processing chamber 11 is made of, for example, aluminum, and can be hermetically sealed.

[0021] A loading / unloading port 11t for the wafer 100 is provided on the side of the processing chamber 11. The loading / unloading port 11t hermetically seals the processing chamber 11 and is equipped with a gate 11g that can be opened and closed when loading and unloading the wafer 100. The wafer 100 and the outer ring 20 are placed at predetermined positions in the processing chamber 11 from the loading / unloading port 11t by the above-mentioned transfer arm 72.

[0022] A gas supply port 13 is provided at the top of the processing chamber 11. A gas supply device (not shown) is connected to the gas supply port 13 through a pipe, and a processing gas used when processing the wafer 100 is supplied through the gas supply port 13.

[0023] A showerhead 18 functioning as an upper electrode is provided below the gas supply port 13. The showerhead 18 is provided with a plurality of gas outlets 18g penetrating the showerhead 18 in the plate thickness direction. The processing gas supplied from the gas supply port 13 is introduced into the processing chamber 11 via the gas outlets 18g. An electrostatic chuck 16 is disposed below the showerhead 18 so as to face the showerhead 18.

[0024] The electrostatic chuck 16 as a substrate support table horizontally supports the wafer 100 to be processed in the processing chamber 11, electrostatically attracts the wafer 100, and also functions as a lower electrode.

[0025] The electrostatic chuck 16 is supported on a support 12 that protrudes vertically upward in a cylindrical shape from the bottom wall near the center of the processing chamber 11. The support 12 supports the electrostatic chuck 16 near the center of the processing chamber 11 a predetermined distance away from the showerhead 18, so as to face and be parallel to the showerhead 18. With this structure, the showerhead 18 and the electrostatic chuck 16 form a pair of parallel plate electrodes.

[0026] The electrostatic chuck 16 also includes a chucking mechanism that electrostatically attracts the wafer 100. The chucking mechanism includes a chuck electrode 16e, a power supply line 45, and a power supply 46. The power supply 46 is connected to the chuck electrode 16e via the power supply line 45. With this mechanism, DC power is supplied from the power supply 46 to the chuck electrode 16e, so that the upper surface of the electrostatic chuck 16 is electrostatically charged, and the wafer 100 is attracted to the chuck electrode 16e.

[0027] A power supply line 41 is connected to the electrostatic chuck 16. A blocking capacitor 42, a matching box 43, and a high-frequency power supply 44 are connected to the power supply line 41. During plasma processing, high-frequency power of a predetermined frequency is supplied from the high-frequency power supply 44 to the electrostatic chuck 16. With this mechanism, the electrostatic chuck 16 functions as a lower electrode. With this configuration, the plasma processing apparatus 1 is configured as, for example, a bottom application type plasma processing apparatus.

[0028] However, the plasma processing apparatus 1 may be configured as an upper application type plasma processing apparatus by connecting a power supply line 41 having a blocking capacitor 42, a matching box 43, a high-frequency power supply 44, etc. to a shower head 18 that functions as an upper electrode.

[0029] Alternatively, a power supply line 41 having a blocking capacitor 42, a matching box 43, a high-frequency power supply 44, etc. may be connected to both the electrostatic chuck 16 and the shower head 18, so that the plasma processing apparatus 1 is configured as an upper-lower application type plasma processing apparatus.

[0030] An insulator ring 15 is disposed on the outer periphery of the electrostatic chuck 16 so as to cover the peripheral portions of the side and bottom surfaces of the electrostatic chuck 16. An outer periphery ring 20 is provided above the insulator ring 15 so as to surround the outer periphery of the electrostatic chuck 16.

[0031] The outer ring 20 is made of, for example, a silicon-based material and adjusts the electric field so that, during etching of the wafer 100, the electric field is not deflected in the vertical direction at the peripheral portion of the wafer 100, i.e., in the direction perpendicular to the surface of the wafer 100.

[0032] A baffle plate 17 is provided between the insulator ring 15 and the side wall of the processing chamber 11. The baffle plate 17 has a plurality of gas exhaust holes 17e penetrating the baffle plate 17 in the plate thickness direction.

[0033] A gas exhaust port 14 is provided below baffle plate 17 of processing chamber 11. A vacuum pump 14p for exhausting the atmosphere inside processing chamber 11 is connected to gas exhaust port 14.

[0034] The area in the processing chamber 11 that is separated by the electrostatic chuck 16 and the baffle plate 17, and the shower head 18, becomes a plasma processing chamber 61. The upper area in the processing chamber 11 that is separated by the shower head 18 becomes a gas supply chamber 62. The lower area in the processing chamber 11 that is separated by the electrostatic chuck 16 and the baffle plate 17 becomes a gas exhaust chamber 63.

[0035] The above-mentioned control unit 50 controls the power supply 46, the matching box 43, the high-frequency power supply 44, the gas supply device, and the like.

[0036] During plasma processing of the wafer 100, the wafer 100 to be processed is placed on the electrostatic chuck 16 and attracted by the chucking mechanism under the control of the control unit 50. The processing chamber 11 is evacuated by a vacuum pump 14p connected to the gas exhaust port 14. When the inside of the processing chamber 11 reaches a predetermined pressure, a processing gas is supplied from a gas supply device (not shown) to the gas supply chamber 62, and then supplied to the plasma processing chamber 61 via the gas discharge port 18g of the shower head 18.

[0037] Furthermore, under the control of the control unit 50, with the shower head 18 serving as the upper electrode being grounded, a high frequency voltage is applied to the electrostatic chuck 16 serving as the lower electrode to generate plasma within the plasma processing chamber 61. A potential gradient is generated between the plasma and the wafer 100 on the lower electrode side due to a self-bias caused by the high frequency voltage, and ions in the plasma are accelerated toward the electrostatic chuck 16, thereby performing an anisotropic etching process.

[0038] (Example of outer ring configuration) Next, a detailed configuration example of the outer circumferential ring 20 according to the embodiment will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of a detailed configuration of the outer circumferential ring 20 according to the embodiment. Fig. 3(a) is a top view of the outer circumferential ring 20 with the wafer 100 disposed inside. Fig. 3(b) is a partially enlarged cross-sectional view of the outer circumferential ring 20 with the wafer 100 disposed inside.

[0039] 3, a wafer 100 to be subjected to plasma processing has, for example, a silicon oxide film 120 on its upper surface. This silicon oxide film 120 is, for example, a film to be etched in the plasma processing apparatus 1.

[0040] A mask pattern 130p having, for example, a plurality of holes 130h is formed on the silicon oxide film 120. The plurality of holes 130h, for example, penetrate the mask pattern 130p, and the silicon oxide film 120 is exposed at the bottom surfaces of the plurality of holes 130h. In the etching process by the plasma processing device 1, the portion of the silicon oxide film 120 exposed from the mask pattern 130p is etched.

[0041] The mask pattern 130p is, for example, an organic film containing carbon, such as a resist film, etc. More specifically, the mask pattern 130p is, for example, a photo-curable resist film that is cured by ultraviolet light or the like.

[0042] The electrostatic chuck 16 has a mounting surface 16p on which the wafer 100 is placed, and a rim portion 16b surrounding the mounting surface 16p. The rim portion 16b has two steps that descend away from the mounting surface 16p toward the outside of the electrostatic chuck 16.

[0043] A part of the lower surface of the outer circumferential ring 20 abuts on the step of the rim portion 16b on the inner side adjacent to the mounting surface 16p. A part of the lower surface of the insulator ring 15 that protrudes toward the mounting surface 16p of the electrostatic chuck 16 abuts on the step of the rim portion 16b on the outer side away from the mounting surface 16p.

[0044] The outer circumferential ring 20 includes an upper ring 21 and lower rings 22 and 23. The upper ring 21 and the lower rings 22 and 23 are mainly composed of, for example, silicon or silicon carbide. In this manner, the outer circumferential ring 20 is made of a material that has sufficient etching selectivity with respect to the silicon oxide film 120 to be etched.

[0045] The lower ring 22 is disposed at an inner position of the outer peripheral ring 20 so as to surround the mounting surface 16p of the electrostatic chuck 16, and is placed on the first step of the electrostatic chuck 16. The lower ring 23 is disposed at an outer position of the outer peripheral ring 20 so as to surround the lower ring 22, and is placed on the insulator ring 15 that protrudes onto the second step of the electrostatic chuck 16.

[0046] The upper ring 21 is disposed on the lower rings 22 and 23. The height of the upper surface of the upper ring 21 above the lower rings 22 and 23 is, in the initial value, substantially equal to the height of the upper surface of the wafer 100 placed on the mounting surface 16p of the electrostatic chuck 16. By taking such a positional relationship, the upper ring 21 adjusts the plasma density to be substantially equal immediately above and outside the wafer 100.

[0047] In addition, the upper ring 21 has protrusions 21ip, 21op protruding from the underside on the lower surface of the inner edge and the lower surface of the outer edge, respectively, and the protrusion 21ip on the underside of the inner edge is fitted into a recess on the upper surface of the lower ring 22, and the protrusion 21op on the underside of the outer edge is fitted into a recess on the upper surface of the lower ring 23.

[0048] A pattern 24p having, for example, a plurality of holes 24h is formed on the upper surface of the upper ring 21. The plurality of holes 24h, for example, penetrate the pattern 24p, and the upper surface of the upper ring 21 is exposed at the bottom surfaces of the plurality of holes 24h.

[0049] Thus, the pattern 24p on the upper surface of the upper ring 21 has a pattern that is approximately the same as the mask pattern 130p on the wafer 100, and the coverage of the pattern 24p on the upper surface of the upper ring 21 is equal to the coverage of the mask pattern 130p on the silicon oxide film 120 on the wafer 100, within a range of -20% to +20%. In addition, the pattern 24p preferably has a film thickness that is approximately the same as that of the mask pattern 130p on the wafer 100, for example.

[0050] Moreover, the pattern 24p on the upper surface of the upper ring 21 is, for example, an organic film containing carbon, similar to the mask pattern 130p on the wafer 100. More specifically, the pattern 24p is, for example, a photocurable resist film cured by ultraviolet light or the like, and is preferably the same film type as the mask pattern 130p on the wafer 100.

[0051] (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing the semiconductor device of the embodiment will be described with reference to Fig. 4 and Fig. 5. The method for manufacturing the semiconductor device of the embodiment includes, for example, a patterning process of the mask film 130 using an imprint technique, and an etching process by a plasma processing device 1.

[0052] FIG. 4 is a cross-sectional view showing an example of a procedure for imprint processing and plasma processing on the wafer 100 according to the embodiment.

[0053] 4(a) to 4(d) show how the imprint process is performed on the wafer 100 by the imprint apparatus.

[0054] As shown in FIG. 4(a), the wafer 100 having the mask film 130 formed on the silicon oxide film 120 is carried into an imprint apparatus, and the pattern surface 80p of the template 80t and the mask film 130 on the wafer 100 are made to face each other.

[0055] The mask film 130 is, for example, a photocurable resist film before the multiple holes 130h are formed in. The template 80t is an original plate for pattern transfer made of a transparent material such as quartz.

[0056] 4(b), the relative positions of the template 80t and the wafer 100 are brought closer to each other, and the pattern surface 80p of the template 80t is pressed against the mask film 130 on the wafer 100. At this time, a slight gap is maintained between the pattern surface 80p of the template 80t and the silicon oxide film 120 on the wafer 100 so that the template 80t and the wafer 100 do not come into contact with each other.

[0057] 4(c), with the pattern surface 80p pressed against the mask film 130, light LR such as ultraviolet light is irradiated from above the template 80t by a light source 80s of an imprinting apparatus. The light LR from the light source 80s passes through the template 80t, which is a transparent member, and is irradiated onto the mask film 130, thereby curing the mask film 130.

[0058] As shown in Fig. 4(d), the template 80t is released from the mask film 130. As a result, a mask pattern 130p having, for example, a plurality of holes 130h is formed. Since the template 80t is pressed against the wafer 100 so as to create a gap between the template 80t and the wafer 100, a mask residual film 130r having a certain thickness is formed on the bottom surface of the plurality of holes 130h.

[0059] 4(e), the thickness of the entire mask pattern 130p is reduced by etching using oxygen plasma, for example, to remove the mask residual film 130r from the bottom surface of the hole 130h. The process of removing the mask residual film 130r may be performed in the plasma processing apparatus 1 described above before the etching process of the silicon oxide film 120 is performed.

[0060] 4(f), plasma processing is performed on the wafer 100 in the plasma processing apparatus 1. At this time, the wafer 100 is placed inside the outer circumferential ring 20 having the above-mentioned pattern 24p on its outermost surface.

[0061] In the etching process in the plasma processing apparatus 1, for example, a corrosive processing gas is supplied into the processing chamber 11 to generate plasma. As a result, the silicon oxide film 120 exposed from the mask pattern 130p is etched, and a plurality of holes 120h are formed in the silicon oxide film 120.

[0062] At this time, although processing conditions are used that give the mask pattern 130p high etching selectivity with respect to the silicon oxide film 120, the mask pattern 130p is also slightly etched. The etching product generated by etching the mask pattern 130p becomes an organic deposition film DEP containing carbon, and is deposited on the side walls of the plurality of holes 120h formed in the silicon oxide film 120. This protects the side walls of the plurality of holes 120h, and suppresses side etching or the like from occurring on the side walls.

[0063] Here, in the vicinity of the outer edge of the wafer 100, the coverage of the mask pattern 130p per unit area of ​​the silicon oxide film 120 is smaller than, for example, in the vicinity of the center of the wafer 100. However, outside the outer edge of the wafer 100, a pattern 24p is formed on the outermost surface of the outer ring 20, which is made of, for example, the same type of film as the mask pattern 130p and contains components of the deposition film DEP generated by plasma reaction.

[0064] Therefore, depositional etching products are supplied to the outer edge of the wafer 100 not only from the mask pattern 130p but also from the pattern 24p on the outer circumferential ring 20, forming a deposition film DEP that protects the side surfaces of the holes 120h. This prevents side etching and the like from occurring on the side walls of the holes 120h, even at the outer edge of the wafer 100.

[0065] By the above etching process, a silicon oxide pattern 120p having a plurality of holes 120h is formed. The wafer 100 which has been subjected to the etching process is discharged from the plasma processing apparatus 1.

[0066] Thereafter, the mask pattern 130p on the silicon oxide pattern 120p is removed by ashing using oxygen plasma, for example. At this time, the deposition film DEP on the side walls of the holes 120h is also removed.

[0067] After this, a semiconductor device according to the embodiment is manufactured on the wafer 100 through a number of further steps.

[0068] Details of the imprint process on the wafer 100 are shown in Fig. 5. Fig. 5 is a top view showing an example of a detailed procedure of the imprint process on the wafer 100 according to the embodiment.

[0069] 5(a), a mask film 130 is formed on the wafer 100 by a spin coating method or the like, and the entire wafer 100 is divided into a plurality of shot regions SHw. However, the mask film 130 may be formed by, for example, an inkjet method or the like. When the mask film 130 is formed by the inkjet method, the mask film 130 may be formed sequentially for each shot region SHw for each imprinting process of the template 80t performed for each shot region SHw, as described below.

[0070] As shown in Fig. 5(b), in the imprint process, a template 80t is pressed against the mask film 130 for each of the shot regions SHw, and a mask pattern 130p is formed. In the example of Fig. 5, the imprint process proceeds from the outermost shot region SHw at the upper left of the page toward the left side of the page. At this stage, the mask residual film 130r remains formed on the bottom surfaces of the holes 130h of the mask pattern 130p that has already been formed.

[0071] Although some of the holes 130h are missing at the boundaries of the shot area SHw, this is for the convenience of drawing and does not mean that the holes 130h will be formed in a missing state in the actual imprint process.

[0072] As shown in FIG. 5C, for example, when imprint processing is performed on the top shot area SHw on the paper, imprint processing is then performed on the shot areas SHw in the second row from the top on the paper, for example, from right to left.

[0073] As shown in Fig. 5(d), the imprint process is performed by reversing the direction of movement from left to right for each step. This type of processing order is sometimes called the raster method.

[0074] As shown in FIG. 5(e), the imprint processing for all shot regions SHw is completed.

[0075] 5(f), the mask residual film 130r of the mask patterns 130p formed in each of the shot regions SHw is removed by, for example, etching using oxygen plasma, thereby exposing the silicon oxide film 120 on the wafer 100 from the bottom surfaces of the holes 130h.

[0076] (Manufacturing method of outer ring) Next, an example of a manufacturing method of the outer circumferential ring 20 of the embodiment will be described with reference to Fig. 6. Fig. 6 is a top view showing an example of a procedure for forming a pattern 24p on the upper surface of the upper ring 21 according to the embodiment. The manufacturing method of the outer circumferential ring 20 may also be included in the manufacturing method of the semiconductor device of the embodiment.

[0077] In manufacturing the outer peripheral ring 20, for example, a silicon-based member mainly composed of silicon or silicon carbide is machined to form the upper ring 21 and the lower rings 22 and 23. In addition, as described below, a pattern 24p is formed on the upper surface of the molded upper ring 21 by using, for example, an imprint technique.

[0078] 6(a), a carbon-based film 24 such as a photocurable resist film is formed on the upper surface of the upper ring 21 by, for example, an inkjet method, in the same manner as the mask pattern 130p of the wafer 100, and the entire surface is divided into a plurality of shot regions SHr. Note that the carbon-based film 24 may be formed in each shot region SHw in sequence for each imprinting process of the template 80t.

[0079] Moreover, it is preferable that the carbon-based film 24 has a thickness substantially equal to that of the mask film 130 before the imprint process in the above-mentioned FIG. 4(a) etc. This allows the pattern 24p after the imprint process to have a thickness substantially equal to that of the mask pattern 130p on the wafer 100, for example.

[0080] 6(b), in the imprint process for the upper ring 21, a template is pressed against the carbon-based film 24 for each of the multiple shot regions SHr, forming a pattern 24p. At this time, it is preferable to use the same type of template having the same pattern as the template 80t used when performing the imprint process for the wafer 100.

[0081] 6, the imprint process proceeds from the outermost shot area SHr at the top left of the page toward the left side of the page. At this stage, the carbon-based residual film 24r remains formed on the bottom surfaces of the multiple holes 24h of the already formed pattern 24p.

[0082] Although some of the holes 24h are missing at the boundaries of the shot area SHr, this is for the convenience of drawing and does not mean that the holes 24h will be formed in a missing state in the actual imprint process.

[0083] As shown in Figure 6(c), when imprint processing is performed on the shot area SHr at the top of the paper, imprint processing is then performed on the shot area SHr in the second row from the top of the paper from right to left in the raster processing order, as in the example of Figure 5.

[0084] As shown in FIG. 6(d), the imprint process is further carried out while the proceeding direction is reversed left and right for each stage.

[0085] As shown in FIG. 6(e), the imprint processing for all shot regions SHr is completed.

[0086] 6(f), the carbon-based residual film 24r of the patterns 24p formed in each of the shot regions SHr is removed by, for example, etching using oxygen plasma, thereby exposing the top surface of the upper ring 21 from the bottom surfaces of the holes 24h.

[0087] In this manner, the outer circumferential ring 20 of the embodiment is manufactured.

[0088] In addition, when the process of removing the mask residual film 130r of the wafer 100 shown in FIG. 5(f) described above is performed in a plasma processing apparatus 1, the process of FIG. 6(f) may also be performed in the plasma processing apparatus 1 in parallel with the process on the wafer 100.

[0089] In this case, the upper ring 21 is carried into the processing chamber 11 of the plasma processing apparatus 1 in the state shown in FIG. 6(e).

[0090] (Example of using the outer ring) Next, a manufacturing flow of a semiconductor device using the outer periphery ring 20 of the embodiment will be described with reference to Fig. 7 and Fig. 8. Fig. 7 is a flow diagram showing an example of a usage cycle of the outer periphery ring 20 according to the embodiment.

[0091] 7, a silicon-based member such as silicon or silicon carbide is molded to form the upper ring 21 and the lower rings 22, 23 (step S101). A carbon-based film 24 is formed on the molded upper ring 21, and an imprint process is performed to form a pattern 24p (step S102). In this way, the outer circumferential ring 20 is manufactured.

[0092] The outer circumferential ring 20 on whose outermost surface the pattern 24p is formed is used for plasma processing in the plasma processing apparatus 1 (step S103).

[0093] As described above, a material having high etching selectivity is selected as the material for the outer circumferential ring 20, for example, when etching the silicon oxide film 120. However, by the plasma processing, in addition to etching the pattern 24p on the outer circumferential ring 20, the upper surface of the outer circumferential ring 20 exposed from the pattern 24p is also slightly etched.

[0094] Therefore, after the plasma processing, it is determined whether the outer circumferential ring 20 has reached the end of its life (step S104). The life can be determined based on whether the cumulative time during which the outer circumferential ring 20 has been used in the plasma processing has exceeded a predetermined time. The amount of etching of the outer circumferential ring 20 may be measured, and the life may be determined based on whether the amount of etching has exceeded a predetermined value.

[0095] The upper ring 21 and the lower rings 22, 23 constituting the outer circumferential ring 20 may have different lifetimes. For example, the upper ring 21 located on the outermost surface of the outer circumferential ring 20 is more easily exposed to plasma and tends to have a shorter lifetime than the lower rings 22, 23. Therefore, it is preferable that different lifetimes are set for the upper ring 21 and the lower rings 22, 23 and a lifetime determination is performed for each of them.

[0096] If the outer circumferential ring 20 has not reached the end of its life (step S104: No), the pattern 24p remaining on the upper surface of the outer circumferential ring 20 is removed by ashing using, for example, oxide plasma (step S105). Also, although the used pattern 24p has been removed, a new pattern 24p is formed on the outer circumferential ring 20 (step S102), and is used for plasma processing until the end of its life.

[0097] If the outer circumferential ring 20 has reached the end of its life (step S104: Yes), the use of the outer circumferential ring 20 is terminated.

[0098] This completes the usage cycle of the outer peripheral ring 20 of the embodiment.

[0099] When the outer ring 20 reaches the end of its life, it is discarded or the material is melted and used to form a new outer ring 20 .

[0100] 8 is a flow diagram showing an example of a procedure for plasma processing using the outer circumferential ring 20 according to the embodiment. The flow in Fig. 8 shows details of the process in step S103 in Fig. 7 described above.

[0101] 8, a plurality of wafers 100, for example, one lot of wafers 100, are set in the load lock 81 of the plasma processing apparatus 1 (step S201). Under the control of the control unit 50, the atmosphere in the load lock 81 is exhausted by a pump or the like (not shown), and the load lock 81 is depressurized to a state in which the wafers 100 can be vacuum-transferred.

[0102] Further, a plurality of outer circumferential rings 20, for example the same number as the wafers 100 set in the load lock 81, are set in the load lock 91 (step S202). The patterns 24p have already been formed on the upper surfaces of these outer circumferential rings 20.

[0103] Further, under the control of the control unit 50, the atmosphere in the load lock 91 is exhausted by a pump or the like (not shown), and the pressure in the load lock 91 is reduced, making it possible to vacuum-transport the outer ring 20.

[0104] Under the control of the control unit 50, a set of lower rings 22, 23 and upper ring 21 constituting the outer circumferential ring 20 are sequentially loaded into the processing chamber 11 under reduced pressure (step S203). Also, one wafer 100 is loaded into the processing chamber 11 under reduced pressure (step S204).

[0105] The wafer 100 is placed on the mounting surface 16p of the electrostatic chuck 16 and electrostatically attracted to the mounting surface 16p. As a result, the outer periphery of the wafer 100 is placed on the outer periphery of the outer periphery of the wafer 100, where the outer periphery ring 20 having the pattern 24p formed thereon is disposed.

[0106] The control unit 50 supplies a processing gas from the gas supply port 13 into the processing chamber 11, and also supplies high frequency power from the high frequency power supply 44 to the electrostatic chuck 16. As a result, plasma is generated in the processing chamber 11, and the wafer 100 is etched (step S205).

[0107] By the above-mentioned etching process, for example, a plurality of holes 120h are formed in the silicon oxide film 120 on the wafer 100. At this time, etching products are supplied from the mask pattern 130p on the wafer 100 and the pattern 24p on the outer peripheral ring 20, and a deposition film is formed on the side walls of the plurality of holes 120h, thereby protecting the side walls of the holes 120h.

[0108] When the etching process for the wafer 100 is completed, the control unit 50 stops the supply of power from the high frequency power supply 44 and also stops the supply of the processing gas into the processing chamber 11, thereby extinguishing the plasma.

[0109] Under the control of the control unit 50, the processed wafer 100 is unloaded from the processing chamber 11 under reduced pressure and collected in the load lock 82 (step S206). Also, under the control of the control unit 50, the used outer ring 20 is unloaded from the processing chamber 11 under reduced pressure and collected in the load lock 92 (step S207).

[0110] At this time, the lower rings 22 and 23 do not need to be collected before the end of their life. It is preferable that the pattern 24p is re-formed for the upper ring 21 every time it is used once for etching a single wafer 100. For this reason, the upper ring 21 is collected after each etching process, regardless of whether it has reached the end of its life or not.

[0111] After the wafers 100 and the upper ring 21 are removed, the control unit 50 determines whether the etching process has been completed for all the wafers 100 set in the load lock 81 (step S208). If the etching process has been completed for all the wafers 100 (step S208: Yes), the etching process for that lot is completed.

[0112] If there is an unprocessed wafer 100 (step S208: No), the control unit 50 repeats the processes from step S203 onwards.

[0113] With the above, the plasma processing using the outer circumferential ring 20 of the embodiment is completed.

[0114] When the plasma processing for all the wafers 100 is completed, for example, one lot of the peripheral rings 20 are sent to the processing in and after step S104 in FIG.

[0115] (Overview) In the manufacturing process of a semiconductor device, for example, an etching process may be performed on a wafer. In the etching process, for example, a part of a film to be etched is covered with a mask pattern, and the part exposed from the mask pattern is etched. At this time, a part of the mask pattern is etched, and etching products are deposited on the sidewalls of the film to be etched, thereby suppressing side etching or the like from occurring on the sidewalls of the film to be etched.

[0116] However, since the coverage of the mask pattern on the film to be etched is lower at the outer edge of the wafer than near the center of the wafer, a sufficient amount of deposition film does not adhere to the sidewall, which may result in side etching of the film to be etched. This may result in the desired processed shape not being obtained at the outer edge of the wafer, or in variations in the processed shape between the center and outer edge of the wafer.

[0117] According to the plasma processing apparatus 1 of the embodiment, the outer ring 20 has a pattern 24p on its outermost surface, which pattern 24p contains components of a deposition film generated by a plasma reaction. As a result, at the outer edge of the wafer 100, etching products are also supplied from the pattern 24p on the outer ring 20.

[0118] Therefore, for example, a sufficient amount of deposition film can be attached to the side wall of the hole 120h of the silicon oxide film 120, which is the film to be etched, to suppress side etching, etc., and also suppress the variation in processing characteristics between the center and outer edge of the wafer 100.

[0119] The plasma processing apparatus 1 of the embodiment includes a load lock 91 for storing the outer circumferential ring 20, and a transfer arm 72 for transferring the outer circumferential ring between the load lock 91 and the processing chamber 11.

[0120] This allows, for example, an unused outer circumferential ring 20 to be carried into the processing chamber 11 for each etching process while maintaining the entire plasma processing apparatus 1 under reduced pressure. This reduces the time required to install the outer circumferential ring 20, improving the throughput of the plasma processing apparatus 1, and also allows the etching process conditions for each wafer 100 to be kept constant.

[0121] According to the plasma processing apparatus 1 of the embodiment, the transfer arm 72 transfers the outer periphery ring 20 between the processing chamber 11 and the load lock 92 that recovers the outer periphery ring 20 used in processing the wafer 100.

[0122] This allows the outer circumferential ring 20 to be replaced after each etching process, for example, while maintaining the entire plasma processing apparatus 1 under reduced pressure. This reduces the time required to replace the outer circumferential ring 20, thereby improving the throughput of the plasma processing apparatus 1.

[0123] According to the method for manufacturing a semiconductor device of the embodiment, the coverage of the outermost surface of the pattern 24p of the outer circumferential ring 20 is −20% or more and +20% or less of the coverage of the mask pattern 130p of the wafer 100 on the wafer 100 surface.

[0124] This makes it possible to make the supply amounts of etching products, which are components of the deposited film, closer to each other at the center and the outer edge of the wafer 100. This makes it possible to further suppress the variation in processing characteristics between the center and the outer edge of the wafer 100.

[0125] According to the method for manufacturing a semiconductor device of the embodiment, the mask pattern 130p and the pattern 24p contain, for example, carbon, and more specifically, are mainly composed of resist.

[0126] In this way, the mask pattern 130p and the pattern 24p contain the same kind of components and are made of the same kind of film, so that the etching conditions can be made more similar between the center and the outer edge of the wafer 100. This makes it possible to further suppress the variation in the processing characteristics between the center and the outer edge of the wafer 100.

[0127] According to the semiconductor device manufacturing method of the embodiment, when forming the pattern 24p on the outermost surface of the outer periphery ring 20, a template of the same type as the template 80t used to form the mask pattern 130p of the wafer 100 is used. This allows the pattern 24p that is approximately identical to the mask pattern 130p of the wafer 100 to be formed on the outermost surface of the outer periphery ring 20.

[0128] Therefore, the etching conditions at the center and the outer edge of the wafer 100 can be made even closer to each other, and the variation in processing characteristics between the center and the outer edge of the wafer 100 can be further suppressed.

[0129] According to the semiconductor device manufacturing method of the embodiment, after processing the wafer 100, the outer circumferential ring 20 is unloaded from the processing chamber 11, the used pattern 24p is removed, and the pattern 24p is formed on the outermost surface. This allows the outer circumferential ring 20 to be repeatedly used until it reaches the end of its life, thereby reducing the manufacturing cost of the semiconductor device.

[0130] (Variations 1 and 2) Next, configuration examples of the outer circumferential rings 20a, 20b according to the first and second modifications of the embodiment will be described with reference to Figures 9 and 10. In the outer circumferential rings 20a, 20b according to the first and second modifications, the patterns 24pa, 24pb formed on the upper surface are different from those in the above-described embodiment.

[0131] 9 and 10 are top views showing an example of the configuration of the outer circumferential rings 20a and 20b according to the embodiment modifications 1 and 2. In Fig. 9 and Fig. 10, the same components as those in the above-mentioned embodiment, such as the wafer 100, are denoted by the same reference numerals as those in the above-mentioned embodiment, and the description thereof will be omitted.

[0132] 9 and 10 show patterns 24pa and 24pb after the carbon-based residual film 24r is removed in the outer rings 20a and 20b, respectively. Also, in the wafer 100 of FIG. 9 and 10, a mask pattern 130p after the mask residual film 130r is removed is shown.

[0133] As shown in FIGS. 9 and 10, the peripheral rings 20a, 20b do not have to have a pattern similar to the mask pattern 130p on the wafer 100, for example.

[0134] 9, the outer circumferential ring 20a of the first modification has, for example, a pattern 24pa in which annular grooves 24c are formed concentrically on the outermost surface. The upper surface of the outer circumferential ring 20a is exposed from the bottom surface of the grooves 24c.

[0135] In the outer circumferential ring 20a of the first modification, the coverage of the pattern 24pa on the upper surface of the outer circumferential ring 20a is equal to the coverage of the mask pattern 130p on the silicon oxide film 120 on the wafer 100 within the range of −20% to +20%.

[0136] Also in the outer circumferential ring 20a of the first modification, the pattern 24pa on the upper surface of the outer circumferential ring 20a is an organic film containing carbon, similar to, for example, the mask pattern 130p on the wafer 100. More specifically, the pattern 24pa is a photocurable resist film cured by ultraviolet light or the like, and is preferably the same film type as the mask pattern 130p on the wafer 100.

[0137] 10, the outer circumferential ring 20b of the second modification has, for example, a pattern 24pb on its outermost surface, in which grooves 24s are formed radially outward from the outer circumferential ring 20b. The top surface of the outer circumferential ring 20b is exposed from the bottom surface of the grooves 24s.

[0138] In the outer circumferential ring 20b of the second modification, the coverage of the pattern 24pb on the upper surface of the outer circumferential ring 20b is equal to the coverage of the mask pattern 130p on the silicon oxide film 120 on the wafer 100 within the range of −20% to +20%.

[0139] In the outer circumferential ring 20b of the second modification, the pattern 24pb on the upper surface of the outer circumferential ring 20b is an organic film containing carbon, similar to the mask pattern 130p on the wafer 100. More specifically, the pattern 24pb is a photocurable resist film cured by ultraviolet light or the like, and is preferably the same film type as the mask pattern 130p on the wafer 100.

[0140] According to the plasma processing apparatus including the outer peripheral rings 20a and 20b of the first and second modifications, the same effects as those of the plasma processing apparatus 1 of the above-described embodiment can be achieved.

[0141] (Other variations) When etching the wafer, not only the above-mentioned hole pattern but also a line and space pattern in which lines and spaces are alternately arranged, a dot pattern in which a plurality of protrusions are arranged, and various other mask patterns can be used. Therefore, for example, a line and space pattern, a dot pattern, or other pattern may be formed on the upper surface of the peripheral ring in accordance with the mask pattern formed on the wafer.

[0142] The mask pattern on the wafer and the pattern on the top surface of the outer ring may be formed using photolithography instead of imprinting. In this case, the mask pattern on the wafer and the pattern on the top surface of the outer ring can be formed by irradiating a resist film or the like with exposure light through a reticle having a predetermined pattern. In this case, the same type of reticle as that used to form the mask pattern may be used when forming the pattern on the top surface of the outer ring.

[0143] Furthermore, the mask pattern formed on the wafer can be formed not only from the above-mentioned resist film, but also from a film containing carbon, such as a SOC (Spin On Carbon) film or a CVD (Chemical Vapor Deposition) carbon film.

[0144] Even in this case, the pattern on the upper surface of the outer ring can be formed from a film containing carbon, such as the resist film described above. The resist film, SOC film, and CVD carbon film have similar compositions and etching characteristics, so that the same effects as those of the embodiment and modified examples 1 and 2 described above can be obtained even in this case.

[0145] However, for example, the pattern of the outer ring may be made of an SOC film, a CVD carbon film, etc., in accordance with the film type of the mask pattern on the wafer. This allows the etching conditions at the center and the outer edge of the wafer to be closer to each other, and further suppresses the variation in processing characteristics between the center and the outer edge of the wafer.

[0146] In addition, when forming a mask pattern on the wafer and a pattern on the upper surface of the outer ring from an SOC film or a CVD carbon film, a resist pattern or the like may be formed on the SOC film or the CVD carbon film by photolithography technology or imprint technology, and the SOC film or the CVD carbon film may be etched using this as a mask.

[0147] Moreover, the film to be etched may be not only the silicon oxide film described above, but also a polysilicon film, a single crystal silicon film, etc. The single crystal silicon film may be formed on a wafer using, for example, an epitaxial growth method, or the like, and the single crystal silicon film constituting a part of the wafer may be etched as it is.

[0148] In such a case, the outer ring can be made of a silicon-based material such as silicon oxide or silicon carbide, which provides an outer ring with high etching selectivity with respect to the polysilicon or single crystal silicon film being etched.

[0149] Furthermore, when a polysilicon film or a single crystal silicon film is to be etched, a mask pattern may be formed from a film containing silicon, such as a silicon oxide film, instead of a mask pattern formed from a film containing carbon, such as a resist film, an SOC film, or a CVD carbon film. In this case, a deposition film containing silicon is formed from the mask pattern to become a sidewall protective film.

[0150] Therefore, for example, the pattern on the outer ring can be formed from a film containing silicon, such as a silicon oxide film, in accordance with the mask pattern on the wafer, so that etching products that become components of the deposited film can be supplied to the outer edge of the wafer from the pattern on the outer ring.

[0151] When the pattern on the outer ring is made of a silicon oxide film or the like, the pattern on the outer ring after use can be removed by etching under conditions that are highly selective for the components of the outer ring, or the pattern on the outer ring can be removed by polishing using chemical mechanical polishing (CMP) or the like.

[0152] Furthermore, when a pattern different from the mask pattern of the wafer is formed on the outer ring as in the first and second modifications, a reticle or template different from the reticle or template used to form the mask pattern is used.

[0153] Since the coverage of the mask pattern on the wafer can vary, in the above case, multiple types of reticles or templates having different coverages may be prepared for forming the pattern on the outer ring so that the coverage of the pattern on the outer ring is within ±20% of the coverage of the mask pattern.

[0154] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0155] 1...plasma processing apparatus, 11...processing chamber, 16...electrostatic chuck, 18...shower head, 20, 20a, 20b...peripheral ring, 21...upper ring, 22, 23...lower ring, 24p, 24pa, 24pb...pattern, 44...high frequency power supply, 50...control unit, 80t...template, 81, 82, 91, 92...load lock, 100...wafer, 120...silicon oxide film, 130p...mask pattern.

Claims

1. a processing vessel for processing a substrate; an upper electrode installed in the processing chamber; a substrate support table having a lower electrode facing the upper electrode and on which the substrate is placed; an outer circumferential ring disposed on an outer edge of the substrate mounting table and surrounding the periphery of the substrate; a power source that supplies power to at least one of the upper electrode and the lower electrode to generate plasma in the processing chamber; The outer ring is having a pattern on its outermost surface, the pattern including a component of a deposition film generated by a plasma reaction; Plasma processing equipment.

2. The pattern is mainly composed of resist, SOC, CVD carbon, or silicon oxide. The plasma processing apparatus according to claim 1 .

3. A container for storing the outer ring; a recovery container for recovering the outer ring used in processing the substrate; a transport arm configured to transport the outer ring between the storage vessel and the processing vessel and between the processing vessel and the recovery vessel.

3. The plasma processing apparatus according to claim 1 or 2.

4. A substrate is loaded into a processing chamber having an upper electrode; placing the substrate on a substrate placement table having a lower electrode facing the upper electrode in the processing chamber; supplying power to at least one of the upper electrode and the lower electrode to generate plasma in the processing chamber to process the substrate; When processing the substrate, an outer circumferential ring having a pattern on its outermost surface, the pattern including a component of a deposition film generated by a plasma reaction, is disposed on the outer periphery of the substrate mounting table; A method for manufacturing a semiconductor device.

5. After processing the substrate, The outer ring is removed from the processing vessel. removing the pattern of the outer ring carried out from the processing vessel; forming the pattern on the outermost surface of the outer ring from which the pattern has been removed; The method for manufacturing a semiconductor device according to claim 4 .

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