GaN-Based Adjustable Current Driver Circuit

Abstract

A circuit for providing an adjustable output driver current for use in lidar or other similar GaN driver applications. The circuit is configured to allow a high current GaN driver FET to provide a desired high slew rate driver current (I DRV ) to obtain the gate-source voltage (V GS ) for the driver FET, stored on an external capacitor. GS An externally provided reference current is used to generate the desired value of the pulse I. The capacitor value far exceeds the relatively low input capacitance of the GaN driver FET. DRV When required, the voltage on the capacitor is applied to the gate of the driver FET, thereby generating the desired I DRV The reference charging current replenishes any charge lost on the capacitor, resulting in the same desired I DRV can be obtained.

Description

[Technical field]

[0001] The present invention relates generally to current driver circuits, and more particularly to Gallium Nitride (GaN) Field Effect Transistor (FET) based current driver circuits with the ability to adjust the output current based on a reference current and to maintain a constant output current for a given reference current despite changes in temperature, circuit impedance, power supply voltage, etc. [Background technology]

[0002] A typical current driver circuit includes a current mirror, a driver and a control transistor. A reference current input to the current mirror is replicated to an output drive current. The driver receives a control signal indicating a pulse for the drive current and drives the control transistor. The control transistor turns the current mirror on and off based on the control signal to prevent or enable the current mirror from generating the drive current.

[0003] 1 is a schematic diagram of a conventional current driver circuit 100, which includes a current mirror 120, a control signal driver 140 and its corresponding control transistor 135. The current mirror 120 includes transistors 125 and 130. The drain and gate terminals of transistor 130 are connected together and a reference current I REF The source terminal of transistor 130 is connected to ground 110. The gate terminal of transistor 125 is connected to the gate and drain terminals of transistor 130, and also receives I REF The source terminal of transistor 125 is connected to ground 110.

[0004] The drain terminal of transistor 125 is coupled to a high drive power supply voltage V HV Transistor 125 is connected to a power supply voltage node 115 that provides a high drive power supply voltage V HV The output current of the current mirror 120, i.e., the driver current I DRVTransistor 125 acts as a drive transistor such that when a load, e.g., a laser diode, is connected in series with power supply voltage node 115 and transistor 125, a drive current I DRV flows through the laser diode, causing it to output a laser beam.

[0005] A control signal driver 140 receives the control signal CTL 105 and drives the gate terminal of the control transistor 135, which in turn drives the current mirror 120 and the drive current I DRV , and acts as a switch controlling the reference current I. The drain terminal of transistor 135 is connected to the gate terminal of transistor 125 and the gate and drain terminals of transistor 130. The source terminal of transistor 135 is connected to ground 110. In response to control transistor 135 acting as a closed switch, the gate terminals of drive transistor 125 and transistor 130 are connected to ground 110 causing them to act as open switches and the reference current I REF and the drive current I DRV from flowing through current mirror 120. In response to control transistor 135 acting as an open switch, the voltages on the gate terminals of transistor 130 and drive transistor 125 rise above the threshold voltage V Th can rise above the reference current I REF Based on the drive current I DRV The following is generated.

[0006] Some implementations of the current driver circuit 100, such as in light detection and ranging (lidar) systems, have a drive current I DRV or the drive current I, which is controlled in a feedback system. DRV For example, in a lidar system, a very large drive current I is required to drive a laser diode and image the environment. DRV and a very high pulse frequency is used. To implement the very high pulse frequency, the reference current I REF is very large, and the input capacitance C of the drive transistor 125 ISSmust be charged quickly. For example, C ISS The 600 picofarad (pF) drive transistor 125 must be charged to 5 volts (V) in 1 nanosecond (ns), resulting in an I REF A current that large and drawn that quickly from the supply voltage will cause substantial supply voltage ripple due to wiring impedances such as inductance, resistance, etc. For example, a trace with only a single ohm (Ω) impedance will result in a 3V drop when 3A of current passes through it.

[0007] Furthermore, the drive current I DRV Finer control of the value of I provides finer control of the intensity of the light emitted by the laser diode, thereby allowing the lidar system to adjust the intensity of the light based on the range of distances it is imaging. However, in current driver circuit 100, a fixed voltage is applied to the gate terminal of drive transistor 125 and I REF and if transistor 130 is omitted, the gate-source voltage V GS must turn on the drive transistor 125 and generate the desired drive current despite variations due to temperature, circuit impedance, power supply voltage variations, and process variations in transistor technology, as discussed above. Then, the actual drive current I DRV varies widely with temperature, circuit impedance, power supply voltage and process variations, such that current driver circuits cannot be used to achieve the desired distance or range resolution required by a lidar system over all environmental or system conditions. Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention addresses the disadvantages of conventional driver circuits discussed above by providing a current driver circuit that is capable of adjusting the output current based on a reference current and maintaining a constant output current for a given reference current despite changes in temperature, circuit impedance, power supply voltage, etc. [Means for solving the problem]

[0009] The present invention, as described herein, is an adjustable current driver circuit comprising a circuit for charging a storage capacitor from a first power supply voltage based on an externally provided reference current, and a pulse controller circuit for, in response to a control signal, connecting the storage capacitor to a gate of a power transistor to drive current through the power transistor, or for disconnecting the storage capacitor from the gate of the power transistor and connecting the gate of the power transistor to ground to prevent current from flowing through the power transistor.

[0010] The circuit for charging the capacitor preferably comprises a current mirror.

[0011] The power transistor is preferably a high current, high slew rate Gallium Nitride (GaN) field effect transistor (FET) connected to a second power supply voltage, the second power supply voltage being greater than the first power supply voltage. The current mirror and pulse generator circuit comprises a plurality of GaN FET transistors, all of which are substantially smaller in size than the GaN FET power transistor.

[0012] A resistor may be connected to the pulse generator circuit and the power transistor to release the charge on the storage capacitor and interrupt the flow of current through the power transistor when the control signal is clamped on.

[0013] The above and other preferred features described herein, including various novel details of the implementation and combination of elements, will now be described in more detail with reference to the accompanying drawings and set forth in the claims. It is to be understood that the specific methods and apparatus are shown merely as examples and not as limitations of the claims. As will be understood by those skilled in the art, the principles and features of the teachings herein can be employed in various and numerous embodiments without departing from the scope of the claims.

[0014] The features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0015] [Figure 1] 1 illustrates a schematic diagram of a conventional current driver circuit; [Diagram 2] 1 illustrates an adjustable current driver circuit according to the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] In the following detailed description, reference is made to specific embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice them. It should be understood that other embodiments may be utilized and that various structural, logical and electrical changes may be made. The combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in their broadest sense, but are instead taught merely to describe particularly representative examples of the present teachings.

[0017] 2 illustrates an adjustable current driver circuit 200 in accordance with the present invention. As described in detail below, the circuit of the present invention can be implemented as a low power integrated circuit to provide an adjustable output driver current for use in lidar or other similar GaN driver applications. The circuit provides a high current GaN driver FET 295 with an appropriate gate-to-source voltage (V GS ) required for the driver FET 295. GS To generate the reference current I REF is used. The V generated by the circuit GS adjusts for variations in process characteristics, temperature or power supply voltage. GS The voltage is stored on an external capacitor 250. The value of the capacitor 250 is determined by the parasitic capacitance C ISS , but the size is still practical given the low value of input capacitance for GaN FETs.

[0018] When a desired value of pulsed current is needed (i.e., when driver FET 295 needs to be activated), the voltage on capacitor 250 is applied to the gate of driver FET 295 through pulse controller 270, which connects capacitor 250 to the gate of driver FET 295, thereby generating the desired, scaled-up driver current. When driver FET 295 is to be turned off, pulse controller 270 opens the connection to capacitor 250, shorting the gate of driver FET 295 to ground.

[0019] Any charge lost on capacitor 250 due to charge transfer to driver FET 295 is reflected by reference current I REF The reference charging current I CHGIt is replenished thereby, so that the same desired rapid and large driver current can be obtained with the next command pulse, creating the next rapid and large slew rate pulse. Advantageously, since the capacitor is already pre-charged with charge before the output current pulse occurs, the instantaneous draw of current from the power supply charging the gate of driver FET 295 is extremely reduced. This reduces power supply voltage spikes.

[0020] The circuit preferably includes a safety driver cutoff when the command signal is fixed on, as described in more detail below.

[0021] Turning now to the details of the preferred embodiment of the invention illustrated in FIG. 2, the adjustable current driver circuit 200 includes a current mirror 220, a capacitor 250, a pulse controller 270, and a drive transistor 295. The current mirror 220 receives, in this example, a reference current I REF from an external current source 245 and outputs a charging current I dd from the power supply voltage V CHG 215B to charge the capacitor 250. As shown in FIG. 2, the current mirror 220 includes transistors 225, 230, 235, and 240, which are connected together in a conventional arrangement. The pulse controller 270 includes transistors 280 and 285. The transistors 225, 230, 235, and 240 of the current mirror 220, the transistors 280 and 285 of the pulse controller 270, and the drive transistor 295 are all preferably enhancement mode GaN FET semiconductor devices and are all preferably monolithically integrated onto a single semiconductor die.

[0022] The current mirror 220 has a conventional topology, with the gate and drain terminals of transistor 225 connected together, and in this example, receiving I REF2. A source terminal of transistor 225 is connected to a drain terminal of transistor 235. A gate terminal of transistor 235 is connected to the gate and drain terminals of transistor 240 and to the source terminal of transistor 230 at node 255. A gate terminal of transistor 230 is connected to the gate and drain terminals of transistor 225. A drain terminal of transistor 230 is connected to power supply voltage source 215B.

[0023] In the operation of the circuit, the charging current I CHG is the reference current I REF 2. The power supply voltage source 215B is drawn by the current mirror 220 based on I to charge the capacitor 250 to the desired voltage that will be applied to the gate terminal of the drive transistor 295. REF The change to the value of results in a charging current I CHG and the change in the charge stored on the capacitor 250. REF The variation of I provides dynamic control of the voltage across capacitor 250, such that capacitor 250 can apply different voltages to the gate terminal of drive transistor 295 in response to temperature, supply voltage, variations in circuit impedance, and process variations. By extension, I REF The variation of the drive current I through the drive transistor 295 by controlling the voltage applied to its gate terminal. DRV This allows for dynamic control of the

[0024] The capacitance of the capacitor 250 is the input capacitance C of the drive transistor 295. ISS , so that the voltage across capacitor 250 is much greater than the desired V GS As I CHG In the preferred embodiment of the present invention shown in FIG. REF 215B supplies a charging current I CHG to allow the adjustable current driver circuit 200 to supply an available power supply voltage V dd In other implementations, the reference current I REFis applied directly to node 255 and charges capacitor 250 directly.

[0025] In accordance with the present invention, the nearly instantaneous energy required for drive transistor 295 is drawn primarily from the charge stored in capacitor 250, rather than from the power supply voltage source, thereby greatly reducing power supply voltage spikes from the nearly instantaneous current draw from the power supply voltage source. The reduced power supply voltage spikes also reduce resistive and inductive noise spikes in other predriver circuits. While drive transistor 295 acts as an open switch, the charge drawn from capacitor 250 is I CHG It is supplemented by I CHG I REF , which, despite its very small magnitude, is sufficient to recharge the capacitor 250 between pulses of the transistor 295. To illustrate using an example, the drive current I DRV pulses every microsecond (μs), causing the drive transistor 295 to act as a closed switch for 5 ns. CHG is the drive current I DRV The capacitor 250 is charged for an intervening 995 nanoseconds before the next pulse of .

[0026] A pulse controller 270 has its input connected to node 255 and its output connected at node 290 to the gate terminal of a drive transistor 295 and receives a control signal CTL 205. The controller 270 includes a driver 275 and transistors 280 and 285. The driver 275 receives CTL 205 and is connected to the gate terminals of transistors 280 and 285. The drain terminal of transistor 280 is connected to node 255 and the source terminal of transistor 280 is connected to the gate terminal of drive transistor 295 at node 290. The drain terminal of transistor 285 is connected to the gate terminal of drive transistor 295 and the source terminal of transistor 280 at node 290.

[0027] The drive transistor 295 is turned on and the drive current I DRVWhen CTL 205 indicates that should be generated, transistor 285 acts as an open switch, disconnecting the gate terminal of drive transistor 295 from ground 210. Transistor 280 acts as a closed switch, connecting the gate terminal of transistor 295 to capacitor 250 at node 255. The charge stored on capacitor 250 increases the voltage on the gate terminal of drive transistor 295 to its threshold voltage V Th Rise above it and turn it on, I REF The drive current I is proportional to DRV When CTL 205 indicates that drive transistor 295 should be turned off, transistor 280 acts as an open switch, disconnecting the gate terminal of drive transistor 295 from capacitor 250. Transistor 285 acts as a closed switch, connecting the gate terminal of drive transistor 295 to ground 210, causing the gate voltage of drive transistor 295 to drop rapidly to ground.

[0028] The drain terminal of the drive transistor 295 is connected to a second power supply voltage source 215A, which receives a power supply voltage V dd Much higher supply voltage V HV The source terminal of the drive transistor 295 is connected to ground 210. The drive current I DRV is derived from a second power supply voltage source 215A.

[0029] In some implementations, a resistor 260 is connected to node 290 and ground 210 as a safety mechanism in case the pulse controller 270 malfunctions and causes the drive transistor 295 to be turned on for longer than a predetermined safety threshold time. Resistor 260 discharges capacitor 250 to zero over a period of time in response to CTL 205 or pulse controller 270 indicating that drive transistor 295 will be turned on for longer than the safety threshold time. By discharging capacitor 250 over time, resistor 260 reduces the gate voltage of drive transistor 295 to its threshold voltage V Th295 to turn off the drive transistor 295 and drive current I DRV The resistance of resistor 260 is chosen to achieve a desired safety threshold time before drive transistor 295 is turned off.

[0030] As previously described herein, the reference current I REF is a current driver circuit 100 shown in FIG. REF Extremely scaled down compared to the input. Very large drive current I DRV is drawn from a very large power supply voltage source 215A and is achieved based on the relative sizes of the transistors of current mirror 220 compared to drive transistor 295. For example, transistors 235 and 240 are substantially the same size, and drive transistor 295 is approximately 30,000 times the size of transistors 235 and 240. A drive current I equal to 30 A DRV The reference current I is only 1mA. REF In this way, the effect on the available supply voltage in the integrated circuit is reduced, resulting in a drive current I that is several orders of magnitude larger, varying on the order of tens of GA / sec. DRV To generate this, a small reference current I REF is sufficient. REF Changing the size of I DRV Change the size of .

[0031] Returning to the exemplary implementation of the adjustable current driver circuit as part of a lidar system, I REF Changing the size of I DRV and the magnitude of I DRV The lidar system proportionally varies the corresponding intensity of light emitted by a laser diode driven by the I. In this way, the lidar system can carefully control the intensity of light based on the range of distances and environmental conditions it is imaging. While the lidar system is imaging the environment, the I. DRV can be dynamically adjusted. DRVDynamic adjustment of the light intensity allows the lidar system to adapt to different distances, maintain constant light intensity over different environmental and process conditions, and / or modulate light intensity over time to implement a time-of-flight imaging process.

[0032] The above description and drawings should be considered merely as illustrations of specific embodiments that achieve the features and advantages described herein. Modifications and substitutions of specific process conditions can be made. Thus, the embodiments of the present invention are not considered to be limited by the above description and drawings. [Explanation of symbols]

[0033] 100 Current driver circuit 105 Control signal CTL 110 Grand 115 Power Supply Node 120 Current Mirror 125 Transistor 130 Transistor 135 Control Transistor 140 Control Signal Driver 200 Adjustable Current Driver Circuit 205 Control signal CTL 210 Grand 215A power supply 215B Power Supply 220 Current Mirror 225 Transistor 230 Transistor 235 Transistor 240 Transistor 245 Current Source 250 Capacitor 255 nodes 260 resistor 270 Pulse Controller 275 Driver 280 Transistors 285 Transistor 290 nodes 295 Drive Transistor I CHG charging current I DRV Drive Current I REF Reference current V HV High drive power supply voltage

Claims

1. The charge current I is generated from the first power supply voltage based on a reference current provided by an external current source. CHG a reference current I REF The charging current I CHG , thereby deriving the reference current I REF The change in the value of the charging current I CHG and a corresponding change in the value of the charge stored on the storage capacitor; a pulse controller circuit for connecting the storage capacitor to a gate of a power transistor to drive the power transistor and allow a drive current to flow through the power transistor, or for disconnecting the storage capacitor from the gate of the power transistor and connecting the gate of the power transistor to ground to prevent the drive current from flowing through the power transistor, in response to a control signal, the pulse controller circuit being connected to ground, an input side of the pulse controller circuit being connected to the current mirror and the one end of the storage capacitor, an output side of the pulse controller circuit being connected to the gate of the power transistor, and a voltage for charging the storage capacitor being applied to the gate of the power transistor; The storage capacitor has a capacitance greater than the input capacitance of the power transistor, whereby the reference current I REF The change in the charging current I CHG and a corresponding change in charge stored in the storage capacitor, when the storage capacitor is connected to the gate of the power transistor, DRV A corresponding change to the adjustable current in the driver circuit.

2. 2. The adjustable current driver circuit of claim 1, wherein the power transistor comprises a first Gallium Nitride (GaN) field effect transistor (FET) connected to a second power supply voltage, the second power supply voltage being higher than the first power supply voltage.

3. 3. The adjustable current driver circuit of claim 2, wherein the current mirror comprises a plurality of GaN FET transistors and the pulse controller circuit comprises a plurality of GaN FET transistors, and all of the GaN FET transistors of the current mirror and the pulse controller circuit are smaller in size than the GaN FET transistors controlled by the current driver circuit.

4. The adjustable current driver circuit of claim 1, further comprising a resistor, one end of the resistor connected to the output side of the pulse controller circuit and to the gate of the power transistor, and the other end of the resistor connected to ground, to release charge on the storage capacitor and cut off the flow of the drive current through the power transistor when the control signal is fixed on.

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