Solid-state imaging device and method for manufacturing the same

Abstract

A solid-state imaging device having highly reliable connections between pads and circuits is provided. [Solution] A solid-state imaging device having a first semiconductor substrate on whose surface a photoelectric conversion element is arranged, and a second semiconductor substrate on whose surface at least a part of a circuit for generating a signal based on the charge of the photoelectric conversion element is arranged, the surface of the first semiconductor substrate and the surface of the second semiconductor substrate being arranged so that they face each other, the device has a wiring structure arranged between the first semiconductor substrate and the second semiconductor substrate, and a pad on whose first surface an external terminal is connected, the first surface of the pad is located between an imaginary plane that includes the surface of the first semiconductor substrate and is parallel to said surface and the surface of the second semiconductor substrate, the second surface being the surface opposite to the first surface is located between the first surface and the surface of the second semiconductor substrate, and the second surface of the pad is connected to the wiring structure so that the pad is connected to a circuit arranged on the second semiconductor substrate via the wiring structure.

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device, and more particularly to a pad portion. [Background technology]

[0002] In order to obtain high-definition images, CCD-type and amplified solid-state imaging devices used in digital still cameras and camcorders are required to have finer pixels. However, the finer the pixels are, the smaller the light-receiving area of ​​the photoelectric conversion element that detects the light contained in the pixel becomes, resulting in a decrease in sensitivity. Patent Document 1 discloses a configuration in which a first substrate on which a photoelectric conversion element and a transfer transistor are arranged and a second substrate on which other circuits are arranged are joined together to form a solid-state imaging device in order to secure a light receiving area of ​​the photoelectric conversion element in an amplified CMOS solid-state imaging device. In the solid-state imaging device of Patent Document 1, a connection portion penetrating the second substrate is connected to a pad (input / output pad), and the pad is connected from the back surface side of the second substrate. This pad is formed on the back surface of the second substrate after the second substrate is polished to expose the second connection portion. Patent Document 2 discloses a method for manufacturing an electronic component, which bonds a first substrate having an image sensor and a first conductive area to a second substrate having an integrated circuit and a second conductive area. After bonding the first substrate and the second substrate, the first conductive area and the second conductive area are exposed, and a conductive layer is deposited to form an electrical connection between the first conductive area and the second conductive area. The first conductive area or the conductive layer is used as a pad (external connection pad). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-191081 A [Patent Document 2] Special Publication No. 2010-514177 Summary of the Invention [Problem to be solved by the invention]

[0004] In the configuration of Patent Document 1, the electrical path connecting the pad and the first substrate becomes long. As a result, the performance may decrease due to an increase in connection resistance, and the reliability of the connection between the pad and the first substrate may decrease. In the configuration of Patent Document 2, the reliability of the connection between the pad and the second conductive area decreases. Furthermore, the manufacturing method of Patent Document 1 requires a step of providing a liner to separate the connection portion from the second substrate, a step of polishing the second substrate, and a step of forming an input / output pad, which complicates the process.The manufacturing method of Patent Document 2 requires a step of providing openings with different depths in the first conductive area and the second conductive area, which complicates the process. Therefore, an object of the present invention is to provide a solid-state imaging device having highly reliable connections between pads and circuits, and a method for manufacturing a solid-state imaging device that can easily form connections between pads and circuits. [Means for solving the problem]

[0005] A first manufacturing method of a solid-state imaging device of the present invention is a manufacturing method of a solid-state imaging device having a pad to be connected to an external terminal, the method including a bonding process of bonding a first member having a first semiconductor substrate on which a photoelectric conversion element is arranged and a first wiring structure including a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is arranged and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; before and an exposing step of exposing the pad by removing a portion of the first semiconductor substrate. A second manufacturing method of a solid-state imaging device of the present invention is a manufacturing method of a solid-state imaging device having a pad to be connected to an external terminal, comprising a bonding step of bonding a first member having a first semiconductor substrate on which a photoelectric conversion element is disposed and a first wiring structure including a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; before and an exposing step of exposing the pad by removing a part of the second semiconductor substrate. And the exposure Prior to the step, a step of forming a plurality of vias connected to the pads is included. The present invention relates to a method for manufacturing a solid-state imaging device. Effect of the Invention

[0006] According to the present invention, it is possible to provide a solid-state imaging device having highly reliable connections between pads and circuits, and also to easily form connections between pads and circuits. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a solid-state imaging device according to a first embodiment. [Diagram 2] 1 is a schematic plan view of a solid-state imaging device according to a first embodiment. [Diagram 3] 1 is a circuit diagram of a solid-state imaging device according to a first embodiment. [Figure 4] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the solid-state imaging device in the first embodiment. [Diagram 5] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the solid-state imaging device in the first embodiment. [Figure 6] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the solid-state imaging device in the first embodiment. [Figure 7] 11 is a schematic cross-sectional view of a solid-state imaging device according to a second embodiment. FIG. [Figure 8]11A to 11C are schematic cross-sectional views of a solid-state imaging device according to a third embodiment and schematic cross-sectional views for explaining a manufacturing method thereof. [Figure 9] 11 is a schematic cross-sectional view of a solid-state imaging device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The solid-state imaging device of the present invention has a first semiconductor substrate having a photoelectric conversion element disposed on a surface thereof, and a second semiconductor substrate having at least a part of a circuit for generating a signal based on the charge of the photoelectric conversion element disposed on a surface thereof. The first semiconductor substrate and the second semiconductor substrate are disposed so that their surfaces face each other. A wiring structure is disposed between the first semiconductor substrate and the second semiconductor substrate. The solid-state imaging device has a pad to which an external terminal is connected, and the external terminal is connected to a first surface of the pad. In the first solid-state imaging device, a first surface of the pad is located between a virtual plane that includes a surface of the first semiconductor substrate and is parallel to the surface of the second semiconductor substrate, and a second surface that is the surface opposite to the first surface is located between the first surface and the surface of the second semiconductor substrate. The second surface of the pad is connected to the wiring structure so that the pad is connected to a peripheral circuit disposed on the second semiconductor substrate via the wiring structure. In the second solid-state imaging device, a part of the peripheral circuit is disposed on a first semiconductor substrate. A first surface of the pad is located between a surface of the first semiconductor substrate and an imaginary plane including the surface of the second semiconductor substrate and parallel to the surface, and a second surface, which is the surface opposite to the first surface, is located between the first surface and the surface of the first semiconductor substrate. The second surface of the pad is connected to the wiring structure so that the pad is connected to a part of the peripheral circuit disposed on the first semiconductor substrate via the wiring structure, and the part of the peripheral circuit disposed on the first semiconductor substrate is connected to a part of the peripheral circuit disposed on the second semiconductor substrate via the wiring structure. With this configuration, it is possible to provide a solid-state imaging device in which the connection between the pads and the peripheral circuitry is highly reliable.

[0009] The method for manufacturing a solid-state imaging device of the present invention includes a step of bonding a first member and a second member. The first member includes a first semiconductor substrate having a photoelectric conversion element disposed on its surface, and a first wiring structure disposed on the surface of the first semiconductor substrate. The second member includes a second substrate having at least a part of a peripheral circuit disposed on its surface for generating a signal based on the charge of the photoelectric conversion element, and a second wiring structure disposed on the surface of the second semiconductor substrate. The bonding step is performed so as to connect the first wiring structure and the second wiring structure. After the bonding step, the method includes a step of thinning the first semiconductor substrate from the back surface side of the first semiconductor substrate. Before the bonding step, a pad connected to an external terminal is connected to the first wiring structure or the second wiring structure, and after the thinning step, the method includes a step of exposing the pad to the first semiconductor substrate side. Such a manufacturing method makes it possible to easily form connections between the pads and the peripheral circuits.

[0010] The present invention will be described in detail below with reference to the drawings. The above-mentioned first solid-state imaging device will be described with reference to Examples 1 to 3, and the second solid-state imaging device will be described with reference to Example 4. In the description of the embodiments, the main surface of the first substrate and the main surface of the second substrate are the surfaces of the substrates. For each substrate, the surface opposite to the main surface (front surface) is the back surface of the first substrate and the back surface of the second substrate. In addition, for each substrate, the upward direction is the direction from the back surface to the main surface (front surface), and the downward direction and the depth direction are the direction from the main surface (front surface) of the substrate to the back surface. As a solid-state imaging device, the first substrate is disposed on the second substrate in accordance with the display direction of the drawing, and the direction from the second substrate to the first substrate may be referred to as the upward direction, and the direction from the first substrate to the second substrate may be referred to as the downward direction.

[0011] Example 1 A first embodiment of the present invention will be described with reference to FIGS.

[0012] First, the circuit of the solid-state imaging device of the first embodiment will be described with reference to Fig. 3. In this embodiment, the case where the signal charge is, for example, electrons will be described. The solid-state imaging device of Fig. 3 has a pixel section 301 in which a plurality of photoelectric conversion elements are arranged. It also has a peripheral circuit section 302 having peripheral circuits including a readout circuit for reading out signals from the pixel section 301, a control circuit for driving the pixel section 301 and the readout circuit, and a signal processing circuit for processing the readout signals. In the pixel section 301, a photoelectric conversion element 303, a transfer transistor 304, an amplification transistor 306, and a reset transistor 307 are arranged. A configuration including at least one photoelectric conversion element 303 is defined as a pixel. In this embodiment, one pixel includes the photoelectric conversion element 303, the transfer transistor 304, the amplification transistor 306, and the reset transistor 307. The anode of the photoelectric conversion element 303 is grounded. The source of the transfer transistor 304 is connected to the cathode of the photoelectric conversion element 303, and the drain region of the transfer transistor 304 is connected to the gate electrode of the amplification transistor 306. The same node as the gate electrode of the amplification transistor 306 is defined as a node 305. The reset transistor is connected to the node 305, and the potential of the node 305 is set to an arbitrary potential (for example, a reset potential). Here, the amplification transistor 306 is a part of a source follower circuit, and outputs a signal according to the potential of the node 305 to a signal line RL. The node 305 may also be called a floating diffusion. A circuit including the transfer transistor 304, the amplification transistor 306, and the reset transistor 307 is a pixel circuit. The peripheral circuit section 302 indicates an area other than the pixel section 301. In the peripheral circuit section 302, peripheral circuits including a readout circuit and a control circuit are arranged. The peripheral circuit has a vertical scanning circuit VSR, which is a control circuit for supplying a control signal to the gate electrode of the transistor of the pixel section 301. The peripheral circuit also has a readout circuit RC, which holds the signal output from the pixel section 301 and performs signal processing such as amplification, addition, and AD conversion. The peripheral circuit also has a horizontal scanning circuit HSR, which is a control circuit for controlling the timing of sequentially outputting signals from the readout circuit RC.

[0013] Here, the solid-state imaging device of the first embodiment is configured by bonding two members. The two members are a first member 308 having a first substrate 101 and a second member 309 having a second substrate 121. The first substrate 101 is provided with a photoelectric conversion element 303 and a transfer transistor 304 of the pixel unit 301, and the second substrate 121 is provided with an amplification transistor 306, a reset transistor 307, and a peripheral circuit unit 302 of the pixel unit 301. A control signal is supplied from the peripheral circuit unit 302 of the second member 309 to the gate electrode of the transfer transistor 304 of the first member 308 via a connection unit 310. The configuration of the connection unit 310 will be described later. A signal generated in the photoelectric conversion element 303 of the first member 308 is read out to the drain region of the transfer transistor 304, that is, the node 305. The node 305 includes a configuration provided in the first member 308 and a configuration provided in the second member 309. With this configuration, the area of ​​the photoelectric conversion element 303 can be increased and the sensitivity can be improved, compared to the conventional case where all pixel units are arranged on one member (i.e., one substrate). Furthermore, compared to the conventional case where all pixel units are arranged on one member (i.e., one substrate), if the area of ​​the photoelectric conversion element is the same, it is possible to provide more photoelectric conversion elements 303, enabling a multi-pixel configuration. Note that it is sufficient that at least the photoelectric conversion element is arranged on the first substrate, and the amplification transistor 306 may be arranged on the first substrate. Also, a configuration may be adopted in which the photoelectric conversion element and the gate electrode of the amplification transistor are connected without providing a transfer transistor. In the present invention, the elements arranged on the first substrate can be selected arbitrarily, and the configuration of the pixel circuit can also be selected arbitrarily.

[0014] A specific planar layout of such a solid-state imaging device will be described with reference to the schematic plan view of the solid-state imaging device in Fig. 2. Fig. 2(A) shows the planar layout of the first member 308, i.e., the first substrate (101), and Fig. 2(B) shows the planar layout of the second member 309, i.e., the second substrate (121).

[0015] In FIG. 2A, the first member 308 includes a pixel section 301A in which a plurality of photoelectric conversion elements are arranged, and a pad section 312A in which a pad 313 is arranged. In the pixel section 301A, a plurality of photoelectric conversion elements 303, transfer transistors 304, and connection sections 310 and 311 shown in FIG. 3 are arranged. In addition, in the pad section 312A, a connection section 314A for connection to the second member 309 is arranged at the same position as the pad 313 in a plan view. An external terminal is connected to the pad 313. An example of the external terminal is a bonding wire connected to the pad 313 by a wire bonding method. A plurality of pads 313 are arranged in the solid-state imaging device, and include a pad (output pad) that outputs a signal (image signal) based on the charge generated in the photoelectric conversion element, and a pad (input pad) to which a voltage or the like for driving a peripheral circuit supplied from the outside is input.

[0016] Next, in FIG. 2B, the pixel section 301B, the peripheral circuit section 302, and the pad section 312B are arranged in the second member 309. In the pixel section 301B, a part of the pixel circuit is arranged, and the amplification transistor 306, the reset transistor 307, the connection section 310, and the connection section 311 in FIG. 3 are arranged in a plurality of places. In the peripheral circuit section 302, a part of the peripheral circuit is arranged, and a horizontal scanning circuit HSR, a vertical scanning circuit VSR, and a read circuit RC are arranged. The pad section 312B has a protection diode circuit 315. In the pad section 312B, a connection section 314B for connection to the first member 308 is arranged at the same position as the protection diode circuit 315 in a plan view. The protection diode circuit 315 and the connection section 314B do not have to be arranged at the same position in a plan view. The protection diode circuit 315 is connected to the peripheral circuit. Specifically, a plurality of protection diode circuits 315 are provided as shown in FIG. 2B, and the protection diode circuits 315 connected to each pad 313 are connected to the vertical scanning circuit VSR, the horizontal scanning circuit HSE, or the readout circuit RC. As described above, the second substrate 121 is provided with a pixel circuit arranged in the pixel section 301, a peripheral circuit arranged in the peripheral circuit section 302, and a protection diode circuit arranged in the pad section 312B. These circuits are semiconductor integrated circuits, and are composed of many semiconductor elements including transistors, diodes, resistance elements, capacitance elements, etc. By operating the integrated circuit composed of semiconductor elements, a signal based on the charge (signal charge) of the photoelectric conversion element 303 is generated.

[0017] The first member 308 and the second member 309 having the planar layout shown in Fig. 2(A) and Fig. 2(B) are laminated together to form the solid-state imaging device of this embodiment. Specifically, the pixel section 301A and the pixel section 301B are arranged so as to overlap each other. The connection section 314A and the connection section 314B are connected, and the connection section 310 and the connection section 311 of the first member are connected to the connection section 310 and the connection section 311 of the second member. In Fig. 2, the region of the first member 308 corresponding to the peripheral circuit section 302B of the second member 309 is shown as the peripheral circuit section 302A. A part of the scanning circuit, i.e., a part of the peripheral circuit, may be arranged in the peripheral circuit section 302A.

[0018] Next, a schematic cross-sectional view of the solid-state imaging device shown in Figures 2 and 3 will be described with reference to Figure 1. In Figure 1, the same components as those in Figures 2 and 3 are denoted by the same reference numerals, and description thereof will be omitted.

[0019] The first member 308 has a first wiring structure 149 and a first substrate 101. The first substrate 101 is, for example, a silicon semiconductor substrate, and has a main surface 102 and a back surface 103. A transistor is disposed on the main surface 102 of the first substrate. The first wiring structure 149 has interlayer insulating films 104 to 106, a gate electrode layer 107 including gate electrodes and wiring, wiring layers 109 and 111 including a plurality of wirings, and contact layers 108 and 110 including a plurality of contacts or vias. Here, the number of layers of the interlayer insulating film, wiring layer, and contact layer included in the first wiring structure 149 can be set arbitrarily. In this embodiment, the number of layers of the wiring layer is two. The wiring layer 111 of the first wiring structure 149 includes a connection portion. In the pixel section 301 of the first member 308, the first substrate 101 is provided with an n-type semiconductor region 112 constituting a photoelectric conversion element, an n-type semiconductor region 114 which is the drain of a transfer transistor, and an element isolation structure 119. The transfer transistor is composed of the n-type semiconductor region 112, the n-type semiconductor region 114, and a gate electrode 113 included in the gate electrode layer 107. Here, the charge stored in the n-type semiconductor region 112 is transferred to the n-type semiconductor region 114 by the gate electrode 113. The potential based on the charge transferred to the n-type semiconductor region 114 is transmitted to the second member 309 via the contact of the contact layer 108, the wiring of the wiring layer 109, the via of the contact layer 110, and the wiring of the wiring layer 111. The wiring of the wiring layer 111 constitutes a connection section 311. The photoelectric conversion element may be a buried photodiode having a p-type semiconductor region, or may be a photogate, and may be appropriately changed.

[0020] On the back surface 103 side of the first substrate 101 of the pixel section 301, a planarization layer 115, a color filter layer 116 including a plurality of color filters, a planarization layer 117, and a microlens layer 118 including a plurality of microlenses are arranged in this order. In Fig. 1, the plurality of color filters and the plurality of microlenses are arranged corresponding to one photoelectric conversion element, that is, for each pixel, but one may be provided for each plurality of pixels. The solid-state imaging device of this embodiment is a so-called back-illuminated solid-state imaging device in which light is incident from the microlens layer 118 side and received by the photoelectric conversion element.

[0021] The pad portion 312 of the first member 308 is provided with a pad 313 and an opening 100 exposing the pad 313 for connecting to an external terminal. In this embodiment, the pad 313 is taken as an example of an input pad. The pad 313 is a conductive film and has a first surface 3131 and a second surface 3132 opposite to the first surface. The first surface 3131 of the pad 313 is exposed on the first substrate 101 side, and an external terminal is connected to the first surface 3131. Also, a connection portion 314A is provided for transmitting a voltage input from the pad 313 to the second member 309. The connection portion 314A is arranged at the same position as the pad 313 in a plan view. In addition, in the first member 308, an arbitrary circuit element 120 is provided in an area corresponding to the peripheral circuit portion 302 of the second member 309 as shown in FIG. 1.

[0022] The second member 309 has a second wiring structure 150 and a second substrate 121. The second substrate 121 is, for example, a silicon semiconductor substrate, and has a main surface 122 and a back surface 123. A transistor is disposed on the main surface 122 of the second substrate. The second wiring structure 150 has interlayer insulating films 124-127, a gate electrode layer 128 including gate electrodes and wiring, wiring layers 130, 132, 134 including a plurality of wirings, and contact layers 129, 131, 133 including a plurality of contacts or vias. Here, the number of interlayer insulating films, wiring layers, and contact layers included in the second wiring structure 150 can be set arbitrarily. In this embodiment, the number of wiring layers in the second wiring structure 150 is three, which is more than the number of wiring layers in the first wiring structure 149. The wiring layer 134 includes a connection portion. In the pixel section 301 of the second member 309, the second substrate 121 is provided with a well 135 constituting an amplifying transistor of the pixel circuit, an n-type semiconductor region 138 constituting the source-drain region of the amplifying transistor, and an element isolation structure 136. The amplifying transistor is provided in the well 135 and is composed of a gate electrode 137 included in the gate electrode layer 128 and the n-type semiconductor region 138 constituting the source-drain region. Here, the connection section 311 of the first member 308 and the gate electrode 137 of the amplifying transistor are connected via the wiring of the wiring layer 134, the via of the contact layer 133, the wiring of the wiring layer 132, the via of the contact layer 131, the wiring of the wiring layer 130, and the contact of the contact layer 129. 1, the wiring of the wiring layers 109, 111, 134, 132, and 130, the contacts or vias of the contact layers 108, 110, 133, 131, and 129, and the gate electrode 137. Other circuits (e.g., a reset transistor) of the pixel section 301 are not shown.

[0023] Next, at least a part of the peripheral circuit including control circuits such as a horizontal scanning circuit and a vertical scanning circuit and a readout circuit is disposed in the peripheral circuit section 302 of the second member 309. FIG. 1 shows an n-type transistor and a p-type transistor in an arbitrary circuit included in the peripheral circuit. An n-type transistor including a gate electrode 140 included in the gate electrode layer 128 and an n-type source / drain region 141 is disposed in a p-type well 139. A p-type transistor including a gate electrode 143 included in the gate electrode layer 128 and a p-type semiconductor region 144 constituting a p-type source / drain region is disposed in an n-type well 142. A protection diode circuit 315 for inputting a signal from a pad 313 of the first member 308 and a connection portion 314B for connecting to the first member 308 are disposed on the pad portion 312 of the second member 309. The connection portion 314B is disposed in the same position as the protection diode circuit 315 in a plan view. The protection diode circuit 315 of this embodiment includes two diodes 145 and 146 formed from semiconductor regions, and two resistors 147 and 148 formed from the gate electrode layer 128.

[0024] The resistor 147 is an input of the protection diode circuit 315, and the resistor 148 is an output of the protection diode. The protection diode circuit 315 has the following configuration. One end of the resistor 147 is connected to the pad 313, and the other end of the resistor 147 is connected to the anode of the diode 145, the cathode of the diode 146, and one end of the resistor 148 via the wiring layer 130. The other end of the resistor 148 is connected to a circuit element 320 of the subsequent peripheral circuit section 302 (for example, the vertical scanning circuit VSR or the horizontal scanning circuit HSR). That is, at a node represented by the wiring layer 130, the other end of the resistor 147, the anode of the diode 145, the cathode of the diode 146, and one end of the resistor 148 are connected. The cathode of the diode 145 is connected to a predetermined voltage VDD by a wiring not shown, and the anode of the diode 146 is connected to a voltage VSS different from the predetermined voltage by a wiring not shown. Here, the voltage relationship is VDD>input voltage>VSS. Also, VSS may be a reference voltage GND as long as it is lower than VDD. By providing such a protection diode circuit, for example, when a voltage larger than the sum of the forward voltage drop of VDD and the diode 145 is input to the pad 313, a forward bias is applied to the diode 145, and a current flows from the node to VDD. Therefore, it is possible to prevent a voltage larger than the sum of the forward voltage drop of VDD and the diode 145 from being applied to the circuit at the subsequent stage. Also, when a voltage smaller than the difference between the forward voltages of VSS and the diode 146 is input to the pad, a forward bias is applied to the diode 146, and a current flows from VSS to the node. Therefore, it is possible to prevent a voltage smaller than the difference between the forward voltages of VSS and the second diode 146 from being applied to the circuit at the subsequent stage. Note that the resistors 147 and 148 have the effect of dropping the input voltage and reducing the absolute value of the voltage applied to the subsequent stage.

[0025] The protection diode circuit 315 shown in this embodiment is an example and is not limited to this embodiment. A protection diode circuit with a generally used configuration is applicable. For example, the above protection diode circuit 315 is effective when the input voltage satisfies VDD > input voltage > VSS. However, a protection diode circuit corresponding to VDD < input voltage or input voltage < VSS may be provided as needed. In this case, only one diode may be used for the protection diode circuit. Here, the input pad is taken as an example, but similarly, the protection diode circuit 315 can also be connected to the output pad. In that case, the resistor 148 can be used as the input of the protection diode circuit 315, the resistor 147 can be used as the output of the protection diode circuit 315, and the other end of the resistor 148 can be connected to the circuit element 320 of the peripheral circuit section 302 (e.g., the readout circuit RC) in the previous stage. Also, the protection diode circuit may be arranged in the electrical path between the pixel circuit and the pad. The protection diode circuit 315 connected to the output pad can also suppress the output of an abnormal signal to the outside of the device when an abnormal signal occurs inside the solid-state imaging device. A protection circuit such as the protection diode circuit 315 can reduce the intrusion of external noise from the pad 313. Also, it can protect the subsequent-stage circuit against misinput and surge voltage. As causes of external noise, as described above, misinput, voltage surge, etc. can be cited. In particular, in protecting the peripheral circuit from the voltage surge caused by electrostatic discharge (ESD: Electro-Static Discharge), it is very meaningful to arrange the protection diode circuit 315 on the second substrate 121. Since the voltage surge caused by electrostatic discharge is likely to be mixed in without distinguishing between the input pad and the output pad, it is desirable that the protection diode circuits be arranged corresponding to both the input pad and the output pad respectively. Note that, as an example of the protection circuit arranged to reduce the intrusion of external noise, the protection diode circuit is taken as an example, but it is not limited to the protection circuit using a diode, and a protection circuit using a transistor can also obtain the same effect. Note that the protection diode circuit 315 may be omitted, and the input pad may be connected to the peripheral circuit or the pixel circuit, or the output pad may be connected to the peripheral circuit.However, in terms of improving electrical reliability, it is desirable to provide a protection circuit between the input pad and / or output pad and the peripheral circuit unit 302. Also, the protection circuit may be disposed midway along the electrical path between the pixel circuit and the pad.

[0026] In the solid-state imaging device of this embodiment, the main surface 102 of the first substrate 101 and the main surface 122 of the second substrate 121 are arranged in a direction facing each other via the first wiring structure 149 and the second wiring structure 150 (opposite arrangement). That is, the first substrate 101, the first wiring structure 149, the second wiring structure 150, and the second substrate 121 are arranged in this order. The upper surface of the first wiring structure 149 and the upper surface of the second wiring structure 150 are bonded together at the bonding surface X. That is, the first member 308 and the second member 309 are bonded together at the bonding surface X. The bonding surface X is composed of the upper surface of the first wiring structure 149 and the upper surface of the second wiring structure 150. As a result, the first wiring structure 149 and the second wiring structure 150 are integrated to form the wiring structure 151 between the first substrate 101 and the second substrate 121. The wiring structure 151 has five wiring layers, 109, 111, 130, 132, and 134. Note that a connecting member such as microbonding may be used between the first wiring structure 149 and the second wiring structure 150, or metal bonding may be used. Such bonding is achieved by connection parts 311 and 314.

[0027] A pad 313 of the solid-state imaging device for transmitting signals to and from the outside is disposed on the upper portion of the surface of the second substrate 121, which is the main surface 122 of the second member 309, and an opening 100 is provided on the first member 308 side.

[0028] That is, both the first surface 3131 and the second surface 3132 of the pad 313 are located closer to the first substrate 101 than the main surface 122. Here, consider a virtual plane 1020 by expanding the main surface 102 of the first substrate 101. The virtual plane 1020 is a surface that is an imaginary extension of the main surface 102, is parallel to the main surface 102, and includes the main surface 102. Therefore, in FIG. 1, the virtual plane 1020 crosses the opening 100. The pad 313 is located between the main surface 122 of the second substrate 121 and the virtual plane 1020. In detail, the first surface 3131 of the pad 313 is located between the virtual plane 1020 and the second surface 3132, and the second surface 3132 of the pad 313 is located between the first surface 3131 and the main surface of the second substrate 121. In this embodiment, the pad 313 is disposed in the same layer as the first wiring layer 109, counting from the imaginary plane 1020 side, among the five wiring layers.

[0029] In this manner, the pad 313 is located between the main surface 122 of the second substrate 121 and the virtual plane 1020, so that the distance between the pad 313 and the second substrate 121 can be made smaller than the distance between the first substrate 101 and the second substrate 121. As a result, the electrical path between the pad 313 and the peripheral circuit can be shortened. As a result, the delay and loss of signals in the input and / or output can be reduced. The distance (spacing) between the first substrate 101 and the second substrate 121 is practically in the range of 1 μm to 10 μm. If the distance between the pad 313 and the second substrate 121 is 5 μm or less, it can be said that the electrical path is sufficiently short. The distance (spacing) between the first substrate 101 and the second substrate 121 is preferably 1.5 μm to 3.0 μm, and in this case, the electrical path from the pad 313 to the protection diode circuit 315 can be made several μm or less, or even on the submicron order.

[0030] In addition, since there is no need to provide an opening in the second member 309, it is possible to reduce the intrusion of moisture into the peripheral circuit section of the second member 309. In this embodiment, the number of elements arranged near the pad section 312A of the first member 308 can be easily made smaller than the number of elements arranged near the pad section 312B of the second member 309. Then, the elements arranged near the pad section of the first member 308 can be placed farther away than the elements arranged near the pad section of the second member 309. Therefore, it is possible to further reduce the influence of moisture from the opening 100 for the pad on the elements. In addition, since the external terminal is arranged on the back side of the first member 308, it becomes easier to connect to the pad 313, and connection failures are reduced.

[0031] In the pad section 312, the pad 313 is connected to the protection diode circuit 315 via the contact layer 110 and the wiring layer 111 (connection portion 314A) of the first wiring structure 149, and further via the wiring layer 134 (connection portion 314B) of the second wiring structure 150, the contact layer 133, the wiring layer 132, the contact layer 131, the wiring layer 130, the contact layer 129, and the gate electrode layer 128. In this manner, the second surface 3132 of the pad 313 is connected to the wiring structure 151. With this configuration, the pad 313 is located between the main surface 122 of the second substrate 121 and the virtual plane 1020, and an electrical path is formed from the second surface 3132 of the pad 313, so that the electrical path between the pad 313 and the protection diode circuit 315 can be shortened. As a result, the electrical path between the pad 313 and the peripheral circuit can also be shortened.

[0032] As described above, the pad portion 312B has the connection portion 314B for connection to the first member at the same position as the protection diode circuit 315 in a plan view. Furthermore, the pad portion 312A has the connection portion 314A for connection to the second member 309 at the same position as the pad 313 in a plan view. By connecting the connection portion 314A and the connection portion 314B, the protection diode circuit 315 and the pad 313 are also arranged at the same position in a plan view, so that the protection diode circuit 315 and the pad 313 overlap each other. Therefore, it is possible to connect the protection diode circuit 315 and the pad 313 via the shortest electrical path. When the protective diode circuit 315 is omitted, the peripheral circuit section 302 and the circuit element 320 may be disposed at a position overlapping the pad 313 and connected to the pad 313 via the wiring structure 151 .

[0033] Moreover, in this embodiment, pad 313 is connected to a plurality of vias in contact layer 133. In this manner, by connecting wiring structure 151 and pad 313, which is easily subjected to external force, at a plurality of locations, the force applied to wiring structure 151 is dispersed, and impact on second substrate 10 and wiring structure 151 is mitigated. Even if the connection with any of the vias is damaged, the connection between pad 313 and wiring structure 151 is more likely to be maintained, improving reliability.

[0034] Next, a method for manufacturing the solid-state imaging device of this embodiment will be described with reference to Figs. 4 to 6. Fig. 4 is a schematic cross-sectional view showing the manufacturing process of the first member 308, Fig. 5 is a schematic cross-sectional view showing the manufacturing process of the second member 309, and Fig. 6 is a schematic cross-sectional view showing the manufacturing process after the first member 308 and the second member 309 are bonded together. A manufacturing process of the first member 308 in Fig. 1 will be described with reference to Fig. 4. In Fig. 4, the configuration that will later become the first member 308 in Fig. 1 is designated as 308', and the portions that will become the pixel section 301, peripheral circuit section 302, pad section 312, and circuit element 120 that is a part of the peripheral circuit in Fig. 1 are designated as 304', 302', 312', and 120'.

[0035] First, a semiconductor substrate is prepared, and elements are formed on the semiconductor substrate. A semiconductor substrate 401 having a main surface 402 and a back surface 403 and a thickness D3 is prepared. The semiconductor substrate 401 is, for example, a silicon semiconductor substrate. An element isolation structure 119 is formed on the semiconductor substrate 401. The element isolation structure 119 includes an insulator such as a silicon oxide film, and has, for example, a LOCOS or STI structure. Then, a well (not shown) of an arbitrary conductivity type is formed on the semiconductor substrate 401. After that, n-type semiconductor regions 112 and 114 and p-type semiconductor regions (not shown) that constitute photoelectric conversion elements and transistors are formed. In addition, a gate electrode layer 107 including a gate electrode including a gate electrode 113 of a transfer transistor is formed. The gate electrode layer is formed, for example, by deposition and patterning of a polysilicon layer, and may include not only a gate electrode but also wiring. Here, the method of forming the gate electrode, element isolation, and semiconductor region can be formed by a general semiconductor process, and detailed description will be omitted. As a result of the above, the configuration of FIG. 4(A) is obtained.

[0036] Next, a wiring structure is formed on the main surface 402 of the semiconductor substrate 401. The wiring structure includes interlayer insulating films 104', 105, and 106, contact layers 108 and 110, and wiring layers 109 and 111. Here, the interlayer insulating film 104' will later become the interlayer insulating film 104 in FIG. 1. The interlayer insulating film 104' covers the gate electrode layer 107, the contact layer 108 is disposed on the interlayer insulating film 104', and the wiring layer 109 and the pad 313 are disposed on the interlayer insulating film 104'. Also, the interlayer insulating film 105 covers the wiring layer 109, the contact layer 110 is disposed on the interlayer insulating film 105, the wiring layer 111 is disposed on the interlayer insulating film 105, and the interlayer insulating film 106 is disposed on the interlayer insulating film 105 and has an opening that exposes the wiring of the wiring layer 111. The upper surface of the wiring structure is formed by the upper surface of the interlayer insulating film 106 and the upper surface of the wiring layer 111 .

[0037] Here, the interlayer insulating film is a silicon oxide film. However, the interlayer insulating film may be formed of a silicon nitride film, an organic resin, or the like. The wiring layer is made of wiring mainly made of aluminum or wiring mainly made of copper. The contact is made of, for example, tungsten, and the via can be formed integrally with wiring mainly made of tungsten or copper. Here, the wiring layer 111 includes the connection parts 314A and 311A, and is made of wiring mainly made of copper. The wiring layer 109 is made of wiring mainly made of aluminum. The pad 313 is disposed in the same layer as the wiring layer 109, and is mainly made of aluminum. The manufacturing method of these wiring layer, contact layer, interlayer insulating film, and pad 313 can be formed by a general semiconductor process, and detailed description will be omitted. As described above, the configuration of FIG. 4(B) is obtained. In FIG. 4(B), the reference numerals 104', 105, 106, 108 to 111 will later become the first wiring structure 149 in FIG. 1. Moreover, the connection portion 311A ​​will later constitute the connection portion 311.

[0038] Next, a manufacturing process of the second member 309 in Fig. 1 will be described with reference to Fig. 5. In Fig. 5, the configuration that will later become the second member 309 in Fig. 1 is designated as 309', and the portions that will become the pixel section 301, the peripheral circuit section 302, the pad section 312, and the protection diode circuit 315 in Fig. 1 are designated as 304', 302', 312', and 315'.

[0039] First, a semiconductor substrate is prepared, and elements are formed on the semiconductor substrate. A semiconductor substrate 404 having a main surface 405 and a back surface 406 and a thickness D4 is prepared. Then, an element isolation structure 136 is formed on the semiconductor substrate 404 using a LOCOS or STI structure. Also, p-type wells 135, 139 and an n-type well 142 are formed on the semiconductor substrate 404. Then, n-type semiconductor regions 138, 141 and a p-type semiconductor region 144 that can become source and drain regions constituting transistors, and a semiconductor region constituting a diode are formed. Then, a gate electrode layer 128 including gate electrodes 137, 140, 143 and wiring (resistance) of the transistors is formed by deposition and patterning of a polysilicon layer. Here, the method of forming the gate electrode, element isolation, and semiconductor region can be formed by a general semiconductor process, and detailed description will be omitted. As a result of the above, the configuration of FIG. 5(A) is obtained.

[0040] Next, a wiring structure is formed on the main surface 405 of the semiconductor substrate 404. The wiring structure has interlayer insulating films 124 to 127, contact layers 129, 131, and 133, and wiring layers 130, 132, and 134. The interlayer insulating film 124 covers the gate electrode layer 128, the contact layer 129 is disposed in the interlayer insulating film 124, and the wiring layer 130 is disposed on the interlayer insulating film 124. The interlayer insulating film 125 covers the wiring layer 130, the contact layer 131 is disposed in the interlayer insulating film 125, the wiring layer 132 is disposed on the interlayer insulating film 125, and the interlayer insulating film 126 covers the wiring layer 132 and is disposed on the interlayer insulating film 125. The contact layer 133 is disposed on the interlayer insulating film 126, the wiring layer 134 is disposed on the interlayer insulating film 126, and the interlayer insulating film 127 is disposed on the interlayer insulating film 126 and has an opening that exposes the wiring of the wiring layer 134. The upper surface of the wiring structure is formed by the upper surface of the interlayer insulating film 127 and the upper surface of the wiring layer 134.

[0041] Here, the interlayer insulating film is a silicon oxide film. It may also be formed of a silicon nitride film, an organic resin, or the like. The wiring layer is composed of wiring mainly made of aluminum or wiring mainly made of copper. Here, the wiring layer 134 includes connection portions 314B and 311B and is composed of wiring mainly made of copper. The manufacturing methods of these wiring layers, contact layers, and interlayer insulating films can be formed by general semiconductor processes, and detailed descriptions thereof are omitted. Thus, the configuration of FIG. 5(B) is obtained. In FIG. 5(B), reference numerals 124 to 127, 129 to 134, etc. will later become the first wiring structure 150 in FIG. 1. Also, the connection portion 311B will later constitute the connection portion 311.

[0042] The first member 308' and the second member 309' shown in FIGS. 4(B) and 5(B) are bonded together such that the main surfaces 402 and 405 of the semiconductor substrates face each other. That is, the uppermost surface of the wiring structure of the first member 308' and the uppermost surface of the wiring structure of the second member 309' are joined. Here, since the connection portions 311A, 311B and the connection portions 314A, 314B are composed of wiring mainly made of copper, they can be bonded by copper metal bonding during the bonding process. After the first member 308' and the second member 309' are bonded, the semiconductor substrate 401 is thinned from the back surface 403 side of the semiconductor substrate 401 of the first member 308' to make the semiconductor substrate 401 into a thin film. The thinning can be performed by CMP (chemical mechanical polishing) or etching. Then, the semiconductor substrate 401 becomes the semiconductor substrate 407, and the thickness becomes from D3 to D1 (D1 < D3) (FIG. 6(A)). By thinning the semiconductor substrate 401 in this way to make the semiconductor substrate 407, it becomes possible for incident light to efficiently enter the photoelectric conversion element later. Also, at this time, the thickness D1 of the semiconductor substrate 407 < the thickness D4 of the semiconductor substrate 404.

[0043] Next, a planarization layer 409 made of resin, a color filter layer 410, a planarization layer 411 made of resin, and a microlens layer 412 are formed on the back surface 408 of the semiconductor substrate 407 in this order. The manufacturing methods of these planarization layers, color filter layer, and microlens layer can be formed by general semiconductor processes, and detailed descriptions are omitted. Here, the microlens layer may be formed up to the region 312' that becomes the pad portion. Through the above steps, the configuration of FIG. 6(B) is obtained.

[0044] Then, an opening 100 for exposing the pad 313 is formed. Here, a photoresist mask having an arbitrary opening is provided on the microlens layer 412 using photolithography technology. Then, using dry etching technology, the microlens layer 412, planarization layer 411, color filter layer 410, planarization layer 409, semiconductor substrate 407, and the interlayer insulating film 104' are removed to form the opening 100 and expose the pad 313 from this opening 100.

[0045] Then, a microlens layer 118, planarization layers 117, 115, a color filter layer 116, a first substrate 101, and an interlayer insulating film 104 are formed. In this way, the configuration of FIG. 1 is obtained. Note that the semiconductor substrate 404, main surface 405, back surface 406, and thickness D4 in FIG. 6(B) correspond to the second substrate 121, main surface 122, back surface 123, and thickness D2 in FIG. 1. Here, although there is no change in the thicknesses D4 and D2, the semiconductor substrate 404 may be thinned so that D2 < D4. Although the number of steps increases due to the thinning, miniaturization of the solid-state imaging device becomes possible.

[0046] As described above, by performing etching for exposing the pads from the back surface 408 side of the thinned semiconductor substrate 407, it is possible to shorten the time required for etching to form the pads. Furthermore, the pads 313 can be formed in the same process as the wiring of the wiring layer 109, and the number of steps can be reduced. Moreover, the pads 313 are preferably made of a metal containing aluminum as a main component in order to reduce the connection resistance with the external terminals as in this embodiment. During etching, the pads 313 can also function as an etching stopper.

[0047] The present invention is not limited to the steps described in the manufacturing method of this embodiment, and the order of steps may be changed. The manufacturing order of the first member 308 and the second member 309 can be set appropriately. Furthermore, it is also possible to purchase the first member 308 and the second member 309 and bond them together to form the structure. It is also possible to use SOI substrates for the semiconductor substrates 401 and 402.

[0048] Example 2 A second embodiment of the present invention will be described with reference to Fig. 7. Fig. 7(A) and Fig. 7(B) are schematic cross-sectional views of a solid-state imaging device, and each corresponds to Fig. 1. In Fig. 7, the same elements as in Fig. 1 are given the same reference numerals, and the description thereof will be omitted.

[0049] In this embodiment, the configuration different from that of the first embodiment is the opening 700 and the pad 701 in FIG. 7(A) and the opening 702 and the pad 701 in FIG. 7(B). In this embodiment, the opening 700 and the opening 702 are deeper than those of the first embodiment, and the pad 701 is closer to the main surface 122 of the second member 309 than that of the first embodiment. As described above, the pad may be disposed at any position as long as it is disposed closer to the first member 308 than the main surface 122 of the second member 309 and between the virtual plane 1020 and the main surface 122. However, by disposing the pad close to the second member 309 as in this embodiment, it is possible to reduce the connection resistance from the pad 701 to the protection diode circuit 315 compared to the first embodiment. In this embodiment, the wiring structure 151 has five wiring layers as in the first embodiment, but the pad 701 is disposed in the same layer as the third wiring layer 134 counting from the virtual plane 1020 side among the five wiring layers. In this way, it is preferable to arrange the pad 701 in the wiring layer (wiring layers 134, 132, 130) farther from the virtual plane 1020 than the wiring layer (wiring layers 109, 111) on the virtual plane 1020 side. That is, when the number of wiring layers N is an odd number, it is preferable to arrange the pad 701 in the same layer as the (N+1) / 2 to Nth wiring layers counting from the virtual plane 1020 side. When the number of wiring layers N is an even number, it is preferable to arrange the pad 313 in the same layer as the 1+(N / 2) to Nth wiring layers counting from the virtual plane 1020 side. Also, in FIG. 7(B), the shape of the opening 702 is different from the opening 100 of the first embodiment and the opening 700 of FIG. 7(A). As shown in FIG. 7(B), unnecessary interlayer insulating films and semiconductor substrates located outside the pad portion of the first member 308 may be removed. Also, by making the first member 308 smaller than the second member 309 or by offsetting the end faces of the first member 308 and the second member 309 in advance, it is possible to omit part or all of the process of etching the first member 308 to provide the opening 702. The opening 702 opens toward the end of the device, but in order to prevent moisture and the like from entering the pad portion, it is preferable to provide a through hole in the first substrate 101 so that the opening 700 is a space surrounded by the first substrate 101, as shown in FIG.

[0050] The pad 701 is disposed in the same layer as the wiring layer 134 of the second member 309. Here, the same layer means that they are formed in the same process or have the same height from the main surface. The pad 701 is included in the same layer as the wiring layer 134 and is formed in the same process. Therefore, it is preferable that the wiring layer 134 is a wiring mainly composed of aluminum. In this embodiment, the wiring is mainly composed of copper as in the first embodiment, but since it is the same layer as the pad 701, it is more preferable that the wiring layer 134 is a wiring mainly composed of aluminum. In this case, the connection portion 311 may be joined by a microbump or the like.

[0051] (Third Example) Third Embodiment A third embodiment of the present invention will be described with reference to Fig. 8. Fig. 8(C) is a schematic cross-sectional view of a solid-state imaging device of this embodiment, and corresponds to Fig. 1. Figs. 8(A) and 8(B) are schematic cross-sectional views for explaining a method for manufacturing a solid-state imaging device of this embodiment, and correspond to Fig. 6. In Fig. 8, the same components as those in Figs. 1 and 6 are denoted by the same reference numerals, and description thereof will be omitted.

[0052] The configuration of this embodiment differs from that of the first embodiment in the configuration of the opening 811 and the protective film 806 in FIG. 8(C). The protective film 806 of this embodiment covers the sidewall (side surface) of the first substrate 101 having the opening 811. Furthermore, the protective film 806 extends from the sidewall to cover the periphery of the first surface 3131 of the pad 313. By having such a protective film 806, it is possible to reduce the intrusion of moisture into the inside of the device from the opening 811. Furthermore, if an external terminal for connecting with the pad 313 comes into contact with a conductor such as the first substrate 101, leakage occurs. The protective film 806 prevents the external terminal from coming into contact with the conductor, and suppresses the occurrence of leakage. Furthermore, the protective film 806 of this embodiment is also disposed on the incident surface of the photoelectric conversion unit of the pixel unit 301 (i.e., the back surface 103 of the first substrate 101), and can also function as an anti-reflection film. Incidentally, by having the protective film 806, the configuration of the opening is different from that of the first embodiment. Furthermore, the configurations of the planarization layer 807, the color filter layer 808, the planarization layer 809, and the microlens layer 810 may also be changed to configurations different from those in the first embodiment.

[0053] The manufacturing method of this embodiment will be described with reference to Fig. 8(A) and Fig. 8(B). The method is the same as that of the first embodiment up to Fig. 6(A), so the description will be omitted. An opening 800 is formed in the semiconductor substrate 407 of Fig. 6(A) by photolithography and etching techniques to form the first substrate 101. The opening 800 is formed so as to expose the pad 313. Thereafter, a silicon nitride film 801, which can serve as a protective film, is formed by a method such as plasma CVD so as to cover the side of the opening 800 and the rear surface 103 of the first substrate 101, thereby obtaining the configuration of Fig. 8(A).

[0054] Thereafter, a planarization layer 802, a color filter layer 803, a planarization layer 804, and a microlens layer 805 are formed in this order so as to cover the silicon nitride film 801. The materials and manufacturing method are the same as those in the first embodiment. Then, an opening 811 is formed. The opening 811 penetrates the silicon nitride film 801, the planarization layer 802, the color filter layer 803, the planarization layer 804, and the microlens layer 805, and exposes a part of the first surface 3131 of the pad 313 so that the protective film 806 covers only the periphery of the first surface 3131 of the pad 313. Here, the silicon nitride film 801, the planarization layer 802, the color filter layer 803, the planarization layer 804, and the microlens layer 805 become the protective film 806, the planarization layer 807, the color filter layer 808, the planarization layer 809, and the microlens layer 810, respectively. Then, the solid-state imaging device shown in FIG. 8(C) is manufactured.

[0055] (Fourth Example) Third Embodiment A third embodiment of the present invention will be described with reference to Fig. 9. Fig. 9 is a schematic cross-sectional view of a solid-state imaging device according to the third embodiment, and corresponds to Fig. 1. In Fig. 9, the same components as those in Figs. 1 and 6 are given the same reference numerals, and the description thereof will be omitted. This embodiment differs from the first embodiment in that the opening 900 is provided in the second substrate 121 instead of the first substrate 101, and that the protection diode circuit 315 is disposed in the first substrate 101 instead of the second substrate 121. These points will be described below.

[0056] A pad 313 of the solid-state imaging device for exchanging signals with the outside is disposed under the surface of the first substrate 101, which is the main surface 102 of the first member 308, and an opening 900 is provided on the second member 309 side. The pad 313 has a first surface 3131 and a second surface 3132, which is the surface opposite to the first surface 3131. The first surface 3131 of the pad 313 is exposed on the second substrate 121 side, and an external terminal is connected to this first surface 3131. In other words, both the first surface 3131 and the second surface 3132 of the pad 313 are located closer to the second substrate 121 than the main surface 102. Here, the main surface 122 of the second substrate 121 is expanded to consider a virtual plane 1220. The virtual plane 1220 is a surface that is an imaginary extension of the main surface 122, is parallel to the main surface 122, and includes the main surface 122. Therefore, the virtual plane 1220 crosses the opening 900 in FIG. 9. The pad 313 is located between the main surface 122 of the first substrate 101 and the virtual plane 1220. In detail, the first surface 3131 of the pad 313 is located between the virtual plane 1220 and the second surface 3132, and the second surface 3132 of the pad 313 is located between the first surface 3131 and the main surface 102 of the first substrate 101. In this embodiment, the pad 313 is disposed in the same layer as the first wiring layer 130 counting from the virtual plane 1220 side among the five wiring layers. The wiring layer 130 is composed of wiring mainly made of aluminum, and the pad 313 is also composed of aluminum mainly. The wiring layer 111 includes a connection portion 314A and a connection portion 311, and the wiring layer 134 includes a connection portion 314B and a connection portion 311, and each is composed of wiring mainly made of copper.

[0057] As in the second embodiment, the connection resistance can be reduced by arranging the pad 313 in the wiring layer (wiring layers 134, 111, 109) farther from the virtual plane 1220 than the wiring layer (wiring layers 130, 132) on the virtual plane 1220 side. However, in this embodiment, the thickness D1 of the first substrate 101 is smaller than the thickness D2 of the second substrate 121. If the distance between the first surface 3131 of the pad 313 and the back surface 103 of the first substrate 101 becomes extremely small, the mechanical strength of the pad portion 312 decreases. Therefore, it is preferable to arrange the pad 313 in the same layer as the wiring layer (wiring layers 130, 132) on the virtual plane 1220 side to ensure a sufficient distance between the first surface 3131 of the pad 313 and the back surface 103 of the first substrate 101.

[0058] The protection diode circuit 315 is disposed in a pad section 312 of the first member 308. In addition, in the peripheral circuit section 302, a circuit element 320 constituting a certain part of the peripheral circuit is disposed on the first substrate 101, and the circuit element 320 is connected to another part of the peripheral circuit disposed on the second substrate 121 via the wiring structure 151. The wiring layer connecting the peripheral circuits disposed on both substrates includes at least the wiring layer 111 and the wiring layer 134 including a connection section. In the pad section 312, the pad 313 is connected to the protection diode circuit 315 via the contact layer 131 and the wiring layer 132, the contact layer 133 and the wiring layer 134 (connection section 314B) of the second wiring structure 150, and further via the wiring layer 111 (connection section 314A), the contact layer 110, the wiring layer 109, the contact layer 108, and the gate electrode layer 107 of the first wiring structure 149. The second surface 3132 of the pad 313 is connected to the contact layer 131 at a plurality of points. In this manner, when the protection diode circuit 315, which is a part of the semiconductor integrated circuit, is provided on the first substrate 101, a configuration can be adopted in which the pad 313 is located between the main surface 102 and the imaginary plane 1220 to provide an electrical path from the second surface 3132. This configuration can shorten the electrical path between the pad 313 and the protection diode circuit 315, and further between the pad 313 and the peripheral circuit. In this embodiment as well, the distance between the pad 313 and the first substrate 101 is preferably 5 μm or less.

[0059] In this embodiment, the protection diode circuit 315 is connected to a circuit element 320 which is a part of the peripheral circuit, and the circuit element 320 is connected to another part of the peripheral circuit arranged on the second substrate 121 via the wiring structure 151. However, the circuit element 320 of the peripheral circuit is not limited to being connected to the protection diode circuit 315. For example, the protection diode circuit 315 may be connected to a pixel circuit (e.g., a transfer transistor) arranged on the first substrate 101, and the pixel circuit and the peripheral circuit arranged on the second substrate 121 may be connected via the wiring structure 151. In addition, the protection diode circuit 315 may be connected directly to the peripheral circuit arranged on the second substrate 121 via the wiring structure 151, without passing through the peripheral circuit arranged on the first substrate 101. In addition, in the solid-state imaging device of this embodiment, a bonding wire can be used as an external terminal as in the first embodiment, but flip-chip bonding can also be used. By arranging the external terminals on the rear surface 123 of the second substrate 121, it is possible to suppress deterioration or damage to the external terminals, and the intrusion of moisture from around the pads.

[0060] The opening 900 can be formed by etching a part of the second substrate 121 and the second wiring structure 150. In this embodiment, the end of the second substrate 121 may be removed as in the case of FIG. 7B described in the second embodiment, and a protective film may be provided as in the third embodiment.

[0061] As described above, according to the solid-state imaging device of this embodiment, it is possible to provide a solid-state imaging device having highly reliable connections between the pads and the circuitry.

[0062] Hereinafter, as an application example of the solid-state imaging device according to each of the above embodiments, an imaging system incorporating the solid-state imaging device will be described by way of example. The imaging system includes not only devices such as cameras whose main purpose is to capture images, but also devices (e.g., personal computers, mobile terminals) that are provided with an auxiliary imaging function. For example, a camera includes the solid-state imaging device according to the present invention and a processing unit that processes signals output from the solid-state imaging device. This processing unit may include, for example, an A / D converter and a processor that processes digital data output from the A / D converter. The signal to be processed is input to the processing unit via an external terminal such as a bonding wire connected to a pad of the solid-state imaging device.

[0063] As described above, the solid-state imaging device of the present invention can provide a solid-state imaging device having a highly reliable connection between the pads and the circuitry. Also, the present invention can facilitate the connection between the pads and the circuitry.

[0064] The present invention is not limited to the configuration described in the specification, and the conductivity type and the circuit can be changed to the opposite conductivity type. Although the connection portion is described as being made of wiring in the wiring layer, it may be made of vias or microbumps, and may be any configuration that can ensure electrical continuity. The configurations of each embodiment can also be appropriately combined. [Explanation of symbols]

[0065] 301 Pixel section 302 Peripheral circuit section 308 First Component 309 Second member 149 1st wiring structure 150 2nd wiring structure 312 Pad section 313 Pad 101 First board 121 Second board 100 aperture X Connection Surface

Claims

1. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; a step of exposing the pad by removing a part of the first semiconductor substrate after the bonding step,

2. 2. The method for manufacturing a solid-state imaging device according to claim 1, wherein an opening is formed by removing a portion of the first semiconductor substrate in the exposure step, and a semiconductor element is formed in the second semiconductor substrate at a position overlapping the opening.

3. 2. The method for manufacturing a solid-state imaging device according to claim 1, characterized in that an opening is formed by removing a portion of the first semiconductor substrate in the exposure step, and a plurality of semiconductor regions and separation portions separating the plurality of semiconductor regions are formed in the second semiconductor substrate at positions overlapping with the opening.

4. 4. The method for manufacturing a solid-state imaging device according to claim 1, wherein an opening is formed by removing a portion of the first semiconductor substrate in the exposure step, and a protection diode is formed in the second semiconductor substrate at a position overlapping with the opening.

5. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; and exposing the pad by removing a portion of the second semiconductor substrate, 2. A method for manufacturing a solid-state imaging device, comprising the steps of: forming a plurality of vias connected to the pads before the exposing step.

6. 5. The method for manufacturing a solid-state imaging device according to claim 1, further comprising the step of forming a plurality of vias connected to the pads before the exposing step.

7. 7. The method for manufacturing a solid-state imaging device according to claim 1, wherein a step of forming a plurality of vias connected to the pads is performed before the bonding step.

8. 8. The method for manufacturing a solid-state imaging device according to claim 5, wherein the plurality of vias are connected to wiring included in the first wiring structure.

9. 8. The method for manufacturing a solid-state imaging device according to claim 5, wherein the plurality of vias are connected to wiring included in the second wiring structure.

10. 10. The method for manufacturing a solid-state imaging device according to claim 1, wherein the pad is formed in the same layer as a wiring layer included in the first wiring structure.

11. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; and exposing the pad by removing a portion of the second semiconductor substrate, A method for manufacturing a solid-state imaging device, wherein the pad is formed in the same layer as a wiring layer included in the first wiring structure.

12. The method for manufacturing a solid-state imaging device according to claim 11, wherein a plurality of vias are connected to the pad.

13. a first wiring included in a first wiring layer included in the first wiring structure is disposed at a position overlapping the pad; 13. The method for manufacturing a solid-state imaging device according to claim 12, wherein the pad and the first wiring are connected by the plurality of vias.

14. the first wiring structure has a second wiring included in a second wiring layer disposed between the first wiring layer and the second semiconductor substrate; 14. The method for manufacturing a solid-state imaging device according to claim 13, wherein a via that connects the first wiring and the second wiring is disposed at a position overlapping the pad.

15. 15. The method for manufacturing a solid-state imaging device according to claim 14, further comprising the step of forming the via that connects the first wiring and the second wiring before the exposing step.

16. 10. The method for manufacturing a solid-state imaging device according to claim 1, wherein the pad is formed in the same layer as a wiring layer included in the second wiring structure.

17. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; and exposing the pad by removing a portion of the second semiconductor substrate, The method for manufacturing a solid-state imaging device, wherein the pad is formed in the same layer as a wiring layer included in the second wiring structure.

18. 18. The method for manufacturing a solid-state imaging device according to claim 16, wherein the second wiring structure has wiring overlapping the pad.

19. 20. The method for manufacturing a solid-state imaging device according to claim 18, wherein a via that connects the wiring and the pad is disposed at a position overlapping the pad.

20. 20. The method for manufacturing a solid-state imaging device according to claim 18, wherein a plurality of vias connecting the wiring and the pads are arranged at positions overlapping the pads.

21. The method for manufacturing a solid-state imaging device described in claim 16 or 17, characterized in that the second wiring structure has a first wiring arranged in a first wiring layer and a second wiring arranged in a second wiring layer located between the first wiring layer and the second semiconductor substrate, and the first wiring and the second wiring are arranged at a position overlapping the pad.

22. 22. The method for manufacturing a solid-state imaging device according to claim 21, wherein a via connecting the pad and the first wiring and a via connecting the first wiring and the second wiring are arranged in positions overlapping the pad.

23. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; and exposing the pad by removing a portion of the first semiconductor substrate.

24. 24. The method for manufacturing a solid-state imaging device according to claim 23, wherein the pad is formed in the same layer as a wiring layer included in the first wiring structure.

25. 24. The method for manufacturing a solid-state imaging device according to claim 23, wherein the pad is formed in the same layer as a wiring layer included in the second wiring structure.

26. 26. The method for manufacturing a solid-state imaging device according to claim 23, further comprising the step of: providing a plurality of vias connected to the pads.

27. 25. The method for manufacturing a solid-state imaging device according to claim 23, further comprising the step of forming a plurality of vias connected to the pad, the plurality of vias being connected to wiring included in the first wiring structure.

28. 26. The method for manufacturing a solid-state imaging device according to claim 23, further comprising the step of forming a plurality of vias connected to the pad, the plurality of vias being connected to wiring included in the second wiring structure.

29. 29. The method for manufacturing a solid-state imaging device according to claim 26, further comprising a step of forming the plurality of vias before the exposing step.

30. 30. The method for manufacturing a solid-state imaging device according to claim 26, wherein the step of forming the plurality of vias is carried out before the bonding step.

31. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; and an exposing step of exposing the pad connected to an element disposed on the first semiconductor substrate by removing a portion of the second semiconductor substrate.

32. 32. The method for manufacturing a solid-state imaging device according to claim 31, wherein the pad is formed in the same layer as a wiring layer included in the second wiring structure.

33. 33. The method for manufacturing a solid-state imaging device according to claim 31, further comprising the step of: providing a plurality of vias connected to the pads.

34. 33. The method for manufacturing a solid-state imaging device according to claim 31, further comprising the step of forming a plurality of vias connected to the pad, the plurality of vias being connected to wiring included in the second wiring structure.

35. 35. The method for manufacturing a solid-state imaging device according to claim 33, further comprising a step of forming the plurality of vias before the exposing step.

36. 36. The method for manufacturing a solid-state imaging device according to claim 33, wherein the step of forming the plurality of vias is carried out before the bonding step.

37. 37. The method for manufacturing a solid-state imaging device according to claim 5, wherein the exposing step is performed after the bonding step.

38. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; a thinning step of thinning the first semiconductor substrate after the bonding step; a planarization layer forming step, which is performed after the thinning step, in which the planarization layer is formed so that the first semiconductor substrate is located between the planarization layer and the first wiring structure; a step of forming a microlens layer after the planarization layer forming step, the step of forming the microlens layer such that the planarization layer has a portion located between the microlens layer and the first semiconductor substrate; an exposure step of exposing the pad by removing a part of the planarization layer and a part of the first semiconductor substrate after the microlens formation step; 2. A method for manufacturing a solid-state imaging device comprising the steps of:

39. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; a thinning step of thinning the first semiconductor substrate after the bonding step; forming a microlens layer after the thinning step, the microlens layer being formed such that the first semiconductor substrate is located between the microlens layer and the first wiring structure; an exposing step of exposing the pad by removing a portion of the second semiconductor substrate after the forming step; 2. A method for manufacturing a solid-state imaging device comprising the steps of:

40. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; a thinning step of thinning the first semiconductor substrate after the bonding step; a planarization layer forming step, which is performed after the thinning step, in which the planarization layer is formed so that the first semiconductor substrate is located between the planarization layer and the first wiring structure; a step of forming a microlens layer after the planarization layer forming step, the step of forming the microlens layer such that the planarization layer has a portion located between the microlens layer and the first semiconductor substrate; an exposure step of exposing the pad connected to an element disposed on the second semiconductor substrate by removing a part of the planarization layer and a part of the first semiconductor substrate after the microlens formation step; 2. A method for manufacturing a solid-state imaging device comprising the steps of:

41. The method for manufacturing a solid-state imaging device according to any one of claims 1 to 4, 23 to 30 and 38, characterized in that the exposing step is a step of exposing the pad connected to an element arranged on the second semiconductor substrate.

42. a thinning step of thinning the first semiconductor substrate; 38. The method for manufacturing a solid-state imaging device according to claim 1, wherein the exposing step is performed after the thinning step.

43. forming a microlens layer such that the first semiconductor substrate is located between the microlens layer and the first wiring structure; 38. The method for manufacturing a solid-state imaging device according to claim 1, wherein the exposing step is performed after the forming step.

44. forming a microlens layer such that the first semiconductor substrate is located between the microlens layer and the first wiring structure; The forming step is performed after the thinning step, 43. The method for manufacturing a solid-state imaging device according to claim 42, wherein the exposing step is performed after the forming step.

45. A method for manufacturing a solid-state imaging device having a pad to be connected to an external terminal, comprising the steps of: a bonding process for bonding a first member having a first wiring structure including a first semiconductor substrate on which a photoelectric conversion element is disposed and a first metal portion and a first insulating film surrounding the first metal portion, and a second member having a second semiconductor substrate on which a transistor is disposed and a second wiring structure including a second metal portion and a second insulating film surrounding the second metal portion, by metal bonding between the first metal portion and the second metal portion, such that the first wiring structure and the second wiring structure are located between the first semiconductor substrate and the second semiconductor substrate; a thinning step of thinning the first semiconductor substrate after the bonding step; a planarization layer forming step, which is performed after the thinning step, in which the planarization layer is formed so that the first semiconductor substrate is located between the planarization layer and the first wiring structure; a step of forming a microlens layer after the planarization layer forming step, the step of forming the microlens layer such that the planarization layer has a portion located between the microlens layer and the first semiconductor substrate; an exposing step of exposing the pad by removing a part of the planarization layer and a part of the first semiconductor substrate after the microlens forming step; 2. A method for manufacturing a solid-state imaging device comprising the steps of:

46. 46. ​​The method for manufacturing a solid-state imaging device according to claim 45, wherein in the exposing step, the pads connected to elements arranged on the second semiconductor substrate are exposed.

47. 47. The method for manufacturing a solid-state imaging device according to claim 45, further comprising the step of: providing a plurality of vias connected to the pads.

48. 47. The method for manufacturing a solid-state imaging device according to claim 45, further comprising the step of forming a plurality of vias connected to the pad, the plurality of vias being connected to wiring included in the first wiring structure.

49. 47. The method for manufacturing a solid-state imaging device according to claim 45, further comprising the step of forming a plurality of vias connected to the pad, the plurality of vias being connected to wiring included in the second wiring structure.

50. 50. The method for manufacturing a solid-state imaging device according to claim 47, further comprising a step of forming the plurality of vias before the exposing step.

51. 51. The method for manufacturing a solid-state imaging device according to claim 47, wherein the step of forming the plurality of vias is carried out before the bonding step.

52. 52. The method for manufacturing a solid-state imaging device according to claim 45, wherein the exposing step includes a removing step of removing a portion of the first semiconductor substrate arranged at a position overlapping the pad.

53. After the removing step, an insulating film is formed on a portion of the first semiconductor substrate corresponding to the portion removed in the removing step; 53. The method for manufacturing a solid-state imaging device according to claim 52, wherein the exposing step is a step of exposing the pad by removing the part of the insulating film and the planarizing layer.

54. 47. The method for manufacturing a solid-state imaging device according to claim 40, 41 or 46, wherein the element is a protection diode.

55. 55. The method for manufacturing a solid-state imaging device according to claim 1, further comprising the step of thinning the second semiconductor substrate after the bonding step.

56. 56. The method for manufacturing a solid-state imaging device according to claim 1, wherein the bonding in the bonding step is performed by the metal bonding and bonding between the first insulating film and the second insulating film.

57. 57. The method for manufacturing a solid-state imaging device according to claim 1, wherein a main component of the pad is aluminum.

58. 58. The method for manufacturing a solid-state imaging device according to claim 1, wherein the main component of each of the first metal portion and the second metal portion is copper.

59. A method for manufacturing a solid-state imaging device described in any one of claims 1 to 58, characterized in that the distance between the pad and the second semiconductor substrate is smaller than the distance between the first semiconductor substrate and the second semiconductor substrate.

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