Method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device having favorable and stable electric characteristics and high reliability and a manufacturing method of the same, and a display device and a manufacturing method of the same.SOLUTION: In a method for generating a transistor, a semiconductor layer 108 is formed on an insulating layer 103 provided on a substrate 102, a gate insulating layer 110 is formed on the semiconductor layer, a metal oxide layer 114 is formed on the gate insulating layer, and a gate electrode 112 which overlaps with a part of the semiconductor layer is formed on the metal oxide layer. Then, a first element is supplied through the metal oxide layer and the gate insulating layer to a region of the semiconductor layer which does not overlap with the gate electrode. Examples of the first element include phosphorus, boron, magnesium, aluminum, silicon, and the like. When the metal oxide layer is processed, the processing is performed after the first element is supplied to the semiconductor layer.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have attracted attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing the field-effect mobility (sometimes simply referred to as mobility, or μFE).

[0004] Metal oxides that can be used for semiconductor layers can be formed by sputtering or the like, and therefore can be used for the semiconductor layers of transistors that constitute large display devices. Furthermore, since it is possible to use a part of the production equipment for transistors that use polycrystalline silicon or amorphous silicon by modifying it, capital investment can be reduced. Furthermore, transistors that use metal oxides have higher field-effect mobility than transistors that use amorphous silicon, and therefore high-performance display devices equipped with driver circuits can be realized.

[0005] Furthermore, Patent Document 2 discloses a thin film transistor using an oxide semiconductor film having low-resistance regions in source and drain regions, the low-resistance regions containing at least one element selected from the group consisting of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, and lead as a dopant. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-228622 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device with stable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.

[0008] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims. [Means for solving the problem]

[0009] One embodiment of the present invention is a method for manufacturing a semiconductor device, including forming a semiconductor layer, forming a gate insulating layer over the semiconductor layer, forming a metal oxide layer over the gate insulating layer, forming a gate electrode over the metal oxide layer so as to overlap with part of the semiconductor layer, and supplying a first element to a region of the semiconductor layer which is not overlapped with the gate electrode through the metal oxide layer and the gate insulating layer.

[0010] One embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming a semiconductor layer; forming a gate insulating layer over the semiconductor layer; forming a metal oxide layer over the gate insulating layer; forming a gate electrode over the metal oxide layer to overlap with part of the semiconductor layer; supplying a first element to a region of the semiconductor layer that is not overlapped with the gate electrode through the metal oxide layer and the gate insulating layer; and processing the metal oxide layer into an island shape after supplying the first element to the semiconductor layer.

[0011] One embodiment of the present invention is a method for manufacturing a semiconductor device, which includes forming a semiconductor layer, forming a gate insulating layer over the semiconductor layer, forming a metal oxide layer over the gate insulating layer, forming a gate electrode over the metal oxide layer to overlap with part of the semiconductor layer, supplying a first element to a region of the semiconductor layer that is not overlapped with the gate electrode through the metal oxide layer and the gate insulating layer, supplying a second element to a region of the metal oxide layer that is not overlapped with the gate electrode through the gate insulating layer, and processing the metal oxide layer into an island shape. After supplying the first element to the semiconductor layer, the second element may be supplied to the metal oxide layer, or the first element may be supplied to the semiconductor layer after supplying the second element to the metal oxide layer.

[0012] The first element may be, for example, phosphorus, boron, magnesium, aluminum, or silicon, and the second element may be, for example, silicon, phosphorus, argon, krypton, xenon, arsenic, gallium, or germanium.

[0013] The metal oxide layer is preferably processed into islands by wet etching.

[0014] The metal oxide layer preferably includes an aluminum oxide film, or the metal oxide layer and the semiconductor layer preferably include the same metal oxide.

[0015] After forming the metal oxide layer and before forming the gate electrode, it is preferable to perform a first heat treatment, supply the first element to the semiconductor layer, and then perform a second heat treatment at a temperature lower than that of the first heat treatment.

[0016] The semiconductor layer preferably comprises a metal oxide. [Effects of the Invention]

[0017] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with stable electrical characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief explanation of the drawings]

[0019] [Figure 1] 1A is a top view illustrating an example of a transistor, and FIGS. 1B and 1C are cross-sectional views illustrating an example of a transistor. [Figure 2] 2A and 2B are cross-sectional views illustrating an example of a transistor. [Figure 3] 3A is a top view illustrating an example of a transistor, and FIGS. 3B and 3C are cross-sectional views illustrating an example of a transistor. [Figure 4] 4(A) to 4(C) are cross-sectional views showing an example of a transistor. [Figure 5] 5A to 5E are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 6] 6A and 6B are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 7] 7A and 7B are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 8] 8A to 8C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 9]9A to 9C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 10] 10(A) to 10(C) are top views showing an example of a display device. [Figure 11] FIG. 11 is a cross-sectional view showing an example of a display device. [Figure 12] FIG. 12 is a cross-sectional view showing an example of a display device. [Figure 13] FIG. 13 is a cross-sectional view showing an example of a display device. [Figure 14] FIG. 14 is a cross-sectional view showing an example of a display device. [Figure 15] Fig. 15(A) is a block diagram showing an example of a display device, and Fig. 15(B) and Fig. 15(C) are circuit diagrams showing an example of a display device. [Figure 16] 16(A), 16(C), and 16(D) are circuit diagrams showing examples of a display device, and Fig. 16(B) is a timing chart of the display device. [Figure 17] 17(A) and 17(B) are diagrams showing an example of a display module. [Figure 18] 18(A) and 18(B) are diagrams showing an example of an electronic device. [Figure 19] 19(A) to 19(D) are diagrams showing examples of electronic devices. [Figure 20] 20(A) to 20(E) are diagrams showing examples of electronic devices. [Figure 21] 21(A) to 21(F) are diagrams showing examples of electronic devices. [Figure 22] FIG. 22 is a graph showing the etching rate of the metal oxide film according to Example 1. As shown in FIG. [Figure 23] 23(A) and 23(B) are photographs of a cross section of the sample according to Example 1. FIG. [Figure 24] FIG. 24 is a graph showing the electrical characteristics of the transistor according to Example 1. In FIG. [Figure 25] FIG. 25 is a graph showing the reliability evaluation results of the transistor according to Example 1. [Figure 26] 26(A) to 26(D) are graphs showing the electrical characteristics of the transistor according to Example 2. FIG. [Figure 27] FIG. 27 is a graph showing the reliability evaluation results of the transistor according to the second example. [Figure 28] FIG. 28 is a photograph of a cross section of the sample according to Example 2. [Figure 29] 29(A) and 29(B) are graphs showing the structural analysis results and film density of the sample according to Example 3. [Figure 30] FIG. 30 is a photograph of a cross section of the sample according to Example 3. [Figure 31] FIG. 31 is a photograph of a cross section of the sample according to Example 3. DETAILED DESCRIPTION OF THE INVENTION

[0020] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0021] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0022] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0023] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0024] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to the direction perpendicular to the channel length direction. Note that, depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0025] In this specification, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state) when the voltage V between the gate and the source of an n-channel transistor is low. gs is the threshold voltage V th (For p-channel transistors, V th This refers to a state of being (higher than)

[0026] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to Figures 1 to 9. In this embodiment, a transistor will be specifically described as a semiconductor device.

[0027] A semiconductor device according to one embodiment of the present invention includes forming a semiconductor layer, forming a gate insulating layer over the semiconductor layer, forming a metal oxide layer over the gate insulating layer, forming a gate electrode over the metal oxide layer so as to overlap with part of the semiconductor layer, and supplying (also referred to as adding or injecting) a first element to a region of the semiconductor layer that is not overlapped with the gate electrode through the metal oxide layer and the gate insulating layer.

[0028] In one embodiment of the present invention, a first element is supplied to a semiconductor layer by passing through a metal oxide layer and a gate insulating layer in this order. The layer into which the first element penetrates first is most susceptible to damage. Therefore, by providing a metal oxide layer on the gate insulating layer, the first element penetrates into the metal oxide layer first, which can reduce damage to the gate insulating layer and the semiconductor layer. This can improve the reliability of the transistor.

[0029] The semiconductor layer preferably contains a metal oxide, and the following mainly describes the case where the semiconductor layer contains a metal oxide.

[0030] After the metal oxide layer is formed, first heat treatment is preferably performed before the gate electrode is formed. In the first heat treatment, oxygen is preferably supplied from the gate insulating layer to the semiconductor layer.

[0031] The gate insulating layer preferably contains an oxide. The metal oxide layer preferably has low oxygen permeability. This can prevent oxygen contained in the gate insulating layer from being released toward the metal oxide layer and promote the supply of oxygen to the semiconductor layer. Therefore, oxygen vacancies in the semiconductor layer can be compensated for, and the reliability of the transistor can be improved.

[0032] Then, a gate electrode is formed, and the first element is supplied to the semiconductor layer using the gate electrode as a mask, thereby forming a pair of low-resistance regions in the semiconductor layer. That is, the semiconductor layer is formed to have a channel formation region overlapping with the gate electrode and a pair of low-resistance regions sandwiching the channel formation region.

[0033] The first element is, for example, phosphorus, boron, magnesium, aluminum, or silicon.

[0034] The metal oxide layer is preferably impermeable to hydrogen and water. This can prevent hydrogen and water contained in the gate electrode from being released toward the metal oxide layer and from diffusing into the semiconductor layer. Therefore, an increase in carrier density in the channel formation region of the semiconductor layer can be prevented. When the channel formation region of the semiconductor layer has few oxygen vacancies and a low carrier density, the off-state current of the transistor can be significantly reduced and the reliability of the transistor can be improved.

[0035] When processing the metal oxide layer into an island shape using the gate electrode as a mask, it is preferable to process the metal oxide layer after supplying the first element to the semiconductor layer. As described above, supplying the first element to the semiconductor layer through the metal oxide layer can reduce damage to the semiconductor layer and the gate insulating layer. Furthermore, when supplying the first element to the semiconductor layer, the first element can also be supplied to the metal oxide layer. This can increase the etching rate of the metal oxide layer. Therefore, it is possible to differentiate the etching rate of the metal oxide layer between the portion overlapping with the gate electrode and the portion not overlapping with the gate electrode. As a result, it is possible to suppress shape defects of the metal oxide layer due to etching.

[0036] Furthermore, depending on the material and formation conditions, the metal oxide layer may be difficult to process. In such cases, it is preferable to supply a second element to the metal oxide layer and then process it. Supplying the second element reduces the crystallinity of the metal oxide layer, making it easier to process the metal oxide layer.

[0037] The second element is, for example, silicon, phosphorus, argon, krypton, xenon, arsenic, gallium, or germanium.

[0038] There is no limitation on the order of the first element supply step and the second element supply step. Furthermore, if two purposes (reducing the resistance of the semiconductor layer and reducing the crystallinity of the metal oxide layer) can be achieved by supplying the same element, the element supply step may be performed only once.

[0039] For example, an aluminum oxide film can be used as the metal oxide layer. For example, by adding argon to an aluminum oxide film, the aluminum oxide film becomes easier to etch.

[0040] Alternatively, the metal oxide layer and the semiconductor layer preferably contain the same metal oxide.

[0041] The metal oxide layer is preferably processed by wet etching. By using wet etching, the gate insulating layer can be prevented from being etched simultaneously with the metal oxide layer. This prevents the thickness of the gate insulating layer from being reduced, and the thickness of the gate insulating layer can be made uniform.

[0042] After the first element is supplied to the semiconductor layer, a second heat treatment may be performed. The first heat treatment is preferably performed at a relatively high temperature (e.g., 350°C) to sufficiently supply oxygen from the gate insulating layer to the semiconductor layer. On the other hand, if the second heat treatment, which is performed after the formation of the gate electrode and the supply of the first element to the semiconductor layer, is performed at a high temperature, oxygen contained in the channel formation region of the semiconductor layer or the gate insulating layer may diffuse to the low-resistance region or the gate electrode. Therefore, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment.

[0043] In one embodiment of the present invention, the first element can also be supplied to the gate insulating layer. Specifically, by using a gate electrode as a mask, the first element is supplied mainly to a portion of the gate insulating layer that overlaps with a low-resistance region of the semiconductor layer, and the first element is less likely to be supplied to a portion of the gate insulating layer that overlaps with a channel formation region of the semiconductor layer. Therefore, in the second heat treatment, oxygen is supplied from the gate insulating layer to the channel formation region, and oxygen vacancies in the channel formation region are filled. On the other hand, oxygen is less likely to be supplied from the gate insulating layer to the low-resistance region, so that the electrical resistance is less likely to increase. As a result, oxygen vacancies are sufficiently reduced, and a semiconductor layer having both a channel formation region with an extremely low carrier density and source and drain regions with extremely low electrical resistance can be formed, thereby realizing a semiconductor device with excellent electrical characteristics and high reliability.

[0044] [Configuration example 1] FIG. 1A shows a top view of a transistor 100. FIG. 1B shows a cross-sectional view taken along dashed line A1-A2 in FIG. 1A. FIG. 1C shows a cross-sectional view taken along dashed line B1-B2 in FIG. 1A. The dashed line A1-A2 direction corresponds to the channel length direction, and the dashed line B1-B2 direction corresponds to the channel width direction. Note that FIG. 1A omits some of the components of the transistor 100 (such as a gate insulating layer). As with FIG. 1A, some of the components are also omitted in the top views of the transistors shown in the following drawings.

[0045] The transistor 100 includes an insulating layer 103 , an island-shaped semiconductor layer 108 , a gate insulating layer 110 , a metal oxide layer 114 , a gate electrode 112 , and an insulating layer 118 .

[0046] The insulating layer 103 is provided on the substrate 102. The semiconductor layer 108 is provided on the insulating layer 103. The gate insulating layer 110 is in contact with the top surface of the insulating layer 103 and the top surface and side surfaces of the semiconductor layer 108. The metal oxide layer 114 is provided on the gate insulating layer 110. The metal oxide layer 114 has a portion that overlaps with the semiconductor layer 108 with the gate insulating layer 110 interposed therebetween. The gate electrode 112 is provided on the metal oxide layer 114. The gate electrode 112 has a portion that overlaps with the semiconductor layer 108 with the gate insulating layer 110 and the metal oxide layer 114 interposed therebetween. The insulating layer 118 is provided to cover the top surface of the gate insulating layer 110, the side surfaces of the metal oxide layer 114, and the top surface of the gate electrode 112.

[0047] The transistor 100 is a top-gate transistor having a gate electrode 112 on a semiconductor layer 108 .

[0048] 1A and 1B, the transistor 100 may include a conductive layer 120a and a conductive layer 120b over an insulating layer 118. One of the conductive layer 120a and the conductive layer 120b functions as a source electrode, and the other functions as a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to a low-resistance region 108n (described later) through an opening 141a or an opening 141b provided in the insulating layer 118 and the gate insulating layer 110, respectively.

[0049] The semiconductor layer 108 preferably includes a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.

[0050] The semiconductor layer 108 has a region overlapping with the gate electrode 112 and a pair of low-resistance regions 108n that sandwich the region. The region of the semiconductor layer 108 that overlaps with the gate electrode 112 functions as a channel formation region where a channel of the transistor 100 can be formed. The pair of low-resistance regions 108n function as a source region and a drain region of the transistor 100.

[0051] The low-resistance region 108n can also be referred to as a region with lower resistance than the channel formation region, a region with a high carrier concentration, a region with a high oxygen defect density, a region with a high impurity concentration, or an n-type region.

[0052] The low-resistance regions 108n are regions containing one or more impurity elements. Examples of the impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and rare gases (helium, neon, argon, krypton, xenon, etc.). The pair of low-resistance regions 108n preferably contain boron, phosphorus, aluminum, magnesium, or silicon, and more preferably contain boron or phosphorus.

[0053] Note that, due to the influence of heat during the manufacturing process, some of the impurity elements contained in the low-resistance region 108n may diffuse into the channel formation region. The concentration of the impurity elements in the channel formation region is preferably 1 / 10 or less, more preferably 1 / 100 or less, of the concentration of the impurity elements in the low-resistance region 108n.

[0054] The gate insulating layer 110 has a region that is in contact with the channel formation region of the semiconductor layer 108 and overlaps with the gate electrode 112. The gate insulating layer 110 has a region that is in contact with the pair of low-resistance regions 108n of the semiconductor layer 108 and does not overlap with the gate electrode 112.

[0055] When the semiconductor layer 108 contains a metal oxide, the gate insulating layer 110 preferably contains an oxide. In particular, the gate insulating layer 110 is preferably an oxide film that can release oxygen by heating.

[0056] By performing heat treatment in a state where the gate insulating layer 110 containing oxide is provided in contact with the top surface of the semiconductor layer 108, oxygen released from the gate insulating layer 110 can be supplied to the semiconductor layer 108. As a result, oxygen vacancies in the semiconductor layer 108 can be filled, and a highly reliable transistor can be realized.

[0057] In one embodiment of the present invention, heat treatment is performed before the gate electrode 112 is formed and the impurity element is supplied to the semiconductor layer 108, and oxygen is supplied from the gate insulating layer 110 to the semiconductor layer 108. On the other hand, depending on the structure of a transistor or a semiconductor device or display device including the transistor, heat treatment may be performed after the gate electrode 112 is formed and the impurity element is supplied to the semiconductor layer 108. At this time, oxygen contained in a channel formation region of the semiconductor layer 108 may diffuse to the low-resistance region 108n or the gate electrode 112. Furthermore, oxygen may be supplied from the gate insulating layer 110 to the low-resistance region 108n. When oxygen is supplied to the low-resistance region 108n, the carrier density may decrease and the electrical resistance may increase.

[0058] Therefore, it is preferable that the above impurity element be contained in a region of the gate insulating layer 110 that is in contact with the pair of low-resistance regions 108n, i.e., a region that does not overlap with the gate electrode 112. The region of the gate insulating layer 110 that does not overlap with the gate electrode 112 preferably has an impurity concentration higher than that of a region of the gate insulating layer 110 that overlaps with the gate electrode 112 and lower than that of the low-resistance region 108n. By supplying the above impurity element to an oxide film that can release oxygen by heating, the amount of released oxygen can be reduced. Therefore, when the above impurity element is contained in a region of the gate insulating layer 110 that is in contact with the low-resistance region 108n, oxygen is less likely to be supplied from the gate insulating layer 110 to the low-resistance region 108n, and the low-resistance region 108n can maintain a low electrical resistance.

[0059] By adopting such a structure, oxygen vacancies are sufficiently reduced, and a semiconductor device having both a channel formation region with extremely low carrier density and source and drain regions with extremely low electrical resistance, and thus having excellent electrical characteristics and high reliability can be realized.

[0060] The insulating layer 103 and the gate insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contain an oxide. For the insulating layer 103 and the gate insulating layer 110, for example, an oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film can be used. In this way, oxygen desorbed from the insulating layer 103 or the gate insulating layer 110 during heat treatment or the like in the manufacturing process of the transistor 100 can be supplied to the channel formation region of the semiconductor layer 108, thereby reducing oxygen vacancies in the semiconductor layer 108.

[0061] FIG. 2(A) shows an enlarged cross-sectional view of a region P surrounded by a dashed line in FIG. 1(B).

[0062] The gate insulating layer 110 includes a region 110d containing the above-described impurity element. The region 110d is located at least at the interface with the low-resistance region 108n or in the vicinity thereof. The region 110d is also located at least at the interface with the insulating layer 103 or in the vicinity thereof in a region where the semiconductor layer 108 and the gate electrode 112 are not provided. As shown in FIGS. 1B, 1C, and 2A, the region 110d is preferably not provided in a portion in contact with a channel formation region of the semiconductor layer 108.

[0063] The insulating layer 103 has a region 103d containing the above-described impurity element at or near the interface in contact with the gate insulating layer 110. Furthermore, as shown in FIG. 2A, the region 103d may also be provided at or near the interface in contact with the low-resistance region 108n. In this case, the impurity concentration in the portion overlapping with the low-resistance region 108n is lower than that in the portion in contact with the gate insulating layer 110.

[0064] Here, the impurity concentration in the low-resistance region 108n preferably has a concentration gradient such that the concentration increases toward the gate insulating layer 110. This results in a lower resistance toward the upper part of the low-resistance region 108n, thereby more effectively reducing the contact resistance with the conductive layer 120a (or the conductive layer 120b). Furthermore, since the total amount of impurity elements in the low-resistance region 108n can be reduced compared to when the concentration is uniform throughout the low-resistance region 108n, the amount of impurities that can diffuse into the channel formation region due to the influence of heat during the manufacturing process can be kept low.

[0065] Furthermore, it is preferable that the impurity concentration in the region 110d has a concentration gradient such that the concentration increases toward the low-resistance region 108n. In the gate insulating layer 110 using an oxide film capable of releasing oxygen by heating, the region 110d containing the above-described impurity elements can release less oxygen than other regions. Therefore, the region 110d located at or near the interface with the low-resistance region 108n of the gate insulating layer 110 functions as an oxygen blocking layer and can effectively reduce the amount of oxygen supplied to the low-resistance region 108n.

[0066] The impurity element is supplied to at least the semiconductor layer 108 using the gate electrode 112 as a mask. Furthermore, it is preferable to supply the impurity element also to the gate insulating layer 110. This allows the region 110d to be formed in a self-aligned manner at the same time as the formation of the low-resistance region 108n.

[0067] In FIG. 2(A) and other figures, the region 110d is illustrated with a hatched pattern only near the semiconductor layer 108 in the gate insulating layer 110 in order to exaggerate the fact that the portion of the gate insulating layer 110 with a high impurity concentration is located at or near the interface with the semiconductor layer 108. However, in reality, the gate insulating layer 110 contains the above-mentioned impurity elements throughout its entire thickness.

[0068] The impurity element is preferably supplied by plasma ion doping or ion implantation, which makes it easy to adjust the depth to which ions are added, and thus makes it easy to add ions to a region including the gate insulating layer 110 and the semiconductor layer 108.

[0069] The supply conditions of the impurity element are preferably set so that the impurity concentration is highest in the region of the semiconductor layer 108 on the gate insulating layer 110 side or in or near the interface between the semiconductor layer 108 and the gate insulating layer 110. This allows the impurity element to be supplied to both the semiconductor layer 108 and the gate insulating layer 110 at an appropriate concentration in a single process. Furthermore, supplying the impurity element at a high concentration to the upper part of the low-resistance region 108n to reduce the resistance can reduce the contact resistance between the low-resistance region 108n and the source electrode or drain electrode. Furthermore, forming a region with a high concentration of the impurity element near the low-resistance region 108n of the gate insulating layer 110 reduces the diffusivity of oxygen in this region, thereby further suppressing the diffusion of oxygen in the gate insulating layer 110 toward the low-resistance region 108n.

[0070] The low resistance region 108n and the region 110d each have an impurity concentration of 1×10 19 atoms / cm 3 More than 1×10 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 5x10 or more 22 atoms / cm 3 Less than 1×10, more preferably 20 atoms / cm 3 More than 1×10 22 atoms / cm 3 It is preferable that the low-resistance region 108n includes a region where the impurity concentration is higher than that of the region 110d of the gate insulating layer 110, since this can further reduce the electrical resistance of the low-resistance region 108n.

[0071] The impurity concentrations in the low-resistivity region 108n and the region 110d can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side with XPS analysis.

[0072] When an element that easily bonds with oxygen is used as the impurity element, the impurity element exists in a state of being bonded to oxygen in the semiconductor layer 108. That is, the impurity element removes oxygen from the semiconductor layer 108, causing oxygen vacancies in the semiconductor layer 108, and the oxygen vacancies bond with hydrogen in the film to generate carriers. Furthermore, since the impurity element in the semiconductor layer 108 exists stably in an oxidized state, it is difficult for it to be desorbed by heat or the like applied during the process, and a stable low-resistance region 108n with low electrical resistance can be realized.

[0073] When an element that easily bonds with oxygen is used as the impurity element, the impurity element exists in a state of being bonded to oxygen in the gate insulating layer 110 as in the semiconductor layer 108. When oxygen and the impurity element are bonded and stabilized, oxygen is hardly released from the region containing the impurity element even when heated, and the oxygen is less likely to diffuse to other layers. This allows oxygen to be supplied to the channel formation region while suppressing the supply of oxygen from the gate insulating layer 110 to the low-resistance region 108n. Therefore, oxygen vacancies in the channel formation region can be reduced while preventing the resistance of the low-resistance region 108n from increasing. As a result, a transistor with excellent electrical characteristics and high reliability can be realized.

[0074] The impurity element is preferably an element that bonds with oxygen in the semiconductor layer 108 and the gate insulating layer 110 to stabilize them. For example, it is preferable to use an element whose oxide can exist as a solid under standard conditions. Particularly preferred elements include rare gases, typical nonmetallic elements other than hydrogen, typical metal elements, and transition metal elements, with boron, phosphorus, aluminum, magnesium, and silicon being particularly preferred.

[0075] For example, when boron is used as an impurity element, the boron contained in the low-resistivity region 108n and the region 110d may exist in a state bonded with oxygen. This can be confirmed by observing a spectral peak due to the B2O3 bond in XPS analysis. Furthermore, in XPS analysis, the spectral peak due to the existence of elemental boron is not observed or the peak intensity is so small that it is buried in the background noise at the lower limit of measurement.

[0076] The metal oxide layer 114 is formed using a material that is less permeable to oxygen and hydrogen. The metal oxide layer 114 has a function of suppressing diffusion of oxygen contained in the gate insulating layer 110 toward the gate electrode 112. The metal oxide layer 114 has a function of suppressing diffusion of hydrogen and water contained in the gate electrode 112 toward the gate insulating layer 110. For the metal oxide layer 114, a material that is at least less permeable to oxygen and hydrogen than the gate insulating layer 110 is preferably used.

[0077] By providing the metal oxide layer 114, even when the gate electrode 112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper, it is possible to prevent oxygen from diffusing from the gate insulating layer 110 to the gate electrode 112. Furthermore, even when the gate electrode 112 contains hydrogen, it is possible to prevent hydrogen from diffusing from the gate electrode 112 to the semiconductor layer 108 through the gate insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0078] The metal oxide layer 114 may be either an insulating layer or a conductive layer. If the metal oxide layer 114 is an insulating layer, the metal oxide layer 114 may be part of the gate insulating layer 110. If the metal oxide layer 114 is a conductive layer, the metal oxide layer 114 may be part of the gate electrode 112.

[0079] An insulating material having a higher dielectric constant than silicon oxide is preferably used for the metal oxide layer 114. In particular, an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like is preferably used because the driving voltage can be reduced.

[0080] For example, a conductive oxide such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the metal oxide layer 114. In particular, conductive oxides containing indium are preferred because of their high conductivity.

[0081] It is preferable to use an oxide material containing one or more elements that are the same as those of the semiconductor layer 108 for the metal oxide layer 114. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that for the semiconductor layer 108 for the metal oxide layer 114, because this enables the use of common equipment.

[0082] Alternatively, when a metal oxide material containing indium and gallium is used for both the semiconductor layer 108 and the metal oxide layer 114, it is preferable to use a material with a higher gallium content (content ratio) than the semiconductor layer 108, because this can further improve the blocking property against oxygen. In this case, by using a material with a higher indium content than the metal oxide layer 114 for the semiconductor layer 108, the field-effect mobility of the transistor 100 can be increased.

[0083] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably supplied to the gate insulating layer 110 and the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0084] When the metal oxide layer 114 is a conductive layer, the manufacturing process of the transistor 100 includes a step of forming the metal oxide layer 114 in an island shape. Even when the metal oxide layer 114 is an insulating layer, the metal oxide layer 114 can be formed in an island shape. In this case, processing may be difficult depending on the material and processing method.

[0085] 2B shows an example in which a part (lower part) of the metal oxide layer 114 overlapping with the gate electrode 112 is etched. When the metal oxide layer 114 has such a defective shape, the coverage of the insulating layer 118 is reduced.

[0086] In one embodiment of the present invention, the impurity element is supplied to the semiconductor layer 108 through the metal oxide layer 114. As a result, the impurity element is also supplied to the metal oxide layer 114, and the etching rate of the metal oxide layer 114 can be increased. Therefore, the etching rate of the metal oxide layer 114 can be made different between a portion overlapping with the gate electrode 112 and a portion not overlapping with the gate electrode 112. As a result, the portion of the metal oxide layer 114 overlapping with the gate electrode 112 is less likely to be etched, and defects in the shape of the metal oxide layer 114 can be suppressed. Furthermore, the coverage of the insulating layer 118 can be improved, and poor coverage can be suppressed.

[0087] The gate electrode 112 and the metal oxide layer 114 are processed so that their top surfaces roughly match each other. The island-shaped metal oxide layer 114 can be formed by processing using the gate electrode 112 as a mask.

[0088] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where a lower layer is processed using an upper layer as a mask, or where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" also applies.

[0089] The insulating layer 118 functions as a protective layer that protects the transistor 100. The insulating layer 118 preferably has a function of preventing oxygen that may be released from the gate insulating layer 110 from diffusing to the outside. For example, an inorganic insulating material such as an oxide or a nitride can be used. More specifically, an inorganic insulating material such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, or hafnium aluminate can be used.

[0090] [Configuration example 2] 3A shows a top view of a transistor 100A. 3B shows a cross-sectional view taken along dashed line A1-A2 in FIG. 3A. 3C shows a cross-sectional view taken along dashed line B1-B2 in FIG. 3A. The dashed line A1-A2 direction corresponds to the channel length direction, and the dashed line B1-B2 direction corresponds to the channel width direction.

[0091] The transistor 100A differs from the transistor 100 in that a conductive layer 106 is provided between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region overlapping with the semiconductor layer 108 and the gate electrode 112.

[0092] In the transistor 100A, the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the gate electrode 112 functions as a second gate electrode (also referred to as a top gate electrode). Part of the insulating layer 103 functions as a first gate insulating layer, and part of the gate insulating layer 110 functions as a second gate insulating layer.

[0093] A portion of the semiconductor layer 108 that overlaps with at least one of the gate electrode 112 and the conductive layer 106 functions as a channel formation region. Note that for ease of explanation, the portion of the semiconductor layer 108 that overlaps with the gate electrode 112 may be referred to as a channel formation region hereinafter. However, in reality, a channel can also be formed in a portion that does not overlap with the gate electrode 112 but overlaps with the conductive layer 106 (a portion including the low-resistance region 108n).

[0094] 3C, the conductive layer 106 may be electrically connected to the gate electrode 112 through an opening 142 provided in the metal oxide layer 114, the gate insulating layer 110, and the insulating layer 103. This allows the conductive layer 106 and the gate electrode 112 to have the same potential.

[0095] The conductive layer 106 can be formed using a material similar to that of the gate electrode 112, the conductive layer 120a, or the conductive layer 120b. In particular, it is preferable to use a material containing copper for the conductive layer 106 because wiring resistance can be reduced.

[0096] 3(A) and 3(C), it is preferable that the gate electrode 112 and the conductive layer 106 protrude outward in the channel width direction beyond the end portion of the semiconductor layer 108. In this case, as shown in FIG. 3(C), the entire semiconductor layer 108 in the channel width direction is covered with the gate electrode 112 and the conductive layer 106 via the gate insulating layer 110 and the insulating layer 103.

[0097] With this structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. In this case, it is particularly preferable to apply the same potential to the conductive layer 106 and the gate electrode 112. This allows an electric field for inducing a channel in the semiconductor layer 108 to be effectively applied, thereby increasing the on-state current of the transistor 100A. This also enables miniaturization of the transistor 100A.

[0098] Note that the gate electrode 112 and the conductive layer 106 may not be connected to each other. In this case, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100A may be applied to the other. In this case, the threshold voltage when the transistor 100A is driven by the other electrode can also be controlled by the potential applied to one electrode.

[0099] [Application example] Next, as an application example, a semiconductor device according to one embodiment of the present invention including a transistor and a capacitor will be described with reference to Figure 4. Specifically, an example in which the semiconductor layer 108c including an impurity is used as one electrode of the capacitor and the transistor and the capacitor are formed on the same surface will be described.

[0100] The capacitor 130A shown in FIG. 4A is provided next to the transistor 100 (FIGS. 1A to 1C).

[0101] The capacitor 130A shown in FIG. 4B is provided next to the transistor 100A (FIGS. 3A to 3C).

[0102] The capacitor 130A has a structure in which a gate insulating layer 110 and an insulating layer 118 functioning as dielectrics are provided between a semiconductor layer 108c and a conductive layer 120b.

[0103] The semiconductor layer 108c is provided on the same plane as the semiconductor layer 108. For example, the semiconductor layer 108c can be formed by processing the same metal oxide film as the semiconductor layer 108 and then supplying the same impurity element as that of the low-resistance region 108n.

[0104] With this structure, the capacitor 130A can be manufactured simultaneously with the transistor without increasing the manufacturing process.

[0105] The capacitor 130B shown in FIG. 4C is provided next to the transistor 100A (FIGS. 3A to 3C).

[0106] The capacitor 130B has a structure in which an insulating layer 103 functioning as a dielectric is provided between a conductive layer 106c and a semiconductor layer 108c.

[0107] The conductive layer 106c is provided on the same surface as the conductive layer 106. The conductive layer 106c can be formed by processing the same conductive film as the conductive layer 106.

[0108] The capacitance element 130B can have a thinner dielectric than the capacitance element 130A, and therefore can be a capacitance element with a larger capacitance.

[0109] [Components of semiconductor device] Next, the components included in the semiconductor device of this embodiment will be described in detail, although the description of the components that have already been described may be omitted.

[0110] Although there are no significant limitations on the material of the substrate 102, it is necessary that the substrate 102 has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102.

[0111] Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 and the like. The peeling layer can be used to separate a semiconductor device, after part or all of the semiconductor device is completed thereon, from the substrate 102 and transfer the semiconductor device to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0112] The insulating layer 103 can be formed, for example, using a single layer or a stack of an oxide insulating film or a nitride insulating film. Note that in order to improve the interface characteristics with the semiconductor layer 108, at least a region of the insulating layer 103 that is in contact with the semiconductor layer 108 is preferably formed using an oxide insulating film. Furthermore, the insulating layer 103 is preferably formed using a film that releases oxygen when heated.

[0113] The insulating layer 103 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like, and can be formed as a single layer or a stacked layer.

[0114] When a film other than an oxide film, such as a silicon nitride film, is used on the side of the insulating layer 103 that is in contact with the semiconductor layer 108, it is preferable to perform pretreatment such as oxygen plasma treatment on the surface that is in contact with the semiconductor layer 108, and oxidize the surface or the vicinity of the surface.

[0115] The gate electrode 112, the conductive layer 106 functioning as a gate electrode, and the conductive layers 120a and 120b functioning as a source electrode and a drain electrode can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements.

[0116] Furthermore, the gate electrode 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b may be formed of an oxide conductor (OC) or a metal oxide film such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, or In-Ga-Zn oxide.

[0117] When oxygen vacancies are formed in a metal oxide having semiconducting properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. The metal oxide that has become an electric conductor can be called an oxide conductor (OC).

[0118] The gate electrode 112 and the conductive layer 106 may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. Note that a conductive film containing an oxide conductor is preferably used on the side of the gate electrode 112 in contact with the gate insulating layer 110 or on the side of the conductive layer 106 in contact with the insulating layer 103.

[0119] The gate electrode 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b each preferably contain one or more of the above-mentioned metal elements, particularly titanium, tungsten, tantalum, and molybdenum. In particular, a tantalum nitride film is preferably used. A tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself. Therefore, the tantalum nitride film is suitable as a conductive film in contact with the semiconductor layer 108 or in the vicinity of the semiconductor layer 108.

[0120] The gate insulating layer 110 can be an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that the gate insulating layer 110 is not limited to a single layer and may have a stacked structure of two or more layers.

[0121] At least a region of the gate insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film, and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the gate insulating layer 110 is an insulating film that can release oxygen. For example, oxygen can be supplied to the gate insulating layer 110 by forming the gate insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the formed gate insulating layer 110 in an oxygen atmosphere, or forming an oxide film on the gate insulating layer 110 in an oxygen atmosphere.

[0122] Furthermore, a material such as hafnium oxide, which has a higher dielectric constant than silicon oxide or silicon oxynitride, can also be used for the gate insulating layer 110. This allows the thickness of the gate insulating layer 110 to be increased, thereby suppressing leakage current due to tunneling current. In particular, crystalline hafnium oxide is preferable because it has a higher dielectric constant than amorphous hafnium oxide.

[0123] The semiconductor layer 108 preferably includes an oxide semiconductor. Alternatively, the semiconductor layer 108 may include silicon. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single-crystal silicon).

[0124] The semiconductor layer 108 preferably contains, for example, indium, M (wherein M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0125] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) for the semiconductor layer 108.

[0126] When the semiconductor layer 108 is an In-M-Zn oxide, the sputtering target used to deposit the In-M-Zn oxide preferably has an atomic ratio of In equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such sputtering targets include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5.

[0127] It is preferable to use a target containing a polycrystalline oxide as the sputtering target, since this facilitates the formation of a crystalline semiconductor layer 108. The atomic ratio of the semiconductor layer 108 to be formed varies within a range of ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0128] When describing an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when the atomic ratio of In is 4, the atomic ratio of Ga is 1 or more and 3 or less, and the atomic ratio of Zn is 2 or more and 4 or less. When describing an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when the atomic ratio of In is 5, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is 5 or more and 7 or less. When describing an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when the atomic ratio of In is 1, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is more than 0.1 and 2 or less.

[0129] Here, oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

[0130] Oxygen vacancies formed in the semiconductor layer 108 are problematic because they affect transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen bonds to the oxygen vacancies and they can become carrier sources. When a carrier source is generated in the semiconductor layer 108, the electrical characteristics of the transistor 100 change, typically causing a shift in the threshold voltage. Therefore, it is preferable that the semiconductor layer 108 have as few oxygen vacancies as possible.

[0131] Therefore, in one embodiment of the present invention, an insulating film near the semiconductor layer 108, specifically, the gate insulating layer 110 located above the semiconductor layer 108 and the insulating layer 103 located below the semiconductor layer 108, includes an oxide film. By transferring oxygen from the insulating layer 103 and the gate insulating layer 110 to the semiconductor layer 108 by heat or the like during a manufacturing process, oxygen vacancies in the semiconductor layer 108 can be reduced.

[0132] Metal oxides applicable to the semiconductor layer will be described below.

[0133] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides. For example, nitrogen-containing metal oxides such as zinc oxynitride (ZnON) may be used for the semiconductor layer.

[0134] In this specification, etc., they may be referred to as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

[0135] For example, a CAC (Cloud-Aligned Composite)-OS can be used for the semiconductor layer.

[0136] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and functions as a semiconductor as a whole. When CAC-OS or CAC-metal oxide is used in the light-emitting layer of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0137] Furthermore, CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0138] In addition, in CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0139] Furthermore, the CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to an insulating region and a component with a narrow gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0140] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0141] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors, such as c-axis aligned crystalline oxide semiconductors (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0142] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0143] Nanocrystals are basically hexagonal, but not necessarily regular hexagonal, and may have non-regular hexagonal shapes. The strain may also result in pentagonal, heptagonal, or other lattice arrangements. It is difficult to identify clear grain boundaries in CAAC-OS even near the strain. This indicates that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is because CAAC-OS can tolerate strain due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by the substitution of metal elements.

[0144] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, the layer can also be referred to as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, the layer can also be referred to as an (In,M) layer.

[0145] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, since the crystallinity of metal oxides can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS is unlikely to have impurities or defects (oxygen vacancies (V O It can also be said that these metal oxides have low oxygen vacancies. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0146] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0147] Indium-gallium-zinc oxide (IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, because IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable when made into small crystals (such as the above-mentioned nanocrystals) than large crystals (here, crystals of a few millimeters or a few centimeters).

[0148] The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0149] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0150] A metal oxide film functioning as a semiconductor layer can be formed using either or both of an inert gas and an oxygen gas. The oxygen flow rate (oxygen partial pressure) during the formation of the metal oxide film is not particularly limited. However, in order to obtain a transistor with high field-effect mobility, the oxygen flow rate (oxygen partial pressure) during the formation of the metal oxide film is preferably 0% to 30%, more preferably 5% to 30%, and even more preferably 7% to 15%.

[0151] The metal oxide preferably has an energy gap of 2 eV or more, more preferably 2.5 eV or more, and further preferably 3 eV or more. By using a metal oxide with such a wide energy gap, the off-state current of a transistor can be reduced.

[0152] [Production method example 1] Next, a manufacturing method of a transistor of one embodiment of the present invention will be described with reference to Figures 5 to 9. Figures 5 to 9 show cross sections of a transistor in the channel length direction and the channel width direction at each stage of a manufacturing process.

[0153] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0154] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0155] Furthermore, when processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0156] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0157] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet light (EUV) or X-rays can also be used as the light used for exposure. Instead of light used for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0158] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0159] In Manufacturing Method Example 1, a manufacturing method of the transistor 100A shown in Structural Example 2 will be described with reference to FIGS.

[0160] First, as shown in FIG. 5A, a conductive film is formed over a substrate 102 and processed by etching to form a conductive layer 106 that functions as a gate electrode.

[0161] Next, an insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 5(A)).

[0162] After the insulating layer 103 is formed, treatment for supplying oxygen to the insulating layer 103 may be performed. Examples of the treatment for supplying oxygen include plasma treatment in an oxygen atmosphere, heat treatment in an oxygen atmosphere, treatment using a plasma ion doping method, and treatment using an ion implantation method.

[0163] Next, a metal oxide film is formed on the insulating layer 103 and processed to form an island-shaped semiconductor layer 108 (FIG. 5(B)).

[0164] The metal oxide film is preferably formed by a sputtering method using a metal oxide target.

[0165] It is preferable to use oxygen gas when forming a metal oxide film. When forming a metal oxide film, an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) may be mixed with oxygen gas. The higher the ratio of oxygen gas to the total deposition gas when forming a metal oxide film (hereinafter, also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, resulting in a transistor with a higher on-state current.

[0166] The deposition conditions for the metal oxide film are a substrate temperature of room temperature or higher and 200° C. or lower, preferably room temperature or higher and 140° C. or lower. For example, a substrate temperature of room temperature or higher but lower than 140° C. is preferred because it increases productivity. Furthermore, by depositing a metal oxide film at room temperature or without intentionally heating the substrate, the crystallinity can be reduced.

[0167] Furthermore, before forming the metal oxide film, it is preferable to perform treatment for desorbing water, hydrogen, organic components, and the like adsorbed on the surface of the insulating layer 103, and treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an oxygen-containing atmosphere. Furthermore, if plasma treatment is performed in an atmosphere containing nitric oxide gas, organic substances on the surface of the insulating layer 103 can be suitably removed. After such treatment, it is preferable to form a metal oxide film successively without exposing the surface of the insulating layer 103 to the air.

[0168] The metal oxide film may be processed by wet etching or dry etching, or both. At this time, a part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be etched and become thinner.

[0169] After the metal oxide film is formed or processed into the semiconductor layer 108, heat treatment may be performed to remove hydrogen or water from the metal oxide film or the semiconductor layer 108. The temperature of the heat treatment can be typically set to 150° C. or higher and lower than the strain point of the substrate, 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower.

[0170] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, after heating in the atmosphere, heating can be performed in an atmosphere containing oxygen. Note that the atmosphere for the heat treatment preferably does not contain hydrogen, water, or the like. The heat treatment can be performed in an electric furnace, an RTA apparatus, or the like. The use of an RTA apparatus can shorten the heat treatment time.

[0171] Next, a gate insulating layer 110 and a metal oxide layer 114f are formed in layers to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 5(C)).

[0172] The gate insulating layer 110 is preferably formed using an oxide film such as a silicon oxide film or a silicon oxynitride film by a PECVD method, or may be formed by a PECVD method using microwaves.

[0173] The metal oxide layer 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. In this way, oxygen can be supplied to the gate insulating layer 110 during the formation of the metal oxide layer 114f.

[0174] When the metal oxide layer 114f is formed by a sputtering method using an oxide target containing the same metal oxide as in the case of the semiconductor layer 108, the above method can be used.

[0175] For example, the metal oxide layer 114f may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. For example, when aluminum is used as the metal target, an aluminum oxide film can be formed.

[0176] During deposition of the metal oxide layer 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio) or the higher the oxygen partial pressure in the deposition chamber, the more oxygen can be supplied to the gate insulating layer 110. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and still more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.

[0177] By forming the metal oxide layer 114f by a sputtering method in an atmosphere containing oxygen in this manner, oxygen can be supplied to the gate insulating layer 110 and oxygen can be prevented from being released from the gate insulating layer 110 during the formation of the metal oxide layer 114f. As a result, an extremely large amount of oxygen can be trapped in the gate insulating layer 110. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0178] Next, heat treatment is preferably performed to supply oxygen from the gate insulating layer 110 to the semiconductor layer 108. The heat treatment can be performed at a temperature of 200° C. or higher and 400° C. or lower in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas.

[0179] By performing heat treatment after the metal oxide layer 114f is formed and before the gate electrode 112 is formed, oxygen can be effectively supplied from the gate insulating layer 110 to the semiconductor layer .

[0180] After the metal oxide layer 114f is formed, the metal oxide layer 114f, the gate insulating layer 110, and the insulating layer 103 are partially etched to form an opening 142 that reaches the conductive layer 106. This allows the gate electrode 112 to be formed later and the conductive layer 106 to be electrically connected in the opening 142.

[0181] Next, a conductive film 112f to be the gate electrode 112 is formed on the metal oxide layer 114f (FIG. 5D). The conductive film 112f is preferably formed by sputtering using a metal or alloy sputtering target. Here, the conductive film 112f and the conductive layer 106 are connected to each other through the opening 142.

[0182] Next, the conductive film 112f is partially etched to form the gate electrode 112 (FIG. 5(E)).

[0183] In this manner, by covering the upper and side surfaces of the semiconductor layer 108 and the insulating layer 103 with the metal oxide layer 114f and the gate insulating layer 110, it is possible to prevent the semiconductor layer 108 and the insulating layer 103 from being partially etched and thinned when the gate electrode 112 is etched.

[0184] Next, by using the gate electrode 112 as a mask, a process of supplying the impurity element 140 to the metal oxide layer 114f, the gate insulating layer 110, and the semiconductor layer 108 is performed to form the low-resistance region 108n, the region 110d, and the region 103d (FIG. 6A). The gate electrode 112 serves as a mask so that the impurity element 140 is not supplied to the semiconductor layer 108, the gate insulating layer 110, and the metal oxide layer 114f in a region that overlaps with the gate electrode 112.

[0185] The impurity element 140 can be preferably supplied by plasma ion doping or ion implantation. These methods allow the concentration profile in the depth direction to be controlled with high precision by adjusting the ion acceleration voltage, dose, etc. The use of plasma ion doping can increase productivity. Furthermore, the use of ion implantation using mass separation can increase the purity of the supplied impurity element.

[0186] In the supplying process of the impurity element 140, it is preferable to control the processing conditions so that the concentration is highest at the interface between the semiconductor layer 108 and the gate insulating layer 110, or in a portion close to the interface in the semiconductor layer 108, or in a portion close to the interface in the gate insulating layer 110. This makes it possible to supply the impurity element 140 at an optimum concentration to both the semiconductor layer 108 and the gate insulating layer 110 in a single process.

[0187] Examples of the impurity element 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and rare gases. As the impurity element 140, boron, phosphorus, aluminum, magnesium, or silicon is preferably used, and boron or phosphorus is more preferably used.

[0188] As a source gas for the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, B2H6 gas or BF3 gas can be typically used. When supplying phosphorus, PH3 gas can be typically used. Alternatively, a mixed gas in which these source gases are diluted with a rare gas can be used.

[0189] Other usable source gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. The ion source is not limited to gas, and a solid or liquid may be heated and vaporized.

[0190] The supply of the impurity element 140 can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the metal oxide layer 114f, the gate insulating layer 110, and the semiconductor layer 108.

[0191] The method for supplying the impurity element 140 is not limited, and may be, for example, a plasma treatment or a treatment utilizing thermal diffusion by heating. In the case of a plasma treatment, the impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied and performing the plasma treatment. The apparatus for generating the plasma may be a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like.

[0192] In one embodiment of the present invention, the impurity element 140 can be supplied to the semiconductor layer 108 through the metal oxide layer 114f and the gate insulating layer 110. This can prevent the crystallinity of the semiconductor layer 108 from decreasing when the impurity element 140 is supplied. Therefore, this is particularly suitable for a case where the electrical resistance increases due to a decrease in crystallinity.

[0193] In the step of supplying the impurity element 140, the impurity element 140 is also supplied to a portion of the gate insulating layer 110 that does not overlap with the gate electrode 112. This causes a difference in the ease with which oxygen is released by heating between the portion of the gate insulating layer 110 that overlaps with the gate electrode 112 and the portion that does not overlap with the gate electrode 112. Therefore, even when heat treatment is performed after the step of supplying the impurity element 140, it is possible to suppress oxygen from being supplied from the gate insulating layer 110 to the low-resistance region 108n, and to suppress an increase in the electrical resistance of the low-resistance region 108n.

[0194] Next, using the gate electrode 112 as a hard mask, part of the metal oxide layer 114f is etched to form the metal oxide layer 114 (FIG. 6(B)). This allows the formation of the metal oxide layer 114 whose top surface shape roughly matches that of the gate electrode 112.

[0195] In the step of supplying the impurity element 140, the impurity element 140 is also supplied to the portion of the metal oxide layer 114f that does not overlap with the gate electrode 112. This causes a difference in etching rate between the portion of the metal oxide layer 114f that overlaps with the gate electrode 112 and the portion that does not overlap with the gate electrode 112. This makes it possible to suppress shape defects of the metal oxide layer due to etching.

[0196] Although there is no particular limitation on the method for processing the metal oxide layer 114f, using wet etching can prevent the gate insulating layer 110 from being etched simultaneously with the metal oxide layer 114f. This prevents the thickness of the gate insulating layer 110 from decreasing, and allows the thickness of the gate insulating layer 110 to be made uniform.

[0197] Next, an insulating layer 118 is formed to cover the gate insulating layer 110, the metal oxide layer 114, and the gate electrode 112 (FIG. 7(A)).

[0198] When the insulating layer 118 is formed by a plasma CVD method, if the film formation temperature is too high, impurities contained in the low-resistance region 108n and the like may diffuse to the peripheral portion including the channel formation region of the semiconductor layer 108, and the electrical resistance of the low-resistance region 108n may increase. The film formation temperature for the insulating layer 118 is, for example, 150°C to 400°C, preferably 180°C to 360°C, and more preferably 200°C to 250°C. By forming the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0199] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 118 and the gate insulating layer 110 are partially etched to form openings 141a and 141b that reach the low-resistance region 108n.

[0200] Next, a conductive film is formed over the insulating layer 118 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form conductive layers 120a and 120b (FIG. 7B).

[0201] Through the above steps, the transistor 100A can be manufactured. For example, when the transistor 100A is used in a pixel of a display device, a subsequent step of forming one or more of a protective insulating layer, a planarizing layer, a display element, and a wiring may be added.

[0202] [Production method example 2] In one embodiment of the present invention, the metal oxide layer 114f may be difficult to process depending on its material and formation conditions. In such cases, the processing of the metal oxide layer 114f can be made easier by adding a step of reducing the crystallinity of the metal oxide layer 114f.

[0203] In the manufacturing method example 2, the steps up to the manufacturing of the gate electrode 112 are the same as those in the manufacturing method example 1 (FIGS. 5(A) to 5(E)).

[0204] Thereafter, a step of supplying the impurity element 140 (FIG. 8A) and a step of supplying the impurity element 143 (FIG. 8B) are performed. The step of supplying the impurity element 140 is the same as that in Manufacturing Method Example 1 (FIG. 6A), and as a result, a low-resistance region 108n is formed in the semiconductor layer 108. The impurity element 143 is supplied to at least the metal oxide layer 114f. This allows the metal oxide layer 114f to become a metal oxide layer 114g with low crystallinity. Either the impurity element 140 or the impurity element 143 may be supplied first.

[0205] Examples of the impurity element 143 include silicon, phosphorus, argon, krypton, xenon, arsenic, gallium, germanium, etc. As a source gas for the impurity element 143, a gas containing the above impurity element can be used.

[0206] The supply of the impurity element 143 can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the metal oxide layer 114f.

[0207] Thereafter, the gate electrode 112 is used as a hard mask to etch a part of the metal oxide layer 114g with low crystallinity, thereby forming the metal oxide layer 114 (FIG. 8(C)). This makes it possible to easily form the metal oxide layer 114 whose top surface shape roughly matches that of the gate electrode 112.

[0208] [Production method example 3] When the metal oxide layer 114f is an insulating film, the step of processing the metal oxide layer 114f into an island shape may be omitted.

[0209] Fabrication method example 3 is similar to fabrication method example 1 up to the step of supplying the impurity element 140 (FIGS. 5(A) to 5(E) and 6(A)).

[0210] After the step of supplying the impurity element 140 (FIG. 9(A)), an insulating layer 118 is formed to cover the gate insulating layer 110, the metal oxide layer 114f, and the gate electrode 112 without processing the metal oxide layer 114f (FIG. 9(B)).

[0211] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 118, the metal oxide layer 114f, and a portion of the gate insulating layer 110 are etched to form openings 141a and 141b that reach the low-resistance region 108n.

[0212] Next, a conductive film is formed over the insulating layer 118 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form conductive layers 120a and 120b (FIG. 9C).

[0213] Through the above steps, a transistor including the metal oxide layer 114f can be manufactured.

[0214] In the method for manufacturing a semiconductor device according to this embodiment, a metal oxide layer that is impermeable to oxygen, hydrogen, water, and the like is provided between the gate insulating layer and the gate electrode, so that oxygen can be effectively supplied from the gate insulating layer to the semiconductor layer. This reduces oxygen vacancies in the channel formation region of the semiconductor layer, and improves the reliability of the transistor. Furthermore, the metal oxide layer is processed after forming a low-resistance region of the semiconductor layer by supplying impurity elements. Since the metal oxide layer also contains impurity elements during processing, it is possible to suppress shape defects of the metal oxide layer due to etching.

[0215] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0216] (Embodiment 2) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0217] Since the semiconductor device of one embodiment of the present invention has favorable electrical characteristics, its use in a display device can improve the reliability of the display device. For example, the transistor of one embodiment of the present invention can be used as a transistor included in one or both of a pixel and a driver circuit of the display device.

[0218] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0219] [Top view of the display device] 10A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 that are bonded together with a sealant 712. A pixel portion 702, a source driver 704, and a gate driver 706 are provided in a region sealed by the first substrate 701, the second substrate 705, and the sealant 712. The pixel portion 702 is provided with a plurality of display elements.

[0220] An FPC terminal portion 708 to which an FPC 716 is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Various signals and the like are supplied by the FPC 716 to each of the pixel portion 702, the source driver 704, and the gate driver 706 via the FPC terminal portion 708 and signal lines 710.

[0221] There may be a plurality of gate drivers 706. Furthermore, the gate drivers 706 and the source drivers 704 may each be formed separately on a semiconductor substrate or the like and in the form of a packaged IC chip. The IC chip can be mounted on the first substrate 701 or the FPC 716.

[0222] The transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 702, the source driver 704, and the gate driver 706.

[0223] Examples of the display element provided in the pixel portion 702 include a liquid crystal element and a light-emitting element. Examples of the liquid crystal element include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element. Examples of the light-emitting element include a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), and a semiconductor laser. Examples of the light-emitting element include a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, and a display element that employs a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type.

[0224] A display device 700A shown in FIG. 10B is an example of a display device that can be used as a flexible display, in which a flexible resin layer 743 is used instead of the first substrate 701.

[0225] The display device 700A has a pixel portion 702 that is not rectangular, but has arc-shaped corners. As shown in region P1 in FIG. 10(B), the display device 700A has cutouts in which parts of the pixel portion 702 and the resin layer 743 are cut out. A pair of gate drivers 706 are provided on both sides of the pixel portion 702. The gate drivers 706 are provided at the corners of the pixel portion 702 along the arc-shaped contour.

[0226] The resin layer 743 has a protruding shape at a portion where the FPC terminal portion 708 is provided. In addition, a part of the resin layer 743 including the FPC terminal portion 708 can be folded back to the rear side in a region P2 in FIG. 10B. By folding back a part of the resin layer 743, the display device 700A can be mounted on an electronic device with the FPC 716 overlapping the rear side of the pixel portion 702, thereby saving space in the electronic device.

[0227] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 functions as, for example, a source driver. In this case, the source driver 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, etc.

[0228] 10C is a display device that can be suitably used in electronic devices having a large screen, such as televisions, monitors, personal computers (including notebook and desktop computers), tablet terminals, and digital signage.

[0229] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate drivers 722.

[0230] The plurality of source driver ICs 721 are each attached to an FPC 723. One terminal of each of the plurality of FPCs 723 is connected to the first substrate 701, and the other terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby enabling space saving of the electronic device.

[0231] On the other hand, the gate driver 722 is formed on the first substrate 701. This makes it possible to realize an electronic device with a narrow frame.

[0232] This configuration makes it possible to realize a large-sized, high-resolution display device. For example, it can be applied to display devices with a diagonal screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more. It can also realize a display device with an extremely high resolution, such as 4K2K or 8K4K.

[0233] [Cross-sectional structure of the display device] Figures 11 and 12 show display devices having liquid crystal elements as display elements. Figures 13 and 14 show display devices having EL elements as display elements. Figures 11, 12, and 13 are cross-sectional views taken along dashed line QR in Figure 10(A). Figure 14 is a cross-sectional view taken along dashed line ST in Figure 10(B).

[0234] 11 to 13 and a display device 700A shown in FIG. 14 include a wiring portion 711, a pixel portion 702, a source driver 704, and an FPC terminal portion 708. The wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. FIG. 12 shows a case where the capacitor 790 is not provided. The source driver 704 includes a transistor 752.

[0235] The transistors 750 and 752 are transistors in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. For example, the transistors described in Embodiment 1 can be used for each of the transistors. The display device may also include a transistor in which silicon (amorphous silicon, polycrystalline silicon, or single crystal silicon) is used for a semiconductor layer.

[0236] The transistor used in this embodiment includes a highly purified oxide semiconductor film in which oxygen vacancies are suppressed. The transistor can have a small off-state current. Therefore, the retention time of an electric signal such as an image signal can be increased, and the interval between writing of the image signal or the like can be set to be long. Therefore, the frequency of a refresh operation can be reduced, thereby achieving an effect of reducing power consumption.

[0237] Furthermore, the transistor used in this embodiment can achieve relatively high field-effect mobility and thus can be driven at high speed. For example, by using such a transistor capable of high-speed driving in a display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. In other words, since there is no need to use a semiconductor device formed of a silicon wafer or the like as a separate driver circuit, the number of components in the display device can be reduced. Furthermore, by using a transistor capable of high-speed driving in the pixel portion, a high-quality image can be provided.

[0238] 11 and 13 includes a lower electrode formed by processing the same film as the semiconductor layer of the transistor 750 and having a low resistance, and an upper electrode formed by processing the same conductive film as the source or drain electrode. Two insulating films covering the transistor 750 are provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes.

[0239] 14 includes a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide film as the semiconductor layer. The upper electrode has low resistance, similar to the low-resistance region of the transistor 750. A part of an insulating film functioning as the first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. The upper electrode is connected to wiring obtained by processing the same film as the source and drain electrodes of the transistor.

[0240] A planarization insulating film 770 is provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0241] The transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver 704 may have different structures. For example, a top-gate transistor may be used for one of them, and a bottom-gate transistor may be used for the other. Note that the above-described gate driver 706 is similar to the source driver 704.

[0242] The signal line 710 is formed using the same conductive film as the source and drain electrodes of the transistors 750 and 752. In this case, it is preferable to use a low-resistance material such as a material containing copper, because this reduces signal delays and enables display on a large screen.

[0243] The FPC terminal portion 708 includes a wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to a terminal of the FPC 716 through the anisotropic conductive film 780. Here, the wiring 760 is formed using the same conductive film as the source and drain electrodes of the transistors 750 and 752.

[0244] For example, a flexible substrate such as a glass substrate or a plastic substrate can be used as the first substrate 701 and the second substrate 705. By using a flexible substrate, a flexible display can be realized. When a flexible substrate is used for the first substrate 701, an insulating layer having a barrier property against water and hydrogen is preferably provided between the first substrate 701 and the transistor 750 or the like.

[0245] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and an insulating film 734 in contact with these are provided.

[0246] 11, 12, and 13, a spacer 778 for adjusting the distance between the first substrate 701 and the second substrate 705 is provided between the two substrates. The first substrate 701 and the second substrate 705 are bonded to each other with a sealant 712.

[0247] The display device 700 shown in FIG. 11 includes a vertical electric field type liquid crystal element 775. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is formed over a planarization insulating film 770 and functions as a pixel electrode.

[0248] A material that is transparent to visible light or a material that is reflective to visible light can be used for the conductive layer 772. Examples of materials that are transparent to visible light include oxide materials containing indium, zinc, tin, or the like. Examples of materials that are reflective to visible light include materials containing aluminum, silver, or the like.

[0249] When a material that is reflective to visible light is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a material that is transparent to visible light is used for the conductive layer 772, the display device becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich the liquid crystal element.

[0250] 12 shows an example of a display device 700 using a lateral electric field (e.g., Fringe Field Switching (FFS) mode) liquid crystal element 775. A conductive layer 774 functioning as a common electrode is provided over a conductive layer 772 with an insulating layer 773 interposed therebetween. The alignment state of a liquid crystal layer 776 can be controlled by an electric field generated between the conductive layer 772 and the conductive layer 774.

[0251] 12, a storage capacitor can be formed using a stacked structure of a conductive layer 772, an insulating layer 773, and a conductive layer 774. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0252] 11 and 12, an alignment film may be provided in contact with the liquid crystal layer 776. Furthermore, optical members (optical substrates) such as a polarizing member, a phase difference member, and an anti-reflection member, and light sources such as a backlight and a sidelight may be provided as appropriate.

[0253] Thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, polymer network liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal layer 776. When the in-plane switching mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may also be used.

[0254] The liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, VA-IPS mode, and guest-host mode.

[0255] Furthermore, a time-sequential display method (also called a field sequential driving method) that performs color display based on a time-sequential additive color mixture method may be applied as a driving method for the liquid crystal element. In this case, the color film 736 may not be provided. When the time-sequential display method is used, it is not necessary to provide sub-pixels that exhibit the respective colors of red (R), green (G), and blue (B), for example, and therefore the aperture ratio of the pixel and the resolution of the display device can be improved.

[0256] 13 and a display device 700A shown in Fig. 14 include a light-emitting element 782. The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes a light-emitting substance.

[0257] Examples of light-emitting materials that can be used include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0258] 13 and 14, an insulating film 730 that covers part of a conductive layer 772 is provided over a planarization insulating film 770. Here, the light-emitting element 782 is a top-emission light-emitting element that has a conductive film 788 that transmits visible light. Note that the light-emitting element 782 may have a bottom-emission structure in which light is emitted to the conductive layer 772 side, or a dual-emission structure in which light is emitted to both the conductive layer 772 side and the conductive film 788 side.

[0259] 13, the colored film 736 is provided at a position overlapping with the light-emitting element 782, and the light-shielding film 738 is provided at a position overlapping with the insulating film 730, the lead-out wiring portion 711, and the source driver 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that, as shown in FIG. 14, when a side-by-side method (also called a separate coloring method) is used in which different EL layers 786 are formed in the subpixels of each color, the colored film 736 does not have to be provided.

[0260] In FIG. 14, an EL layer 786 included in a light-emitting element 782 is provided in an island shape over an insulating film 730 and a conductive layer 772. By forming the EL layer 786 so that each subpixel emits a different light color, color display can be achieved without using a colored film 736. A protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 is preferably an inorganic insulating film. More preferably, the protective layer 741 has a stacked structure including at least one inorganic insulating film and at least one organic insulating film.

[0261] 14 has a stacked structure of a supporting substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744, instead of the first substrate 701 shown in FIG. 13. A transistor 750, a capacitor 790, and the like are provided over the insulating layer 744.

[0262] The support substrate 745 is a substrate containing organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing organic resin such as polyimide or acrylic. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is preferably thinner than the support substrate 745.

[0263] 14 has a protective layer 740 instead of the second substrate 705 shown in FIG. 13. The protective layer 740 is bonded to a sealing film 732. A glass substrate, a resin film, or the like can be used as the protective layer 740. The protective layer 740 may be an optical member such as a polarizing plate or a scattering plate, an input device such as a touch sensor, or a configuration in which two or more of these are stacked.

[0264] FIG. 14 also shows a bendable region P2. Region P2 includes a support substrate 745, an adhesive layer 742, and a portion where no inorganic insulating film, such as an insulating layer 744, is provided. A resin layer 746 is provided in region P2, covering the wiring 760. By providing as little inorganic insulating film as possible in region P2 and using a configuration in which only a conductive layer containing a metal or alloy and a layer containing an organic material are stacked, it is possible to prevent cracks from occurring when the display device 700A is bent. Furthermore, by not providing a support substrate 745 in region P2, a portion of the display device 700A can be bent with an extremely small radius of curvature.

[0265] The display device of this embodiment may have an input device such as a touch sensor, etc. That is, the display device of this embodiment may have a function as a touch panel.

[0266] The sensor may be of various types, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, or a pressure-sensitive type, or may be a combination of two or more of these types.

[0267] Touch panels include so-called in-cell touch panels in which the input device is formed inside a pair of substrates, so-called on-cell touch panels in which the input device is formed on the display device, and so-called out-cell touch panels in which the input device is attached to the display device.

[0268] This embodiment mode can be combined with other embodiment modes as appropriate.

[0269] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0270] Since the semiconductor device of one embodiment of the present invention has favorable electrical characteristics, its use in a display device can improve the reliability of the display device. For example, the transistor of one embodiment of the present invention can be used as a transistor included in one or both of a pixel and a driver circuit of the display device.

[0271] 15A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 may not be provided.

[0272] The transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention may also be applied to the protection circuit 506.

[0273] The pixel section 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).

[0274] The driver circuit unit 504 includes driver circuits such as a gate driver 504a that outputs scan signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a includes at least a shift register. The source driver 504b is configured using, for example, a plurality of analog switches. Alternatively, the source driver 504b may be configured using a shift register.

[0275] The terminal portion 507 is a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0276] 15A, the protection circuit 506 is connected to various wirings, such as the scanning line GL between the gate driver 504a and the pixel circuit 501, or the data line DL between the source driver 504b and the pixel circuit 501.

[0277] The gate driver 504a and the source driver 504b may be formed directly on the same substrate as the pixel section 502, or may be formed on a separate substrate and mounted on the substrate on which the pixel section is formed by COG or TAB (Tape Automated Bonding).

[0278] The plurality of pixel circuits 501 shown in FIG. 15(A) can have the configurations shown in FIG. 15(B) and FIG. 15(C), for example.

[0279] 15B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a scanning line GL_m, a potential supply line VL, and the like.

[0280] The potential of one of the pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Alternatively, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0281] 15C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a scanning line GL_m, a potential supply line VL_a, a power supply line VL_b, and the like.

[0282] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the gate of the transistor 554, thereby controlling the luminance of the light-emitting element 572.

[0283] This embodiment mode can be combined with other embodiment modes as appropriate.

[0284] (Fourth embodiment) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0285] A pixel of the display device of this embodiment has a memory for correcting a gray scale displayed in the pixel. The transistor of one embodiment of the present invention can be used as a transistor included in the pixel.

[0286] [Pixel circuit] 16A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0287] The transistor M1 has a gate connected to the wiring G1, one of a source and a drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of a source and a drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401.

[0288] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or an MEMS element can be applied.

[0289] The node connecting the transistor M1 and the capacitor C1 is defined as N1, and the node connecting the transistor M2 and the circuit 401 is defined as N2.

[0290] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. In addition, the potential of the node N2 can be maintained by turning off the transistor M2. In addition, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed in accordance with the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0291] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 1, can be used as one or both of the transistors M1 and M2. Therefore, the potentials of the nodes N1 and N2 can be held for a long period of time due to an extremely small off-state current. Note that when the period for holding the potentials of the nodes is short (specifically, when the frame frequency is 30 Hz or higher), a transistor including a semiconductor such as silicon may be used.

[0292] [Drive method] An example of an operation method of the pixel circuit 400 will be described using Fig. 16(B). Fig. 16(B) is a timing chart relating to the operation of the pixel circuit 400. Note that, to simplify the explanation, the influence of various resistances such as wiring resistance, parasitic capacitance of transistors and wiring, and threshold voltage of transistors will not be taken into consideration here.

[0293] 16B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0294] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supply.

[0295] The node N1 is connected to the line S1 via the transistor M1. ref The node N2 is supplied with a first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is maintained.

[0296] In the period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 is set in a floating state.

[0297] The node N1 is supplied with a second data potential V data At this time, the second data potential V data In other words, the potential of the node N2 changes by a potential dV in response to the first data potential V wThe potential obtained by adding the potential V to the potential dV is input. Note that although dV is shown as a positive value in FIG. 16(B), it may also be a negative value. data is the potential V ref It may be lower.

[0298] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential is close to

[0299] In this way, the pixel circuit 400 can generate a potential to be supplied to the circuit 401 including a display element by combining two types of data signals, and therefore, it is possible to perform gray scale correction within the pixel circuit 400.

[0300] The pixel circuit 400 can also generate a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Furthermore, when a liquid crystal element is used, overdrive driving or the like can be realized.

[0301] [Pixel circuit with liquid crystal element] 16C includes a circuit 401LC, which includes a liquid crystal element LC and a capacitor C2.

[0302] One electrode of the liquid crystal element LC is connected to the node N2 and one electrode of the capacitor C2, and the other electrode is connected to a potential V com2 The other electrode of the capacitor C2 is connected to a wiring to which a potential V com1 Connect with the wiring given.

[0303] The capacitor C2 functions as a storage capacitor. Note that the capacitor C2 can be omitted if not required.

[0304] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, which makes it possible to, for example, achieve high-speed display by overdriving, apply a liquid crystal material with a high driving voltage, etc. Furthermore, by supplying a correction signal to the line S1 or the line S2, it is possible to correct the gradation in accordance with the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0305] [Pixel circuit having a light-emitting element] 16D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0306] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and one of its source and drain connected to the potential V H The other electrode of the capacitor C2 is connected to a wiring to which a potential V com The other electrode of the light-emitting element EL is connected to a wiring to which a potential V L Connect with the wiring given.

[0307] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if it is not necessary.

[0308] Although the anode side of the light-emitting element EL is connected to the transistor M3 in this example, the transistor M3 may be connected to the cathode side. H and potential V L The value of can be changed as appropriate.

[0309] In the pixel circuit 400EL, by applying a high potential to the gate of the transistor M3, a large current can flow through the light-emitting element EL, thereby realizing, for example, HDR display, etc. Furthermore, by supplying a correction signal to the wiring S1 or the wiring S2, it is possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0310] Note that the circuits are not limited to those illustrated in FIGS. 16C and 16D, and may be configured to include additional transistors, capacitors, and the like.

[0311] This embodiment mode can be combined with other embodiment modes as appropriate.

[0312] (Embodiment 5) In this embodiment, a display module of one embodiment of the present invention will be described with reference to FIGS.

[0313] A display module 6000 shown in FIG. 17A includes a display device 6006 connected to an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0314] A display device manufactured using the transistor of one embodiment of the present invention can be used for the display device 6006. The display device 6006 can provide a highly reliable display module.

[0315] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately to match the size of the display device 6006.

[0316] The display device 6006 may have a function as a touch panel.

[0317] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0318] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, etc. The power supply may be a battery 6011.

[0319] FIG. 17(B) is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor.

[0320] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. The display module 6000 also has a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) in an area surrounded by an upper cover 6001 and a lower cover 6002.

[0321] The display device 6006 is provided so as to overlap a printed circuit board 6010 and a battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guide portion 6017a and a light guide portion 6017b.

[0322] Light 6018 emitted from light-emitting unit 6015 passes through light-guiding unit 6017a, passes through the upper part of display device 6006, and passes through light-guiding unit 6017b to reach light-receiving unit 6016. When light 6018 is blocked by a detection target such as a finger or a stylus, a touch operation can be detected.

[0323] A plurality of light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light-receiving units 6016 are provided at positions facing the light-emitting units 6015. This makes it possible to obtain information about the position where a touch operation is performed.

[0324] A light source such as an LED element can be used for the light-emitting unit 6015, and it is particularly preferable to use a light source that emits infrared light. A photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal can be used for the light-receiving unit 6016. Preferably, a photodiode that can receive infrared light can be used.

[0325] The light guiding portions 6017a and 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, thereby preventing external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively prevent the touch sensor from malfunctioning.

[0326] This embodiment mode can be combined with other embodiment modes as appropriate.

[0327] (Sixth embodiment) In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0328] The electronic devices of this embodiment include the semiconductor device of one embodiment of the present invention. For example, the transistor of one embodiment of the present invention can be applied to a transistor of a display device used in a display portion of an electronic device. The transistor of one embodiment of the present invention has stable and favorable electrical characteristics and high reliability, which can improve the reliability of the display device and the electronic device. Therefore, the transistor of one embodiment of the present invention can be used in various electronic devices.

[0329] The display unit of the electronic device of this embodiment can display images with resolutions of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0330] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0331] The electronic device of this embodiment can be incorporated along the curved surface of the inner or outer wall of a house or building, or the interior or exterior of an automobile.

[0332] The electronic device of this embodiment may have an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display unit. In addition, when the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0333] The electronic device of this embodiment may have a sensor (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0334] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0335] An electronic device 6500 shown in FIG. 18A is a portable information terminal that can be used as a smartphone.

[0336] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0337] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 6502.

[0338] FIG. 18B is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0339] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0340] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0341] In an area outside the display unit 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0342] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0343] 19A shows an example of a television set. A television set 7100 includes a display portion 7000 built in a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0344] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 7000.

[0345] 19A can be operated using an operation switch provided on the housing 7101 or a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0346] The television device 7100 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. In addition, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0347] 19B shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7000 is incorporated in the housing 7211.

[0348] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 7000.

[0349] 19(C) and 19(D) show examples of digital signage.

[0350] 19C includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0351] 19D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0352] 19C and 19D, a display device including the transistor of one embodiment of the present invention can be used in the display portion 7000.

[0353] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it will attract people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0354] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, intuitive operation can improve usability.

[0355] 19(C) and 19(D), the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0356] Furthermore, it is also possible to cause the digital signage 7300 or the digital signage 7400 to execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0357] FIG. 20A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0358] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. A detachable lens 8006 is attached to the camera 8000. Note that the lens 8006 and the housing of the camera 8000 may be integrated together.

[0359] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0360] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0361] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0362] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0363] The button 8103 has a function such as a power button.

[0364] A display device including the transistor of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the camera 8000 may have a built-in finder.

[0365] FIG. 20B is a diagram showing the appearance of the head mounted display 8200.

[0366] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0367] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204. The main body 8203 also includes a camera, and can use information on the movements of the user's eyeballs and eyelids as an input means.

[0368] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that come into contact with the user and capable of detecting a current that flows in accordance with the movement of the user's eyeballs. The wearing unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 in accordance with the movement of the user's head.

[0369] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 8204.

[0370] 20C to 20E are diagrams showing the appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0371] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to arrange the display portion 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, it is possible to perform 3D display using parallax. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided, with one display portion being provided for each eye of the user.

[0372] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 8302. A display device with extremely high resolution can also be manufactured using the transistor of one embodiment of the present invention. For example, even when the display is enlarged and viewed using the lens 8305 as shown in FIG. 20(E), the pixels are difficult for a user to view. That is, a highly realistic image can be viewed by the display portion 8302.

[0373] The electronic devices shown in Figures 21(A) to 21(F) have a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0374] 21(A) to 21(F) have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on the display unit, etc.

[0375] The electronic devices shown in FIGS. 21A to 21F will be described in detail below.

[0376] FIG. 21A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 21A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and the strength of antenna reception. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0377] 21B is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is placed in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0378] 21C is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch. The display surface of the display portion 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0379] 21(D) to 21(F) are perspective views showing a foldable mobile information terminal 9201. FIG. 21(D) is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 21(F) is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 21(E) is a perspective view of a state in the process of changing from one of FIG. 21(D) and FIG. 21(F) to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent viewability of the display. A display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0380] This embodiment mode can be combined with other embodiment modes and examples as appropriate. [Example]

[0381] Example 1 In this example, a transistor according to one embodiment of the present invention was fabricated and evaluated. In particular, this example describes the case where the metal oxide layer 114 contains the same metal oxide (IGZO) as the semiconductor layer 108.

[0382] [Etching rate of metal oxide layer 114f] First, the etching rate of the metal oxide layer 114f was evaluated. Six samples were prepared, and the etching rate of the metal oxide layer 114f was evaluated for each sample.

[0383] For each sample, an IGZO film with a thickness of approximately 20 nm was formed as the metal oxide layer 114f. The IGZO film was formed by sputtering using a metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, at an oxygen flow rate of 100% and a substrate temperature of 200°C. After the IGZO film was formed, it was subjected to a heat treatment at 350°C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0384] For the three samples, boron (B) was supplied to the metal oxide layer 114f using a plasma ion doping device without a mass separation mechanism. BH gas was used as the gas for supplying boron, and the acceleration voltage was 40 kV and the dose was 2×10 15 ions / cm 2 For the remaining three samples, boron was not supplied to the metal oxide layer 114f.

[0385] Next, the metal oxide layer 114f was wet-etched. Three types of etchants were used: oxalic acid (5% or less, liquid temperature 60°C, spin treatment), mixed acid (less than 80% phosphoric acid, less than 5% nitric acid, less than 10% acetic acid, 5% or more water, liquid temperature 30°C, spray treatment), and a 30-fold diluted aqueous solution of phosphoric acid (85%) (liquid temperature room temperature, spin treatment). The metal oxide layer 114f of each sample, with and without boron supply, was wet-etched with each etchant.

[0386] The etching rate (unit: nm / min) of each sample is shown in Figure 22. The etching rate was determined by optical interference film thickness measurement.

[0387] It was found that, regardless of which etchant was used, the sample in which boron was supplied to the metal oxide layer 114f (with B doping) had a higher etching rate than the sample in which boron was not supplied (without B doping). In particular, when oxalic acid was used, supplying boron to the metal oxide layer 114f increased the etching rate of the metal oxide layer 114f by about 2.5 times compared to when boron was not supplied.

[0388] From the above, it was found that the etching rate can be increased by supplying boron to the metal oxide layer 114f. It is believed that supplying boron to the metal oxide layer 114f reduces the crystallinity of the metal oxide layer 114f, thereby increasing the etching rate.

[0389] [Cross-section observation of metal oxide layer 114] Next, the metal oxide layer 114f was wet-etched to form the metal oxide layer 114, and the cross section was observed. Here, two samples were prepared and the cross sections were observed.

[0390] 1A to 1C, a stacked layer structure corresponding to the structure of the transistor 100 was formed. Specifically, an insulating layer 103, a semiconductor layer 108, a gate insulating layer 110, a metal oxide layer 114, a gate electrode 112, and an insulating layer 118 were formed over a substrate 102.

[0391] The conditions for forming the metal oxide layer 114f were the same as those described above. After forming the metal oxide layer 114f on the gate insulating layer 110, a molybdenum film was formed as the gate electrode 112. In one of the two samples, boron was supplied to the metal oxide layer 114f using the gate electrode 112 as a mask. In the other, boron was not supplied to the metal oxide layer 114f.

[0392] Then, the metal oxide layer 114f was processed using the gate electrode 112 as a mask to form the metal oxide layer 114. Here, the metal oxide layer 114f was processed using wet etching.

[0393] For wet etching of the metal oxide layer 114f, oxalic acid (5% or less, liquid temperature 60°C, spin treatment) was used. The treatment time was 30 seconds for the sample to which boron was not supplied and 10 seconds for the sample to which boron was supplied. The treatment time was determined based on the results of the etching rate of the metal oxide layer 114f (FIG. 22). Specifically, supplying boron to the metal oxide layer 114f increases the etching rate of the metal oxide layer 114f, so the treatment time for the sample to which boron was supplied was shorter than that for the sample to which boron was not supplied.

[0394] FIG. 23(A) shows a cross-sectional observation photograph of a sample in which boron was not supplied to the metal oxide layer 114f, and FIG. 23(B) shows a cross-sectional observation photograph of a sample in which boron was supplied.

[0395] As shown by the dotted line in Figure 23(A), in the sample in which boron was not supplied to the metal oxide layer 114f, a part (lower part) of the metal oxide layer 114 that overlapped with the gate electrode 112 was etched.

[0396] On the other hand, as shown by the dotted line in Figure 23(B), in the sample to which boron was supplied, etching of the lower part of the metal oxide layer 114 overlapping the gate electrode 112 was suppressed, and it was confirmed that the coverage of the insulating layer 118 was improved.

[0397] From the above, it was found that by using the gate electrode 112 as a mask and supplying boron to the metal oxide layer 114f, it is possible to make a difference in etching rate between the portion to which boron is supplied (the portion not overlapping with the gate electrode 112) and the portion to which boron is not supplied (the portion overlapping with the gate electrode 112). Therefore, the portion of the metal oxide layer 114 that overlaps with the gate electrode 112 is less likely to be etched, and shape defects of the metal oxide layer 114 can be suppressed. This improves the covering property of the insulating layer 118, and suppresses coverage defects.

[0398] [Evaluation of transistor electrical characteristics and reliability] Next, we fabricated transistors and evaluated their electrical characteristics and reliability. Six types of samples were fabricated.

[0399] 3A to 3C, a stacked layer structure corresponding to the structure of the transistor 100A was formed. Specifically, a conductive layer 106, an insulating layer 103, a semiconductor layer 108, a gate insulating layer 110, a metal oxide layer 114, a gate electrode 112, an insulating layer 118, a conductive layer 120a, and a conductive layer 120b were formed over a substrate 102. Furthermore, a planarization film (not shown) was formed over the insulating layer 118, the conductive layer 120a, and the conductive layer 120b.

[0400] In Samples A to C according to one embodiment of the present invention, the impurity element 140 was supplied and then the metal oxide layer 114f was etched to form the metal oxide layer 114, as described in Embodiment 1. In Comparative Samples A to C, the impurity element 140 was supplied after the metal oxide layer 114f was etched and then the metal oxide layer 114 was formed.

[0401] For sample A and comparative sample A, transistors with a channel length of 2 μm and a channel width of 50 μm were fabricated, for sample B and comparative sample B, transistors with a channel length of 3 μm and a channel width of 50 μm were fabricated, and for sample C and comparative sample C, transistors with a channel length of 6 μm and a channel width of 50 μm were fabricated.

[0402] A specific method for manufacturing a transistor will be described below with reference to FIGS.

[0403] First, a tungsten film having a thickness of about 100 nm was formed on a glass substrate (corresponding to the substrate 102) by sputtering and processed to form a conductive layer 106 (FIG. 5(A)).

[0404] Next, a silicon nitride film having a thickness of approximately 240 nm, a silicon nitride film having a thickness of approximately 60 nm, and a silicon oxynitride film having a thickness of approximately 5 nm were formed in this order as the insulating layer 103 on the substrate 102 and the conductive layer 106 by plasma CVD (Figure 5(A)).

[0405] Next, an IGZO film approximately 50 nm thick was formed on the insulating layer 103 and processed to form the semiconductor layer 108 (FIG. 5(B)). The IGZO film was formed by sputtering using a metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, with an oxygen flow rate of 10% and a substrate temperature of room temperature. After the IGZO film was formed, it was subjected to a heat treatment at 350°C for 1 hour in a nitrogen atmosphere, followed by another heat treatment at 350°C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0406] Next, a silicon oxynitride film having a thickness of about 150 nm was formed as a gate insulating layer 110 on the insulating layer 103 and the semiconductor layer 108 by plasma CVD (FIG. 5C).

[0407] Next, an IGZO film with a thickness of approximately 20 nm was formed as the metal oxide layer 114f on the gate insulating layer 110 by sputtering in an oxygen-containing atmosphere (FIG. 5(C)). Forming the metal oxide layer 114f in an oxygen-containing atmosphere allows oxygen to be supplied into the gate insulating layer 110. The IGZO film was formed using a metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, with an oxygen flow rate of 100% and a substrate temperature of 200°C. After the IGZO film was formed, a heat treatment was performed at 350°C for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0408] Next, a molybdenum film having a thickness of about 100 nm was formed as a conductive film 112f on the metal oxide layer 114f by sputtering (FIG. 5(D)), and processed to form a gate electrode 112 (FIG. 5(E)).

[0409] Next, for Samples A to C according to one embodiment of the present invention, boron (B) was supplied using a plasma ion doping apparatus (FIG. 6A). In this step, boron was supplied to the semiconductor layer 108, the gate insulating layer 110, and the metal oxide layer 114f using the gate electrode 112 as a mask. BH gas was used as the gas for supplying boron, and the acceleration voltage was 40 kV and the dose was 2×10 15 ions / cm 2 Thereafter, the metal oxide layer 114f was processed by wet etching to form the metal oxide layer 114 (FIG. 6(B)). For wet etching of the metal oxide layer 114f, oxalic acid (5% or less, liquid temperature 60°C, spin treatment) was used, and the treatment time was 10 seconds.

[0410] On the other hand, for comparative samples A to C, the metal oxide layer 114f was first processed by wet etching to form the metal oxide layer 114. The metal oxide layer 114f was wet-etched using oxalic acid (5% or less, liquid temperature 60°C, spin treatment) for 30 seconds. After that, boron (B) was supplied using a plasma ion doping device. In this process, boron was supplied to the semiconductor layer 108 and the gate insulating layer 110 using the gate electrode 112 as a mask.

[0411] The subsequent steps were the same for both the sample and the comparative sample. A silicon oxynitride film with a thickness of approximately 300 nm was formed as an insulating layer 118 on the gate insulating layer 110, the metal oxide layer 114, and the gate electrode 112 by plasma CVD (FIG. 7A).

[0412] Next, openings were made in parts of the gate insulating layer 110 and the insulating layer 118. Then, a molybdenum film with a thickness of approximately 100 nm was formed by sputtering and processed to form conductive layers 120a and 120b (FIG. 7B).

[0413] Thereafter, an acrylic film having a thickness of about 1.5 μm was formed as a flattening film (not shown), and heat treatment was carried out at 250° C. for 1 hour in a nitrogen atmosphere.

[0414] In this manner, each sample was prepared.

[0415] Next, the Id-Vg characteristics of the transistors of each sample were measured, and the Id-Vg characteristics results of the transistors of each sample are shown in FIG.

[0416] The Id-Vg characteristics of the transistor were measured under the following conditions: the voltage applied to the gate electrode 112 (gate voltage (Vg)) and the voltage applied to the conductive layer 106 (back gate voltage (Vbg)) were applied in steps of 0.25 V from −15 V to +20 V. The voltage applied to the source electrode (source voltage (Vs)) was set to 0 V (comm), and the voltage applied to the drain electrode (drain voltage (Vd)) was set to 0.1 V and 20 V.

[0417] 24, no significant difference in the Id-Vg characteristics was observed between Sample A and Comparative Sample A. Similarly, no significant difference in the Id-Vg characteristics was observed between Sample B and Comparative Sample B, or between Sample C and Comparative Sample C.

[0418] From the above, it was confirmed that the order of the process of processing the metal oxide layer 114f and the process of supplying boron does not significantly affect the Id-Vg characteristics of the transistor. In other words, it was found that a transistor with good electrical characteristics can be manufactured even if the metal oxide layer 114f is processed after supplying boron in order to prevent etching of the part (lower part) of the metal oxide layer 114 that overlaps with the gate electrode 112.

[0419] Next, a stress test of the transistors was performed on Sample B and Comparative Sample B.

[0420] The stress test used was a gate bias thermal stress test (GBT test). GBT testing is a type of accelerated testing that can quickly evaluate changes in transistor characteristics that occur over long periods of use. In this GBT test, the substrate on which the transistor is formed is maintained at 60°C, and a voltage of 0V is applied to the transistor's source and drain, and 20V or -20V is applied to the gate. This condition is maintained for 3,600 seconds. A test in which a positive voltage is applied to the gate is referred to as PBTS (Positive Bias Temperature Stress), and a test in which a negative voltage is applied is referred to as NBTS (Negative Bias Temperature Stress). The substrate on which the transistor is formed was also maintained at 60°C, and 10,000 lx of white LED light was irradiated. A voltage of 0V is applied to the transistor's source and drain, and 20V or -20V is applied to the gate. This condition is maintained for 3,600 seconds. In this case, the test in which a positive voltage is applied to the gate is referred to as PBTIS (Positive Bias Temperature Illumination Stress), and the test in which a negative voltage is applied is referred to as NBTIS (Negative Bias Temperature Illumination Stress).

[0421] FIG. 25 shows the results of PBTS and NBTIS for Sample B and Comparative Sample B.

[0422] As shown in FIG. 25, there was no significant difference in the amount of change in threshold voltage (ΔVth) between Sample B and Comparative Sample B for both PBTS and NBTIS.

[0423] From the above, it was confirmed that the order of the process of processing the metal oxide layer 114f and the process of supplying boron does not significantly affect the GBT test results of the transistor. In other words, it was found that a highly reliable transistor can be manufactured even if the metal oxide layer 114f is processed after supplying boron in order to prevent etching of the part (lower part) of the metal oxide layer 114 that overlaps with the gate electrode 112. [Example]

[0424] Example 1 In this example, a transistor according to one embodiment of the present invention was fabricated and evaluated. In particular, in this example, aluminum oxide (AlO x ) membrane will be described.

[0425] In this example, a transistor was fabricated and its electrical characteristics and reliability were evaluated. Four types of samples were fabricated. In this example, a transistor with a channel length of 2 μm and a channel width of 50 μm was fabricated.

[0426] In Samples D and E of one embodiment of the present invention, transistors including the metal oxide layer 114f were formed without performing a step of processing the metal oxide layer 114f by using the gate electrode 112 as a mask. On the other hand, in Comparative Samples F and G, the metal oxide layer 114f was etched to form transistors including the metal oxide layer 114f.

[0427] A specific method for manufacturing a transistor will be described below with reference to FIGS.

[0428] First, a tungsten film having a thickness of about 100 nm was formed on a glass substrate (corresponding to the substrate 102) by sputtering and processed to form a conductive layer 106 (FIG. 5(A)).

[0429] Next, a silicon nitride film having a thickness of approximately 240 nm, a silicon nitride film having a thickness of approximately 60 nm, and a silicon oxynitride film having a thickness of approximately 5 nm were formed in this order as the insulating layer 103 on the substrate 102 and the conductive layer 106 by plasma CVD (Figure 5(A)).

[0430] Next, an IGZO film was formed on the insulating layer 103 and processed to form a semiconductor layer 108 (FIG. 5(B)).

[0431] For samples D and E, the IGZO film was formed to a thickness of approximately 30 nm by sputtering using a metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, with an oxygen flow rate of 10% and a substrate temperature of room temperature. After the IGZO film was formed, it was subjected to a heat treatment in a nitrogen atmosphere at 350°C for 1 hour, followed by another heat treatment in a mixed atmosphere of oxygen and nitrogen at 350°C for 1 hour.

[0432] For comparative samples F and G, the IGZO film was formed to a thickness of approximately 40 nm by sputtering using a metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, at an oxygen flow rate of 30% and a substrate temperature of 200°C. After the IGZO film was formed, it was subjected to a heat treatment in a nitrogen atmosphere at 400°C for 1 hour, and then to a heat treatment in a mixed atmosphere of oxygen and nitrogen at 400°C for 1 hour.

[0433] Next, a silicon oxynitride film having a thickness of approximately 150 nm was formed as a gate insulating layer 110 on the insulating layer 103 and the semiconductor layer 108 by plasma CVD (FIG. 5C). Here, comparative samples F and G were subjected to a heat treatment at 400° C. for 1 hour in a nitrogen atmosphere.

[0434] Next, an aluminum oxide film was formed as the metal oxide layer 114f over the gate insulating layer 110 by sputtering in an atmosphere containing oxygen (FIG. 5C). The aluminum oxide film was formed to a thickness of approximately 10 nm in Samples D and E, and to a thickness of approximately 5 nm in Comparative Samples F and G. After the aluminum oxide film was formed, it was subjected to heat treatment at 350° C. for 1 hour in a mixed atmosphere of oxygen and nitrogen.

[0435] Next, a molybdenum film was formed as the conductive film 112f on the metal oxide layer 114f by sputtering (FIG. 5D) and processed to form the gate electrode 112 (FIG. 5E). The molybdenum film was formed to a thickness of approximately 300 nm in Samples D and E, and to a thickness of approximately 200 nm in Comparative Samples F and G.

[0436] Next, for Samples D and E to which one embodiment of the present invention is applied, boron (B) or phosphorus (P) was supplied using an ion implantation apparatus having a mass separation mechanism ( FIG. 9A ). In this step, boron or phosphorus was supplied to the semiconductor layer 108, the gate insulating layer 110, and the metal oxide layer 114f using the gate electrode 112 as a mask. Boron was supplied to Sample D, and phosphorus was supplied to Sample E.

[0437] On the other hand, for comparative samples F and G, the metal oxide layer 114f was processed by wet etching to form the metal oxide layer 114. Then, boron or phosphorus was supplied using an ion implantation apparatus. In this process, boron or phosphorus was supplied to the semiconductor layer 108 and the gate insulating layer 110 using the gate electrode 112 as a mask. Boron was supplied to comparative sample F, and phosphorus was supplied to comparative sample G.

[0438] The beam energy when supplying boron was 30 keV, and the beam energy when supplying phosphorus was 80 keV. The dose of boron or phosphorus was 3 × 10 15 / cm 2 For comparative sample F, it is 1 × 10 16 / cm 2 It was decided.

[0439] The subsequent steps were the same for both the sample and the comparative sample. A silicon oxynitride film having a thickness of approximately 300 nm was formed as the insulating layer 118 on the gate insulating layer 110, the metal oxide layer 114f (or the metal oxide layer 114), and the gate electrode 112 by plasma CVD (FIG. 9B).

[0440] Next, openings were made in parts of the metal oxide layer 114f, the gate insulating layer 110, and the insulating layer 118. Then, a molybdenum film with a thickness of approximately 100 nm was formed by sputtering and processed to form conductive layers 120a and 120b (FIG. 9C).

[0441] Thereafter, an acrylic film having a thickness of about 1.5 μm was formed as a flattening film (not shown), and heat treatment was carried out at 250° C. for 1 hour in a nitrogen atmosphere.

[0442] In this manner, each sample was prepared.

[0443] Next, the Id-Vg characteristics of the transistors of each sample were measured, and the Id-Vg characteristics results of the transistors of each sample are shown in FIG.

[0444] The Id-Vg characteristics of the transistor were measured under the following conditions: the voltage applied to the gate electrode 112 (gate voltage (Vg)) and the voltage applied to the conductive layer 106 (back gate voltage (Vbg)) were varied from -15 V to +20 V in steps of 0.25 V. The voltage applied to the source electrode (source voltage (Vs)) was set to 0 V (comm), and the voltage applied to the drain electrode (drain voltage (Vd)) was set to 0.1 V and 10 V for Samples D and E, and 0.1 V and 5.1 V for Comparative Samples F and G.

[0445] As shown in FIGS. 26(A) to 26(D), good Id-Vg characteristics were obtained in all four samples fabricated in this example.

[0446] From the above, it was confirmed that even if the metal oxide layer 114f is not processed and boron or phosphorus is supplied through the metal oxide layer 114f and the transistor has the metal oxide layer 114f, the Id-Vg characteristics of the transistor are not significantly affected.

[0447] Next, a stress test of the transistors was carried out for Samples D and E.

[0448] The conditions of the stress test were the same as those in Example 1.

[0449] FIG. 27 shows the results for PBTS, NBTS, PBTIS, and NBTIS for Samples D and E.

[0450] As shown in FIG. 27, in all of PBTS, NBTS, PBTIS, and NBTIS, Samples D and E showed favorable results with threshold voltage fluctuations (ΔVth) of ±1 V or less.

[0451] From the above, it was confirmed that even if the metal oxide layer 114f is not processed, but boron or phosphorus is supplied through the metal oxide layer 114f, and the transistor has the metal oxide layer 114f, the results of the stress test of the transistor are not significantly affected.

[0452] 28 shows a cross-sectional photograph of a sample to which one embodiment of the present invention is applied. As shown in FIG. 28, a metal oxide layer 114f is formed over a gate insulating layer 110. In the sample to which one embodiment of the present invention is applied, a step of processing the metal oxide layer 114f using the gate electrode 112 as a mask was not performed. Therefore, it was confirmed that the metal oxide layer 114f has a region in contact with the gate electrode 112 and a region in contact with the insulating layer 118. [Example]

[0453] In this example, an aluminum oxide film that can be used for the metal oxide layer 114 of a transistor of one embodiment of the present invention was formed and evaluated. The results are described.

[0454] [Etching of aluminum oxide film] In this example, the results of forming an aluminum oxide film and performing wet etching will be described.

[0455] First, aluminum oxide (AlO) with a thickness of about 50 nm was deposited on a glass substrate by sputtering in an oxygen-containing atmosphere. x ) film was formed.

[0456] Figure 29(A) shows the results of structural analysis using an XRD device. As indicated by the arrow in Figure 29(A), peaks derived from Al2O3 crystals were observed. Furthermore, when the film density was measured using X-ray reflectometry (XRR), the film density of the aluminum oxide film was found to be 3.98 g / cm 3 It was.

[0457] Next, the aluminum oxide film was wet-etched using dilute hydrofluoric acid (DHF).

[0458] The upper part of FIG. 30 shows cross-sectional observation photographs of a sample that has not been wet-etched (no etching treatment) and a sample that has been wet-etched (etched treatment).

[0459] As shown in the upper part of Figure 30, wet etching did not progress on the aluminum oxide film. This is thought to be due to the high crystallinity of the aluminum oxide film. In each photograph of Figure 30, a coat layer is formed on the aluminum oxide film.

[0460] Next, an aluminum oxide film with a thickness of approximately 50 nm was formed on the glass substrate by sputtering in an oxygen-containing atmosphere, and then argon (Ar) was supplied to the aluminum oxide film using a plasma ion doping system. The acceleration voltage was 30 kV and the dose was 1 × 10. 16 ions / cm 2 It was decided.

[0461] Figure 29(B) shows the results of structural analysis using an XRD device. As indicated by the arrow in Figure 29(B), the peaks derived from Al2O3 crystals seen in Figure 29(A) were not observed. Furthermore, when the film density was measured using XRR, the film density of the aluminum oxide film supplied with argon was 2.45 g / cm3. 3 This shows that supplying argon can destroy the Al2O3 crystals and reduce the film density of the aluminum oxide film.

[0462] Next, the aluminum oxide film was wet-etched with argon using diluted hydrofluoric acid.

[0463] The bottom row of FIG. 30 shows cross-sectional observation photographs of a sample to which argon was supplied and which was not subjected to wet etching (no etching treatment) and a sample to which the treatment was performed (etching treatment).

[0464] As shown in the bottom of Figure 30, when argon was supplied to the aluminum oxide film, wet etching progressed and the aluminum oxide film on the glass was removed. This shows that supplying argon to the aluminum oxide film reduces its crystallinity, making it possible to wet-etch the aluminum oxide film.

[0465] [Etching of aluminum oxide films in laminated structures] Next, a stacked structure corresponding to the gate insulating layer 110, the metal oxide layer 114f (aluminum oxide film), and the gate electrode 112 was formed on a glass substrate, and the aluminum oxide film was wet-etched. Two samples were fabricated.

[0466] First, a silicon oxynitride (SiON) film (corresponding to the gate insulating layer 110) is formed on a glass substrate, and then an aluminum oxide (AlO) film having a thickness of about 50 nm is deposited on the SiON film by sputtering in an oxygen-containing atmosphere. x ) film (corresponding to the metal oxide layer 114f) was formed.

[0467] Next, AlO x On the film, a molybdenum (Mo) film (corresponding to the gate electrode 112) was formed.

[0468] For one of the two samples, a Mo film was used as a mask, and an AlO x The film was supplied with argon (Ar). x The membrane was not supplied with argon.

[0469] Next, using the Mo film as a mask, AlO x The film was wet-etched using dilute hydrofluoric acid (DHF). The etching time was 30 seconds for the sample supplied with argon and 60 seconds for the sample not supplied with argon.

[0470] The top and bottom images of Figure 31 show cross-sectional observations of a sample without argon supply, respectively. The left side of Figure 31 shows a sample that has not been wet-etched (no etching), and the right side shows a sample that has been wet-etched (etched).

[0471] As shown in the upper part of Figure 31, AlO x In the film, AlO x It was confirmed that both the parts of the AlO film that overlapped with the Mo film and the parts that did not overlap remained. This means that wet etching did not proceed. On the other hand, as shown in the bottom of Figure 31, x In the film, AlO x The part of the film that did not overlap with the Mo film was removed, and AlO x It was confirmed that only the part of the film overlapping with the Mo film remained. x Wet etching progresses in the area of ​​the film where argon is supplied (the area that does not overlap with the Mo film), and AlO x It was found that the film was removed. x It was found that wet etching did not progress in the part of the film to which argon was not supplied (the part overlapping the Mo film).

[0472] From the above, we used a Mo film as a mask and x It was found that supplying argon to the film makes it possible to differentiate the etching rate between the area where argon is supplied (areas not overlapping with the Mo film) and the area where it is not supplied (areas overlapping with the Mo film). x Wet etching progresses in the area where argon is supplied (the area that does not overlap with the Mo film), and AlOx It was found that the film could be removed. [Explanation of symbols]

[0473] 100: transistor, 100A: transistor, 102: substrate, 103: insulating layer, 103d: region, 106: conductive layer, 106c: conductive layer, 108: semiconductor layer, 108c: semiconductor layer, 108n: low resistance region, 110: gate insulating layer, 110d: region, 112: gate electrode, 112f: conductive film, 114: metal oxide layer, 114f: metal oxide layer, 114g: metal oxide layer, 118: insulating layer, 120a: conductive layer, 120b: conductive layer, 130A: capacitance element, 130B: capacitance element, 140: impurity element, 141a: opening, 141b: opening, 142: opening, 143: impurity element, 400: pixel circuit, 400EL: pixel circuit, 400LC: pixel circuit, 401: circuit, 401EL: circuit, 401LC: circuit, 501: pixel circuit, 502: pixel unit, 504: drive circuit unit, 504a: gate driver, 504b: source driver, 506: protection circuit, 507: terminal unit, 550: transistor, 552: transistor, 554: transistor, 560: capacitance element, 562: capacitance element, 570: liquid crystal element, 572: light-emitting element, 700: display device, 700A: display device, 700B: display device, 701: first substrate, 702: Pixel section, 704: source driver, 705: second substrate, 706: gate driver, 708: FPC terminal section, 710: signal line, 711: wiring section, 712: sealing material, 716: FPC, 717: IC, 721: source driver IC, 722: gate driver, 723: FPC, 724: printed circuit board, 730: insulating film, 732: sealing film, 734: insulating film, 736: colored film, 738: light-shielding film, 740: protective layer, 741: protective layer, 742: adhesive layer, 743: resin layer, 744: insulating layer, 745: supporting substrate, 746: resin layer, 750: transistor, 752: transistor Transistor, 760: wiring, 770: planarization insulating film, 772: conductive layer, 773: insulating layer, 774: conductive layer, 775: liquid crystal element, 776: liquid crystal layer, 778: spacer, 780: anisotropic conductive film, 782: light emitting element, 786: EL layer, 788: conductive film, 790: capacitance element, 6000: display module, 6001: upper cover, 6002: lower cover, 6005: FPC, 6006: display device, 6009: frame, 6010: printed circuit board, 6011: battery, 6015: light emitting section, 6016: light receiving section, 6017a: light guiding section, 6017b: light guiding section, 6018: light,6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television device ,7101: Housing, 7103: Stand, 7111: Remote control device, 7200: Notebook personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 8000: Camera, 800 1: Housing, 8002: Display, 8003: Operation buttons, 8004: Shutter button, 8006: Lens, 8100: Viewfinder, 8101: Housing, 8102: Display, 8103: Buttons, 8200: Head-mounted display, 8201: Wearing part, 8202: Lens, 8203: Main body, 8204: Display, 8205: Cable, 8206: Battery, 8300: Head-mounted display, 8301: Housing, 8302 : Display unit, 8304: Fixing device, 8305: Lens, 9000: Housing, 9001: Display unit, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Portable information terminal, 9102: Portable information terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

[Claim 1] A method for manufacturing a semiconductor device comprising forming a first semiconductor layer and a second semiconductor layer; forming a first insulating layer having a function as a gate insulating layer above the first semiconductor layer and above the second semiconductor layer; forming a metal oxide layer above the first insulating layer, the metal oxide layer having an area overlapping with each of the first semiconductor layer and the second semiconductor layer via the first insulating layer; After forming the metal oxide layer, a heat treatment is performed, After the heat treatment, a gate electrode is formed above the metal oxide layer, the gate electrode having a region overlapping with a part of the first semiconductor layer via the metal oxide layer and the first insulating layer; supplying a first element to the first semiconductor layer through the gate electrode, the metal oxide layer, and the first insulating layer, and supplying the first element to the second semiconductor layer through the metal oxide layer and the first insulating layer; supplying a second element to at least the metal oxide layer through the gate electrode after supplying the first element; After supplying the second element, the metal oxide layer is etched using the gate electrode as a mask to form an island-shaped metal oxide layer; forming a second insulating layer above the gate electrode and above the first insulating layer after forming the island-shaped metal oxide layer; forming a first conductive layer above the second insulating layer and electrically connected to the first semiconductor layer; The metal oxide layer is formed in an atmosphere containing oxygen, the first element is phosphorus, boron, magnesium, aluminum, or silicon; the second element is silicon, phosphorus, argon, krypton, xenon, arsenic, gallium, or germanium; the first conductive layer has a region overlapping the second insulating layer and the second semiconductor layer via the first insulating layer; A method for manufacturing a semiconductor device, wherein each of the first conductive layer and the second semiconductor layer functions as a capacitor electrode.

Images