Electronic Packages and Systems

Abstract

To provide an electronic package with PHY-less die-to-die IO interconnects, having various bump pitches utilizing PHY-less designs.SOLUTION: An electronic package 300 being a multi-die package with interconnects between dies comprises a package substrate 382, and a first die 3301 over the package substrate. The first die 3301 comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. The electronic package 300 further comprises a second die 3302 over the package substrate. The second die 3302 comprises a second IO bump map. Bumps of the second IO bump map have a second pitch that is different than the first pitch. The electronic package comprises interconnects 341 between the first IO bump map and the second IO bump map. The interconnects are on a bridge 340.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to semiconductor devices, and more particularly, to electronic packages having PHY-less inter-die IO interconnects. [Background technology]

[0002] Die disaggregation into multiple chiplets is a growing trend in the semiconductor manufacturing industry to provide increased functionality, improved performance, and improved outcomes at advanced processing nodes. Die disaggregation requires that the individual chiplets can communicate with each other through input / output (IO) bumps. Depending on the interconnect density and bump pitch required, the channels may be implemented in different architectures. For example, C4 bumps may utilize channels in a standard package substrate. At more advanced technology nodes, microbumps may be used in conjunction with channels implemented in an embedded bridge die.

[0003] Currently, IOs are designed at the physical layer (PHY). This process results in a need for hard IP (HIP) to be custom designed for each IO region. Thus, designing different chiplets involves significant circuit design effort and silicon risk. The need for custom HIP in PHY-based designs also limits the portability needed for easy scaling to support different packaging technologies. Furthermore, there is a lack of interoperability between PHY-based designs with different bump pitches. [Brief description of the drawings]

[0004] [Figure 1A] FIG. 2 is a plan view of a portion of a die having IOs implemented in the PHY layer.

[0005] [Figure 1B] FIG. 1 illustrates a plan view of a portion of a die having IO implemented on a PHY-less layer in accordance with an embodiment.

[0006] [Figure 2A] FIG. 13 is a plan view of an IO bump map for a transmit region and a receive region having a first bump pitch, according to an embodiment.

[0007] [Figure 2B] FIG. 13 is a plan view of an IO bump map for transmit and receive regions having a second bump pitch, according to an embodiment.

[0008] [Figure 2C] FIG. 13 is a plan view of an IO bump map for transmit and receive regions having a third bump pitch, according to an embodiment.

[0009] [Figure 3A] 1 is a cross-sectional view of an electronic package having a die communicatively coupled through a bridge in the electronic package according to an embodiment.

[0010] [Figure 3B] FIG. 13 is a schematic plan view illustrating a channel through bridge between IO bump maps having the same bump pitch, according to an embodiment.

[0011] [Figure 3C] FIG. 13 is a schematic plan view illustrating a channel through bridge between IO bump maps having different pitches, according to an embodiment.

[0012] [Figure 3D] 1 is a cross-sectional view of an electronic package having a die communicatively coupled through a package substrate according to an embodiment.

[0013] [Figure 3E] 1 is a schematic plan view illustrating channels through a package substrate between IO bump maps having different pitches, according to an embodiment.

[0014] [Figure 4A]4A-4C are a top view and a cross-sectional view of a bridge providing a channel between the bump maps, according to an embodiment;

[0015] [Figure 4B] 2A-2C are cross-sectional views of a package substrate providing a channel between the bump maps and a top view of a pair of bump maps according to an embodiment.

[0016] [Figure 4C] FIG. 4C is a plan view of the intralayer routing of the package substrate in FIG. 4B with selected power and ground pads reduced, according to an embodiment.

[0017] [Figure 5A] 1 is an eye diagram illustrating crosstalk present in a standard package channel when using a PHY-less architecture, according to an embodiment.

[0018] [Figure 5B] 4 is an eye diagram illustrating the reduction in crosstalk provided when a leadway is provided between a channel and a receiving circuit, according to an embodiment.

[0019] [Figure 5C] FIG. 13 is a plan view of a bump map in which a transmit circuit is located below a transmit bump and a receive circuit is connected to the receive bump by a leadway, according to an embodiment.

[0020] [Figure 6] 1 is a schematic diagram of a computing device constructed in accordance with an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Described herein is an electronic package with PHY-less die-to-die IO interconnect, according to various embodiments. In the following description, various aspects of an exemplary implementation are described using terms commonly employed by those skilled in the art to convey the essence of their operation to others skilled in the art. However, it will be apparent to one skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the exemplary implementation. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the exemplary implementation.

[0022] Various operations are described sequentially as multiple separate operations in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order presented.

[0023] As mentioned above, die disaggregation creates the challenge of providing IO channels between chiplets. Currently, IO between chiplets is implemented using dedicated hard IP (HIP) PHYs. HIP PHYs require a traditional level of customization and manual design. This increases the design cost of new chiplets, especially when scaling to more advanced processing nodes. Furthermore, current PHY layers are not interoperable with each other. That is, a chiplet with an IO bump map with a first pitch cannot easily be mated with a chiplet with an IO bump map with a second pitch.

[0024] An example of a PHY-based IO bump area is shown in FIG. 1A, which is a macro view of IO area 180 and logic area 185 of die 100. The view shown in FIG. 1A is after bump removal. As shown, IO area 180 includes a regular repeating pattern of blocks 181 / 182. The regular repeating pattern represents a manually designed bump area. In contrast, logic area 185 can be seen to be a monolithic structure representing logic and routing designed using an automated placement and routing tool.

[0025] Thus, embodiments disclosed herein include the use of PHY-less IO bump maps and circuit / floorplan placement. In embodiments, interoperability is provided by maintaining the width of the IO bump map along the edge of the die (i.e., the shoreline width) uniform among IO bump maps with various bump pitches. The depth of a given IO bump map into the die may vary while maintaining the same shoreline width. In this manner, a consistent number of signaling bumps may be provided for IO bump maps with different bump pitches.

[0026] Furthermore, PHY-less design eliminates the need for custom HIP for each device. For example, the IO circuits of a chiplet are primarily composed of digital cells from standard libraries. These cells can be easily taped out by a digital design flow to minimize circuit design effort and silicon risk.

[0027] An example of PHY-less IO bump area 187 is shown in FIG. 1B, which is a macro view of IO area 187 and logic area 185 of die 100. The view shown in FIG. 1B is after bump removal. As shown, there is no discernible repeating pattern in IO area 187. This shows IO area 187 as designed by an automated place and route tool.

[0028] 2A, a plan view of an IO bump map 250 according to an embodiment is shown. In the illustrated embodiment, a transmission region T X and the receiving region R X A transmission area T X is located along the die edge 220 and has a receiving area R X is the transmission area T X 2A ). In an embodiment, IO bump map 250 may have signaling bumps 253, power bumps 254, and ground bumps 255. Bumps 253, 254, 255 may be arranged in a hexagonal pattern. However, in different embodiments, other bump layout patterns may be used.

[0029] In the embodiment, the bumps 253, 254, 255 are spaced apart from each other at a pitch P 1 The pitch P 1 is measured in a direction perpendicular to the die edge 220. The bumps 253, 254, 255 have a pitch P 2 The pitch P 1 and pitch P 2 may be different in some embodiments. In other embodiments, the pitch P 1 and pitch P 2 may be substantially similar to each other. 1 may be 55 μm, and the pitch P 2 may be 98 μm.

[0030] In the embodiment, the transmission region T X and the receiving region R X 2A , each row has ten signaling bumps 253 and each column has twelve signaling bumps 253. 1-5 and 6 rows 251 1-6, providing a total of 60 signaling bumps 253. However, it will be recognized that the 60 signaling bumps 253 are exemplary in nature, and that scaling efforts such as those disclosed herein may place any number of signaling bumps 253 in the bump map 250 (and any number of signaling bumps 253 in each of the rows 251 and / or columns 252).

[0031] In an embodiment, the bump map 250 has a shoreline width W along the die edge 220. 1 In an embodiment, the transmission region T X is the depth D in the die. 1 The receiving area R X Also, the same depth D 1 The first pitch P 1 The depth D is 412.5 μm. 1 and the second pitch P 2 is the shoreline width W of about 490 μm 1 In an embodiment, the ratio of signaling bumps 253 to power bumps 254 and ground bumps 255 is 4:1.

[0032] As shown in FIG. 2B, interoperability between bump maps 250 with different pitches requires a consistent number of signaling bumps 253 and a uniform shoreline width W 1 2B, a plan view of a bump map 250 according to an additional embodiment is shown. In an embodiment, the bump map 250 of FIG. 2B has a third pitch P 3 and the fourth pitch P 4 The third pitch P 3 is measured perpendicular to the die edge 220, and the fourth pitch P 4 is measured parallel to the die edge 220. In an embodiment, the third pitch P 3 is the first pitch P 1 The fourth pitch P may be smaller. 4 is the second pitch P 2 For example, the first pitch P1 When is 55 μm, the third pitch P 3 may be 36 μm, and the second pitch P 2 When is 98 μm, the fourth pitch P 4 may be 65.3 μm.

[0033] However, the number of signaling bumps 253 in FIG. 2B and the shoreline width W in FIG. 2 is the number of signaling bumps 253 in FIG. 2A and the shoreline width W in FIG. 1 A consistent number of signaling bumps 253 and a uniform shoreline width W is achieved by increasing the number of columns 252 and decreasing the number of rows 251 in the bump map 250 of FIG. 2B. For example, the bump map 250 in FIG. 2B has 7.5 columns 252. 1-7.5 and 4 rows 251 1-4 By reducing the number of rows 251, the depth D of the bump map 250 in FIG. 2 is reduced compared to bump map 250 of FIG. 2A.

[0034] 2A illustrates a minimum bump pitch of 55 μm and FIG. 2B illustrates a minimum bump pitch of 36 μm, it will be appreciated that it is also possible to scale to different bump pitches while maintaining a uniform shoreline width and number of signaling bumps 253. For example, a minimum bump pitch of 45 μm and a minimum bump pitch of 25 μm may also have bump maps 250 that are interoperable with each other. A minimum bump pitch of 45 μm may have 6 columns 252 and 5 rows 253, and a minimum bump pitch of 25 μm may have 10 columns and 3 rows 253. It will be appreciated that a minimum bump pitch greater than 55 μm and less than 25 μm may also be provided while maintaining a uniform shoreline width and number of signaling bumps.

[0035] Interoperable bump map 250 may also be provided on conventional C4 bumps. Such an embodiment is shown in FIG. 2C. In an embodiment, C4 signaling bumps 253 are arranged at a fifth pitch P of about 110 μm perpendicular to die edge 220. 5 and a sixth pitch P of 196 μm parallel to the die edge 220 6 The larger bump pitch P 5 and P 6 reduces the number of signaling bumps 253 that can be included in the bump map 250. For example, 12 signaling bumps 253 are included in the bump map 250. X Area and R X The shoreline width W 3 is the shoreline width W in Figures 2A and 2B 1 and / or W 2 That is, in some embodiments, the shoreline width W 3 In an embodiment, T X Area and R X The depth D of each region 3 may be about 412.5 μm.

[0036] 3A, a cross-sectional view of an electronic package 300 is shown, according to an embodiment. In an embodiment, electronic package 300 may have a package substrate 382 attached to a board 380 (e.g., a motherboard) by interconnects 383. In an embodiment, interconnects 383 are shown as solder balls. However, it will be appreciated that interconnects 383 may have any suitable interconnect architecture (e.g., sockets, etc.).

[0037] In an embodiment, the package substrate 382 has a layer of insulating material surrounding the conductive traces (not shown). In an embodiment, the package substrate 382 may be a cored substrate or a coreless substrate. In an embodiment, the bridge 340 is embedded in the package substrate 382. The bridge 340 is connected to the first die 330. 1 The second die 330 2341 to communicatively couple to the bridge 340. For example, the bridge 340 may comprise silicon with a metal layer disposed in a back end region.

[0038] In an embodiment, the first die 330 1 and a second die 330 2 The first die 330 may be any type of semiconductor device. For example, the first die 330 1 and a second die 330 2 may be a processor (e.g., CPU, GPU), memory, a system on a chip (SoC), etc. In some embodiments, the first die 330 1 and a second die 330 2 In another embodiment, the first die 330 1 The second die 330 2 In some embodiments, the first die 330 may be a different type of die. 1 The minimum pitch of the bumps 353 on the second die 330 2 The minimum pitch of the bumps 353 on the first die 330 may be different from that of the bumps 353 on the first die 330. 1 The bump map of the second die 330 2 The bump maps may be interoperable with the bump maps of the previous example.

[0039] Referring now to FIG. 3B, a second die 330 according to an embodiment 2 a first die 330 communicatively coupled to the 1 3 shows a schematic plan view of a first die 330. 1 is the first bump map 350 1 and a second die 330 2 is the second bump map 350 2 The first bump map 350 1 is T X area 355 1 and R X area 356 1 T X area 3551 The first die 330 1 The second bump map 350 is located close to the edge of the 2 is T X area 355 2 Pairs of and R X area 356 2 T X area 355 2 One of the die 330 2 The die edge is located close to the edge of the die. X and R X This eliminates the need to create a different design with the T X In region 355, R is located deeper within die 330. X Providing region 356 simplifies the design effort. As shown, T X area 355 1 and T X area 355 2 The shoreline widths W of the two are equal to each other.

[0040] In the illustrated embodiment, three modules are included on each die (i.e., the first die 330 1 T in X area 355 1 and R X area 356 1 Pair of second die 330 2 T in X area 355 2 Pairs of and R X area 356 2 3B). However, it will be appreciated that any number (i.e., one or more) of modules may be provided along the die edge. Additional modules may be laterally adjacent to the module shown in FIG. 3B to provide additional bandwidth.

[0041] In an embodiment, T X Region 355 is connected to R on the opposite die 330 by channel 341 in bridge 340. X 356. For example, TX area 355 1 R by channel 341 X area 356 2 and each T X area 355 2 R varies by channel 341 X area 356 1 is combined with

[0042] 3C, a schematic plan view of an electronic package 300 according to an additional embodiment is shown. In FIG. 1 is the T having the first bump pitch X area 355 1 and R X area 356 1 A first bump map 350 having 1 and a second die 330 2 T with the second bump pitch X area 355 2 and R X area 356 2 A second bump map 350 having 2 Despite the difference in bump pitch, the first bump map 350 1 and a second bump map 350 2 include a uniform shoreline width W, and thus are able to communicate with each other through bridge 340. X area 355 1 is connected to the second R by channel 341 in bridge 340. X area 356 2 and a second T X area 355 2 is connected to the first R X area 356 1 may be communicatively coupled to

[0043] In an embodiment, the first bump map 350 1 may be similar to bump map 250 in FIG. 2A, and a second bump map 350 2may be similar to bump map 250 in FIG. 2B. That is, first bump map 350 1 The minimum bump pitch in the second bump map 350 may be 55 μm. 2 The minimum bump pitch in the first bump map 350 may be 36 μm. 1 and a second bump map 350 2 It will be appreciated that the minimum bump pitch may be any value as long as the shoreline width W remains the same.

[0044] Referring now to Figure 3D, a cross-sectional view of an electronic package 300 according to an additional embodiment is shown. The electronic package 300 in Figure 3D is similar to the electronic package 300 in Figure 3A, except that the bridge 340 is omitted. Instead, the channel 341 is on (or embedded in) the package substrate. Such an electronic package 300 is suitable for a die 330 having a standard C4 bump pitch. That is, the minimum pitch of the bumps 353 may be 110 μm.

[0045] 3E, a schematic top view of the electronic package 300 of FIG. 3D is shown, according to an embodiment. As shown, T X and R X The modular design of the region allows for circuit reuse across different packaging technologies. For example, the first die 330 1 is T X area 355 1 and R X area 356 1 A first bump map 350 having 1 and the second die 330 2 is T X area 355 2 and R X area 356 2 A second bump map 350 having 2 The second bump map 350 may include 2 may have a minimum bump pitch of 110 μm suitable for use with C4 bumps.

[0046] A uniform shoreline width W results in a first bump map 350 1 The second bump map is 350 2 Interoperable with Bump Map 350 1 and 350 2 are compatible with each other, so the first bump map 350 1 The module bump map design may be modified such that for each module, 12 signals out of a total of 60 signals are assigned to the second bump map 350 (e.g., similar to the embodiment shown in FIG. 2C). 2 Thus, the first bump map 350 1 The only change to is a simple change in the far back end layer and bumps, i.e., the underlying circuitry can remain the same whether a 55 μm bump pitch or a 110 μm bump pitch is used.

[0047] 4A, a combined plan view and cross-sectional view of an electronic package 400 according to an embodiment is shown. In FIG. 4A, a first bump map 450 1 and a second bump map of 450 2 is provided in plan view, with the lower bridge 440 shown in cross section. 1 and a second bump map of 450 2 Each of T X Area and R X It may have a region. X Region (i.e., T X 1 and T X 2) is located along the die edge and R X The area (i.e., R X 1 and R X 2) are stacked within the die.

[0048] In the cross-sectional portion of FIG. 4A, a bridge 440 is shown having multiple metal layers M1-M4. A pair of channels 441 are shown within the bridge 440. X1 and R X 2. A first channel 441 between the bumps 453 in 1-2 is disposed on the first metal layer M1, and T X 2 and R X 1. A second channel 441 between the bumps 453 at 2-1 are located on the third metal layer M3. In an embodiment, the channels 441 within a module are matched in length to minimize skew between all data lanes and the clock. The inter-module channels are also matched. In the illustrated matched design, the channels 441 2-1 is the T in the M3 layer X 1 signal via landing. However, the high density routing design rules of the bridge architecture make such routing easily achievable.

[0049] 4B, a combined plan view and cross-sectional view of an electronic package 400 according to an additional embodiment is shown. In FIG. 4B, a first bump map 450 1 and a second bump map of 450 2 4 is provided in plan view, with the underlying package substrate 482 shown in cross section. 1 and a second bump map of 450 2 is shown as being suitable for C4 bumps (e.g., having a minimum bump pitch of 110 μm). In this manner, the channel 441 can be implemented with the channel 441 in a standard package substrate 482 without the need for a bridge.

[0050] The package substrate 482 may have multiple metal layers. For example, five metal layers L1-L5 are shown. Channel 441 1-2 is provided in the second metal layer L2, and the channel 441 2-1 is provided on the fourth metal layer L4. 1-2 and 441 2-14A. However, the design rules of the conventional package substrate 482 do not allow for easy routing. One solution is to use a T X 2 and R X 2 and swap the positions of the channels 441 and 442. 2-1 Channel 441 1-2 A solution would be to make the 128-bit ...

[0051] Thus, the embodiments disclosed herein provide a routing architecture that includes reduced power and ground pads in the second layer L2, 441 1-2 An example of such an embodiment is shown in FIG. 4C. In FIG. 4C, channel 441 1-2 4. A plan view of the second metal layer L2 is shown having a set of power pads 454 and ground pads 455. Some of the power pads 454 and ground pads 455 may be reduced as indicated by the circles with Xs in them. For example, if all of the power pads 454 and ground pads 455 are reduced to T X 2 regions. Some, but not all, of the power pads 454 and ground pads 455 are X 2 Region and T X In one embodiment, the first bump map 450 1 The edges of the 450 are given a second bump map 450 to simplify routing. 2 In the second metal layer L2, the T X Since all of the 1 signal is terminated, the channel 441 in the fourth metal layer L4 2-1 The routing may be done with minimal reduction.

[0052] 5A-5C, a pair of eye diagrams and plan views are provided illustrating equalization routing (i.e., leadways) according to an embodiment. To fully utilize the benefits of a PHY-less design, the transmit and receive circuits need to be simple. However, such circuits present challenges for both advanced package channels (e.g., channels above a bridge) and standard channels within a package substrate. As shown in the eye diagram of FIG. 5A, bridge channels exhibit strong RC behavior, while standard package channels exhibit strong reflections and amplified crosstalk. That is, it is difficult to use the same circuitry for both types of channels, especially with the simple driver circuitry of a PHY-less design.

[0053] Therefore, the embodiments disclosed herein provide a trace length of R X This involves adding on-die leadway routing on the module. Furthermore, the on-die leadway routing is X As shown in Figure 5B, the leadway routing is X As a result of adding this to the module, the eye diagram of a standard package channel is significantly smoothed.

[0054] 5C, a plan view of a bump map 550 according to an embodiment is shown. X Area and R X As shown in the figure, T X Bump 553 T is T X Located directly above circuit 571. X Circuits 571 are shown in dashed outline and are X Bump 553 T In contrast, R X The circuit 572 is R X Bump 553 R In an embodiment, R X The circuit 572 is R XThe leadways 575 are arranged in an array along the edge of the region. X Bump 553 R and R X Provides electrical coupling between the circuit 572. For example, R X Bump 553 R1 Leadway 575 1 By R X coupled to circuit 572, R X Bump 553 R2 Leadway 575 2 By R X coupled to circuit 572, R X Bump 553 R3 Leadway 575 3 By R X coupled to circuit 572, R X Bump 553 R4 Leadway 575 4 By R X is coupled to circuit 572.

[0055] In an embodiment, the leadway 575 may be implemented in a back-end metal layer of the die. In a specific embodiment, the leadway 575 is implemented in an M14 or M15 layer of the die below the bump layer. An embodiment may include a leadway 575 having any length to provide the required equalization. In some embodiments, the leadway 575 may have a length between 200 μm and 600 μm. For example, a leadway 575 of about 400 μm in the M15 layer may provide about 65 ohms to the channel.

[0056] Furthermore, the inclusion of leadways 575 has a minor impact on channels mounted above the bridge substrate. In this manner, the same circuitry may be utilized for both standard package substrate channels and advanced packaging architectures utilizing bridge substrates.

[0057] 6 illustrates a computing device 600 according to one implementation of the present invention. The computing device 600 houses a board 602. The board 602 may include a number of components, including, but not limited to, a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the board 602. In some implementations, the at least one communication chip 606 is also physically and electrically coupled to the board 602. In further implementations, the communication chip 606 may be part of the processor 604.

[0058] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0059] The communications chip 606 enables wireless communication for data transmission to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated device is completely wire-free, although in some embodiments this may not be the case. The communications chip 606 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The computing device 600 may include multiple communications chips 606. For example, a first communications chip 606 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and a second communications chip 606 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0060] The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of the invention, the processor's integrated circuit die may be part of an electronic package having a PHY-less IO bump map according to embodiments described herein. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory.

[0061] The communications chip 606 also includes an integrated circuit die packaged within the communications chip 606. According to other implementations of the invention, the integrated circuit die of the communications chip may be part of an electronic package having a PHY-less IO bump map according to embodiments described herein.

[0062] The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations and examples for the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the art will recognize.

[0063] These variations may be made to the present invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and claims. Rather, the scope of the invention should be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0064] Example 1: An electronic package comprising: a package substrate; a first die above the package substrate, the first die having a first IO bump map, the bumps of the first IO bump map having a first pitch; a second die above the package substrate, the second die having a second IO bump map, the bumps of the second IO bump map having a second pitch different from the first pitch; and an interconnect between the first IO bump map and the second IO bump map.

[0065] Example 2: The electronic package of Example 1, wherein the first bump map has a first width along an edge of the first die and the second bump map has a second width along an edge of the second die, the first width matching the second width.

[0066] Example 3: The electronic package of Example 1 or Example 2, wherein the first bump map has a first depth within the first die and the second bump map has a second depth within the second die, the first depth being different from the second depth.

[0067] Example 4: The electronic package of Examples 1-3, wherein the interconnect is within a package substrate.

[0068] Example 5: The electronic package of Examples 1-3, further comprising a bridge, the interconnect being on the bridge.

[0069] Example 6: The electronic package of Examples 1-5, wherein the first pitch is about 55 μm or greater and the second pitch is about 55 μm or less.

[0070] Example 7: The electronic package of Examples 1-6, wherein the second pitch is about 45 μm, about 36 μm, or about 25 μm.

[0071] Example 8: An electronic package as described in Examples 1-7, wherein a first bump map has a first number of signal bumps and a second bump map has a second number of signal bumps, the first number of signal bumps being equal to the second number of signal bumps.

[0072] Example 9: The electronic package of example 8, wherein the first number of signal bumps is 60.

[0073] Example 10: The electronic package of Examples 1-9, wherein the first bump map has a first transmitting area and a first receiving area, the first transmitting area being along an edge of the first die, and the second bump map has a second transmitting area and a second receiving area, the second transmitting area being along an edge of the second die.

[0074] Example 11: An electronic package comprising: a package substrate having multiple metal layers embedded therein, where a first metal layer, a third metal layer, and a fifth metal layer are power and / or ground layers, and a second metal layer and a fourth metal layer are signaling layers; a first die above the package substrate, the first die having a first bump map having a first transmitting area and a first receiving area; and a second die above the package substrate, the second die having a second bump map having a second transmitting area and a second receiving area, wherein the first transmitting area is electrically coupled to the second receiving area by a channel in the second metal layer and the second transmitting area is electrically coupled to the first receiving area by a channel in the fourth metal layer.

[0075] Example 12: The electronic package of example 11, wherein the set of power pads and the set of ground pads are subtracted from the second metal layer.

[0076] Example 13: The electronic package of example 12, wherein the reduced set of power pads and reduced ground pads includes all of the power pads and all of the ground pads below the second transmission region.

[0077] Example 14: The electronic package of example 12, wherein none of the power pads are subtracted from the fourth metal layer and none of the ground pads are subtracted from the fourth metal layer.

[0078] Example 15: The electronic package of Examples 11-15, wherein an edge of the first bump map is offset from an edge of the second bump map.

[0079] Example 16: The electronic package of Example 15, wherein the first bump map has a first width along an edge of the first die and the second bump map has a second width along the edge of the second die, the first width being equal to the second width.

[0080] Example 17: The electronic package of Examples 11-16, wherein the channel in the second metal layer and the channel in the fourth metal layer have the same length.

[0081] Example 18: A semiconductor die comprising: a semiconductor substrate having an IO transmitting area having a plurality of transmitting circuits and an IO receiving area having a plurality of receiving circuits; a plurality of metal layers above the semiconductor substrate; a plurality of first bumps above the IO transmitting area, where each of the transmitting circuits aligns with each of the first bumps; and a plurality of second bumps above the IO receiving area, where each of the receiving circuits does not align with each of the second bumps.

[0082] Example 19: The semiconductor die of Example 18, wherein each of the first bumps is electrically coupled to a respective transmitting circuit by a vertical interconnect through the multiple metal layers, and each of the second bumps is electrically coupled to a respective receiving circuit by a vertical interconnect and a horizontal leadway segment within the multiple metal layers.

[0083] Example 20: The semiconductor die of example 19, wherein the horizontal leadway segment has a length of about 200 μm or greater.

[0084] Example 21: The semiconductor die of Examples 18-20, wherein the horizontal leadway adds approximately 65 ohms to the electrical channel between the second bump and the receiving circuit.

[0085] Example 22: The semiconductor die of Examples 18-21, wherein the multiple receiver circuits are arranged in an array within the IO receive area.

[0086] Example 23: An electronic system comprising: a board; an electronic package coupled to the board; a first die above a package substrate, the first die having a first IO bump map, the bumps of the first IO bump map having a first pitch; a second die above the package substrate, the second die having a second IO bump map, the bumps of the second IO bump map having a second pitch different from the first pitch; and an interconnect between the first IO bump map and the second IO bump map.

[0087] Example 24: The electronic system of Example 23, wherein the first bump map has a first width along an edge of the first die and the second bump map has a second width along the edge of the second die, the first width matching the second width.

[0088] Example 25: An electronic package as described in Example 23 or Example 24, wherein the first bump map has a first depth within the first die and the second bump map has a second depth within the second die, the first depth being different from the second depth. [Other possible aspects] [Aspect 1] A package substrate; a first die above the package substrate, the first die having a first IO bump map, the bumps of the first IO bump map having a first pitch; a second die above the package substrate, the second die having a second IO bump map, the bumps of the second IO bump map having a second pitch different than the first pitch; an interconnection between the first IO bump map and the second IO bump map; 1. An electronic package comprising: [Aspect 2] The first bump map has a first width along an edge of the first die, and the second bump map has a second width along an edge of the second die, the first width matching the second width. 2. The electronic package of embodiment 1. [Aspect 3] The first bump map has a first depth within the first die and the second bump map has a second depth within the second die, the first depth being different from the second depth. 2. The electronic package of embodiment 1. [Aspect 4] The interconnect is in the package substrate. 2. The electronic package of embodiment 1. [Aspect 5] Further equipped with a bridge, The interconnect is on the bridge. 2. The electronic package of embodiment 1. [Aspect 6] The first pitch is about 55 μm or greater, and the second pitch is about 55 μm or less. 2. The electronic package of embodiment 1. [Aspect 7] The second pitch is about 45 μm, about 36 μm, or about 25 μm. 2. The electronic package of embodiment 1. [Aspect 8] The first bump map has a first number of signal bumps and the second bump map has a second number of signal bumps, the first number of signal bumps equal to the second number of signal bumps. 2. The electronic package of embodiment 1. [Aspect 9] The first number of signal bumps is 60. 9. The electronic package of embodiment 8. [Aspect 10] The first bump map above is A first transmission area; A first receiving area; having the first transmit region is along an edge of the first die; The second bump map above is A second transmission area; A second receiving area; having The second transmit region is along an edge of the second die. 2. The electronic package of embodiment 1. [Aspect 11] a package substrate having multiple metal layers embedded therein, the package substrate including a first metal layer, a third metal layer, and a fifth metal layer being power and / or ground layers, and a second metal layer and a fourth metal layer being signaling layers; a first die above the package substrate, the first die having a first bump map having a first transmit area and a first receive area; a second die above the package substrate, the second die having a second bump map having a second transmit area and a second receive area; Equipped with The first transmit region is electrically coupled to the second receive region by a channel in the second metal layer, and the second transmit region is electrically coupled to the first receive region by a channel in the fourth metal layer. Electronic package. [Aspect 12] A set of power pads and a set of ground pads are subtracted from the second metal layer. 12. The electronic package of embodiment 11. [Aspect 13] The reduced set of power pads and the reduced ground pads include all of the power pads and all of the ground pads below the second transmission area. 13. The electronic package of embodiment 12. [Aspect 14] None of the power pads are subtracted from the fourth metal layer, and none of the ground pads are subtracted from the fourth metal layer. 13. The electronic package of embodiment 12. [Aspect 15] The edges of the first bump map are offset from the edges of the second bump map. 12. The electronic package of embodiment 11. [Aspect 16] The first bump map has a first width along an edge of the first die, and the second bump map has a second width along an edge of the second die, the first width being equal to the second width. 16. The electronic package of embodiment 15. [Aspect 17] The channel in the second metal layer and the channel in the fourth metal layer have the same length. 12. The electronic package of embodiment 11. [Aspect 18] A semiconductor substrate, an IO transmit area having a plurality of transmit circuits; an IO receiving area having multiple receiving circuits; A semiconductor substrate having a plurality of metal layers over the semiconductor substrate; a plurality of first bumps above the IO transmit area, each transmit circuit aligned with each first bump; a plurality of second bumps above the IO receiving area, each receiving circuit not aligned with each second bump; 1. A semiconductor die comprising: [Aspect 19] Each of the first bumps is electrically coupled to a respective transmitting circuit by a vertical interconnect through the plurality of metal layers, and each of the second bumps is electrically coupled to a respective receiving circuit by a vertical interconnect and a horizontal leadway segment within the plurality of metal layers. 19. The semiconductor die of embodiment 18. [Aspect 20] The horizontal leadway segment has a length of about 200 μm or greater. 20. The semiconductor die of embodiment 19. [Aspect 21] 20. The semiconductor die of embodiment 19, wherein the horizontal leadway adds approximately 65 ohms to the electrical channel between the second bump and the receiving circuit. [Aspect 22] The plurality of receiving circuits are arranged in an array within the IO receiving area. 19. The semiconductor die of embodiment 18. [Aspect 23] Board and an electronic package coupled to the board; a first die above the package substrate, the first die having a first IO bump map, the bumps of the first IO bump map having a first pitch; a second die above the package substrate, the second die having a second IO bump map, the bumps of the second IO bump map having a second pitch different than the first pitch; an interconnection between the first IO bump map and the second IO bump map; 1. An electronic system comprising: [Aspect 24] The first bump map has a first width along an edge of the first die, and the second bump map has a second width along an edge of the second die, the first width matching the second width. 24. The electronic system of claim 23. [Aspect 25] The first bump map has a first depth within the first die and the second bump map has a second depth within the second die, the first depth being different from the second depth. 24. The electronic package of embodiment 23.

Claims

1. A package substrate; a first die above the package substrate, the first die having a first IO bump map, first bumps of the first IO bump map having a first pitch; a second die above the package substrate, the second die having a second IO bump map, second bumps of the second IO bump map having a second pitch different than the first pitch; an interconnection between the first IO bump map and the second IO bump map; Equipped with the first IO bump map has a first width along a first edge of the first die and the second IO bump map has a second width along a second edge of the second die, the first width coinciding with the second width; the second pitch is smaller than the first pitch; the number of the second bumps is greater than the number of the first bumps; the first bumps and the second bumps are arranged in a matrix when viewed from above the package substrate; a number of columns in the second IO bump map that cross the second edge is greater than a number of columns in the first IO bump map that cross the first edge; the number of rows in the second IO bump map along the second edge is less than the number of rows in the first IO bump map along the first edge; Electronic package.

2. The first bump includes a plurality of first ground bumps, the second bumps include a plurality of second ground bumps; The number of the second ground bumps is greater than the number of the first ground bumps. The electronic package of claim 1 .

3. The first bump includes a plurality of first signaling bumps; the second bumps include a plurality of second signaling bumps; The number of the second signaling bumps is equal to the number of the first signaling bumps; 3. An electronic package according to claim 1 or 2.

4. The electronic package of claim 3, wherein the number of the first signaling bumps and the number of the second signaling bumps is 60.

5. The first bump includes a plurality of first power bumps; the second bumps include a plurality of second power bumps; a number of the second plurality of power bumps is greater than a number of the first plurality of power bumps; 5. An electronic package according to any one of claims 1 to 4.

6. A package substrate; a first die above the package substrate, the first die having a first IO bump map, first bumps of the first IO bump map having a first pitch; a second die above the package substrate, the second die having a second IO bump map, second bumps of the second IO bump map having a second pitch different than the first pitch; an interconnection between the first IO bump map and the second IO bump map; Equipped with the first IO bump map having a first transmission region; the second IO bump map having a second transmit region; the first transmit region is along a first edge of the first die; the second transmit region is along a second edge of the second die. Electronic package.

7. The first IO bump map further has a first receiving area; the second IO bump map further comprising a second receiving area; The electronic package of claim 6.

8. The first receiving area is disposed on an opposite side of the first transmitting area from the first edge in a first direction from the first die to the second die; the second receiving area is disposed on an opposite side of the second transmitting area from the second edge in a second direction from the second die to the first die.

8. The electronic package of claim 7.

9. The package substrate has, in a direction intersecting a top surface of the package substrate, a fourth metal layer, a third metal layer, a second metal layer, and a first metal layer, in that order from the top surface; the first transmitting area and the second receiving area are electrically coupled by the first metal layer; the second transmitting area and the first receiving area are electrically coupled by the third metal layer; 9. An electronic package according to claim 7 or 8.

10. The first bump of the first transmitting area and the second bump of the second receiving area are electrically coupled by a first channel arranged in the first metal layer; the second bump of the second transmitting area and the first bump of the first receiving area are electrically coupled by a second channel disposed in the third metal layer; The length of the first channel is equal to the length of the second channel.

10. The electronic package of claim 9.

11. A package substrate; a first die above the package substrate, the first die having a first IO bump map, first bumps of the first IO bump map having a first pitch; a second die above the package substrate, the second die having a second IO bump map, second bumps of the second IO bump map having a second pitch different than the first pitch; an interconnection between the first IO bump map and the second IO bump map; Equipped with the first IO bump map has a first ground bump; the second IO bump map has a second ground bump; the first ground bump is along a first edge of the first die; the second ground bump is along a second edge of the second die. Electronic package.

12. The first IO bump map further includes a first signaling bump disposed on an opposite side of the first ground bump from the first edge in a first direction from the first die to the second die; the second IO bump map further includes a second signaling bump disposed on an opposite side of the second ground bump from the second edge in a second direction from the second die to the first die.

12. The electronic package of claim 11.

13. The first IO bump map further includes a first power bump disposed on an opposite side of the first signaling bump from the first ground bump in the first direction; the second IO bump map further includes a second power bump disposed on an opposite side of the second signaling bump from the second ground bump in the second direction.

13. The electronic package of claim 12.

14. The first IO bump map has a first width along the first edge and the second IO bump map has a second width along the second edge, the first width being equal to the second width.

14. An electronic package according to any one of claims 6 to 13.

15. An electronic package as described in any one of claims 6 to 14, wherein the second pitch is smaller than the first pitch.

16. The first IO bump map has a first depth within the first die and the second IO bump map has a second depth within the second die, the first depth being different from the second depth.

16. An electronic package according to any one of claims 1 to 15.

17. The interconnect is in the package substrate.

17. An electronic package according to any one of claims 1 to 16.

18. Further equipped with a bridge, The interconnect is on the bridge.

18. An electronic package according to any one of claims 1 to 17.

19. the first pitch is 55 μm or greater; 19. An electronic package according to any one of claims 1 to 18.

20. The second pitch is 45 μm, 36 μm, or 25 μm.

20. An electronic package according to any one of claims 1 to 19.

21. Board and an electronic package coupled to the board; a first die over a package substrate, the first die having a first IO bump map, first bumps of the first IO bump map having a first pitch; a second die above the package substrate, the second die having a second IO bump map, second bumps of the second IO bump map having a second pitch different than the first pitch; an interconnection between the first IO bump map and the second IO bump map; Equipped with the first IO bump map has a first width along a first edge of the first die and the second IO bump map has a second width along a second edge of the second die, the first width coinciding with the second width; the second pitch is smaller than the first pitch; the number of the second bumps is greater than the number of the first bumps; the first bumps and the second bumps are arranged in a matrix when viewed from above the package substrate; a number of columns in the second IO bump map that cross the second edge is greater than a number of columns in the first IO bump map that cross the first edge; the number of rows in the second IO bump map along the second edge is less than the number of rows in the first IO bump map along the first edge; Electronic system.

22. The first bump includes a plurality of first ground bumps, the second bumps include a plurality of second ground bumps; The number of the second ground bumps is greater than the number of the first ground bumps.

22. The electronic system of claim 21.

23. The first bump includes a plurality of first signaling bumps; the second bumps include a plurality of second signaling bumps; The number of the second signaling bumps is equal to the number of the first signaling bumps; 23. An electronic system according to claim 21 or 22.

24. The method of claim 20, wherein the first bump comprises a plurality of first power bumps; the second bumps include a plurality of second power bumps; a number of the second plurality of power bumps is greater than a number of the first plurality of power bumps; 24. An electronic system according to any one of claims 21 to 23.

25. The first IO bump map has a first depth within the first die and the second IO bump map has a second depth within the second die, the first depth being different from the second depth.

25. An electronic system according to any one of claims 21 to 24.

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