Integrated circuit element and method of manufacture thereof

Abstract

To provide an integrated circuit element, and a manufacturing method of the same.SOLUTION: An integrated circuit element comprises: a plurality of conductive lines being extended in a horizontal direction parallel to the main surface of a substrate, and alternately overlapped on the substrate along a vertical direction vertical to the main surface; a plurality of insulation films which is interposed between the plurality of conductive lines, respectively, and is extended in the horizontal direction; a channel film extended in the vertical direction in the plurality of conductive lines and a channel hole penetrating the plurality of insulation films; and a plurality of outer blocking dielectric films interposed between the plurality of conductive lines and the channel film in at least one part of the plurality of conductive lines. The width of each of the plurality of outer blocking dielectric films in the horizontal direction is wider towards the main surface.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present invention relates to an integrated circuit device and a method for manufacturing the same, and more particularly to an integrated circuit device having a non-volatile vertical memory device and a method for manufacturing the same. [Background technology]

[0002] In order to satisfy excellent performance and economical price, there is a demand for increasing the integration degree of integrated circuit devices. In particular, the integration degree of memory devices is an important factor that determines the product price. The integration degree of two-dimensional memory devices is mainly determined by the area occupied by unit memory cells, and is therefore greatly affected by the level of fine pattern formation technology. However, since fine pattern formation requires expensive equipment and the area of ​​a chip die is limited, the integration degree of two-dimensional memory devices is still limited even though it has increased. Therefore, a vertical memory device having a three-dimensional structure is required. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the technical concept of the present invention is to provide an integrated circuit device and a manufacturing method thereof, in which a blocking dielectric film is formed on both the inside and outside of a channel hole in a three-dimensional vertical memory device having a high aspect ratio.

[0004] The problems that the technical idea of ​​the present invention is intended to solve are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0005] An integrated circuit device according to the technical idea of ​​the present invention includes, on a substrate, a plurality of conductive lines extending in a horizontal direction parallel to a main surface of the substrate and overlapping each other along a vertical direction perpendicular to the main surface; a plurality of insulating films interposed between each of the plurality of conductive lines and extending in the horizontal direction; a channel film extending in the vertical direction within a channel hole penetrating the plurality of conductive lines and the plurality of insulating films; and a plurality of outer blocking dielectric films interposed between the plurality of conductive lines and the channel film in at least some of the plurality of conductive lines, wherein the horizontal width of each of the plurality of outer blocking dielectric films becomes wider as it approaches the main surface.

[0006] According to the technical idea of ​​the present invention, an integrated circuit device includes: a first stacked structure on a substrate, the first stacked structure including a plurality of first conductive lines extending in a first direction parallel to a main surface of the substrate and overlapping each other along a vertical direction perpendicular to the main surface; a second stacked structure on the first stacked structure, the plurality of second conductive lines extending in the first direction parallel to a main surface of the substrate and overlapping each other along a vertical direction perpendicular to the main surface; a channel film extending in the vertical direction within a channel hole penetrating the first stacked structure and the second stacked structure; and a plurality of outer blocking dielectric films interposed between the plurality of first conductive lines and the second conductive lines and the channel film in all of the plurality of first conductive lines and at least some of the plurality of second conductive lines, wherein a horizontal width of each of the outer blocking dielectric films becomes wider as it approaches the main surface.

[0007] The integrated circuit device according to the technical idea of ​​the present invention includes a substrate, a plurality of conductive lines extending in a horizontal direction parallel to a main surface of the substrate and overlapping each other along a vertical direction perpendicular to the main surface; a plurality of insulating layers interposed between the plurality of conductive lines and extending in the horizontal direction; a channel layer extending in the vertical direction within a channel hole penetrating the plurality of conductive lines and the plurality of insulating layers; a charge storage layer and a first blocking dielectric layer extending in an extension direction of the channel layer within the channel hole between the plurality of conductive lines and the channel layer; and a first blocking dielectric layer interposed between the plurality of conductive lines and the first blocking dielectric layer in at least some of the plurality of conductive lines. a plurality of second blocking dielectric layers interposed between the plurality of conductive lines and the insulating layers and between the plurality of conductive lines and the plurality of insulating layers, wherein a first width in the horizontal direction of the second blocking dielectric layer of an uppermost conductive line among the plurality of conductive lines operating as a memory cell, a second width in the horizontal direction of the second blocking dielectric layer of a lowermost conductive line among the plurality of conductive lines operating as a memory cell, and a third width in the horizontal direction of the second blocking dielectric layer of a central conductive line closest to the uppermost conductive line and the lowermost conductive line at an equal distance in the vertical direction, based on one of the channel holes, are wider than the first width and the second width is wider than the third width.

[0008] According to the technical concept of the present invention, a method for manufacturing an integrated circuit device includes the steps of: forming a structure in which a plurality of insulating films and a plurality of sacrificial films are stacked on a substrate; forming a channel hole penetrating the structure; forming a first blocking dielectric film, a charge storage film, and a tunneling dielectric film in the channel hole in that order; forming a channel film on the tunneling dielectric film in the channel hole; removing the plurality of sacrificial films to form conductive line spaces between the plurality of insulating films; forming a second blocking pre-dielectric film conformally covering an inner wall of the conductive line space; removing a portion of the second blocking pre-dielectric film to separate it into a plurality of second blocking dielectric films; and forming a conductive line filling the conductive line space, wherein a horizontal width of each of the plurality of second blocking dielectric films is wider as it approaches the substrate. [Brief description of the drawings]

[0009] [Figure 1] 1 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept; [Diagram 2] 1 is a plan view of an integrated circuit device according to an embodiment of the inventive concept; [Figure 3A] 3 is a cross-sectional view taken along line X1-X1' in FIG. 2. [Figure 3B] FIG. 3B is an enlarged cross-sectional view of the dotted line area indicated by BX1 in FIG. 3A. [Figure 3C] FIG. 3B is an enlarged cross-sectional view of the dotted line area indicated by BX2 in FIG. 3A. [Figure 3D] FIG. 3B is an enlarged cross-sectional view of the dotted line area indicated by BX3 in FIG. 3A. [Figure 3E] FIG. 3B is an enlarged cross-sectional view of the dotted line area indicated by BX4 in FIG. 3A. [Figure 4] 1 is an enlarged cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept; [Diagram 5] 1 is an enlarged cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept; [Figure 6]1 is an enlarged cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept; [Figure 7A] 1 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept; [Figure 7B] FIG. 7B is an enlarged cross-sectional view of the dotted line area indicated by BX1 in FIG. 7A. [Figure 7C] FIG. 7B is an enlarged cross-sectional view of the dotted line area indicated by BX3 in FIG. 7A. [Figure 8A] 1 is a plan view of an integrated circuit device according to an embodiment of the inventive concept; [Figure 8B] 8B is a cross-sectional view taken along the line K1-K1' in FIG. 8A. [Figure 8C] 8B is a cross-sectional view according to another embodiment of the present invention taken along the line K1-K1' of FIG. 8A. [Figure 9A] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 9B] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 9C] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 9D] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 9E] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 9F] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 9G] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 9H] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 9I] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 10A] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 10B] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 10C] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 11A] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 11B] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 11C] 1A to 1C are cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. [Figure 12] 1 is a block diagram of an integrated circuit device according to an embodiment of the inventive concept. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the accompanying drawings.

[0011] FIG. 1 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept.

[0012] Referring to FIG. 1, an equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure is illustrated.

[0013] The memory cell array MCA includes a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL (BL1, BL2, ..., BLm), a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. A plurality of memory cell strings MS are also formed between the plurality of bit lines BL (BL1, BL2, ..., BLm) and the common source line CSL.

[0014] Each of the memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and a number of memory cell transistors MC1, MC2, ..., MCn-1, MCn. The drain regions of the string select transistors SST are connected to bit lines BL (BL1, BL2, ..., BLm), and the source regions of the ground select transistors GST are also connected to a common source line CSL. The common source line CSL is also a region where the source regions of the ground select transistors GST are commonly connected.

[0015] The string selection transistor SST is also connected to a string selection line SSL, and the ground selection transistor GST is also connected to a ground selection line GSL. The memory cell transistors MC1, MC2, ..., MCn-1, MCn are also connected to a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn), respectively.

[0016] FIG. 2 is a plan view showing an integrated circuit device according to an embodiment of the technical concept of the present invention, FIG. 3A is a cross-sectional view taken along line X1-X1' in FIG. 2, and FIGS. 3B to 3E are enlarged cross-sectional views of the dotted areas indicated by BX1 to BX4 in FIG. 3A, respectively.

[0017] 2 and 3A, an integrated circuit device 10 includes a substrate 102 having an active region AC, and a memory cell array MCA is formed on the active region AC of the substrate 102. The memory cell array MCA may have a circuit configuration as described with reference to FIG.

[0018] The substrate 102 may have a major surface 102M extending in an X-direction and a Y-direction. In some embodiments, the substrate 102 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). In other embodiments, the substrate 102 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0019] A plurality of conductive lines 160 extend along the XY plane on the substrate 102 in a horizontal direction parallel to the main surface 102M, and are arranged to be spaced apart from each other and overlap each other in the Z direction perpendicular to the main surface 102M of the substrate 102. A plurality of insulating films 110 also extend in the horizontal direction on the substrate 102. The insulating films 110 are interposed between the plurality of conductive lines 160, one at a time.

[0020] A plurality of channel holes CHH are formed through the plurality of conductive lines 160 and the plurality of insulating films 110, and a plurality of channel structures CHS are also extended in the vertical direction (Z direction) in the plurality of channel holes CHH. Each of the plurality of channel structures CHS may include a semiconductor pattern 120 in contact with the substrate 102 and partially filling the channel hole CHH, a channel film 150 in contact with the semiconductor pattern 120 and extending in the vertical direction (Z direction) in the channel hole CHH, a buried insulating film 156 filling an internal space of the channel film 150, and a drain region 158 in contact with the channel film 150 and filling an upper portion of the inlet side of the channel hole CHH.

[0021] Each of the plurality of channel holes CHH has a tapered shape in which the diameter becomes smaller toward the main surface 102M of the substrate 102. That is, the diameter of the top surface of the channel hole CHH is formed to be larger than the diameter of the bottom surface of the channel hole CHH. Such a phenomenon becomes more pronounced as the number of the plurality of conductive lines 160 and the plurality of insulating films 110 increases.

[0022] In some embodiments, the channel film 150 may have a cylindrical shape with an internal space, and the internal space of the channel film 150 may also be filled with a buried insulating film 156. The channel film 150 may also be composed of doped or undoped polysilicon. The buried insulating film 156 may also be composed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the buried insulating film 156 may be omitted, in which case the channel film 150 may have a pillar structure without an internal space. The drain region 158 may also be composed of doped polysilicon. The drain regions 158 may also be mutually insulated by an insulating pattern 114. The insulating pattern 114 may also be composed of an oxide, a nitride, or a combination thereof.

[0023] The plurality of channel structures CHS includes a plurality of gate insulating layers 140. Each of the plurality of gate insulating layers 140 may include a tunneling dielectric layer 145, a charge storage layer 143, and a first blocking dielectric layer 141 in this order from the channel layer 150.

[0024] The tunneling dielectric layer 145 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, aluminum oxide, and zirconium oxide.

[0025] The charge storage layer 143 may be a charge trapping layer or a floating gate conductive layer. When the charge storage layer 143 is a floating gate conductive layer, it may include, for example, polysilicon. When the charge storage layer 143 is a charge trapping layer, it may include at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, aluminum nitride, and aluminum gallium nitride.

[0026] The first blocking dielectric layer 141 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k material. The dielectric constant of the material included in the first blocking dielectric layer 141 is higher than the dielectric constant of the material included in the tunneling dielectric layer 145. The first blocking dielectric layer 141 is also referred to as an inner blocking dielectric layer because it is present inside the channel hole CHH.

[0027] The plurality of gate insulating layers 140 extend along a straight line extending away from the substrate 102 within the channel hole CHH, and the horizontal width of the plurality of gate insulating layers 140 becomes narrower as it approaches the main surface 102M of the substrate 102. That is, the tunneling dielectric layer 145, the charge storage layer 143, and the first blocking dielectric layer 141 constituting the plurality of gate insulating layers 140 may have the same tendency. For example, the horizontal width of the first blocking dielectric layer 141 becomes narrower as it approaches the main surface 102M of the substrate 102.

[0028] A second blocking dielectric layer 130 may be formed between each of the insulating layers 110 to cover a portion of the first blocking dielectric layer 141 and the conductive line 160. The second blocking dielectric layer 130 may be formed of substantially the same material as the first blocking dielectric layer 141. However, the etch rate of the second blocking dielectric layer 130 is different from that of the first blocking dielectric layer 141. That is, the density of the second blocking dielectric layer 130 is different from that of the first blocking dielectric layer 141. The second blocking dielectric layer 130 is also referred to as an outer blocking dielectric layer since it exists outside the channel hole CHH. The second blocking dielectric layer 130 will be described in detail later.

[0029] The widths of the conductive lines 160 and the insulating layers 110 in the first horizontal direction (X direction) are also defined by the word line cut regions WLC. The conductive lines 160 are also repeatedly arranged at regular intervals by the word line cut regions WLC.

[0030] In the substrate 102, a plurality of common source regions CSR are also extended along a second horizontal direction (Y direction). The plurality of common source regions CSR are also impurity regions doped with impurities at a high concentration. A portion of the plurality of word line cut regions WLC is also filled with a common source pattern CSP. The common source pattern CSP may constitute a common source line CSL exemplified in FIG. 1. The common source pattern CSP is also extended long in the second horizontal direction (Y direction) on the plurality of common source regions CSR.

[0031] An insulating spacer 170 may be formed in the word line cut region WLC to cover a sidewall of the common source pattern CSP. The insulating spacer 170 serves to electrically insulate the common source pattern CSP from the plurality of conductive lines 160. The common source pattern CSP and the insulating spacer 170 are also covered by a capping insulating film 172.

[0032] The common source pattern CSP may be made of a metal such as tungsten, copper, or aluminum; a conductive metal nitride such as titanium nitride or tantalum nitride; a transition metal such as titanium or tantalum; or a combination thereof. The insulating spacer 170 and the capping insulating film 172 may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. A metal silicide film (not shown) may be interposed between the common source region CSR and the common source pattern CSP to reduce contact resistance.

[0033] The conductive lines 160 between two adjacent word line cut regions WLC may constitute the ground selection line GSL, the word lines WL (WL1, WL2, ..., WLn-1, WLn), and the string selection line SSL described with reference to FIG. 1. The number of the conductive lines 160 stacked on the substrate 102 along the Z direction may be selected in various ways as necessary. For example, the conductive line 160 closest to the substrate 102 may constitute the ground selection line GSL. Also, the two conductive lines 160 farthest from the substrate 102 may constitute the string selection line SSL. The string selection line SSL may include a portion separated by the string selection line cut region SSLC. The string selection line cut region SSLC is also filled with an insulating film 184. The insulating film 184 may be composed of an oxide, a nitride, an air gap, or a combination thereof.

[0034] In the memory cell array MCA, a plurality of bit lines BL are also extended in a first horizontal direction (X direction) on the plurality of channel structures CHS. A plurality of bit line contact pads 182 are also interposed between the plurality of channel structures CHS and the plurality of bit lines BL. The drain region 158 of each of the plurality of channel structures CHS is also connected to a corresponding one of the plurality of bit lines BL through the bit line contact pad 182. The plurality of bit line contact pads 182 are also insulated from each other by an insulating film 180. The insulating film 180 may be composed of an oxide, a nitride, or a combination thereof.

[0035] 3B to 3E, the horizontal width of each of the second blocking dielectric layers 130 increases as it approaches the origin of the Z direction perpendicular to the major surface 102M of the substrate 102. FIG.

[0036] Each of the plurality of conductive lines 160 is also composed of a liner conductive film 161 and a central conductive film 163. The liner conductive film 161 may include a metal silicide, such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide. The central conductive film 163 may include a metal, such as tungsten, nickel, cobalt, or tantalum, or doped polysilicon.

[0037] The integrated circuit device 10 may include a plurality of second blocking dielectric layers 130 interposed between the plurality of conductive lines 160 and the first blocking dielectric layer 141 in at least some of the plurality of conductive lines 160. Specifically, the second blocking dielectric layer 130 is formed to abut a portion of the first blocking dielectric layer 141 between each of the plurality of insulating layers 110 and to surround the conductive lines 160. Each of the plurality of second blocking dielectric layers 130 has a horizontal width of about 100 nm or less, and preferably has a horizontal width of about 60 nm or less.

[0038] In some embodiments, the second blocking dielectric layer 130 is not formed on an upper conductive line 160 of the plurality of conductive lines 160. The second blocking dielectric layer 130 may have a second width 130W2 on an intermediate conductive line 160 of the plurality of conductive lines 160. The second blocking dielectric layer 130 may have a third width 130W3 on a lower conductive line 160 of the plurality of conductive lines 160. Here, the second width 130W2 is narrower than the third width 130W3.

[0039] The sum of the vertical thickness of one conductive line 160 and the vertical thickness of the second blocking dielectric film 130 surrounding it is also constant across the multiple conductive lines 160. Therefore, the horizontal width of each of the multiple second blocking dielectric films 130 becomes wider as it approaches the origin of the Z direction perpendicular to the main surface 102M of the substrate 102, and therefore the vertical thickness of the multiple conductive lines 160 becomes thinner as it approaches the origin of the Z direction perpendicular to the main surface 102M of the substrate 102.

[0040] In other words, among the plurality of conductive lines 160, the conductive line 160 located at the top may have a first thickness 160H1, the conductive line 160 located at the middle may have a second thickness 160H2, and the conductive line 160 located at the bottom may have a third thickness 160H3. Here, the first thickness 160H1 is thicker than the second thickness 160H2, and the second thickness 160H2 is thicker than the third thickness 160H3.

[0041] The second blocking dielectric layer 130 may be interposed between the semiconductor pattern 120 filling the bottom end of the channel hole CHH and the conductive line 160. That is, the semiconductor pattern 120 and the conductive line 160 may not directly contact each other but may be spaced apart by a certain distance. However, since the gate insulating layer 140 is not formed on the bottom end of the channel hole CHH where the semiconductor pattern 120 is formed, the second blocking dielectric layer 130 does not contact the first blocking dielectric layer 141.

[0042] As described above, the horizontal width of the first blocking dielectric film 141 becomes narrower as it approaches the origin of the Z direction perpendicular to the main surface 102M of the substrate 102. In addition, the material constituting the first blocking dielectric film 141 and the material constituting the second blocking dielectric film 130 are substantially the same. In other words, the narrower the horizontal width of the first blocking dielectric film 141, the wider the horizontal width of the second blocking dielectric film 130.

[0043] Generally, as the number of bits increases in a vertical NAND flash memory device, a difference in diameter of the channel hole occurs between the top and bottom. Therefore, it is very difficult in a manufacturing process to conformally form a gate insulating film, especially a blocking dielectric film at the outermost part, with the same width along the inner wall of a channel hole having a high aspect ratio and a difference in diameter. Therefore, the gate insulating film is formed relatively thick in the upper region of the channel hole and relatively thin in the lower region. As a result, a difference in speed occurs in reading / writing a program according to the word line, which causes a problem in the reliability of the integrated circuit device.

[0044] To solve this problem, the integrated circuit device 10 according to the technical concept of the present invention includes a second blocking dielectric layer 130 disposed between the conductive line 160 and the first blocking dielectric layer 141 to compensate for a thickness difference of the first blocking dielectric layer 141 that occurs during the manufacturing process. Here, the second blocking dielectric layer 130 is formed to have a wider width as it approaches the main surface 102M of the substrate 102. That is, in the integrated circuit device 10, the horizontal width for functioning as a blocking dielectric layer may be equal to or greater than a predetermined value across the entire conductive lines 160.

[0045] Ultimately, the integrated circuit device 10 according to the technical concept of the present invention provides consistent program read / write speeds for each word line, and has improved electrical characteristics and reliability.

[0046] 4-6 are enlarged cross-sectional views of integrated circuit devices according to embodiments of the inventive concept.

[0047] Most of the components and materials constituting the integrated circuit devices 20, 30, and 40 described below are substantially the same as or similar to those described above with reference to Figures 2 through 3E, and therefore, for ease of explanation, the following description will focus on the differences from the integrated circuit device 10 (Figure 3A) described above.

[0048] Referring to FIG. 4, an enlarged cross-sectional structure of a portion corresponding to the dotted line area indicated by BX1 in FIG. 3A is illustrated, and integrated circuit element 20 has generally the same structure as integrated circuit element 10 illustrated in FIG. 3A.

[0049] However, in the integrated circuit element 20, the second blocking dielectric film 130 is not formed on the uppermost conductive line 160 among the plurality of conductive lines 160, and in addition, the uppermost conductive line 160 may penetrate into a portion of the first blocking dielectric film 141 and have a convex sidewall 160S toward the channel film 150.

[0050] That is, in the integrated circuit device 20, the distance between the upper conductive line 160 and the channel film 150 is relatively closer than that of the integrated circuit device 10 illustrated in FIG. 3A.

[0051] Referring to FIG. 5, an enlarged cross-sectional structure of a portion corresponding to the dotted area indicated by BX1 in FIG. 3A is illustrated, and integrated circuit element 30 has generally the same structure as integrated circuit element 10 illustrated in FIG. 3A.

[0052] However, the integrated circuit device 30 may include a plurality of second blocking dielectric layers 130 interposed between the plurality of conductive lines 160 and the first blocking dielectric layer 141 for all of the plurality of conductive lines 160 .

[0053] That is, the second blocking dielectric layer 130 may be interposed in the uppermost conductive line 160 of the plurality of conductive lines 160, with the first width 130W1 being narrower than the second width 130W2 (FIG. 3C).

[0054] Referring to FIG. 6, an enlarged cross-sectional structure of a portion corresponding to the dotted line area indicated by BX4 in FIG. 3A is illustrated, and an integrated circuit element 40 has a configuration generally identical to that of the integrated circuit element 10 illustrated in FIG. 3A.

[0055] However, in the integrated circuit device 40 , a gate dielectric layer 132 is interposed between the conductive line 160 and the semiconductor pattern 120 filling the bottom end of the channel hole CHH, in addition to the second blocking dielectric layer 130 .

[0056] That is, the semiconductor pattern 120 and the conductive line 160 may be spaced apart from each other by a certain distance, but may not be in direct contact with each other. However, since the gate insulating film 140 is not formed on the bottom end of the channel hole CHH where the semiconductor pattern 120 is formed, the second blocking dielectric film 130 does not contact the first blocking dielectric film 141.

[0057] In addition, the gate dielectric layer 132 extends into a portion of the semiconductor pattern 120 and has a convex sidewall.

[0058] FIG. 7A is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept, and FIGS. 7B and 7C are enlarged cross-sectional views of dotted areas marked BX1 and BX3, respectively, of FIG. 7A.

[0059] Most of the components and materials constituting the integrated circuit device 50 described below are substantially the same as or similar to those described above with reference to Figures 2 through 3E, and therefore, for ease of explanation, the following description will focus on the differences from the integrated circuit device 10 (Figure 3A) described above.

[0060] 7A to 7C, an integrated circuit element 50 has a configuration generally identical to that of the integrated circuit element 10 illustrated in FIG. 3A, but in the integrated circuit element 50, the vertical thickness 160H of each of the multiple conductive lines 160 is the same.

[0061] The substrate 102 may include a plurality of second blocking dielectric films 130 interposed between the plurality of conductive lines 160 and the first blocking dielectric film 141, the horizontal width of which becomes wider as it approaches the origin of the Z direction, which is perpendicular to the main surface 102M of the substrate 102.

[0062] Therefore, the sum of the vertical thickness 160H of one conductive line 160 and the vertical thickness of the second blocking dielectric film 130 surrounding it becomes larger as it approaches the origin of the Z direction perpendicular to the main surface 102M of the substrate 102. Instead, the vertical thickness of the insulating films 110 becomes thinner as it approaches the origin of the Z direction perpendicular to the main surface 102M of the substrate 102.

[0063] In other words, in the plurality of insulating films 110, the insulating film 110 located at the top may have a first thickness 110H1, the insulating film 110 located at the middle may have a second thickness 110H2, and the insulating film 110 located at the bottom may have a third thickness 110H3. Here, the first thickness 110H1 is thicker than the second thickness 110H2, and the second thickness 110H2 is thicker than the third thickness 110H3.

[0064] FIG. 8A is a plan view showing an integrated circuit element according to an embodiment of the technical concept of the present invention, FIG. 8B is a cross-sectional view along line K1-K1' of FIG. 8A, and FIG. 8C is a cross-sectional view according to another embodiment of line K1-K1' of FIG. 8A.

[0065] Most of the components and materials constituting the integrated circuit device 60 described below are substantially the same as or similar to those described above with reference to Figures 2 through 3E, and therefore, for ease of explanation, the following description will focus on the differences from the integrated circuit device 10 (Figure 3A) described above.

[0066] First, referring to FIGS. 8A and 8B, an integrated circuit device 60 may include a first laminated structure 100 and a second laminated structure 200 on the first laminated structure 100. As shown in FIG.

[0067] The second stacked structure 200 is also formed such that a long axis of the second stacked structure 200 in a horizontal direction is parallel to a long axis of the first stacked structure 100 in a horizontal direction. The first stacked structure 100 and the second stacked structure 200 are stacked to expose the bit line contact pads 182. In the XY direction, the width of the first stacked structure 100 is wider than the width of the second stacked structure 200. A plurality of stacked structures are stacked such that their long axes are parallel to each other. Unlike the illustrated example, the plurality of stacked structures may have a shape in which three or more stacked structures are stacked.

[0068] The first laminated structure 100 may include a first conductive line layer P1 to a fifth conductive line layer P5, and the second laminated structure 200 may include a sixth conductive line layer P6 to a tenth conductive line layer P10, but this is merely an example and is not limited thereto.

[0069] Each of the first stacked structure 100 and the second stacked structure 200 has substantially the same structure as the integrated circuit element 10 (FIG. 3A). Before the second stacked structure 200 is formed, an interlayer insulating film PI may be formed on the first stacked structure 100. The interlayer insulating film PI may cover the insulating film 110 of the first stacked structure 100. The interlayer insulating film PI may expose upper surfaces of a plurality of first channel structures CHS1 through a planarization process.

[0070] A plurality of first channel structures CHS1 penetrating the first laminated structure 100 and a plurality of second channel structures CHS2 penetrating the second laminated structure 200 are provided. The plurality of second channel structures CHS2 are also formed to be connected to the plurality of first channel structures CHS1. In some embodiments, lower portions of the plurality of second channel structures CHS2 and upper portions of the plurality of first channel structures CHS1 are also formed to overlap. In addition, a diameter of an uppermost surface of the second channel structure CHS2 is larger than a diameter of a lowermost surface of the first channel structure CHS1.

[0071] In some embodiments, the horizontal width of each of the plurality of second blocking dielectric layers 130 across the first stacked structure 100 and the second stacked structure 200 may be wider as it approaches the origin of the Z direction perpendicular to the substrate 102 .

[0072] In the drawings, dotted areas indicated by BX1 to BX4 correspond to FIGS. 3B to 3E, respectively. That is, in the second stacked structure 200, the second blocking dielectric film 130 is not formed on the upper conductive line 160 of the plurality of conductive lines 160. In the second stacked structure 200, the second blocking dielectric film 130 may have a second horizontal width 130W2 on the conductive line 160 located at the middle end of the plurality of conductive lines 160. In the first stacked structure 100, the second blocking dielectric film 130 may have a third horizontal width 130W3 on the lower conductive line 160 of the plurality of conductive lines 160. Here, the second width 130W2 is narrower than the third width 130W3.

[0073] Next, referring to Figures 8A and 8C, the integrated circuit device 60 includes a first stacked structure 100 and a second stacked structure 200 on the first stacked structure 100, and may further include a polysilicon capping film PSC covering the top surface of the first channel structure CHS1.

[0074] The polysilicon capping film PSC may be disposed between the first channel structure CHS1 and the second channel structure CHS2, which is also a result of forming the second channel structure CHS2 after forming the first channel structure CHS1.

[0075] 9A through 9I are cross-sectional views illustrating a method for fabricating an integrated circuit device according to an embodiment of the inventive concept in a process sequence.

[0076] In this embodiment, an exemplary manufacturing method of the integrated circuit element 10 described with reference to Figures 2 to 3E will be described. Figures 9A to 9I show enlarged cross-sectional configurations of a portion corresponding to the dotted line region indicated by S1 in Figure 3A in a process sequence.

[0077] The method for manufacturing the integrated circuit device may include the following process steps. When an embodiment can be implemented differently, certain process steps may be performed out of the order described. For example, two steps described as successive may be performed substantially simultaneously, or may be performed in the reverse order from that described.

[0078] 9A, an active region AC is defined in a substrate 102, and a plurality of insulating films 110 and a plurality of sacrificial films 115 are stacked on the substrate 102 one by one.

[0079] Of the multiple insulating films 110, a lowest insulating film 110L in contact with the substrate 102 can have a thickness (D1) thinner than the other insulating films 110. The multiple insulating films 110 are made of silicon oxide, and the multiple sacrificial films 115 are also made of silicon nitride.

[0080] The plurality of sacrificial layers 115 each serve to provide a space for forming a ground selection line GSL, a plurality of word lines WL, and a plurality of string selection lines SSL in a subsequent process. Of the plurality of sacrificial layers 115, the first sacrificial layer 115 from the substrate 102 may provide a space for forming the ground selection line GSL. Of the plurality of insulating layers 110, the insulating layer 110 in contact with an upper surface of the first sacrificial layer 115 may have a thickness D2 that is thicker than the other insulating layers 110. The plurality of insulating layers 110 and the plurality of sacrificial layers 115 may each be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or an atomic layer deposition (ALD) process.

[0081] Referring to FIG. 9B, after forming an insulating pattern 114 on the top insulating film 110 of the plurality of insulating films 110, the insulating pattern 114 is used as an etching mask to etch the plurality of insulating films 110 and the plurality of sacrificial films 115 to form a channel hole CHH exposing the substrate 102.

[0082] The horizontal width CHHW of the channel hole CHH is also tapered, narrowing further closer to the substrate 102. The insulating pattern 114 may also be comprised of a single or multiple layers of oxide, nitride, or a combination thereof.

[0083] Referring to FIG. 9C, a semiconductor pattern 120 is partially filled in the channel hole CHH, and then a gate insulating film 140, a channel film 150 and a buried insulating film 156 are sequentially formed to form a drain region 158 that fills the upper portion of the inlet side of the channel hole CHH.

[0084] The gate insulating film 140 may also include a first blocking dielectric film 141, a charge storage film 143, and a tunneling dielectric film 145. In the channel hole CHH, the gate insulating film 140 and the channel film 150 may each have a cylindrical shape. In some embodiments, in the process of forming the channel film 150, the gate insulating film 140 may be penetrated and a portion of the upper surface of the semiconductor pattern 120 may be removed, so that a recessed surface 120R may be formed on the upper surface of the semiconductor pattern 120. Thus, the channel film 150 may contact the recessed surface 120R of the semiconductor pattern 120.

[0085] A deposition process and an etch-back process may be repeatedly performed to form the first blocking dielectric layer 141, the charge storage layer 143, the tunneling dielectric layer 145, the channel layer 150, and the buried insulating layer 156. The deposition process may be performed by a CVD, LPCVD (low pressure chemical vapor deposition) process, or an ALD process.

[0086] The first blocking dielectric layer 141 may also be made of silicon oxide, the charge storage layer 143 may also be made of silicon nitride, and the tunneling dielectric layer 145 may also be made of silicon oxide, i.e., the gate insulating layer 140 may have an oxide-nitride-oxide (ONO) structure.

[0087] The channel film 150 may also be composed of doped or undoped polysilicon. The buried insulating film 156 may also be composed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The drain region 158 may also be composed of doped polysilicon, metal, conductive metal nitride, or a combination thereof.

[0088] Referring to FIG. 9D, the insulating pattern 114, the insulating films 110, and the sacrificial films 115 are etched to form a word line cut region WLC that penetrates the insulating pattern 114, the insulating films 110, and the sacrificial films 115 and exposes the substrate 102, and then impurity ions are implanted into the substrate 102 through the word line cut region WLC to form a common source region CSR.

[0089] Referring to FIG. 9E, a plurality of sacrificial layers 115 are removed through the word line cut region WLC to form a plurality of conductive line spaces LS.

[0090] The sacrificial layers 115 are selectively removed by a wet etching process to provide a plurality of conductive line spaces LS between the insulating layers 110. A portion of the gate insulating layer 140 may be exposed through the conductive line spaces LS.

[0091] The process of forming the conductive line spaces LS may include a process of horizontally etching the sacrificial layers 115 using an etching recipe having an etching selectivity with respect to the insulating layer 110. For example, when the sacrificial layers 115 are silicon nitride and the insulating layer 110 is silicon oxide, the horizontal etching step may be performed using an etching solution containing phosphoric acid.

[0092] Referring to FIG. 9F, a second blocking preliminary dielectric layer 130P filling the conductive line space LS is formed on the resultant structure of FIG. 9E.

[0093] The second blocking preliminary dielectric film 130P is formed to conformally cover the surfaces exposed through the conductive line spaces LS and the word line cut regions WLC while filling the conductive line spaces LS. The second blocking preliminary dielectric film 130P may be formed by an ALD process, a CVD process, or a plasma oxidation process.

[0094] In some embodiments, a formation process having a relatively uniform step coverage, such as an ALD process, is used so that the second blocking pre-dielectric layer 130P is formed to substantially the same thickness in the different conductive line spaces LS.

[0095] Referring to FIG. 9G, a wet etching process is performed to remove a portion of the second blocking preliminary dielectric layer 130P (FIG. 9F), so that a second blocking dielectric layer 130 having a predetermined thickness is formed in the conductive line space LS.

[0096] In some embodiments, the second blocking pre-dielectric layers 130P (FIG. 9F) are etched differentially using an etching process having a relatively non-uniform etch distribution, e.g., a wet etching process, such that the second blocking pre-dielectric layers 130 are formed to different thicknesses in different conductive line spaces LS.

[0097] Since the etching solution used in the wet etching process permeates from a direction away from the substrate 102 to a direction closer to the substrate 102, the horizontal width of each of the multiple second blocking dielectric films 130 tends to become wider as it approaches the origin of the Z direction, which is perpendicular to the substrate 102.

[0098] At least some of the conductive line spaces LS may include a plurality of second blocking dielectric films 130. That is, in some embodiments, the second blocking dielectric film 130 is not formed in the conductive line spaces LS located at the upper ends of the conductive line spaces LS.

[0099] Referring to FIG. 9H, a plurality of conductive lines 160 are formed filling the plurality of conductive line spaces LS (FIG. 9G).

[0100] To this end, the spaces defined by the second blocking dielectric film 130 in the conductive line spaces LS (FIG. 9G) may be filled with a liner conductive film and a central conductive film through the word line cut regions WLC. The central conductive film may also be made of a metal, for example, tungsten. In the conductive line spaces LS (FIG. 9G), the sidewalls, bottom surface and top surface of the conductive line 160 are also covered by the second blocking dielectric film 130. Then, the conductive line 160 may be formed inside the remaining conductive line spaces LS (FIG. 9G).

[0101] Referring to FIG. 9I, an insulating spacer 170, a common source pattern CSP, and a capping insulating layer 172 are formed in the word line cut region WLC.

[0102] In some embodiments, to form the insulating spacer 170 in the word line cut region WLC, a spacer insulating film may first be formed to cover the inner wall of the word line cut region WLC, and then the spacer insulating film is etched back to expose the common source region CSR at the bottom surface of the word line cut region WLC, leaving the insulating spacer 170 on the inner sidewall of the word line cut region WLC.

[0103] To form the common source pattern CSP, a conductive material is formed inside and outside the word line cut region WLC so that the space defined by the insulating spacer 170 in the word line cut region WLC is filled with the conductive material, and then unnecessary portions of the conductive material can be removed by CMP (chemical mechanical polishing) or etch-back.

[0104] To form the capping insulating film 172, an insulating material is formed on the resultant structure on which the insulating spacer 170 and the common source pattern CSP are formed to fill the remaining space of the word line cut region WLC, and then a portion of the insulating material is removed by a CMP process or an etch-back process to expose the upper surface of the insulating pattern 114 and the upper surface of the drain region 158.

[0105] Then, as illustrated in FIG. 3A , an insulating film 180 is formed to cover the insulating pattern 114, the drain region 158, and the capping insulating film 172, and a portion of the insulating film 180, a portion of the insulating pattern 114, a portion of the insulating film 110, and a portion of the upper two word lines WL in the plurality of word lines WL are removed to form a string selection line cut region SSLC, and the string selection line cut region SSLC can be filled with an insulating film 184.

[0106] Finally, a plurality of bit line contact holes 180H penetrating a portion of the insulating film 180 are formed, a conductive material is filled in the plurality of bit line contact holes 180H to form a plurality of bit line contact pads 182, and a plurality of bit lines BL connected to the plurality of bit line contact pads 182 are formed on the insulating film 180, thereby manufacturing the integrated circuit element 10 illustrated in FIG. 3A.

[0107] 10A through 10C are cross-sectional views illustrating a method for fabricating an integrated circuit device according to an embodiment of the inventive concept in a process sequence.

[0108] Most of the manufacturing steps constituting the method for manufacturing an integrated circuit device described below are substantially the same as or similar to those described above with reference to Figures 9A to 9I, except for the method for forming the second blocking dielectric layer 130. Therefore, for ease of explanation, the differences from the above-described method for manufacturing an integrated circuit device will be mainly described.

[0109] Referring to FIG. 10A, a second blocking preliminary dielectric layer 130P filling the conductive line space LS is formed on the resultant structure of FIG. 9E.

[0110] The second blocking preliminary dielectric film 130P is formed to conformally cover the surfaces exposed through the conductive line spaces LS and the word line cut regions WLC while filling the conductive line spaces LS. The second blocking preliminary dielectric film 130P may be formed by an ALD process, a CVD process, or a plasma oxidation process.

[0111] In some embodiments, a formation process having relatively non-uniform step coverage, such as a plasma oxidation process, is used such that the second blocking pre-dielectric layer 130P is formed to different thicknesses in different conductive line spaces LS.

[0112] Referring to FIG. 10B, a dry etching process is performed to remove a portion of the second blocking preliminary dielectric layer 130P (FIG. 10A), so that a second blocking dielectric layer 130 having a predetermined thickness is formed in the conductive line space LS.

[0113] In some embodiments, the second blocking pre-dielectric layer 130P (FIG. 9F) is substantially uniformly etched using an etching process having a relatively uniform etch distribution, e.g., a dry etching process, such that the second blocking pre-dielectric layers 130 are formed to different thicknesses in different conductive line spaces LS.

[0114] Since the etching gas used in the dry etching process penetrates equally regardless of the distance from the substrate 102, the horizontal width of each of the multiple second blocking dielectric films 130 tends to become wider as it approaches the origin of the Z direction, which is perpendicular to the substrate 102.

[0115] At least some of the conductive line spaces LS may include a plurality of second blocking dielectric films 130. That is, in some embodiments, the second blocking dielectric film 130 is not formed in the conductive line spaces LS located at the upper ends of the conductive line spaces LS.

[0116] Referring to FIG. 10C, a plurality of conductive lines 160 are formed to fill the plurality of conductive line spaces LS (FIG. 10B).

[0117] To this end, the spaces defined by the second blocking dielectric layer 130 in the conductive line spaces LS (FIG. 10B) may be filled with a liner conductive layer and a central conductive layer through the word line cut regions WLC. The central conductive layer may also be made of a metal, for example, tungsten (W). In the conductive line spaces LS (FIG. 10B), the sidewalls, bottom surface and top surface of the conductive line 160 are also covered by the second blocking dielectric layer 130. And, the conductive line 160 may also be formed inside the remaining conductive line spaces LS (FIG. 10B).

[0118] 11A through 11C are cross-sectional views illustrating a method for fabricating an integrated circuit device according to an embodiment of the inventive concept.

[0119] Most of the manufacturing steps constituting the method for manufacturing an integrated circuit device described below are substantially the same as or similar to those described above with reference to Figures 9A to 9I, except for the method for forming the second blocking dielectric layer 130. Therefore, for ease of explanation, the differences from the above-described method for manufacturing an integrated circuit device will be mainly described.

[0120] Referring to FIG. 11A, a second blocking preliminary dielectric layer 130P filling the conductive line space LS is formed on the resultant structure of FIG. 9E.

[0121] The second blocking preliminary dielectric film 130P is formed to conformally cover the surfaces exposed through the conductive line spaces LS and the word line cut regions WLC while filling the conductive line spaces LS. The second blocking preliminary dielectric film 130P may be formed by an ALD process, a CVD process, or a plasma oxidation process.

[0122] In some embodiments, a formation process having relatively non-uniform step coverage, such as a plasma oxidation process, is used such that the second blocking pre-dielectric layer 130P is formed to different thicknesses in different conductive line spaces LS.

[0123] Referring to FIG. 11B, a wet etching process is performed to remove a portion of the second blocking preliminary dielectric layer 130P (FIG. 11A), so that a second blocking dielectric layer 130 having a predetermined thickness is formed in the conductive line space LS.

[0124] In some embodiments, the second blocking pre-dielectric layers 130P (FIG. 11A) are differentially etched using an etching process having a relatively non-uniform etch distribution, e.g., a wet etching process, such that the second blocking pre-dielectric layers 130 are formed to different thicknesses in different conductive line spaces LS.

[0125] Since the etching solution used in the wet etching process permeates from a direction away from the substrate 102 to a direction closer to the substrate 102, the horizontal width of each of the multiple second blocking dielectric films 130 tends to become wider as it approaches the origin of the Z direction, which is perpendicular to the substrate 102.

[0126] Among the plurality of conductive line spaces LS, the conductive line space LS located at the upper end may extend into a portion of the first blocking dielectric film 141 and have a convex sidewall toward the channel film 150 .

[0127] Referring to FIG. 11C, a plurality of conductive lines 160 are formed to fill the plurality of conductive line spaces LS (FIG. 11B).

[0128] To this end, the spaces defined by the second blocking dielectric layer 130 in the conductive line spaces LS (FIG. 11B) may be filled with a liner conductive layer and a central conductive layer through the word line cut regions WLC. The central conductive layer may also be made of a metal, for example, tungsten (W). In the conductive line spaces LS (FIG. 11B), the sidewalls, bottom surface and top surface of the conductive line 160 are also covered by the second blocking dielectric layer 130. And, the conductive line 160 may also be formed inside the remaining conductive line spaces LS (FIG. 11B).

[0129] The uppermost conductive line 160 of the plurality of conductive lines 160 may extend into a portion of the first blocking dielectric film 141 and have a convex sidewall 160 S facing the channel film 150 .

[0130] 12 is a block diagram of an integrated circuit device according to an embodiment of the technical concept of the present invention. Referring to FIG. 12, in an integrated circuit device 1200, a NAND cell array 1230 is also coupled to a core circuit unit 1210. For example, the NAND cell array 1230 may include the integrated circuit devices 10 to 60 described above. The core circuit unit 1210 may include a control logic 1211, a row decoder 1212, a column decoder 1213, a sense amplifier 1214, and a page buffer 1215.

[0131] The control logic 1211 may communicate with a row decoder 1212, a column decoder 1213, and a page buffer 1215. The row decoder 1212 may communicate with a NAND cell array 1230 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. The column decoder 1213 may communicate with the NAND cell array 1230 via a plurality of bit lines BL. The sense amplifier 1214 is connected to the column decoder 1213 when a signal is output from the NAND cell array 1230, and is not connected to the column decoder 1213 when a signal is transmitted to the NAND cell array 1230.

[0132] For example, the control logic 1211 transmits a row address signal to the row decoder 1212, which decodes the signal and transmits the row address signal to the NAND cell array 1230 via the string selection line SSL, the word line WL, and the ground selection line GSL. The control logic 1211 transmits a column address signal to the column decoder 1213 or the page buffer 1215, which decodes the signal and transmits the column address signal to the NAND cell array 1230 via the bit lines BL. The signal of the NAND cell array 1230 is transmitted to the sense amplifier 1214 via the column decoder 1213, amplified therein, and also transmitted to the control logic 1211 via the page buffer 1215.

[0133] Although the embodiments of the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art to which the present invention pertains can understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood to be illustrative and not restrictive in all respects. [Explanation of symbols]

[0134] 10,20,30,40,50,60 Integrated circuit elements 110 Insulating film 120 Semiconductor Pattern 130 Second blocking dielectric film 140 Gate insulating film 141 First blocking dielectric film 150 Channel Membrane 160 Conductive Line 100 First laminated structure 200 Second laminated structure

Claims

1. a plurality of conductive lines extending on a substrate in a horizontal direction parallel to a major surface of the substrate and overlapping each other along a vertical direction perpendicular to the major surface; a plurality of insulating layers interposed between the conductive lines and extending in the horizontal direction; a channel film extending in the vertical direction within a channel hole penetrating the plurality of conductive lines and the plurality of insulating films; a plurality of outer blocking dielectric films interposed between the plurality of conductive lines and the channel film in at least some of the plurality of conductive lines; The horizontal width of each of the outer blocking dielectric films is wider toward the major surface, The channel hole has a tapered shape with a diameter decreasing toward the main surface, an inner blocking dielectric layer extending along an extension direction of the channel layer between the plurality of conductive lines and the channel layer in the channel hole, An integrated circuit device, wherein the horizontal width of the inner blocking dielectric film decreases closer to the major surface.

2. 2. The integrated circuit device of claim 1, wherein the outer blocking dielectric layer is not interposed on the uppermost conductive line among the plurality of conductive lines.

3. 3. The integrated circuit device of claim 2, wherein the upper conductive line penetrates a portion of the inner blocking dielectric layer and has a convex sidewall toward the channel layer.

4. 2. The integrated circuit device of claim 1, wherein the vertical thickness of each of the plurality of conductive lines decreases toward the major surface.

5. 2. The integrated circuit device of claim 1, wherein the vertical thickness of each of the plurality of conductive lines is substantially the same as one another.

6. the material constituting the inner blocking dielectric film and the material constituting the outer blocking dielectric film are substantially the same; 2. The integrated circuit device of claim 1, wherein an etch rate of the inner blocking dielectric layer is different from an etch rate of the outer blocking dielectric layer.

7. a semiconductor pattern disposed on a lower end of the channel film and partially filling the channel hole; 2. The integrated circuit device of claim 1, wherein the outer blocking dielectric layer is interposed between the semiconductor pattern and the conductive line.

8. a gate dielectric layer is interposed between the semiconductor pattern and the outer blocking dielectric layer; 8. The integrated circuit device of claim 7, wherein the gate dielectric layer extends into a portion of the semiconductor pattern and has a convex sidewall.

9. 2. The integrated circuit device of claim 1, further comprising a tunneling dielectric layer and a charge storage layer between the channel layer and the inner blocking dielectric layer, the tunneling dielectric layer and the charge storage layer extending along an extension direction of the channel layer.

10. a plurality of conductive lines extending on a substrate in a horizontal direction parallel to a major surface of the substrate and overlapping each other along a vertical direction perpendicular to the major surface; a plurality of insulating layers interposed between the conductive lines and extending in the horizontal direction; a channel film extending in the vertical direction within a channel hole penetrating the plurality of conductive lines and the plurality of insulating films; a charge storage layer and a first blocking dielectric layer extending in a direction in which the channel layer extends between the plurality of conductive lines and the channel layer in the channel hole; a plurality of second blocking dielectric layers interposed between the plurality of conductive lines and the first blocking dielectric layer and between the plurality of conductive lines and the plurality of insulating layers in at least some of the plurality of conductive lines; The channel hole has a tapered shape with a diameter decreasing toward the main surface, an inner blocking dielectric layer extending along an extension direction of the channel layer between the plurality of conductive lines and the channel layer in the channel hole, the horizontal width of the inner blocking dielectric film narrows toward the major surface, an integrated circuit device, wherein a first width in the horizontal direction of a second blocking dielectric film of an uppermost conductive line among the plurality of conductive lines operating as a memory cell, a second width in the horizontal direction of a second blocking dielectric film of a lowermost conductive line among the plurality of conductive lines operating as a memory cell, and a third width in the horizontal direction of a second blocking dielectric film of a central conductive line closest to the uppermost conductive line and the lowermost conductive line and at an equal distance in the vertical direction, based on one of the channel holes, are wider than the first width and the second width is wider than the third width.

11. 11. The integrated circuit device of claim 10, wherein the first blocking dielectric layer is formed continuously along an inner side of one of the channel holes.

12. 11. The integrated circuit device of claim 10, wherein a sum of a vertical thickness of each of the plurality of conductive lines and a vertical thickness of the second blocking dielectric layer surrounding the conductive lines based on one of the channel holes is substantially equal to one another.

13. The charge storage layer is made of silicon nitride, Each of the first and second blocking dielectric layers is made of silicon oxide; 11. The integrated circuit device of claim 10, wherein an etch rate of the first blocking dielectric layer and an etch rate of the second blocking dielectric layer are different from each other.

14. Each of the plurality of second blocking dielectric layers has a width in the horizontal direction of about 100 nm or less; 11. The integrated circuit device of claim 10, wherein at least some of the plurality of second blocking dielectric layers have a width in the horizontal direction that is less than about 60 nm.

15. forming a structure in which a plurality of insulating films and a plurality of sacrificial films are stacked on a substrate; forming a channel hole penetrating the structure, the channel hole having a tapered shape with a diameter decreasing toward a main surface of the substrate; forming a first blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer in the channel hole, the first blocking dielectric layer having a width in a horizontal direction narrower as it approaches the main surface; forming a channel film on the tunneling dielectric film in the channel hole; removing the sacrificial layers to form conductive line spaces between the insulating layers; forming a second blocking pre-dielectric layer conformally covering an inner wall of the conductive line space; removing a portion of the second blocking preliminary dielectric layer to separate the second blocking preliminary dielectric layer into a plurality of second blocking dielectric layers; forming a conductive line filling the conductive line space; the first blocking dielectric layer extends in the channel hole between the plurality of conductive lines and the channel layer along an extension direction of the channel layer; A method for manufacturing an integrated circuit device, wherein the horizontal width of each of the plurality of second blocking dielectric layers increases as the second blocking dielectric layers approach the substrate.

16. The step of forming the second blocking preliminary dielectric layer comprises: the second blocking pre-dielectric layer is formed to substantially the same thickness in different conductive line spaces using a formation process having a relatively uniform step coverage; The step of dividing the second blocking dielectric layer into a plurality of second blocking dielectric layers comprises:

16. The method of claim 15, wherein the plurality of second blocking dielectric layers are formed to different thicknesses in different conductive line spaces by utilizing an etching process having a relatively non-uniform etch distribution.

17. After forming the second blocking preliminary dielectric layer, 16. The method of claim 15, further comprising forming the second blocking pre-dielectric layer to different thicknesses in different conductive line spaces using a formation process having a relatively non-uniform step coverage.

18. The channel hole is formed in a tapered shape with a diameter that decreases toward the substrate, 16. The method of claim 15, wherein the horizontal width of the first blocking dielectric layer is narrower as it approaches the substrate.

19. 16. The method of claim 15, wherein the second blocking pre-dielectric layer in the conductive line space located at an upper end of the conductive line space is completely removed.

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