Electronic device and semiconductor integrated circuit device

Abstract

To provide an electronic apparatus that can increase the signal accuracy in USB communication without inhibiting a reduction in size of a semiconductor integrated circuit device.SOLUTION: An electronic apparatus comprises: an integrated circuit board that is provided with a USB circuit block; a first USB interface; a second USB interface; a printed circuit board on which a source clock circuit outputting a source clock is arranged; and a ball grid array that includes a first ball grid, a second ball grid, and a third ball grid connecting the integrated circuit board and the printed circuit board with each other. The first ball grid electrically connects the USB circuit block and the first USB interface with each other. The second ball grid electrically connects the USB circuit block and the second USB interface with each other. The third ball grid electrically connects the source clock circuit and the USB circuit block with each other. The third ball grid is located between the first ball grid and the second ball grid.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to an electronic device and a semiconductor integrated circuit device. [Background technology]

[0002] In recent years, as semiconductor devices have become more highly integrated and functional, semiconductor integrated circuit devices with many functions, such as SoCs (System on Chip) and FPGAs (Field-Programmable Gate Arrays) in which many functions are built into one semiconductor device, and electronic devices equipped with such semiconductor integrated circuit devices have become widespread. Such semiconductor integrated circuit devices with many functions require many terminals for inputting and outputting signals according to the functions. For this reason, so-called ball grid arrays (BGAs), which allow the arrangement of more terminals by arranging multiple terminals (ball grids) in a lattice pattern, have become widespread.

[0003] However, in a semiconductor integrated circuit device that employs a BGA, multiple terminals are arranged at a narrow pitch, which increases the risk of electrical crosstalk and the like occurring between the terminals, and as a result, there is a risk of the semiconductor integrated circuit device malfunctioning.

[0004] To address such problems, Patent Document 1 discloses a technique for reducing the effects of electrical crosstalk by shielding signal wiring that is a concern due to electrical crosstalk in a semiconductor integrated circuit and a printed wiring board having a BGA. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2000-349192 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, the technology described in Patent Document 1 requires multiple terminals for shielding signal wiring, which is a concern due to electrical crosstalk, and this hinders miniaturization of semiconductor integrated circuit devices. In particular, technology related to USB (Universal Serial Bus) communication has progressed rapidly in recent years, and communication speeds have improved, so there is a demand to reduce the risk that noise such as electrical crosstalk will affect signals used in USB communication. At the same time, one semiconductor integrated circuit device and electronic device often include multiple terminals for USB communication, and as a result, the number of terminals for USB communication provided in a semiconductor integrated circuit device is increasing.

[0007] In such semiconductor integrated circuit devices and electronic devices having a USB communication function, there is a demand for improving the signal accuracy of USB communication without impeding miniaturization of the semiconductor integrated circuit devices. In other words, in semiconductor integrated circuit devices and electronic devices having a USB communication function, there is room for improvement in terms of the signal accuracy of USB communication without impeding miniaturization. [Means for solving the problem]

[0008] One aspect of the electronic device according to the present invention is an integrated circuit board having a USB circuit block; A first USB interface; A second USB interface; a first connection wiring electrically connected to the first USB interface, a second connection wiring electrically connected to the second USB interface, and a source clock output a printed circuit board on which a source clock circuit for the a ball grid array including a first ball grid, a second ball grid, and a third ball grid electrically connecting the integrated circuit board and the printed circuit board; Equipped with the first ball grid electrically connects the USB circuit block and the first USB interface via the first connection wiring; the second ball grid electrically connects the USB circuit block and the second USB interface via the second connection wiring; the third ball grid electrically connects the source clock circuit and the USB circuit block; The third ball grid is located between the first ball grid and the second ball grid.

[0009] One aspect of the semiconductor integrated circuit device according to the present invention is A semiconductor integrated circuit device electrically connected to a printed circuit board, an integrated circuit board having a USB circuit block; a ball grid array electrically connecting the integrated circuit board and the printed circuit board; Equipped with the ball grid array includes a first ball grid, a second ball grid, and a third ball grid; the first ball grid is electrically connected to the USB circuit block; the second ball grid is electrically connected to the USB circuit block; the third ball grid propagates a source clock supplied to the USB circuit block; The third ball grid is located between the first ball grid and the second ball grid. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 is a perspective view of the printing device as seen from the +Y side. [Diagram 2] FIG. 2 is a perspective view of the printing device as seen from the +Y side when the cover of the printing device is open. [Diagram 3] FIG. 2 is a perspective view of the printing device as seen from the -Y side. [Figure 4] 3 is a cross-sectional view of the printing device taken along line Ee in FIG. 2. [Diagram 5] FIG. 2 is a block diagram showing the functional configuration of the printing apparatus. [Figure 6]FIG. 2 is a block diagram showing the functional configuration of a control circuit; [Figure 7] 1 is a cross-sectional view showing a structure of a semiconductor integrated circuit device. [Figure 8] 1 is a diagram showing an example of an arrangement of a plurality of terminals provided on a terminal mounting surface; [Figure 9] 2 is a diagram for explaining the relationship between a plurality of terminals provided on a terminal mounting surface and various circuits provided on an IC chip. FIG. [Figure 10] 3 is a diagram for explaining the arrangement of a plurality of terminals 310 included in a terminal area 321. FIG. [Figure 11] 2 is a diagram showing an example of internal wiring of a semiconductor integrated circuit device 200. FIG. [Figure 12] 13 is a diagram for explaining the arrangement of a plurality of terminals 310 included in a terminal area 321 in the second embodiment. FIG. [Figure 13] FIG. 11 is a diagram showing an example of internal wiring of a semiconductor integrated circuit device 200 according to a second embodiment. [Figure 14] 13 is a diagram showing an example of an arrangement of a plurality of terminals 310 provided on a terminal mounting surface 301 in the third embodiment. FIG. [Figure 15] 13 is a diagram for explaining the arrangement of a plurality of terminals 310 included in a terminal area 321 in the third embodiment. FIG. [Figure 16] FIG. 11 is a diagram showing an example of internal wiring of a semiconductor integrated circuit device 200 according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] A preferred embodiment of the present invention will be described below with reference to the drawings. The drawings used are for convenience of explanation. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention. In this embodiment, a printing device will be described as an example of an electronic device of the present invention, but the electronic device according to the present invention is not limited to a printing device and may be, for example, various electronic devices such as a personal computer, a projector, and a television.

[0012] 1. First embodiment 1.1 Printing device structure The external structure of a printing device 1, which is an example of an electronic device, will be described with reference to Figs. 1 to 3. In the following, the description will be given using the X, Y, and Z directions, which are perpendicular to each other. The starting point side of an arrow indicating the X direction will be referred to as the -X side, and the tip side as the +X side, the starting point side of an arrow indicating the Y direction will be referred to as the -Y side, and the tip side as the +Y side, and the starting point side of an arrow indicating the Z direction will be referred to as the -Z side, and the tip side as the +Z side. Note that the description will be given assuming that the X, Y, and Z directions are perpendicular to each other, but this does not mean that the components of the printing device 1 are necessarily perpendicular to each other.

[0013] Fig. 1 is a perspective view of the printing device 1 as viewed from the +Y side. Fig. 2 is a perspective view of the printing device 1 as viewed from the +Y side when the cover 20 of the printing device 1 is open. Fig. 3 is a perspective view of the printing device 1 as viewed from the -Y side. As shown in Fig. 1, the printing device 1 has a housing 10 and a cover 20 that is located on the +Z side of the housing 10 and is provided so as to be able to be opened and closed.

[0014] 2 and 3, the housing 10 includes a wall 11 located on the +Y side, a wall 12 located on the +X side, a wall 13 located on the +Z side, a wall 14 located on the -Y side, a wall 15 located on the -X side, and a wall 16 located on the -Z side, and has a generally rectangular parallelepiped shape with an internal storage space. The printing device 1 is used in a state where it is installed with the wall 16 facing downward. In other words, the wall 16 of the housing 10 is the bottom of the printing device 1 and corresponds to the installation surface.

[0015] A display unit 40 and an operation unit 41 are located on the wall 13. The display unit 40 is configured with a display panel such as a liquid crystal panel, an electronic paper panel, or an organic electroluminescence panel. Such a display unit 40 displays various information based on the operation and state of the printing device 1. In addition to the above-mentioned display panel, the display unit 40 may also include indicator lights such as LEDs that indicate the power supply state of the printing device 1 and the transmission state of various data transmitted to the printing device 1. The operation unit 41 accepts various operations by a user who uses the printing device 1. In other words, the printing device 1 can execute various processes based on the operation of the operation unit 41 by the user. The printing device 1 may also include a touch panel in which the display unit 40 and the operation unit 41 are integrated.

[0016] As shown in FIG. 2, a USB (Universal Serial Bus) connection terminal 21 for communicating with various devices provided outside the printing device 1 is located on the wall 11, and as shown in FIG. 3, a USB connection terminal 22 for communicating with the outside of the printing device 1 is located on the wall 15. Devices connected to the USB connection terminals 21 and 22 include external devices such as personal computers and digital cameras, and external storage media on which image data is stored. In the following description, when there is no need to distinguish between external devices such as personal computers and digital cameras and external storage media on which image data is stored, they may be referred to as external devices, etc. Also, the USB connection terminals 21 and 22 are connected to cables that perform USB communication. The connector may be any of a USB connector, a miniUSB connector, a MicroUSB connector, etc.

[0017] 3, a power supply terminal 23 configured as, for example, an inlet socket to which an alternating current voltage AC from a commercial power source is input is located on the wall portion 15. Here, the power supply terminal 23 is not limited to an inlet socket to which an alternating current voltage AC is input, but may be, for example, a DC plug to which an external AC adapter is connected. In this case, a DC voltage converted to a DC voltage by the AC adapter may be supplied to the power supply terminal 23.

[0018] A supply port 31 for supplying a medium into the housing 10 is located on the -Y side of the wall 13. Also, a discharge port 32 for discharging the medium supplied into the housing 10 is located on the wall 11. The medium supplied from the supply port 31 is transported inside the housing 10, and ink is ejected in synchronization with the timing of the medium transport, causing the ink to land on the medium and forming an image. The medium on which the image has been formed is then discharged from the discharge port 32.

[0019] The internal structure of the housing 10 through which the medium is transported will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of the printing device 1 taken along line Ee shown in Fig. 2. As shown in Fig. 4, the printing device 1 has a head unit 50, a transport unit 60, and a printed circuit board 100 inside the housing 10.

[0020] The head unit 50 includes an ejection head 51, a carriage 52, and a liquid storage unit 53. The carriage 52 is supported on the -Y side by a carriage guide shaft 54 ​​so as to be capable of reciprocating motion. And, while being supported by the carriage guide shaft 54, the carriage 52 reciprocates along the main scanning direction along the X direction.

[0021] The liquid storage section 53 is located on the +Z side of the carriage 52. Ink to be ejected from the nozzles of the ejection head 51 is stored in this liquid storage section 53. The ejection head 51 is attached to the -Z side of the carriage 52. The liquid storage section 53 and the ejection head 51 are connected by a liquid flow path (not shown). This allows the ink stored in the liquid storage section 53 to be supplied to the ejection head 51. In addition, an ejection surface 55 having a plurality of nozzles that eject ink to a medium is located on the -Z side of the ejection head 51.

[0022] The transport unit 60 includes medium support parts 61 and 62 and a transport roller pair 63 and 64. The medium support part 61 and the medium support part 62 form a transport path HK for transporting the medium supplied from the supply port 31 to the discharge port 32. Then, the transport roller pair 63 and 64 are driven, so that the medium supplied from the supply port 31 is transported toward the discharge port 32 along the transport path HK. Specifically, the medium supplied from the supply port 31 is transported from the medium support part 61 toward the medium support part 62 as the transport roller pair 63 is driven. The medium support part 62 is located on the -Z side of the discharge head 51 attached to the carriage 52. That is, the medium support part 62 is located facing the discharge surface 55 of the discharge head 51 attached to the carriage 52 along the Z direction. Then, while the medium is transported along the transport path HK and supported by the medium support part 62, ink is ejected from the nozzles provided on the ejection surface 55 of the ejection head 51, causing the ink to land on the medium and form an image.

[0023] The printed circuit board 100 is provided on the -Z side of the transport path HK, on ​​the wall 14 of the housing 10. The printed circuit board 100 is a plate-shaped member extending along the wall 14. In addition, a plurality of circuits including a semiconductor integrated circuit device 200 are mounted on the printed circuit board 100. The operation of each part of the printing device 1 is controlled by a plurality of circuits including the semiconductor integrated circuit device 200 mounted on the printed circuit board 100.

[0024] 1.2 Printer Functional Configuration Next, a description will be given of the functional configuration of the printing device 1. Fig. 5 is a block diagram showing the functional configuration of the printing device 1. As shown in Fig. 5, the printing device 1 includes a control circuit 201, a power supply circuit 202, an ejection signal output circuit 203, a head unit 50, a transport unit 60, and a display unit 40.

[0025] An AC voltage AC from a commercial power source or the like is input to the power supply circuit 202 from outside the printing device 1. The power supply circuit 202 converts the input AC voltage AC into a DC voltage of a predetermined voltage value and outputs the converted voltage as a voltage VDD to the control circuit 201. Such a power supply circuit 202 is an AC / DC converter that converts the AC voltage AC into a DC voltage VDD, and is configured, for example, by a flyback circuit. Here, the voltage VDD generated in the power supply circuit 202 is supplied as a power supply voltage for various components of the printing device 1. For this reason, the power supply circuit 202 may be configured to include a step-down circuit that steps down the voltage VDD and a step-up circuit that steps up the voltage VDD. That is, the power supply circuit 202 may generate signals of various voltage values ​​used in the printing device 1, including the voltage VDD, based on the AC voltage AC, and supply the signals to the corresponding components.

[0026] The control circuit 201 generates various control signals for controlling the operation of the printing device 1 based on at least one of an image information signal IMG1 input via the USB connection terminal 21 from an external device or the like provided outside the printing device 1 and an image information signal IMG2 input via the USB connection terminal 22, and outputs the generated control signals to the corresponding components. In this way, the control circuit 201 controls the operation of the printing device 1. In the following description, when there is no need to distinguish between the image information signal IMG1 and the image information signal IMG2, they may be simply referred to as the image information signal IMG.

[0027] Specifically, the control circuit 201 generates a waveform defining signal dCOM, which is a digital signal for defining the waveform of the ejection signal COM output from the ejection signal output circuit 203, and outputs it to the ejection signal output circuit 203. The ejection signal output circuit 203 converts the input waveform defining signal dCOM into an analog signal, and then generates the ejection signal COM by amplifying the analog signal by class D. Then, the ejection signal COM generated by the ejection signal output circuit 203 is supplied to the head unit 50. Here, the waveform defining signal dCOM may be an analog signal as long as it is a signal that can define the waveform of the ejection signal COM. In addition, the ejection signal output circuit 203 may be configured with a class A amplifier circuit, a class B amplifier circuit, a class AB amplifier circuit, or the like as long as it is capable of amplifying the waveform defined by the waveform defining signal dCOM to a predetermined voltage value.

[0028] The control circuit 201 also generates an ejection control signal DATA for controlling the ejection of ink from the ejection head 51 included in the head unit 50, and outputs it to the head unit 50. Specifically, the ejection head 51 includes a nozzle (not shown) and a drive element (not shown) for ejecting ink from the nozzle. The ejection head 51 then supplies an ejection signal COM supplied from the ejection signal output circuit 203 to the drive element at a timing based on the ejection control signal DATA supplied from the control circuit 201. This drives the drive element, and an amount of ink corresponding to the drive of the drive element is ejected from the nozzle of the ejection head 51.

[0029] The control circuit 201 also generates a transport control signal SK for controlling the transport unit 60 and supplies it to the transport unit 60. The transport unit 60 transports the medium along the transport path HK by controlling the drive of the transport roller pair 63, 64 described above in accordance with the input transport control signal SK. Then, ink is ejected from the ejection head 51 in synchronization with the timing at which the transport unit 60 transports the medium based on the transport control signal SK, thereby achieving the desired transport of the medium. The ink lands at the position, forming a desired image on the medium.

[0030] Furthermore, the control circuit 201 generates a display control signal SH for controlling the display of various information on the display unit 40, and supplies the signal to the display unit 40. The display unit 40 displays various information such as operation information and status information of the printing device 1 in accordance with the display control signal SH. This notifies the user of the operation status, etc. of the printing device 1.

[0031] In the printer 1 configured as above, the control circuit 201, the power supply circuit 202, and the ejection signal output circuit 203 are mounted on the printed circuit board 100 described above. Here, the control circuit 201 that controls the operation of the printer 1 is configured to include, for example, a CPU (Central Processing Unit). Note that the control circuit 201 may include at least one of a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), and an FPGA (Field Programmable Gate Array) instead of or in addition to the CPU. At least a part of such a control circuit 201 is, for example, a SoC (System on a Chip), and is configured by the semiconductor integrated circuit device 200 described above.

[0032] 1.3 Control circuit configuration 1.3.1 Control circuit functional configuration Here, the functional configuration of control circuit 201 including semiconductor integrated circuit device 200 will be described with reference to Fig. 6. Fig. 6 is a block diagram showing the functional configuration of control circuit 201. As shown in Fig. 6, control circuit 201 includes semiconductor integrated circuit device 200, memory group 250, control signal generating circuit 260, and source clock circuit 270.

[0033] The semiconductor integrated circuit device 200 includes a CPU 210, a USB signal communication controller 220, a memory controller 230, a control signal communication controller 240, and a bus wiring 211. The semiconductor integrated circuit device 200 operates using, as a power supply voltage, a voltage generated by a potential difference between a voltage VDD output by a power supply circuit 202 and a voltage VSS serving as a reference potential.

[0034] The semiconductor integrated circuit device 200 generates a source signal generation signal XT-out of a predetermined potential based on the power supply voltage. The semiconductor integrated circuit device 200 then supplies the generated source signal generation signal XT-out to the source clock circuit 270 via a wiring 262 arranged on the printed circuit board 100. The source clock circuit 270 includes, for example, a crystal oscillator and an oscillation circuit for oscillating the crystal oscillator. The source clock circuit 270 then supplies a signal of a specific frequency obtained by oscillating the crystal oscillator at a specific frequency based on the source signal generation signal XT-out as a source clock signal XT-in to the semiconductor integrated circuit device 200 via a wiring 261 arranged on the printed circuit board 100. The semiconductor integrated circuit device 200 operates at a timing based on the period of the source clock signal XT supplied thereto or the period of a signal obtained by dividing or multiplying the source clock signal XT. That is, the source clock circuit 270 is arranged on the printed circuit board 100 and outputs the source clock signal XT-in. Here, the source clock signal XT-in is an example of the source clock.

[0035] The bus wiring 211 communicatively connects the CPU 210 with the USB signal communication controller 220, the memory controller 230, and the control signal communication controller 240.

[0036] The USB signal communication controller 220 is electrically connected to the USB connection terminal 21 via a wiring 221 provided on the printed circuit board 100. When an external device such as an external device 2 is connected to the USB connection terminal 21, an image information signal IMG1 is input from the external device 2 to the USB signal communication controller 220 via the wiring 221. The communication controller 220 is electrically connected to the USB connection terminal 22 via a wiring 222 provided on the printed circuit board 100. When the external storage memory 3 is connected to the USB connection terminal 22, an image information signal IMG2 is input from the external storage memory 3 to the USB signal communication controller 220 via the wiring 222. Note that the external storage memory 3 may be communicatively connected to the USB connection terminal 21, and the external device 2 may be communicatively connected to the USB connection terminal 22.

[0037] Here, each of the image information signals IMG1 and IMG2 is a differential signal that complies with a communication method capable of data transfer at a high frequency of 5 GHz or more, for example, a communication method of USB 3.0 or later. That is, the USB signal communication controller 220 is a circuit block that supports a communication method capable of data transfer at a high frequency of 5 GHz or more, in other words, the USB signal communication controller 220 is a circuit block that supports a communication speed of 5 Gbps or more. In the following description, one signal of the image information signal IMG1 propagated as a pair of differential signals through the wiring 221 may be referred to as a differential signal IMG1+, and the other signal of the image information signal IMG1 propagated as a pair of differential signals through the wiring 221 may be referred to as a differential signal IMG1-. Similarly, one signal of the image information signal IMG2 propagated as a pair of differential signals through the wiring 222 may be referred to as a differential signal IMG2+, and the other signal of the image information signal IMG2 propagated as a pair of differential signals through the wiring 222 may be referred to as a differential signal IMG2-. That is, the printed circuit board 100 is provided with a pair of wirings 221 for propagating the differential signals IMG1+, IMG1-, and a pair of wirings 222 for propagating the differential signals IMG2+, IMG2-.

[0038] In the semiconductor integrated circuit device 200, the USB signal communication controller 220 may be configured with one circuit block that processes the image information signals IMG1 and IMG2 input from the USB connection terminals 21 and 22, or may be configured with two or more circuit blocks, that is, a circuit block that processes the image information signal IMG1 input from the USB connection terminal 21 and a circuit block that processes the image information signal IMG2 input from the USB connection terminal 22. Here, the USB signal communication controller 220 is an example of a USB circuit block, one of the USB connection terminals 21 and 22 is an example of a first USB interface, and the other of the USB connection terminals 21 and 22 is an example of a second USB interface. One of the wiring 221 that electrically connects the USB signal communication controller 220 and the USB connection terminal 21 and the wiring 222 that electrically connects the USB signal communication controller 220 and the USB connection terminal 22, which are arranged on the printed circuit board 100, is an example of a first connection wiring, and the other is an example of a second connection wiring.

[0039] The image information signals IMG1, IMG2 input to the USB signal communication controller 220 are input to the CPU 210 via the bus wiring 211. The CPU 210 generates a control signal for reading out corresponding information from the memory group 250 based on the input image information signals IMG1, IMG2, and outputs it to the memory controller 230 via the bus wiring 211.

[0040] The memory controller 230 generates a memory control signal MCS for accessing a memory cell included in the memory group 250 in which corresponding information is stored, based on a control signal input from the CPU 210, and outputs the signal to the memory group 250 via a wiring 231 arranged on the printed circuit board 100. As a result, the memory controller 230 reads out desired information stored in the memory group 250, and outputs the read information to the CPU 210. As a result, the desired information stored in the memory group 250 is supplied to the CPU 210. Here, the memory group 250 may be configured to include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like.

[0041] The CPU 210 generates a control signal for controlling the operation of the printing device 1 based on the image information signals IMG1, IMG2 input via the USB connection terminals 21, 22 and the information stored in the memory group 250 read by the memory controller 230. The CPU 210 then inputs the generated control signal to the control signal communication controller 240 via the bus wiring 211. The control signal communication controller 240 generates a print control signal PCS including various information for controlling the operation of the printing device 1 based on the control signal input from the CPU 210, and outputs it to the control signal generation circuit 260 via wiring 241 arranged on the printed circuit board 100.

[0042] Specifically, the control signal generating circuit 260 generates various signals such as a waveform defining signal dCOM, an ejection control signal DATA, a transport control signal SK, and a display control signal SH that control the operation of the printing device 1 based on the print control signal PCS input from the semiconductor integrated circuit device 200, and outputs them to corresponding components of the printing device 1. Such a control signal generating circuit 260 may be composed of multiple electronic components including one or multiple integrated circuits, or may be configured as a part of the semiconductor integrated circuit device 200.

[0043] Here, the print control signal PCS output by the control signal communication controller 240 may be, for example, a signal conforming to the UART (Universal Asynchronous Receiver / Transmitter) communication standard, or may be a signal conforming to the I2C (Inter-Integrated Circuit) communication standard. The control signal communication controller 240 is configured to include a plurality of circuit blocks that generate and output signals corresponding to the waveform defining signal dCOM, the ejection control signal DATA, the transport control signal SK, and the display control signal SH, and the print control signal PCS output by the control signal communication controller 240 may be configured to include a plurality of signals corresponding to the waveform defining signal dCOM, the ejection control signal DATA, the transport control signal SK, and the display control signal SH, respectively.

[0044] 1.3.2 Structure of semiconductor integrated circuit devices Next, the structure of the semiconductor integrated circuit device 200 will be described. FIG. 7 is a cross-sectional view showing the structure of the semiconductor integrated circuit device 200. In the following, the description will be given using the x-direction, y-direction, and z-direction, which are independent of the X-direction, Y-direction, and Z-direction shown in FIG. 1 to FIG. 4 and are perpendicular to each other. In addition, the starting point side of an arrow indicating the x-direction may be referred to as the -x side, and the tip side thereof as the +y side, the starting point side of an arrow indicating the y-direction may be referred to as the -y side, and the tip side thereof as the +y side, and the starting point side of an arrow indicating the z-direction may be referred to as the -z side, and the tip side thereof as the +z side. In addition, the description will be given assuming that the x-direction, the y-direction, and the z-direction are perpendicular to each other, but this does not necessarily mean that the components of the semiconductor integrated circuit device 200 are perpendicular to each other.

[0045] As shown in FIG. 7, the semiconductor integrated circuit device 200 includes a base substrate 300, an IC chip 360, and a housing 350. The base substrate 300 includes a housing 350 and an IC chip 360. The housing 350 includes a housing 35 ... base substrate 300.

[0046] The IC chip 360 has the above-mentioned CPU 210, USB signal communication controller 220, memory controller 230, and control signal communication controller 240 mounted thereon.

[0047] The base substrate 300 is located on the -z side of the IC chip 360. The IC chip 360 is mounted on the base substrate 300 with a bonding member 370 such as an adhesive. The base substrate 300 and the IC chip 360 are electrically connected via bonding wires 380. In other words, the base substrate 300 is provided with the CPU 210, the USB signal communication controller 220, the memory controller 230, and the control signal communication controller 240.

[0048] The base substrate 300 is provided with a plurality of wiring patterns including wiring patterns pIMG1+, pIMG1-, pIMG2+, pIMG2-, pXT-in, and pXT-out, which will be described later, and a plurality of electrodes (not shown). The bonding wire 380 is electrically connected to an electrode (not shown) formed on the surface of the +z side of the base substrate 300. A plurality of electrodes are also provided on the surface of the -z side of the base substrate 300. Each of the plurality of electrodes provided on the surface of the -z side of the base substrate 300 is provided with a terminal 310 including a solder ball. The base substrate 300 is electrically connected to the printed circuit board 100 by the terminal 310 including the solder ball. The plurality of terminals 310 electrically connecting the base substrate 300 and the printed circuit board 100 of the semiconductor integrated circuit device 200 constitute a so-called ball grid array (BGA) that electrically and mechanically connects the base substrate 300 and the printed circuit board 100. That is, the base substrate 300 included in the semiconductor integrated circuit device 200 in this embodiment and the printed circuit board 100 provided in the printing device 1 are electrically connected by a BGA configured with a plurality of terminals 310 including solder balls. In the following description, the -z side surface of the base substrate 300 on which the BGA is configured with the plurality of terminals 310 is referred to as the terminal mounting surface 301.

[0049] In the semiconductor integrated circuit device 200 configured as described above, a signal input to the semiconductor integrated circuit device 200 via the multiple terminals 310 provided on the terminal mounting surface 301 is propagated through the electrodes and wiring pattern provided on the base substrate 300 and the bonding wires 380, and is input to the IC chip 360. Also, a signal output from the IC chip 360 is output to the printed circuit board 100 via the bonding wires 380, the electrodes and wiring pattern provided on the base substrate 300, and the multiple terminals 310. Here, the base substrate 300 provided with the IC chip 360 on which the USB signal communication controller 220 is mounted is an example of an integrated circuit board. Also, since the multiple terminals 310 electrically connect the IC chip 360 and the printed circuit board 100 via the base substrate 300, the IC chip 360 is also an example of an integrated circuit board in a broad sense, and further, a configuration in which the IC chip 360 on which the USB signal communication controller 220 is mounted and the base substrate 300 are integrated together is also an example of an integrated circuit board in a broad sense.

[0050] The housing 350 is located on the +z side of the IC chip 360, and is joined to the base substrate 300 so as to cover the IC chip 360. The housing 350 contains an epoxy resin or the like, and protects the IC chip 360.

[0051] 1.3.3 Terminal arrangement on the terminal mounting surface In the semiconductor integrated circuit device 200 configured as described above, since the multiple terminals 310 are arranged at high density, there is a risk that signals propagating through each of the multiple terminals 310 may interfere with each other. In particular, when the multiple terminals 310 form a BGA as shown in this embodiment, since the multiple terminals 310 are exposed to each other, the influence of mutual interference of signals is significant, and since the multiple terminals 310 are arranged at high density, it is difficult to provide circuit elements or the like for reducing mutual interference on the printed circuit board 100 or the base substrate 300. Therefore, in the semiconductor integrated circuit device 200 configured with a BGA, it is required to reduce the risk of signals propagating through each of the multiple terminals 310 interfering with each other by optimally arranging the signals propagating through each of the multiple terminals 310.

[0052] In particular, technology relating to USB (Universal Serial Bus) communication has advanced rapidly in recent years, and communication speeds have been improving. Therefore, in the semiconductor integrated circuit device 200 capable of USB communication as shown in this embodiment, in order to improve the communication quality of the USB communication, it is required to reduce the risk of noise such as electrical crosstalk being superimposed on the signal input to the USB signal communication controller 220 that executes various processes relating to the USB communication.

[0053] Furthermore, in the semiconductor integrated circuit device 200 in which signals compliant with a plurality of USB communications with image information signals IMG1, IMG2 are input via USB connection terminals 21, 22 as shown in this embodiment, it is necessary to reduce the risk of noise affecting each of the image information signal IMG1 input via USB connection terminal 21 and the image information signal IMG2 input via USB connection terminal 22. If shielding processing to reduce the effects of noise is individually performed on these signals, the number of multiple terminals 310 constituting the BGA of the semiconductor integrated circuit device 200 will increase, which may hinder the miniaturization of the semiconductor integrated circuit device 200.

[0054] In response to the problems that arise in the semiconductor integrated circuit device 200 that is electrically connected to the printed circuit board 100 by such a BGA and has a plurality of USB communication functions, the semiconductor integrated circuit device 200 of the printing device 1 in this embodiment includes a base substrate 300 provided with an IC chip 360 on which a USB signal communication controller 220 is mounted, a wiring 221 electrically connected to the USB connection terminal 21, a wiring 222 electrically connected to the USB connection terminal 22, and the printed circuit board 100 on which a source clock circuit 270 for outputting a source clock signal XT-in is arranged, and an IC chip 360 on which the USB signal communication controller 220 is mounted. and a plurality of terminals 310 constituting a BGA that electrically connects a base substrate 300 on which a chip 360 is provided and the printed circuit board 100, the plurality of terminals 310 constituting the BGA including a terminal 310 electrically connecting the USB signal communication controller 220 and the USB connection terminal 21, a terminal 310 electrically connecting the USB signal communication controller 220 and the USB connection terminal 22, and a terminal 310 electrically connecting the source clock circuit 270 and the USB signal communication controller 220 and propagating a source clock signal XT-in that serves as a source of a clock signal indicating the operation timing of the USB signal communication controller 220. Among the plurality of terminals 310 constituting the BGA, the terminal 310 propagating the source clock signal XT-in is located between the terminal 310 electrically connecting the USB signal communication controller 220 and the USB connection terminal 21 and the terminal 310 electrically connecting the USB signal communication controller 220 and the USB connection terminal 22. The semiconductor integrated circuit device 200 and the USB signal communication controller 220 operate at timings determined by a signal obtained by dividing or multiplying this source clock signal XT-in.

[0055] In the semiconductor integrated circuit device 200 configured as above, the USB signal communication controller 220 included in the semiconductor integrated circuit device 200 operates at a timing based on the source clock signal XT-in. Therefore, the image information signal IMG1 input to the USB signal communication controller 220 via the USB connection terminal 21 and the image information signal IMG2 input to the USB signal communication controller 220 via the USB connection terminal 22 are also propagated at a timing based on the source clock signal XT-in. By locating the terminal 310 propagating the source clock signal XT-in between the terminal 310 propagating the image information signal IMG1, which is a signal propagated at a timing based on the source clock signal XT-in, and the terminal 310 propagating the image information signal IMG2, which is a signal propagated at a timing based on the source clock signal XT-in, the risk of a signal with a different operation timing being superimposed as noise on the source clock signal XT-in is reduced. And, by reducing the risk of noise being superimposed on the source clock signal XT-in, the accuracy of the image information signals IMG1, IMG2 propagated at the timing based on the source clock signal XT-in is improved. Furthermore, since the source clock signal XT-in is shielded by the terminal 310 through which the image information signal IMG1 is propagated and the terminal 310 through which the image information signal IMG2 is propagated, there is no need to provide a separate shield terminal for reducing noise superimposed on the source clock signal XT-in, and as a result, the risk of hindering the miniaturization of the semiconductor integrated circuit device 200 is also reduced.

[0056] A specific example of the arrangement of the terminals 310 through which the source clock signal XT-in and the image information signals IMG1 and IMG2 propagate among the multiple terminals 310 provided on the terminal mounting surface 301 of the semiconductor integrated circuit device 200 configured as above will be described. In describing a specific example of the arrangement of the terminals 310 through which the source clock signal XT-in and the image information signals IMG1 and IMG2 propagate, first, the arrangement of the multiple terminals 310 provided on the terminal mounting surface 301 will be described.

[0057] FIG. 8 is a diagram showing an example of the arrangement of a plurality of terminals 310 provided on the terminal mounting surface 301. As shown in FIG. 8, the terminal mounting surface 301 includes sides 302 and 303 that extend in a direction along the x-axis and face each other in a direction along the y-axis, and sides 304 and 305 that extend in a direction along the y-axis and face each other in a direction along the x-axis. And, side 304 intersects both sides 302 and 303, and side 305 intersects both sides 302 and 303. That is, the base substrate 300 is substantially rectangular with sides 302 to 305 as its outer periphery.

[0058] As shown in FIG. 8, a plurality of terminals 310 are arranged in P parallel rows along the x-axis on the terminal mounting surface 301, and the P parallel terminals 310 are provided in Q columns along the y-axis. That is, a total of P×Q terminals 310 are arranged in a grid pattern on the terminal mounting surface 301. Here, in the following description, among the P×Q terminals 310 provided on the terminal mounting surface 301, the terminal 310 that is the i-th from the side 304 side along the x-axis and the j-th from the side 302 side along the y-axis may be referred to as terminal 310[i,j] (i is any of 1 to P, and j is any of 1 to Q).

[0059] FIG. 9 is a diagram for explaining the relationship between a plurality of terminals 310 provided on the terminal mounting surface 301 and various circuits provided in the IC chip 360. As shown in FIG. 9, terminal regions 321 to 328 including a plurality of terminals 310 are located on the terminal mounting surface 301. Here, i1 to i4 shown in FIG. 9 indicate positions along the x-axis such that 1 < i1 < i2 < i3 < i4 < P, and j1 to j2 indicate positions along the y-axis such that 1 < j1 < j2 < Q.

[0060] The terminal region 321 has a plurality of terminals 310 located in a region surrounded by terminals 310[1,j1 + 1], 310[i1,j1 + 1], 310[1,j2], and 310[i1,j2]. And, the plurality of terminals 310 included in the terminal region 321 are electrically connected to the USB signal communication controller 220 and propagate the image information signal IMG1 and the image information signal IMG2.

[0061] The terminal area 322 has a plurality of terminals 310 located in an area surrounded by terminals 310[i1+1,j1+1], 310[i2,j1+1], 310[i1+1,j2], and 310[i2,j2]. The plurality of terminals 310 included in the terminal area 322 are electrically connected to the control signal communication controller 240, and transmit a signal corresponding to the ejection control signal DATA among the print control signal PCS.

[0062] The terminal region 323 has a plurality of terminals 310 located in a region surrounded by terminals 310[i2+1,j1+1], 310[i3,j1+1], 310[i2+1,j2], and 310[i3,j2]. The plurality of terminals 310 included in the terminal region 323 propagate voltages VDD and VSS that function as power supplies for the semiconductor integrated circuit device 200.

[0063] The terminal area 324 has a plurality of terminals 310 located in an area surrounded by terminals 310[i3+1,j1+1], 310[i4,j1+1], 310[i3+1,j2], and 310[i4,j2]. The plurality of terminals 310 included in the terminal area 324 are electrically connected to the control signal communication controller 240, and are used to transmit the control signal PCS to the semiconductor integrated circuit device. The signal transmitting section 202 transmits a signal corresponding to a display control signal SH for controlling an indicator lamp such as an LED that indicates the power supply state of the device 200 and the transmission state of various data.

[0064] The terminal area 326 has a plurality of terminals 310 located in an area surrounded by terminals 310[i4+2,j1+1], 310[P,j1+1], 310[i4+2,j2], and 310[P,j2]. The plurality of terminals 310 included in the terminal area 326 are electrically connected to the control signal communication controller 240, and transmit a signal corresponding to a transport control signal SK for controlling the operation of the transport unit 60, among the print control signals PCS.

[0065] The terminal area 327 has a plurality of terminals 310 located in an area surrounded by terminals 310[1,j2+2], 310[P,j2+2], 310[1,Q], and 310[P,Q]. The plurality of terminals 310 included in the terminal area 327 are electrically connected to the memory controller 230, and a memory control signal MCS is transmitted therethrough.

[0066] The terminal area 325 has a plurality of terminals 310 located in the area of ​​terminals 310[i4+1,j1+1] to 310[i4+1,j2], and the terminal area 328 has a plurality of terminals 310 located in the area of ​​terminals 310[1,j2+1] to 310[P,j2+1]. The plurality of terminals 310 included in the terminal areas 325 and 328 are located where a voltage VSS serving as a reference potential of the semiconductor integrated circuit device 200 is propagated. The terminal areas 325 and 327 function as shield terminals for reducing the possibility of mutual interference of signals between adjacent terminal areas.

[0067] Among the multiple terminals 310 provided on the terminal mounting surface 301 configured as above, the arrangement of the terminal area 321 including the multiple terminals 310 electrically connected to the USB signal communication controller 220, which is characteristic of the semiconductor integrated circuit device 200 in this embodiment, will be described in detail. Here, in the printing device 1 in this embodiment, in the terminal area 321 where the multiple terminals 310 electrically connected to the USB signal communication controller 220 are located, the terminal 310 through which the differential signal IMG1+ propagates, the terminal 310 through which the differential signal IMG1- propagates, the terminal 310 through which the differential signal IMG2+ propagates, and the terminal 310 through which the differential signal IMG2- propagates are arranged, as well as the terminal 310 through which the source clock signal XT-in propagates, and the terminal 310 through which the source generated signal XT-out propagates. In the following description, the terminal 310 through which the differential signal IMG1+ propagates is referred to as terminal tIMG1+, the terminal 310 through which the differential signal IMG1- propagates is referred to as terminal tIMG1-, the terminal 310 through which the differential signal IMG2+ propagates is referred to as terminal tIMG2+, the terminal 310 through which the differential signal IMG2- propagates is referred to as terminal tIMG2-, the terminal 310 through which the source clock signal XT-in propagates is referred to as terminal tXT-in, and the terminal 310 through which the source generated signal XT-out propagates is referred to as terminal tXT-out.

[0068] Fig. 10 is a diagram for explaining the arrangement of a plurality of terminals 310 included in the terminal area 321. In Fig. 10, a terminal tXT-in through which the source clock signal XT-in propagates, a terminal tXT-out through which the source generated signal XT-out propagates, terminals tIMG1+, tIMG1- through which the image information signal IMG1 propagates, and terminals tIMG2+, tIMG2- through which the image information signal IMG2 propagates are arranged in one direction. That is, in Fig. 10, the terminals tXT-in, tXT-out, tIMG1+, tIMG1-, tIMG2+, tIMG2- are arranged in the x direction or y direction on the terminal mounting surface 301 shown in Fig. 8.

[0069] As shown in FIG. 10, a terminal tIMG1+ that transmits a differential signal IMG1+, which is one of a pair of image information signals IMG1 supplied as a pair of differential signals via the USB connection terminal 21, transmits the differential signal IMG1+ between the USB signal communication controller 220 and an external device, etc., and The terminal tIMG1+ is located adjacent to the terminal tIMG1- that propagates the differential signal IMG1-, which is the other signal of the image information signals IMG1 supplied as a pair of differential signals via the terminal 21. Furthermore, the terminal tIMG2+ that propagates the differential signal IMG2+, which is one signal of the image information signals IMG2 supplied as a pair of differential signals via the USB connection terminal 22, is located adjacent to the terminal tIMG2- that propagates the differential signal IMG2-, which is the other signal of the image information signals IMG2 supplied as a pair of differential signals via the USB connection terminal 22. Terminal tXT-in, which propagates source clock signal XT-in supplied to USB signal communication controller 220, and terminal tXT-out, which propagates source generated signal XT-out, which is a signal for oscillating an oscillator such as a quartz oscillator included in source clock circuit 270 and is used to generate source clock signal XT-in, are located between terminal tIMG1+, which propagates differential signal IMG1+, and terminal tIMG2-, which propagates differential signal IMG2-.

[0070] As described above, the terminal tXT-in through which the source clock signal XT-in supplied to the semiconductor integrated circuit device 200 propagates is located between the terminal tIMG1+ through which the differential signal IMG1+ of the image information signal IMG1 of the differential signal, which is a signal with a timing based on the source clock signal XT-in, propagates, and the terminal tIMG2- through which the differential signal IMG2- of the image information signal IMG2 of the differential signal, which is a signal with a timing based on the source clock signal XT-in, propagates. Therefore, the terminal tIMG1+ through which one differential signal IMG1+ of the image information signal IMG1 of the differential signal, which is a signal with a timing based on the source clock signal XT-in, propagates, and the terminal tIMG2- through which the other differential signal IMG2- of the image information signal IMG2 of the differential signal, which is a signal with a timing based on the source clock signal XT-in, propagate, function as shield terminals for protecting the terminal tXT-in through which the source clock signal XT-in propagates from noise such as electrical crosstalk.

[0071] As a result, the possibility of noise being superimposed on the terminal tXT-in through which the source clock signal XT-in propagates is reduced, and therefore the accuracy of the source clock signal XT-in is improved, and the propagation accuracy of the image information signals IMG1, IMG2 propagated at the timing based on the source clock signal XT-in can be improved.

[0072] Furthermore, since terminal tIMG1+ through which differential signal IMG1+ is propagated and terminal tIMG2- through which differential signal IMG2- is propagated function as shield terminals that protect terminal tXT-in through which source clock signal XT-in is propagated from IMG noise, there is no need to provide a shield terminal for reducing the risk of noise being superimposed on terminal tXT-in through which source clock signal XT-in is propagated. As a result, it is possible to reduce the number of terminals provided in semiconductor integrated circuit device 200. Therefore, the risk that an increase in the number of terminals due to the increased functionality of semiconductor integrated circuit device 200 will hinder the miniaturization of semiconductor integrated circuit device 200 is reduced.

[0073] Here, the fact that terminal tXT-in propagating the source clock signal XT-in is located between terminal tIMG1+ propagating the differential signal IMG1+ and terminal tIMG2- propagating the differential signal IMG2- does not necessarily mean that terminal tXT-in is located on the imaginary line connecting terminals tIMG1+ and tIMG2-, but also includes that at least a part of terminal tXT-in is located between terminals tIMG1+ and terminal tIMG2- when viewed from a direction intersecting the direction in which terminals tIMG1+ and terminals tIMG2- are arranged. Similarly, the fact that terminal tXT-out propagating source signal generation signal XT-out is located between terminal tIMG1+ propagating differential signal IMG1+ and terminal tIMG2- propagating differential signal IMG2- does not necessarily mean that terminal tXT-out is located on the virtual line connecting terminals tIMG1+ and tIMG2-, but also includes that at least a part of terminal tXT-out is located between terminals tIMG1+ and terminal tIMG2- when viewed from a direction intersecting the direction in which terminals tIMG1+ and terminals tIMG2- are arranged.

[0074] Also, as shown in FIG. 10, terminal tIMG1- which propagates differential signal IMG1-, which is the other signal of image information signal IMG1, is located between terminal tIMG1+ which propagates differential signal IMG1+ and terminal tXT-in which propagates source clock signal XT-in, and terminal tIMG2+ which propagates differential signal IMG2+, which is one signal of image information signal IMG2, is located between terminal tIMG2- which propagates differential signal IMG2- and terminal tXT-in which propagates source clock signal XT-in.

[0075] As a result, in addition to the terminal tIMG1+ through which one differential signal IMG1+ of the image information signal IMG1 which is a differential signal whose timing is based on the source clock signal XT-in is propagated, and the terminal tIMG2- through which the other differential signal IMG2- of the image information signal IMG2 which is a differential signal whose timing is based on the source clock signal XT-in is propagated, the terminal tIMG1- through which the other differential signal IMG1- of the image information signal IMG1 which is a differential signal whose timing is based on the source clock signal XT-in is propagated, and the terminal tIMG2+ through which one differential signal IMG2+ of the image information signal IMG2 which is a differential signal whose timing is based on the source clock signal XT-in are propagated, function as shield terminals to protect the terminal tXT-in through which the source clock signal XT-in is propagated from noise such as electrical crosstalk. As a result, the risk of noise being superimposed on terminal tXT-in through which the source clock signal XT-in propagates is further reduced, the accuracy of the source clock signal XT-in is further improved, and the propagation accuracy of the image information signals IMG1, IMG2 propagating at a timing based on the source clock signal XT-in can be further improved.

[0076] In this case, as shown in FIG. 10, it is preferable that the terminal tIMG1+ propagating the differential signal IMG1+, which is one of the signals in the image information signal IMG1, and the terminal tIMG1- propagating the differential signal IMG1-, which is the other signal in the image information signal IMG1, are located adjacent to each other, and it is preferable that the terminal tIMG2+ propagating the differential signal IMG2+, which is one of the signals in the image information signal IMG2, and the terminal tIMG2- propagating the differential signal IMG2-, which is the other signal in the image information signal IMG2, are located adjacent to each other.

[0077] This makes it possible to reduce the difference in path length between the propagation path that propagates the differential signal IMG1+, which is one signal of the image information signal IMG1, and the propagation path that propagates the differential signal IMG1-, which is the other signal of the image information signal IMG1, thereby further improving the accuracy of the image information signal IMG1.Similarly, it makes it possible to reduce the difference in path length between the propagation path that propagates the differential signal IMG2+, which is one signal of the image information signal IMG2, and the propagation path that propagates the differential signal IMG2-, which is the other signal of the image information signal IMG2, thereby further improving the accuracy of the image information signal IMG2.

[0078] Furthermore, in the printing device 1 of this embodiment, the terminals tXT-in and tXT-out through which the original clock signal XT-in and the original generated signal XT-out propagate are located between the terminal tIMG1+ through which the differential signal IMG1+ propagates and the terminal tIMG2- through which the differential signal IMG2- propagates, and further, the terminal tIMG1- through which the differential signal IMG1-, which is the other signal of the image information signal IMG1, is located between the terminal tIMG1+ through which the differential signal IMG1+ propagates and the terminal tIMG2- through which the original clock signal XT By positioning the terminal tIMG2+ which propagates differential signal IMG2+, which is one of the signals of the image information signal IMG2, between terminal tIMG2- which propagates differential signal IMG2- and terminal tXT-in which propagates source clock signal XT-in, it is possible to reduce the risk of noise being superimposed on the wiring through which the source clock signal XT-in and the source generated signal XT-out propagate within the semiconductor integrated circuit device 200.

[0079] FIG. 11 is a diagram showing an example of internal wiring of the semiconductor integrated circuit device 200. As shown in FIG.

[0080] 11, the terminal tIMG1+ is electrically connected to the wiring pattern pIMG1+ inside the semiconductor integrated circuit device 200 and propagates the differential signal IMG1+. The terminal tIMG1- is electrically connected to the wiring pattern pIMG1- inside the semiconductor integrated circuit device 200 and propagates the differential signal IMG1-. The terminal tIMG2+ is electrically connected to the wiring pattern pIMG2+ inside the semiconductor integrated circuit device 200 and propagates the differential signal IMG2+. The terminal tIMG2- is electrically connected to the wiring pattern pIMG2- inside the semiconductor integrated circuit device 200 and propagates the differential signal IMG2-. The terminal tXT-in is electrically connected to the wiring pattern pXT-in inside the semiconductor integrated circuit device 200. In this case, since the terminal tXT-in is located between the terminals tIMG1+, IMG1- and the terminals tIMG2+, IMG2-, the wiring pattern pXT-in is located between the wiring patterns pIMG1+, pIMG1- and the wiring patterns pIMG2+, pIMG2-. Therefore, the risk of electrical crosstalk occurring in the wiring pattern pXT-in that is electrically connected to the terminal tXT-in and propagates the source clock signal XT-in inside the semiconductor integrated circuit device 200 is reduced.

[0081] In other words, in the semiconductor integrated circuit device 200 used in the printing device 1 in this embodiment, since the terminal tXT-in is located between the terminals tIMG1+, IMG1- and the terminals tIMG2+, IMG2-, the effects of electrical crosstalk within the semiconductor integrated circuit device 200 can also be reduced.

[0082] Here, among the terminals tIMG1+, tIMG1- that propagate the image information signal IMG1 propagated as a pair of differential signals among the multiple terminals 310 constituting the BGA, the terminal tIMG1+ that propagates the differential signal IMG1+ is an example of a first ball grid, and the terminal tIMG1- that propagates the differential signal IMG1- is an example of a fourth ball grid. Also, among the terminals tIMG2+, tIMG2- that propagate the image information signal IMG2 propagated as a pair of differential signals, the terminal tIMG2- that propagates the differential signal IMG2- is an example of a second ball grid, and the terminal tIMG2+ that propagates the differential signal IMG2+ is an example of a fifth ball grid. Then, the terminal tXT-in that propagates the source clock signal XT-in that is an example of a source clock is an example of a third ball grid, and the terminal tXT-out that propagates the source generated signal XT-out for generating the source clock signal XT-in is an example of a sixth ball grid. The image information signal IMG1 is an example of a pair of first differential signals, and the image information signal IMG2 is an example of a pair of second differential signals.

[0083] 1.4 Effects In the semiconductor integrated circuit device 200 used in electronic devices such as the printer 1 in the first embodiment configured as described above, the terminal 310 propagating the original clock signal XT-in is located between the terminals tIMG1+, tIMG1- when the image information signal IMG1, which is a signal propagated at a timing based on the original clock signal XT-in, is propagated, and the terminals tIMG2+, IMG2- when the image information signal IMG2, which is a signal propagated at a timing based on the original clock signal XT-in, is propagated, thereby reducing the risk of a signal with a different operation timing being superimposed as noise on the terminal tXT-in through which the original clock signal XT-in is propagated. Furthermore, by reducing the risk of noise being superimposed on the terminal tXT-in, the risk of noise being superimposed on the original clock signal XT-in propagating at the terminal tXT-in can be reduced. As a result, the accuracy of the image information signals IMG1, IMG2 that are input to or output from the USB signal communication controller 220 and propagated at a timing based on the source clock signal XT-in is also improved.

[0084] Further, the source clock signal XT-in is supplied to terminals tIMG1+, tIMG1- through which the image information signal IMG1 is transmitted, and terminals tIMG2+, tIMG3- through which the image information signal IMG2 is transmitted. Because the signal is shielded by MG2-, there is no need to provide a separate shield terminal for reducing noise superimposed on the source clock signal XT-in. This reduces the risk of impeding miniaturization of the semiconductor integrated circuit device 200. In other words, the semiconductor integrated circuit device 200 of this embodiment can improve the signal accuracy of the USB communication executed by the USB signal communication controller 220 without impeding miniaturization of the semiconductor integrated circuit device 200.

[0085] 2. Second embodiment The semiconductor integrated circuit device 200 used in the printing device 1 in the second embodiment is different from the semiconductor integrated circuit device 200 in the first embodiment in that terminals tVSS1 to tVSS10 are arranged as shield terminals for reducing the possibility of mutual interference between the propagating signals, as terminals tIMG1+, tIMG1- propagating the image information signal IMG1 propagated as a pair of differential signals, terminals tIMG2+, tIMG2- propagating the image information signal IMG2 propagated as a pair of differential signals, terminal tXT-in propagating the source clock signal XT-in, and terminal tXT-out propagating the source generated signal XT-out. In the following description, the same configuration as the printing device 1 in the first embodiment is given a Saturday reference symbol, and the description thereof will be simplified or omitted.

[0086] FIG. 12 is a diagram for explaining the arrangement of a plurality of terminals 310 included in a terminal area 321 in the second embodiment.

[0087] 12, in the semiconductor integrated circuit device 200 in the second embodiment, a terminal tIMG1+ that transmits a differential signal IMG1+, which is one of the image information signals IMG1 supplied as a pair of differential signals via the USB connection terminal 21, between the USB signal communication controller 220 and an external device, and a terminal tIMG1- that transmits a differential signal IMG1-, which is the other of the image information signals IMG1 supplied as a pair of differential signals via the USB connection terminal 21, between the USB signal communication controller 220 and an external device, are located adjacent to each other. Also, a terminal tIMG2+ that transmits a differential signal IMG2+, which is one of the image information signals IMG2 supplied as a pair of differential signals via the USB connection terminal 22, between the USB signal communication controller 220 and an external device, and a terminal tIMG2- that transmits a differential signal IMG2-, which is the other of the image information signals IMG2 supplied as a pair of differential signals via the USB connection terminal 22, between the USB signal communication controller 220 and an external device, are located adjacent to each other. Furthermore, the terminal tXT-in that propagates the source clock signal XT-in supplied to the USB signal communication controller 220 and the terminal tXT-out that propagates the source generated signal XT-out for generating the source clock signal XT-in are located adjacent to each other. That is, the terminals tXT-in and tXT-out are located between the terminals tIMG1+ and tIMG2-, the terminal tIMG1- is located between the terminals tIMG1+ and tXT-in, and the terminal tIMG2+ is located between the terminals tIMG2- and tXT-in.

[0088] A terminal tVSS4, through which a voltage VSS indicating the reference potential of the semiconductor integrated circuit device 200 is propagated, is located between the terminal tIMG+ propagating the differential signal IMG1+ and the terminal tIMG- propagating the differential signal IMG1-, and the terminal tXT-in propagating the original clock signal XT-in and the terminal tXT-out propagating the original generated signal XT-out. A terminal tVSS7, through which a voltage VSS indicating the reference potential of the semiconductor integrated circuit device 200 is propagated, is located between the terminal tIMG2+ propagating the differential signal IMG2+ and the terminal tIMG2- propagating the differential signal IMG2-, and the terminal tXT-in propagating the original clock signal XT-in and the terminal tXT-out propagating the original generated signal XT-out.

[0089] This further reduces the risk that the image information signal IMG1, which is a pair of differential signals propagating between the terminals tIMG1+ and tIMG1-, will interfere with the source clock signal XT-in propagating between the terminal tXT-in and the source generated signal XT-out propagating between the terminal tXT-out, and further reduces the risk that the image information signal IMG2, which is a pair of differential signals propagating between the terminals tIMG2+ and tIMG2-, will interfere with the source clock signal XT-in propagating between the terminal tXT-in and the source generated signal XT-out propagating between the terminal tXT-out. Thus, in the semiconductor integrated circuit device 200 provided in the printing device 1 in the second embodiment, the accuracy of the source clock signal XT-in can be further improved, and the accuracy of the image information signals IMG1 and IMG2 can be further improved.

[0090] Also, as shown in FIG. 12, on the opposite side of terminal tXT-in of terminal tIMG1+ which propagates differential signal IMG1+ and terminal tIMG1- which propagates differential signal IMG1-, there is located terminal tVSS1 which propagates voltage VSS indicating the reference potential of semiconductor integrated circuit device 200, and on the opposite side of terminal tXT-in of terminal tIMG2+ which propagates differential signal IMG2+ and terminal tIMG2- which propagates differential signal IMG2-, there is located terminal tVSS10 which propagates voltage VSS indicating the reference potential of semiconductor integrated circuit device 200.

[0091] This reduces the risk of the image information signals IMG1, IMG2 generated at a timing based on the source clock signal XT-in interfering with various signals input to the semiconductor integrated circuit device 200, and therefore the accuracy of the image information signals IMG1, IMG2 can be further improved in the semiconductor integrated circuit device 200 provided in the printing device 1 in the second embodiment.

[0092] Furthermore, in a direction intersecting the direction in which the terminals tIMG1+ and tIMG2- are arranged, the terminal tIMG1+ and the terminal tVSS2 through which the voltage VSS indicating the reference potential of the semiconductor integrated circuit device 200 is propagated are positioned so as to overlap, and the terminal tIMG1- and the terminal tVSS3 through which the voltage VSS indicating the reference potential of the semiconductor integrated circuit device 200 is propagated are positioned so as to overlap. That is, the terminals tVSS1 to tVSS4 through which the voltage VSS is propagated are positioned so as to surround the terminals tIMG1+ and tIMG1-. This further reduces the risk of various signals interfering with each other in the image information signal IMG1, and the accuracy of the image information signal IMG1 can be further improved.

[0093] Similarly, in a direction intersecting with the direction in which the terminals tIMG1+ and tIMG2- are arranged, the terminal tXT-in and the terminal tVSS5 through which the voltage VSS indicating the reference potential of the semiconductor integrated circuit device 200 is propagated are positioned so as to overlap, and the terminal tXT-out and the terminal tVSS6 through which the voltage VSS indicating the reference potential of the semiconductor integrated circuit device 200 is propagated are positioned so as to overlap. That is, the terminals tVSS4 to tVSS7 through which the voltage VSS is propagated are positioned so as to surround the terminals tXT-in and tXT-out. This further reduces the risk of various signals interfering with the source clock signal XT-in and the source generated signal XT-out, and further improves the accuracy of the source clock signal XT-in.

[0094] Similarly, in a direction intersecting the direction in which the terminals tIMG1+ and tIMG2- are aligned, the terminal tIMG2+ and the terminal tVSS8 through which the voltage VSS indicating the reference potential of the semiconductor integrated circuit device 200 is propagated are positioned so as to overlap, and the terminal tIMG2- and the terminal tVSS9 through which the voltage VSS indicating the reference potential of the semiconductor integrated circuit device 200 is propagated are positioned so as to overlap. That is, the terminals tVSS7 to tVSS10 through which the voltage VSS is propagated are positioned so as to surround the terminals tIMG2+ and tIMG2-. This further reduces the risk of various signals interfering with each other in the image information signal IMG2, and further improves the accuracy of the image information signal IMG2.

[0095] FIG. 13 is a diagram showing an example of internal wiring of a semiconductor integrated circuit device 200 according to the second embodiment. As shown in FIG. 13, in the semiconductor integrated circuit device 200 of the second embodiment, the terminals tVSS1 to tVSS10 are connected by a common wiring pattern pVSS. The terminal tIMG1+ is electrically connected to the wiring pattern pIMG1+ inside the semiconductor integrated circuit device 200 and propagates the differential signal IMG1+. The terminal tIMG1- is electrically connected to the wiring pattern pIMG1- inside the semiconductor integrated circuit device 200 and propagates the differential signal IMG1-. The terminal tIMG2+ is electrically connected to the wiring pattern pIMG2+ inside the semiconductor integrated circuit device 200 and propagates the differential signal IMG2+. The terminal tIMG2- is electrically connected to the wiring pattern pIMG2- inside the semiconductor integrated circuit device 200 and propagates the differential signal IMG2-. The terminal tXT-in is electrically connected to the wiring pattern pXT-in inside the semiconductor integrated circuit device 200.

[0096] In this case, since the terminals tVSS1 to tVSS4 through which the voltage VSS propagates are positioned so as to surround the terminals tIMG1+ and tIMG1−, the following is true around the wiring pattern pIMG1+ and the wiring pattern pIMG1− inside the semiconductor integrated circuit device 200: Because the wiring pattern pVSS through which the voltage VSS is propagated is located, and the terminals tVSS4 to tVSS7 through which the voltage VSS is propagated are positioned so as to surround the terminals tXT-in, tXT-out, inside the semiconductor integrated circuit device 200, the wiring pattern pVSS through which the voltage VSS is propagated is located around the wiring pattern pXT-in and the wiring pattern pXT-in, and the terminals tVSS7 to tVSS10 through which the voltage VSS is propagated are positioned so as to surround the terminals tIMG2+, tIMG2-, inside the semiconductor integrated circuit device 200, the wiring pattern pVSS through which the voltage VSS is propagated is located around the wiring pattern pIMG2+ and the wiring pattern pIMG2-.

[0097] As a result, in the semiconductor integrated circuit device 200 used in the printing device 1 in the second embodiment, the risk of electrical crosstalk occurring between wiring patterns inside the semiconductor integrated circuit device 200 can also be reduced.

[0098] As described above, in the semiconductor integrated circuit device 200 and the printing device 1 in the second embodiment, the risk of noise being superimposed on the original clock signal XT-in and the image information signals IMG1, IMG2 can be further reduced.

[0099] Here, the terminal tVSS4 is an example of a seventh ball grid, the terminal tVSS7 is an example of an eighth ball grid, the terminal tVSS1 is an example of a ninth ball grid, and the terminal tVSS10 is an example of a tenth ball grid.

[0100] 3. Third embodiment Next, a semiconductor integrated circuit device 200 used in the printing device 1 in the third embodiment will be described. The description will be made with reference to Figures 14 to 16. In the following description, the same components as those in the printing device 1 in the first and second embodiments are given the same reference numerals, and the description thereof will be simplified or omitted.

[0101] In the semiconductor integrated circuit device 200 used in the printing device 1 in the first embodiment, it has been described that a plurality of terminals 310 are arranged in a row, P pieces, along the x direction on the terminal mounting surface 301, and that the arranged P terminals 310 are arranged in Q rows, or in a so-called lattice pattern, along the y direction. However, the semiconductor integrated circuit device 200 used in the printing device 1 in the third embodiment differs from the semiconductor integrated circuit device 200 used in the printing device 1 in the first and second embodiments in that a plurality of terminals 310 are arranged in a staggered pattern on the terminal mounting surface 301, as shown in FIG. 14.

[0102] FIG. 14 shows a plurality of terminals 310 provided on a terminal mounting surface 301 in the third embodiment. 14 is a diagram illustrating an example of an arrangement of terminals 310. As illustrated in Fig. 14, in the semiconductor integrated circuit device 200 according to the third embodiment, on the terminal mounting surface 301, the arrangement of the multiple terminals 310 arranged in even-numbered rows along the y direction and the arrangement of the multiple terminals 310 arranged in odd-numbered rows along the y direction are shifted in the x direction.

[0103] Fig. 15 is a diagram for explaining the arrangement of a plurality of terminals 310 included in a terminal region 321 in the third embodiment. Also, Fig. 16 is a diagram showing an example of internal wiring of the semiconductor integrated circuit device 200 in the third embodiment.

[0104] As shown in FIG. 15, even in the semiconductor integrated circuit device 200 according to the third embodiment, As in the semiconductor integrated circuit device 200 in the second embodiment, a terminal tIMG1+ that propagates a differential signal IMG1+, which is one of the pair of image information signals IMG1 supplied as differential signals, and a terminal tIMG2- that propagates a differential signal IMG2-, which is the other of the pair of image information signals IMG1 supplied as differential signals, are arranged in a direction intersecting the direction in which the terminals tIMG1+ and tIMG2- are arranged. Between terminal tIMG1+ and terminal tXT-in is located terminal tIMG1- which propagates differential signal IMG1-, which is the other signal of image information signals IMG1 supplied as a pair of differential signals, and between terminal tIMG2- and terminal tXT-in is located terminal tIMG2+ which propagates differential signal IMG2+, which is one signal of image information signals IMG2 supplied as a pair of differential signals.

[0105] Terminals tIMG1+ and tIMG1- are located adjacent to each other, and terminals tVSS1 to tVSS3 and tVSS9 are located around terminals tIMG1+ and tIMG1-, through which voltage VSS indicating the reference potential of semiconductor integrated circuit device 200 is propagated. Terminals tXT-in and tXT-out are located adjacent to each other, and terminals tXT-in and tXT-out are located around terminals tXT-in and tXT-out, through which voltage VSS indicating the reference potential of semiconductor integrated circuit device 200 is propagated. Terminals tVSS3 to tVSS5, tVSS9, and tVSS10 are located in the semiconductor integrated circuit device 200. Terminals tIMG2+ and tIMG2- are located adjacent to each other, and terminals tVSS5 to tVSS8, and tVSS10 through which voltage VSS indicating the reference potential of the semiconductor integrated circuit device 200 propagates are located around the terminals tIMG2+ and tIMG2-.

[0106] 16, the terminals tVSS1 to tVSS3, and tVSS9 through which the voltage VSS propagates are positioned so as to surround the terminals tIMG1+ and tIMG1−. Therefore, inside the semiconductor integrated circuit device 200, the wiring pattern pVSS through which the voltage VSS propagates is positioned around the wiring pattern pIMG1+ and the wiring pattern pIMG1−. The terminals tVSS3 to tVSS5, tVSS9, and tVSS10 through which the voltage VSS propagates are positioned so as to surround the terminals tXT-in and tXT-out. Furthermore, inside the semiconductor integrated circuit device 200, the wiring pattern pXT-in and the wiring pattern pVSS through which the voltage VSS is propagated are located around the wiring pattern pXT-in, and the terminals tVSS5 to tVSS8, tVSS10 through which the voltage VSS is propagated are positioned so as to surround the terminals tIMG2+, tIMG2-. Therefore, inside the semiconductor integrated circuit device 200, the wiring pattern pVSS through which the voltage VSS is propagated is located around the wiring pattern pIMG2+ and the wiring pattern pIMG2-.

[0107] Therefore, the semiconductor integrated circuit device 200 used in the printing device 1 in the third embodiment achieves the same effects as the semiconductor integrated circuit device 200 used in the printing device 1 in the second embodiment.

[0108] Although the embodiment and the modified examples have been described above, the present invention is not limited to these embodiments. The present invention is not limited to the above, and may be embodied in various forms without departing from the spirit and scope of the present invention. For example, the above-described embodiments may be appropriately combined.

[0109] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods and results, or configurations with the same purpose and effect). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0110] The following can be derived from the above-described embodiment and modified examples.

[0111] One aspect of the electronic device is an integrated circuit board having a USB circuit block; A first USB interface; A second USB interface; a printed circuit board on which a first connection wiring electrically connected to the first USB interface, a second connection wiring electrically connected to the second USB interface, and a source clock circuit for outputting a source clock are arranged; a ball grid array including a first ball grid, a second ball grid, and a third ball grid electrically connecting the integrated circuit board and the printed circuit board; Equipped with the first ball grid electrically connects the USB circuit block and the first USB interface via the first connection wiring; the second ball grid electrically connects the USB circuit block and the second USB interface via the second connection wiring; the third ball grid electrically connects the source clock circuit and the USB circuit block; The third ball grid is located between the first ball grid and the second ball grid.

[0112] According to this electronic device, the third ball grid through which the source clock supplied to the USB circuit block propagates can be shielded by the first ball grid electrically connecting the USB circuit block to the first USB interface and the second ball grid electrically connecting the USB circuit block to the second USB interface, thereby reducing the risk of noise such as electrical crosstalk being superimposed on the source clock supplied to the USB circuit block. Furthermore, according to this electronic device, there is no need to provide a separate terminal for shielding the third ball grid through which the source clock supplied to the USB circuit block propagates, reducing the risk of an increase in the number of ball grids connecting the printed circuit board and integrated circuit board of the electronic device, thereby reducing the risk of hindering the miniaturization of a semiconductor integrated circuit device having an integrated circuit board and a ball grid array.

[0113] In one aspect of the electronic device, the ball grid array includes a fourth ball grid and a fifth ball grid; the first ball grid propagates one signal of a pair of first differential signals supplied via the first USB interface; the second ball grid propagates one signal of a pair of second differential signals supplied via the second USB interface; the fourth ball grid propagates the other signal of the pair of first differential signals; the fifth ball grid propagates the other signal of the pair of second differential signals; the fourth ball grid is located between the first ball grid and the third ball grid; The fifth ball grid may be located between the second ball grid and the third ball grid.

[0114] According to this electronic device, the difference in the path length along which one signal and the other signal of a pair of first differential signals supplied via the first USB interface propagate can be reduced, improving the accuracy of the pair of first differential signals, and the difference in the path length along which one signal and the other signal of a pair of second differential signals supplied via the second USB interface propagate can be reduced, improving the accuracy of the pair of second differential signals.

[0115] Furthermore, according to this electronic device, the third ball grid through which the source clock supplied to the USB circuit block propagates can be shielded by the first ball grid and fourth ball grid which electrically connect the USB circuit block and the first USB interface, and the second ball grid and fifth ball grid which electrically connect the USB circuit block and the second USB interface. As a result, the risk of noise such as electrical crosstalk being superimposed on the source clock supplied to the USB circuit block can be further reduced.

[0116] In one aspect of the electronic device, the ball grid array includes a sixth ball grid; the sixth ball grid propagates a source signal for generating the source clock; The sixth ball grid may be located between the first ball grid and the third ball grid.

[0117] In one aspect of the electronic device, the ball grid array includes a seventh ball grid and an eighth ball grid; the seventh ball grid and the eighth ball grid propagate a signal of a reference potential of the USB circuit block; the seventh ball grid is located between the first ball grid and the third ball grid; The eighth ball grid may be located between the second ball grid and the third ball grid.

[0118] According to this electronic device, the seventh ball grid and the eighth ball grid, which propagate a signal of the reference potential of the USB circuit block, are located between the first ball grid and the third ball grid, and between the second ball grid and the third ball grid, thereby reducing the risk of interference between the third ball grid, which propagates the source clock supplied to the USB circuit block, and the signals propagating on the first ball grid electrically connecting the USB circuit block and the first USB interface, and the second ball grid electrically connecting the USB circuit block and the second USB interface. As a result, it is possible to further reduce the risk of noise such as electrical crosstalk being superimposed on the source clock supplied to the USB circuit block.

[0119] In one aspect of the electronic device, the ball grid array includes a ninth ball grid and a tenth ball grid; the ninth ball grid and the tenth ball grid propagate a signal of a reference potential of the USB circuit block; The first ball grid is between the ninth ball grid and the third ball grid. Located in The second ball grid may be located between the tenth ball grid and the third ball grid.

[0120] According to this electronic device, it is possible to reduce the risk of interference between a signal different from the signal supplied to the USB circuit block and the third ball grid through which the source clock supplied to the USB circuit block propagates, the first ball grid electrically connecting the USB circuit block and the first USB interface, and the second ball grid electrically connecting the USB circuit block and the second USB interface.

[0121] In one aspect of the electronic device, The USB circuit block may support a communication speed of 5 Gbps or more.

[0122] One aspect of the semiconductor integrated circuit device is A semiconductor integrated circuit device electrically connected to a printed circuit board, an integrated circuit board having a USB circuit block; a ball grid array electrically connecting the integrated circuit board and the printed circuit board; Equipped with the ball grid array includes a first ball grid, a second ball grid, and a third ball grid; the first ball grid is electrically connected to the USB circuit block; the second ball grid is electrically connected to the USB circuit block; the third ball grid propagates a source clock supplied to the USB circuit block; The third ball grid is located between the first ball grid and the second ball grid.

[0123] According to this semiconductor integrated circuit device, the third ball grid through which the source clock supplied to the USB circuit block propagates can be shielded by the first ball grid electrically connected to the USB circuit block and the second ball grid electrically connected to the USB circuit block, and as a result, the risk of noise such as electrical crosstalk being superimposed on the source clock supplied to the USB circuit block can be reduced. Furthermore, according to this semiconductor integrated circuit device, there is no need to provide a separate terminal for shielding the third ball grid through which the source clock supplied to the USB circuit block propagates, reducing the risk of impeding the miniaturization of the semiconductor integrated circuit device.

[0124] In one aspect of the semiconductor integrated circuit device, the ball grid array includes a fourth ball grid and a fifth ball grid; the first ball grid propagates one of a pair of first differential signals supplied to the USB circuit block; the second ball grid propagates one signal of a pair of second differential signals supplied to the USB circuit block; the fourth ball grid propagates the other signal of the pair of first differential signals; the fifth ball grid propagates the other signal of the pair of second differential signals; the fourth ball grid is located between the first ball grid and the third ball grid; The fifth ball grid may be located between the second ball grid and the third ball grid.

[0125] According to this semiconductor integrated circuit device, one signal and the other signal of the pair of first differential signals The difference in the path length along which each signal propagates can be reduced, improving the accuracy of the pair of first differential signals, and the difference in the path length along which each signal propagates between one signal and the other signal of the pair of second differential signals can be reduced, improving the accuracy of the pair of second differential signals.

[0126] Furthermore, according to this semiconductor integrated circuit device, the third ball grid through which the source clock supplied to the USB circuit block propagates can be shielded by the first and fourth ball grids electrically connected to the USB circuit block, and the second and fifth ball grids electrically connected to the USB circuit block, thereby further reducing the risk of noise such as electrical crosstalk being superimposed on the source clock supplied to the USB circuit block.

[0127] In one aspect of the semiconductor integrated circuit device, the ball grid array includes a sixth ball grid; the sixth ball grid propagates a source signal for generating the source clock; The sixth ball grid may be located between the first ball grid and the third ball grid.

[0128] In one aspect of the semiconductor integrated circuit device, the ball grid array includes a seventh ball grid and an eighth ball grid; the seventh ball grid and the eighth ball grid propagate a signal of a reference potential of the USB circuit block; the seventh ball grid is located between the first ball grid and the third ball grid; The eighth ball grid may be located between the second ball grid and the third ball grid.

[0129] According to this semiconductor integrated circuit device, the seventh ball grid and eighth ball grid, which propagate a signal of the reference potential of the USB circuit block, are located between the first and third ball grids, and between the second and third ball grids, thereby reducing the risk of signals propagating on the first ball grid electrically connected to the USB circuit block and the second ball grid electrically connected to the USB circuit block interfering with the third ball grid, which propagates the source clock supplied to the USB circuit block. As a result, it is possible to further reduce the risk of noise such as electrical crosstalk being superimposed on the source clock supplied to the USB circuit block.

[0130] In one aspect of the semiconductor integrated circuit device, the ball grid array includes a ninth ball grid and a tenth ball grid; the ninth ball grid and the tenth ball grid propagate a signal of a reference potential of the USB circuit block; the first ball grid is located between the ninth ball grid and the third ball grid; The second ball grid may be located between the tenth ball grid and the third ball grid.

[0131] According to this semiconductor integrated circuit device, it is possible to reduce the risk of a signal different from the signal supplied to the USB circuit block interfering with the third ball grid through which the source clock supplied to the USB circuit block propagates, the first ball grid electrically connected to the USB circuit block, and the second ball grid electrically connected to the USB circuit block.

[0132] In one aspect of the semiconductor integrated circuit device, The USB circuit block may support a communication speed of 5 Gbps or more. [Explanation of symbols]

[0133] 1...printing device, 2...external device, 3...external storage memory, 10...casing, 11,12,13,14,15,16...wall portion, 20...cover, 21,22...USB connection terminal, 23...power supply terminal, 31...supply port, 32...discharge port, 40...display unit, 41...operation unit, 50...head unit, 51...ejection head, 52...carriage, 53...liquid storage portion, 54...carriage guide shaft, 55...ejection surface, 60...transport unit, 61,62...medium support portion, 63,64...transport roller pair, 100...printed circuit board, 200...semiconductor integrated circuit device, 201...control circuit, 202...power supply circuit, 203...ejection signal output circuit, 210...CPU, 211...bus wiring, 220...USB signal communication controller, 221,222... Wiring, 230... memory controller, 231... wiring, 240... control signal communication controller, 241... wiring, 250... memory group, 260... control signal generation circuit, 261, 262... wiring, 270... source signal clock circuit, 300... base substrate, 301... terminal mounting surface, 302, 303, 304, 305... sides, 310... terminal, 321, 322, 323, 324, 325, 326, 327, 328... terminal area, 350... housing, 360... IC chip, 370... joining member, 380... bonding wire, HK... transport path, pIMG1, pIMG2, pVSS, pXT-in... wiring pattern, tIMG, tIMG1, tIMG2, tVSS1 to tVSS10, tXT-in, tXT-out... terminal

Claims

1. an integrated circuit board provided with a USB circuit block; A first USB interface; A second USB interface; a printed circuit board on which a first connection wiring electrically connected to the first USB interface, a second connection wiring electrically connected to the second USB interface, and a source clock circuit for outputting a source clock are arranged; a ball grid array including a first ball grid, a second ball grid, a third ball grid, a fourth ball grid, and a fifth ball grid electrically connecting the integrated circuit substrate and the printed circuit board; Equipped with the first ball grid electrically connects the USB circuit block and the first USB interface via the first connection wiring; the second ball grid electrically connects the USB circuit block and the second USB interface via the second connection wiring; the third ball grid electrically connects the source clock circuit and the USB circuit block; the first ball grid propagates one signal of a pair of first differential signals supplied via the first USB interface; the second ball grid propagates one signal of a pair of second differential signals supplied via the second USB interface; the fourth ball grid propagates the other signal of the pair of first differential signals; the fifth ball grid propagates the other signal of the pair of second differential signals; the first ball grid, the second ball grid, the third ball grid, the fourth ball grid, and the fifth ball grid are aligned along one direction; the third ball grid is located between the first ball grid and the second ball grid; the fourth ball grid is located between the first ball grid and the third ball grid; the fifth ball grid is located between the second ball grid and the third ball grid; 1. An electronic device comprising:

2. the ball grid array includes a sixth ball grid; the sixth ball grid propagates a source signal for generating the source clock; the sixth ball grid is located between the first ball grid and the third ball grid; 2. The electronic device according to claim 1 .

3. the ball grid array includes a seventh ball grid and an eighth ball grid; the seventh ball grid and the eighth ball grid propagate a signal of a reference potential of the USB circuit block; the seventh ball grid is located between the first ball grid and the third ball grid; the eighth ball grid is located between the second ball grid and the third ball grid; 3. The electronic device according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

4. the ball grid array includes a ninth ball grid and a tenth ball grid; the ninth ball grid and the tenth ball grid propagate a signal of a reference potential of the USB circuit block; the first ball grid is located between the ninth ball grid and the third ball grid; the second ball grid is located between the tenth ball grid and the third ball grid; 4. The electronic device according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

5. The USB circuit block supports communication speeds of 5 Gbps or more.

5. The electronic device according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

6. A semiconductor integrated circuit device electrically connected to a printed circuit board, an integrated circuit board provided with a USB circuit block; a ball grid array electrically connecting the integrated circuit board and the printed circuit board; Equipped with the ball grid array includes a first ball grid, a second ball grid, a third ball grid, a fourth ball grid, and a fifth ball grid; the first ball grid is electrically connected to the USB circuit block; the second ball grid is electrically connected to the USB circuit block; the third ball grid propagates a source clock supplied to the USB circuit block; the first ball grid propagates one of a pair of first differential signals supplied to the USB circuit block; the second ball grid propagates one of a pair of second differential signals supplied to the USB circuit block; the fourth ball grid propagates the other signal of the pair of first differential signals; the fifth ball grid propagates the other signal of the pair of second differential signals; the first ball grid, the second ball grid, the third ball grid, the fourth ball grid, and the fifth ball grid are aligned along one direction; the third ball grid is located between the first ball grid and the second ball grid; the fourth ball grid is located between the first ball grid and the third ball grid; the fifth ball grid is located between the second ball grid and the third ball grid; A semiconductor integrated circuit device comprising:

7. the ball grid array includes a sixth ball grid; the sixth ball grid propagates a source signal for generating the source clock; the sixth ball grid is located between the first ball grid and the third ball grid; 7. The semiconductor integrated circuit device according to claim 6.

8. the ball grid array includes a seventh ball grid and an eighth ball grid; the seventh ball grid and the eighth ball grid propagate a signal of a reference potential of the USB circuit block; the seventh ball grid is located between the first ball grid and the third ball grid; the eighth ball grid is located between the second ball grid and the third ball grid; 8. The semiconductor integrated circuit device according to claim 6, wherein the first and second electrodes are electrically connected to each other.

9. the ball grid array includes a ninth ball grid and a tenth ball grid; the ninth ball grid and the tenth ball grid propagate a signal of a reference potential of the USB circuit block; the first ball grid is located between the ninth ball grid and the third ball grid; the second ball grid is located between the tenth ball grid and the third ball grid; 9. The semiconductor integrated circuit device according to claim 6, wherein the first and second electrodes are electrically connected to each other.

10. The USB circuit block supports communication speeds of 5 Gbps or more.

10. The semiconductor integrated circuit device according to claim 6, wherein the first and second electrodes are electrically connected to each other.

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