Semiconductor Device

Abstract

To provide a semiconductor device which can suppress a temperature rise of a conductive layer of a wiring board when high-frequency current is energized to the conductive layer.SOLUTION: A semiconductor device includes: a wiring board 20 which has a first insulation layer 21a, a first conductive layer 22a arranged on one main surface side of the first insulation layer 21a, a second conductive layer 23a arranged on the other main surface side of the first insulation layer 21a, a magnetic layer 24 which is arranged between the first insulation layer 21a and the first conductive layer 22a or the second conductive layer 23a and has a relative magnetic permeability higher than those of the first and second conductive layers 22a and 23a, and a carbon layer 27 which is arranged between the first insulation layer 21a and the first conductive layer 22a or the second conductive layer 23a and has thermal conductivity higher than those of the first and second conductive layers 22a and 23a in at least a surface direction; a semiconductor chip 3 which is electrically connected to the first and second conductive layers 22a and 23a; and an insulation circuit board 10 which is arranged to be separated from the wiring board 20 and in which the semiconductor chip 3 is mounted.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device (semiconductor module). [Background technology]

[0002] As a semiconductor device used in a power conversion device or the like, a semiconductor device is known in which a plurality of semiconductor elements mounted on an insulating circuit board are electrically connected to each other via a printed circuit board (see Patent Document 1). The semiconductor device described in Patent Document 1 uses a wiring board in which an insulating plate is sandwiched between a first conductive layer and a second conductive layer, and current is passed through each of the first and second conductive layers to increase the amount of current passing.

[0003] Patent Document 2 discloses that a transmission line structure chip built into a low-pass filter is composed of a first double-layer metal foil, a second double-layer metal foil, and an insulator layer formed between the first and second double-layer metal foils, and further discloses a configuration in which a graphite layer and a silver paste layer are arranged in this order around the outer periphery of an enameled copper wire. Patent Document 3 discloses a power module that includes an insulating substrate, a semiconductor device arranged on the insulating substrate, and a graphite plate with anisotropic thermal conductivity, one end of which is connected to the surface side of the semiconductor device and the other end of which is connected to the insulating substrate, and that transmits heat from the surface side of the semiconductor device to the insulating substrate via the graphite plate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2014 / 061211 [Patent Document 2] JP 2011-176558 A [Patent Document 3] JP 2019-71399 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device described in Patent Document 1, when a high-frequency current (pulse current) is applied to each of the first and second conductive layers of the wiring board, a skin effect occurs in which a current flows only near the surface of each of the first and second conductive layers. This skin effect increases the circuit resistance of the first and second conductive layers, which increases Joule heat in the first and second conductive layers, raising concerns about a rise in temperature of the first and second conductive layers. If the temperature rise of the first and second conductive layers is large, it is necessary to increase the area of ​​the first and second conductive layers, which prevents miniaturization of the wiring board and, ultimately, prevents miniaturization of the semiconductor device.

[0006] In view of the above problems, an object of the present invention is to provide a semiconductor device capable of suppressing a temperature rise in a conductive layer of a wiring board when a high frequency current is passed through the conductive layer. [Means for solving the problem]

[0007] One aspect of the present invention is summarized as a semiconductor device comprising: (a) a wiring board including a first insulating layer, a first conductive layer arranged on one main surface side of the first insulating layer, a second conductive layer arranged on the other main surface side of the first insulating layer, a magnetic layer arranged between the first insulating layer and the first or second conductive layer, the magnetic layer having a higher relative magnetic permeability than the first and second conductive layers, and a carbon layer arranged between the first insulating layer and the first or second conductive layer, the carbon layer having a higher thermal conductivity at least in the planar direction than the first and second conductive layers; (b) a semiconductor chip electrically connected to the first and second conductive layers; and (c) an insulating circuit board arranged spaced apart from the wiring board and carrying the semiconductor chip. Effect of the Invention

[0008] According to the present invention, it is possible to provide a semiconductor device capable of suppressing a temperature rise in a conductive layer of a wiring board when a high frequency current is passed through the conductive layer. [Brief description of the drawings]

[0009] [Figure 1]1 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention; [Diagram 2] 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. [Diagram 3] 2 is a schematic cross-sectional view taken along line III-III in FIG. 1. [Figure 4] 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 1. [Diagram 5] 1 is a schematic plan view showing an arrangement of semiconductor chips according to an embodiment of the present invention; [Figure 6] 1 is a schematic plan view showing a plane pattern of a conductive layer of a wiring board according to an embodiment of the present invention; [Figure 7] 1 is a schematic development view showing a configuration of a wiring board according to an embodiment of the present invention; [Figure 8] 1 is a schematic plan view showing a planar pattern of a magnetic layer of a wiring board according to an embodiment of the present invention. [Figure 9] 2 is a schematic plan view showing a planar pattern of a carbon layer of a wiring board according to an embodiment of the present invention. FIG. [Figure 10] 1 is a graph showing the relationship between high-frequency current passed through a conductive layer of a wiring substrate of a conventional semiconductor device and circuit resistance. [Figure 11] 11 is a graph showing evaluation results of heat generation temperatures of wiring substrates of semiconductor devices according to examples and comparative examples of the present invention. [Figure 12] FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 13] FIG. 11 is a schematic cross-sectional view showing a semiconductor device according to a second modified example of the embodiment of the present invention. [Figure 14] FIG. 11 is a schematic cross-sectional view showing a semiconductor device according to a third modified example of the embodiment of the present invention. [Figure 15] FIG. 11 is a schematic cross-sectional view showing a semiconductor device according to a fourth modified example of the embodiment of the present invention. [Figure 16] FIG. 11 is a schematic cross-sectional view showing a semiconductor device according to a fifth modified example of the embodiment of the present invention. [Figure 17] FIG. 13 is a schematic cross-sectional view showing a semiconductor device according to a sixth modified example of the embodiment of the present invention. [Figure 18] FIG. 13 is a schematic cross-sectional view showing a semiconductor device according to a seventh modified example of the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiment and the first to seventh modified examples will be described with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships and ratios. Moreover, the following embodiment and the first to seventh modified examples are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0011] In the following embodiment and first to seventh modifications, the term "first main electrode" refers to an electrode that serves as an emitter electrode or collector electrode in an insulated gate bipolar transistor (IGBT), and an electrode that serves as a source electrode or drain electrode in a field effect transistor (FET) or a static induction transistor (SIT). In addition, the term "second main electrode" refers to an electrode that serves as an emitter electrode or collector electrode that is not the first main electrode in an IGBT, and an electrode that serves as a source electrode or drain electrode that is not the first main electrode in a FET or a SIT. In the following embodiment and first to seventh modifications, a MOSFET is exemplified as a transistor element, and therefore the first main electrode will be described as a drain electrode and the second main electrode as a source electrode.

[0012] In addition, in the following embodiment and first to seventh modified examples, of the three directions that are mutually orthogonal in space, a first direction and a second direction that are mutually orthogonal in the same plane are defined as an X direction and a Y direction, respectively, and a third direction that is orthogonal to each of the first direction and the second direction is defined as a Z direction.

[0013] (Embodiment) Fig. 1 shows a plan view of a semiconductor device 1 according to an embodiment of the present invention. A cross-sectional structure taken along line II-II in Fig. 1 is shown in Fig. 2, a cross-sectional structure taken along line III-III in Fig. 1 is shown in Fig. 3, and a cross-sectional structure taken along line IV-IV in Fig. 1 is shown in Fig. 4.

[0014] 2 to 4, a semiconductor device 1 according to an embodiment of the present invention includes a substrate laminate 2 and a resin sealing body 8 that seals the substrate laminate 2. The substrate laminate 2 includes an insulating circuit board 10, a semiconductor chip 3 mounted on the insulating circuit board 10, and a wiring board 20 that faces the chip mounting surface of the insulating circuit board 10 and is disposed spaced apart from the semiconductor chip 3. Furthermore, the substrate laminate 2 includes a first conductive post 5a, a second conductive post 5b, a third conductive post 5c, a first main circuit terminal 7a, a second main circuit terminal 7b, and a control terminal 7c.

[0015] The resin sealing body 8 is made of, for example, an epoxy-based thermosetting insulating resin. The resin sealing body 8 is molded, for example, by a transmolding method. As shown in FIG. 1, the resin sealing body 8 has a rectangular shape in a plan view, and has one short side 8a and the other short side 8b located opposite to each other in the longitudinal direction which is the X direction (first direction), and one long side 8c and the other long side 8d located opposite to each other in the lateral direction which is the Y direction (second direction) perpendicular to the X direction. The resin sealing body 8 has a thickness in the Z direction (third direction) perpendicular to the X direction and the Y direction (see FIGS. 2 to 4).

[0016] 2 to 4, insulating circuit board 10 has insulating plate 11, conductive plate 12 arranged on one main surface of insulating plate 11, and heat sink plate 13 arranged on the other main surface opposite to the one main surface of insulating plate 11. Conductive plate 12 includes first conductive plate 12a and second conductive plate 12b which are insulated and separated from each other.

[0017] The insulating circuit board 10 may be, for example, a direct copper bonded (DCB) board in which copper is eutectic-bonded to one main surface and the other main surface of a ceramic board, or an AMB board in which metal is disposed by active metal brazing (AMB) on one main surface and the other main surface of a ceramic board. The insulating plate 11 may be made of, for example, silicon nitride (Si3N4), aluminum nitride (AlN), alumina (Al2O3), or the like. The conductive plate 12 and the heat sink 13 are made of, for example, copper (Cu), which has excellent electrical and thermal conductivity, as a metal material.

[0018] As shown in FIG. 5, the insulating plate 11 of the insulating circuit board 10 has a shape, for example, a rectangle in a plan view, and is arranged such that the extension direction of two short sides 11a, 11b located opposite each other in the longitudinal direction, which is the X direction, coincides with the extension direction of two short sides 8a, 8b of the resin sealing body 8, and the extension direction of two long sides 11c, 11d located opposite each other in the lateral direction, which is the Y direction, coincides with the extension direction of two long sides 8c, 8d of the resin sealing body 8.

[0019] The first conductive plate 12a of the insulating circuit board 10 has a solid pattern having a rectangular shape in plan view, for example, and is arranged biased toward one short side 11b of the insulating plate 11 (one short side of the insulating circuit board 10) with its longitudinal direction coinciding with the X direction. The second conductive plate 12b has a solid pattern having a rectangular shape in plan view, for example, and is arranged biased toward the other short side 11a of the insulating plate 11 (the other short side of the insulating circuit board 10) with its longitudinal direction coinciding with the Y direction. The first conductive plate 12a has an area several times larger than that of the second conductive plate 12b.

[0020] Although not shown in detail, heat sink 13 has a solid pattern having a rectangular shape in a plan view, for example, and is disposed inside insulating plate 11 with its longitudinal direction coinciding with the X-direction. In the embodiment, the surface of heat sink 13 becomes the other main surface of insulating circuit board 10, and the surface of heat sink 13 (the other main surface of insulating circuit board 10) is exposed from the other main surface of resin encapsulant 8 opposite to the one main surface.

[0021] 5, the number of semiconductor chips 3 is not limited, but for example, four are arranged. Two of the four semiconductor chips 3 are arranged on one long side 11c of the insulating plate 11 at a predetermined interval along the long side 11c. The remaining two semiconductor chips 3 are arranged on the other long side 11d of the insulating plate 11 at a predetermined interval along the long side 11d.

[0022] Transistor elements are mounted on the semiconductor chip 3. One switching element is configured by connecting the transistor elements of the four semiconductor chips 3 in parallel. As the transistor element, a vertical semiconductor element having an insulated gate structure such as MOSFET or IGBT, in which a main current flows in the depth direction of the semiconductor chip 3, is suitable.

[0023] In the embodiment, a vertical MOSFET with an insulated gate structure mainly made of a semiconductor substrate made of silicon carbide (SiC) is used as a transistor element. The semiconductor substrate may be, for example, a silicon (Si) substrate, or a wide band gap semiconductor substrate such as gallium nitride (GaN) or gallium oxide (Ga2O3).

[0024] As shown in Figures 2, 3 and 5, the semiconductor chip 3 has, for example, a source electrode 3s as a second main electrode and a gate electrode 3g as a control electrode on one of two main surfaces located opposite each other, and a drain electrode 3d as a first main electrode on the other main surface.

[0025] 2 and 3, the drain electrodes 3d of the semiconductor chips 3 are joined and electrically and mechanically connected to the first conductive plate 12a via a joining material 15 such as solder. The four semiconductor chips 3 are mounted on one main surface of the insulating circuit board 10 with their respective drain electrodes 3d connected in parallel to each other.

[0026] 2 to 4, wiring board 20 faces one main surface (chip mounting surface) of insulating circuit board 10 and is disposed spaced apart from semiconductor chip 3. Wiring board 20 is supported by insulating circuit board 10 via first conductive post 5a, second conductive post 5b, third conductive post 5c, and semiconductor chip 3.

[0027] As shown in FIG. 6, the wiring board 20 has a rectangular shape in a plan view, for example, and is arranged such that the extension direction of two short sides 20a, 20b located opposite each other in the longitudinal direction, which is the X direction, coincides with the extension direction of two short sides 8a, 8b of the resin sealing body 8, and the extension direction of two long sides 20c, 20d located opposite each other in the lateral direction, which is the Y direction, coincides with the extension direction of two long sides 8c, 8d of the resin sealing body 8.

[0028] 2 to 4, 6 and 7, the wiring board 20 includes an insulating plate 21 having one and the other main surfaces located opposite to each other, a first conductive layer 22a and a first gate wiring 22b arranged on one main surface side of the insulating plate 21, and a second conductive layer 23a and a second gate wiring 23b arranged on the other main surface side of the insulating plate 21. Note that in FIG. 7, the first gate wiring 22b and the second gate wiring 23b shown in FIG. 6, the openings 24a and 24b of the magnetic layer 24, the openings 27a and 27b of the carbon layer 27, the through holes 25a and 25b, etc. are not shown.

[0029] The wiring board 20 includes a magnetic layer (magnetic sheet) 24 made of a magnetic material having a higher relative magnetic permeability (maximum) than the first conductive layer 22a and the second conductive layer 23a, and a carbon layer 27 embedded in the insulating plate 21 and having a higher thermal conductivity than the first conductive layer 22a and the second conductive layer 23a. In the embodiment, the magnetic layer 24 and the carbon layer 27 are arranged in a laminated manner.

[0030] The first conductive layer 22a and the first gate wiring 22b are formed by patterning the first conductive layer provided on one main surface side of the insulating plate 21 into a predetermined pattern. The second conductive layer 23a and the second gate wiring 23b are formed by patterning the second conductive layer provided on the other main surface side of the insulating plate 21 into a predetermined pattern. The first conductive layer 22a, the first gate wiring 22b, the second conductive layer 23a, and the second gate wiring 23b have a thickness of, for example, about 75 μm. The first conductive layer 22a, the first gate wiring 22b, the second conductive layer 23a, and the second gate wiring 23b are formed of, for example, copper foil or an alloy foil mainly composed of copper.

[0031] The first conductive layer 22a and the first gate wiring 22b are formed in the same pattern as the second conductive layer 23a and the second gate wiring 23b. Therefore, the planar patterns of the first conductive layer 22a and the first gate wiring 22b are illustrated in Fig. 6 and explained, and the illustration and explanation of the planar patterns of the second conductive layer 23a and the second gate wiring 23b are omitted.

[0032] As shown in FIG. 6, the first conductive layer 22a is formed of, for example, a rectangular solid pattern in a plan view, and is disposed in the center of the insulating plate 21 such that the longitudinal direction coincides with the X direction. For example, two first gate wirings 22b are provided. One gate wiring 22b is disposed between one long side 20c of the wiring board 20 and the first conductive layer 22a, and extends in the X direction. The other gate wiring 22b is disposed between the other long side 20d of the wiring board 20 and the first conductive layer 22a, and extends in the X direction. The two gate wirings 22b are separated from the first conductive layer 22a and are electrically insulated and separated from each other.

[0033] The second conductive layer 23a and the second gate wiring 23b are formed in the same pattern as the first conductive layer 22a and the first gate wiring 22b, and overlap with the first conductive layer 22a and the first gate wiring 22b in a plan view. The two second gate wirings 23b are spaced apart from the second conductive layer 23a and are electrically insulated and separated from each other. The first conductive layer 22a and the second conductive layer 23a are used as a current path for passing a main circuit current.

[0034] As shown in Figs. 2 to 4, 6 and 7, the insulating plate 21 has a first insulating layer 21a disposed on the first conductive layer 22a side of the magnetic layer 24 and the carbon layer 27 and having a planar size larger than that of the magnetic layer 24 and the carbon layer 27, a second insulating layer 21b disposed on the second conductive layer 23a side of the magnetic layer 24 and the carbon layer 27 and having a planar size larger than that of the magnetic layer 24 and the carbon layer 27, and a third insulating layer 21c disposed between the first insulating layer 21a and the second insulating layer 21b so as to surround the magnetic layer 24 and the carbon layer 27. The first insulating layer 21a, the second insulating layer 21b and the third insulating layer 21c are formed of a resin sheet made of, for example, a polyimide resin having excellent insulating properties and heat resistance. The third insulating layer 21c may be formed of, for example, an insulating adhesive material. The first insulating layer 21a, the second insulating layer 21b, and the third insulating layer 21c are integrated with the magnetic layer 24 and the carbon layer 27 by, for example, thermocompression bonding.

[0035] That is, the magnetic layer 24 and the carbon layer 27 are embedded in the insulating plate 21 including the first insulating layer 21a, the second insulating layer 21b, and the third insulating layer 21c. One main surface of the magnetic layer 24 on the second conductive layer 23a side is in contact with one main surface of the second insulating layer 21b, and the other main surface of the magnetic layer 24 on the first conductive layer 22a side is in contact with one main surface of the carbon layer 27 on the second conductive layer 23a side. The other main surface of the carbon layer 27 on the first conductive layer 22a side is in contact with the other main surface of the first insulating layer 21a.

[0036] 2 to 4, 7 and 8, the magnetic layer 24 has an outline 24m in plan view that is flush with the outline 22a1 of the first conductive layer 22a and the outline 23a1 of the second conductive layer 23a, or is located inside the outline 22a1 of the first conductive layer 22a and the outline 23a1 of the second conductive layer 23a. In the embodiment, the outline 24m of the magnetic layer 24 is flush with the outline 22a1 of the first conductive layer 22a and the outline 23a1 of the second conductive layer 23a. In other words, the outer peripheral end of the magnetic layer 24 in plan view is aligned with the outer peripheral end of each of the first conductive layer 22a and the second conductive layer 23a.

[0037] The relative magnetic permeability of the magnetic layer 24 is preferably about 5 to 500,000, more preferably about 600 to 500,000. Specific materials of the magnetic layer 24 are preferably stainless steel foil, nickel foil, amorphous foil (composition Fe-Si-B or Co-Fe-Si-BM), permalloy foil (composition Fe-50Ni or Fe-80Ni), Finemet (registered trademark) foil (manufactured by Hitachi Metals, Ltd., composition Fe-Cu-Nb-Si-B), etc. It is more preferable that the magnetic layer 24 is formed of a magnetic material having a higher relative magnetic permeability than copper foil or alloy foil mainly composed of copper. The magnetic layer 24 may be, for example, in the form of a sheet. Alternatively, the magnetic layer 24 may be formed by plating, sputtering, deposition, or the like.

[0038] The thickness of the magnetic layer 24 is preferably 1 μm to 50 μm, more preferably 10 μm to 50 μm. By making the thickness of the magnetic layer 24 50 μm or less, it is possible to prevent the magnetic layer 24 itself from generating heat due to eddy currents flowing in the magnetic layer 24. Furthermore, by making the thickness of the magnetic layer 24 10 μm or more, it is possible to prevent magnetic saturation of the magnetic layer 24 when a large current flows through the first conductive layer 22a and the second conductive layer 23a. Even if the thickness of the magnetic layer 24 is thin, the withstand voltage between the first conductive layer 22a and the second conductive layer 23a can be ensured by adjusting the thicknesses of the first insulating layer 21a and the second insulating layer 21b.

[0039] 2 to 4, 7 and 9, the carbon layer 27 has a contour 27m in plan view that is flush with the contour 22a1 of the first conductive layer 22a and the contour 23a1 of the second conductive layer 23a, or is located inside the contour 22a1 of the first conductive layer 22a and the contour 23a1 of the second conductive layer 23a. In the embodiment, the contour 27m of the carbon layer 27 coincides with the contour 24m of the magnetic layer 24 and is flush with the contour 22a1 of the first conductive layer 22a and the contour 23a1 of the second conductive layer 23a. In other words, the outer peripheral end of the carbon layer 27 in plan view is aligned with the outer peripheral end of each of the first conductive layer 22a and the second conductive layer 23a.

[0040] The contour 27m of the carbon layer 27 does not necessarily have to coincide with the contour 24m of the magnetic layer 24, and the contour 27m of the carbon layer 27 may be located inside or outside the contour 24m of the magnetic layer 24. The thickness of the carbon layer 27 may be the same as the thickness of the magnetic layer 24, or may be thicker or thinner than the magnetic layer 24.

[0041] The thermal conductivity of the carbon layer 27 at least in the planar directions (X direction and Y direction) is higher than the thermal conductivity of the first conductive layer 22a and the second conductive layer 23a (for example, approximately 400 W / mK, which is the thermal conductivity of copper). As the carbon layer 27, for example, a layer containing carbon, such as sheet-like graphite (graphite sheet) or graphene (graphene sheet), can be used. The carbon layer 27 may be made of carbon fiber or a composite material using carbon fiber. For example, examples of the composite material using carbon fiber include carbon fiber reinforced plastic (CFRP) and carbon fiber reinforced carbon composite material. For example, the sheet-like carbon layer 27 may be bonded to the magnetic layer 24 by an adhesive.

[0042] Graphene is a sheet-like material of one atomic layer in which carbon atoms are bonded, and graphite is made of a laminated structure of multiple graphene sheets. Graphite or graphene has anisotropy in thermal conductivity. When graphite or graphene is used for the carbon layer 27, if a material having a higher thermal conductivity (e.g., about 1500 W / mK) in the planar direction (X direction and Y direction) than the thermal conductivity (e.g., about 5 W / mK) in the thickness direction (Z direction) of the carbon layer 27 is used, heat can be instantly diffused in the planar direction of the carbon layer 27.

[0043] Here, since floating capacitance is added when the magnetic layer 24 and the carbon layer 27 are in an electrically floating state, it is preferable to set the magnetic layer 24 and the carbon layer 27 to the same potential as the first conductive layer 22a and the second conductive layer 23a. In the embodiment, as shown in Fig. 2, the magnetic layer 24 and the carbon layer 27 are electrically connected to the first conductive layer 22a via the through-hole wiring 26, and are set to the same potential as the first conductive layer 22a and the second conductive layer 23a.

[0044] 2, one end of the first conductive post 5a is electrically and mechanically connected to the source electrode 3s of the semiconductor chip 3 by a bonding material 16 such as solder, and the other end penetrates the wiring board 20 to be fixed to the wiring board 20 and is electrically and mechanically connected to the first conductive layer 22a and the second conductive layer 23a. That is, one end of the first conductive post 5a is fixed to the insulating circuit board 10 via the semiconductor chip 3, and the other end of the first conductive post 5a is fixed to the wiring board 20. The number of first conductive posts 5a is not limited, but for example, two are provided for each semiconductor chip 3.

[0045] 2, one end of the second conductive post 5b is electrically and mechanically connected to the second conductive plate 12b of the insulating circuit board 10 by a bonding material 16 such as solder, and the other end penetrates the wiring board 20 to be fixed to the wiring board 20 and is electrically and mechanically connected to the first conductive layer 22a and the second conductive layer 23a. That is, one end of the second conductive post 5b is fixed to the insulating circuit board 10, and the other end of the second conductive post 5b is fixed to the wiring board 20. The number of second conductive posts 5b is not limited, but may be, for example, two.

[0046] 3, one end of the third conductive post 5c is electrically and mechanically connected to the gate electrode 3g of the semiconductor chip 3 by a bonding material 16 such as solder, and the other end is fixed through the wiring board 20 and is electrically and mechanically connected to the first gate wiring 22b and the second gate wiring 23b. That is, one end of the third conductive post 5c is fixed to the insulating circuit board 10 via the semiconductor chip 3, and the other end of the third conductive post 5c is fixed to the wiring board 20. The number of third conductive posts 5c is not limited, but for example, one is provided for each semiconductor chip 3.

[0047] 1 to 4, each of the first main circuit terminal 7a, the second main circuit terminal 7b, and the control terminal 7c is sealed with a resin sealing body 8 except for a portion thereof, and a portion thereof protrudes to the outside of the resin sealing body 8. That is, each of the first main circuit terminal 7a, the second main circuit terminal 7b, and the control terminal 7c extends from the inside to the outside of the resin sealing body 8 in the thickness direction (Z direction) of the resin sealing body 8. Each of the first main circuit terminal 7a, the second main circuit terminal 7b, and the control terminal 7c is formed of a conductive pin.

[0048] 2, one end of the first main circuit terminal 7a is electrically and mechanically connected to the first conductive plate 12a of the insulating circuit board 10 by a bonding material 16 such as solder, an intermediate portion thereof passes through the through hole 25a of the wiring board 20, and the other end thereof protrudes from one main surface of the resin sealing body 8. One end of the second main circuit terminal 7b is electrically and mechanically connected to the second conductive plate 12b of the insulating circuit board 10 by a bonding material 16 such as solder, an intermediate portion thereof passes through the through hole 25b of the wiring board 20, and the other end thereof protrudes from one main surface of the resin sealing body 8.

[0049] That is, the first main circuit terminal 7a is electrically connected to the drain electrode 3d of the semiconductor chip 3 via the bonding material 16, the first conductive plate 12a of the insulating circuit board 10, and the bonding material 15. The source electrode 3s of the semiconductor chip 3 is electrically connected to the second main circuit terminal 7b via the bonding material 16, the first conductive post 5a, the first conductive layer 22a and the second conductive layer 23a of the wiring board 20, the second conductive post 5b, the bonding material 16, the second conductive plate 12b of the insulating circuit board 10, and the bonding material 16. The source electrodes 3s of the four semiconductor chips 3 are connected in parallel to each other via the first conductive layer 22a and the second conductive layer 23a of the wiring board 20. The number of the first main circuit terminals 7a and the second main circuit terminals 7b is not limited, but for example, two each are provided.

[0050] 3, one end of the control terminal 7c penetrates the wiring board 20 from one main surface side of the wiring board 20, and the other end protrudes from one main surface of the resin sealing body 8. That is, the control terminal 7c is electrically connected to the gate electrode 3g of the semiconductor chip 3 via the first gate wiring 22b and the second gate wiring 23b of the wiring board 20, the third conductive post 5c, and the bonding material 16. The number of the control terminals 7c is not limited, but for example, two are provided corresponding to the first gate wiring 22b and the second gate wiring 23b. The gate electrodes 3g of the four semiconductor chips 3 are connected in parallel to each other via the first gate wiring 22b and the second gate wiring 23b of the wiring board 20.

[0051] 2 and 8, the magnetic layer 24 has an opening 24a wider than the diameter of the first conductive post 5a at a portion where the first conductive post 5a passes in order to avoid contact with the first conductive post 5a, and the sidewall of the opening 24a of the magnetic layer 24 is spaced apart from the first conductive post 5a. The magnetic layer 24 has an opening 24b wider than the diameter of the second conductive post 5b at a portion where the second conductive post 5b passes in order to avoid contact with the second conductive post 5b, and the sidewall of the opening 24b of the magnetic layer 24 is spaced apart from the second conductive post 5b.

[0052] 2 and 9, the carbon layer 27 has an opening 27a wider than the diameter of the first conductive post 5a at a portion through which the first conductive post 5a passes, in order to avoid contact with the first conductive post 5a, and the sidewall of the opening 27a of the carbon layer 27 is spaced apart from the first conductive post 5a. The carbon layer 27 has an opening 27b wider than the diameter of the second conductive post 5b at a portion through which the second conductive post 5b passes, in order to avoid contact with the second conductive post 5b, and the sidewall of the opening 27b of the carbon layer 27 is spaced apart from the second conductive post 5b.

[0053] <Main circuit current of semiconductor device> Next, the flow of main circuit current in the semiconductor device 1 according to the embodiment of the present invention will be described with reference to Figures 2, 3 and 6. By applying a control voltage from the control terminal 7c to the gate electrodes 3g of each of the four semiconductor chips 3 via the first gate wiring 22b and the second gate wiring 23b of the wiring substrate 20, the transistor elements of each of the four semiconductor chips 3 are brought into a conducting state.

[0054] The main circuit current flows vertically from the first main circuit terminal 7a through the first conductive plate 12a of the insulating circuit board 10, from the drain electrode 3d of each of the four semiconductor chips 3 to the source electrode 3s of each of the four semiconductor chips 3. Furthermore, the main circuit current flows from the source electrode 3s of each of the four semiconductor chips 3 through the first conductive layer 22a and the second conductive layer 23a of the wiring board 20 via the first conductive post 5a. Furthermore, the main circuit current flows through the second conductive post 5b and the second conductive plate 12b of the insulating circuit board 10 to the second main circuit terminal 7b.

[0055] At this time, in the wiring board 20, the main circuit current flows through both the first conductive layer 22a and the second conductive layer 23a, so that the amount of current flowing through the main circuit current can be increased. Also, the main circuit current flows in the direction of the arrow N1 in the first conductive layer 22a, and flows in the direction of the arrow N2 in the second conductive layer 23a. That is, the main circuit current flows in the same direction (arrows N1 and N2) through both the first conductive layer 22a and the second conductive layer 23a.

[0056] <Effects of the embodiment> In the semiconductor device 1 according to the embodiment of the present invention, when the main circuit current is a high-frequency current (pulse current), a magnetic field is generated from both the first conductive layer 22a and the second conductive layer 23a, and an eddy current is generated in a direction that suppresses the generation of the magnetic field. The eddy current is in the opposite direction to the current flowing through the center of the first conductive layer 22a and the second conductive layer 23a, and the eddy current cancels out the current flowing through the center of the first conductive layer 22a and the second conductive layer 23a, resulting in a skin effect in which a current flows only near the surface of the first conductive layer 22a and the second conductive layer 23a. In addition, since the currents flowing through the first conductive layer 22a and the second conductive layer 23a are in the same direction, the first conductive layer 22a and the second conductive layer 23a repel each other due to the magnetic fields generated by both the first conductive layer 22a and the second conductive layer 23a, resulting in a proximity effect in which a current flows to the outside that is not close to each other.

[0057] Here, when the wiring board is a normal printed circuit board in which a single insulating layer is sandwiched between first and second conductive layers, as in conventional semiconductor devices, there is a concern that the circuit resistance of the first and second conductive layers will increase due to the above-mentioned skin effect and proximity effect, as shown in FIG. 10, and Joule heat will increase in the first and second conductive layers.

[0058] In contrast, according to the semiconductor device 1 according to the embodiment of the present invention, a magnetic layer 24 made of a magnetic material having a higher relative magnetic permeability than the first conductive layer 22a and the second conductive layer 23a is provided between the first conductive layer 22a and the second conductive layer 23a of the wiring board 20. As a result, the magnetic fields generated from both the first conductive layer 22a and the second conductive layer 23a are taken in by the magnetic layer 24, so that the skin effect and the proximity effect can be suppressed. As a result, the circuit resistance of the first conductive layer 22a and the second conductive layer 23a in the high frequency range is reduced, and Joule heat generation in the first conductive layer 22a and the second conductive layer 23a of the wiring board 20 can be suppressed, so that the temperature rise of the first conductive layer 22a and the second conductive layer 23a can be suppressed. As a result, the wiring board 20 can be miniaturized, and thus the semiconductor device 1 can be miniaturized.

[0059] Furthermore, by providing the carbon layer 27, which has a higher thermal conductivity than the first conductive layer 22a and the second conductive layer 23a, between the first conductive layer 22a and the second conductive layer 23a of the wiring board 20, the heat trapped in the wiring board 20 can be diffused through the carbon layer 27, thereby improving the heat dissipation (thermal diffusivity) of the wiring board 20. As a result, the temperature rise of the first conductive layer 22a and the second conductive layer 23a can be suppressed.

[0060] Furthermore, the carbon layer 27 captures the magnetic field generated by the first conductive layer 22a and the second conductive layer 23a, thereby further suppressing the proximity effect and the skin effect. As a result, the circuit resistance of the first conductive layer 22a and the second conductive layer 23a in the high frequency range is further reduced, and Joule heat generation in the first conductive layer 22a and the second conductive layer 23a of the wiring board 20 can be further suppressed, thereby further suppressing the temperature rise of the first conductive layer 22a and the second conductive layer 23a.

[0061] Furthermore, when the contour 24m of the magnetic layer 24 and the contour 27m of the carbon layer 27 are located outside the contour 22a1 of the first conductive layer 22a and the contour 23a1 of the second conductive layer 23a in plan view, the portions of the magnetic layer 24 and the carbon layer 27 that protrude outside the first conductive layer 22a and the second conductive layer 23a generate Joule heat due to eddy currents. In contrast, in the wiring board 20 of the embodiment, the contour 24m of the magnetic layer 24 and the contour 27m of the carbon layer 27 are located flush with the contour 22a1 of the first conductive layer 22a and the contour 23a1 of the second conductive layer 23a in plan view or are located inside the contour 22a1 of the first conductive layer 22a and the contour 23a1 of the second conductive layer 23a, thereby suppressing Joule heat of the magnetic layer 24 and the carbon layer 27 caused by eddy currents.

[0062] 11 shows the results of measuring the heat generation temperature in the wiring board for an example of the semiconductor device 1 according to the embodiment and a comparative example in which the wiring board is a normal printed circuit board in which a single insulating layer is sandwiched between a first conductive layer and a second conductive layer. As shown in FIG. 11, the heat generation temperature in the wiring board is obviously lower in the example than in the comparative example. Therefore, it was confirmed that the semiconductor device 1 according to the embodiment can suppress Joule heat generation in the first conductive layer 22a and the second conductive layer 23a.

[0063] (First Modification) As shown in Fig. 12, the semiconductor device 1 according to the first modified example of the embodiment of the present invention differs from the semiconductor device 1 according to the embodiment of the present invention shown in Fig. 2 in that the positions of the magnetic layer 24 and the carbon layer 27 are reversed. One main surface of the magnetic layer 24 contacts one main surface of the carbon layer 27, and the other main surface of the magnetic layer 24 contacts one main surface of the first insulating layer 21a. The other main surface of the carbon layer 27 contacts one main surface of the second insulating layer 21b. The other configuration of the semiconductor device 1 according to the first modified example is similar to that of the semiconductor device 1 according to the embodiment of the present invention, so a duplicated description will be omitted.

[0064] According to the semiconductor device 1 of the first modification, even if the positions of the magnetic layer 24 and the carbon layer 27 are reversed, the same effects as those of the semiconductor device 1 according to the embodiment of the present invention can be achieved.

[0065] (Second Modification) As shown in Fig. 13, the semiconductor device 1 according to the second modification of the embodiment of the present invention is different from the semiconductor device 1 according to the embodiment of the present invention shown in Fig. 2 in that there is no second insulating layer 21b. The other main surface of the magnetic layer 24 is in contact with the second conductive layer 23a. Since the first insulating layer 21a is disposed between the first conductive layer 22a and the second conductive layer 23a, insulation between the first conductive layer 22a and the second conductive layer 23a is maintained. The other configuration of the semiconductor device 1 according to the second modification is similar to that of the semiconductor device 1 according to the embodiment of the present invention, and therefore a duplicated description will be omitted.

[0066] The semiconductor device according to the second modification provides the same effects as the semiconductor device 1 according to the embodiment of the present invention, even when the second insulating layer 21b is not provided and the magnetic layer 24 is in contact with the second conductive layer 23a. Note that the semiconductor device 1 according to the embodiment of the present invention shown in FIG. 2 provides the same effects when the first insulating layer 21a is not provided and one main surface of the carbon layer 27 is in contact with the first conductive layer 22a.

[0067] (Third Modification) As shown in Fig. 14, the semiconductor device 1 according to the third modification of the embodiment of the present invention is different from the semiconductor device 1 according to the embodiment of the present invention shown in Fig. 2 in that the second insulating layer 21b is not present and the positions of the magnetic layer 24 and the carbon layer 27 are reversed. One main surface of the magnetic layer 24 contacts one main surface of the carbon layer 27, and the other main surface of the magnetic layer 24 contacts one main surface of the first insulating layer 21a. The other main surface of the carbon layer 27 contacts the second conductive layer 23a. The other configuration of the semiconductor device 1 according to the third modification is similar to that of the semiconductor device 1 according to the embodiment of the present invention, so a duplicated description will be omitted.

[0068] The semiconductor device 1 according to the third modification provides the same effect as the semiconductor device 1 according to the embodiment of the present invention, even when the second insulating layer 21b is not provided and the magnetic layer 24 and the carbon layer 27 are inverted from each other. Note that the same effect is provided when the first insulating layer 21a is not provided and the magnetic layer 24 and the carbon layer 27 are inverted from each other in the semiconductor device according to the embodiment of the present invention shown in FIG. 2, and the other main surface of the magnetic layer 24 is in contact with the first conductive layer 22a.

[0069] (Fourth Modification) As shown in FIG. 15, the semiconductor device 1 according to the fourth modification of the embodiment of the present invention is different from the semiconductor device 1 according to the embodiment of the present invention shown in FIG. 2 in that a third insulating layer 21d is disposed between the magnetic layer 24 and the carbon layer 27. A fourth insulating layer 21e is disposed around the carbon layer 27. A fifth insulating layer 21f is disposed around the magnetic layer 24. The third insulating layer 21d, the fourth insulating layer 21e, and the fifth insulating layer 21f are formed of a resin sheet made of, for example, polyimide resin. The fourth insulating layer 21e and the fifth insulating layer 21f may be formed of, for example, an insulating adhesive. The other configurations of the semiconductor device 1 according to the fourth modification are the same as those of the semiconductor device 1 according to the embodiment of the present invention, so that repeated explanations will be omitted.

[0070] According to the semiconductor device 1 of the fourth modification, even when the third insulating layer 21d is disposed between the magnetic layer 24 and the carbon layer 27, the same effects as those of the semiconductor device 1 according to the embodiment of the present invention can be achieved.

[0071] (Fifth Modification) As shown in Fig. 16, the semiconductor device 1 according to the fifth modified example of the embodiment of the present invention differs from the semiconductor device 1 according to the embodiment of the present invention shown in Fig. 2 in that the magnetic layer 24 and the carbon layer 27 are in the opposite positions to each other and a third insulating layer 21d is disposed between the magnetic layer 24 and the carbon layer 27. A fourth insulating layer 21e is disposed around the magnetic layer 24. A fifth insulating layer 21f is disposed around the carbon layer 27. The other configurations of the semiconductor device 1 according to the fifth modified example are similar to those of the semiconductor device 1 according to the embodiment of the present invention, and therefore repeated explanations will be omitted.

[0072] According to the semiconductor device 1 of the fifth modified example, even when the magnetic layer 24 and the carbon layer 27 are in the reversed positions and the third insulating layer 21d is disposed between the magnetic layer 24 and the carbon layer 27, the same effects as those of the semiconductor device 1 of the embodiment of the present invention can be achieved.

[0073] (Sixth Modification) The semiconductor device 1 according to the sixth modification of the embodiment of the present invention is different from the semiconductor device 1 according to the embodiment of the present invention shown in FIG. 2 in that, as shown in FIG. 17, a plurality of carbon layers 27, 28 are provided to sandwich the magnetic layer 24. The plurality of carbon layers 27, 28 may be made of the same material or different materials. The contour 28m of the carbon layer 28 coincides with the contour 27m of the carbon layer 27, but is not limited thereto. The carbon layer 28 is provided with an opening 28a to avoid contact with the first conductive post 5a. The other configurations of the semiconductor device 1 according to the sixth modification are the same as those of the semiconductor device 1 according to the embodiment of the present invention, and therefore, a duplicated description will be omitted.

[0074] The semiconductor device 1 according to the sixth modification provides the same effects as the semiconductor device 1 according to the embodiment of the present invention, even when a plurality of carbon layers 27, 28 are provided to sandwich the magnetic layer 24. In the semiconductor device 1 according to the embodiment of the present invention shown in Fig. 2, a plurality of magnetic layers 24 may be arranged to sandwich the carbon layer 27. In this manner, the number of carbon layers 27 and the number of magnetic layers 24 may differ from each other.

[0075] (Seventh Modification) The semiconductor device 1 according to the seventh modification of the embodiment of the present invention differs from the semiconductor device 1 according to the embodiment of the present invention shown in FIG. 2 in that a plurality of carbon layers 27, 28 are provided so as to be stacked as shown in FIG. 18. The plurality of carbon layers 27, 28 may be made of the same material as each other, or may be made of different materials as each other. Although two carbon layers 27, 28 are illustrated in FIG. 18, the semiconductor device 1 may have three or more carbon layers. Other configurations of the semiconductor device 1 according to the seventh modification are similar to those of the semiconductor device 1 according to the embodiment of the present invention, and therefore repeated explanations will be omitted.

[0076] The semiconductor device 1 according to the seventh modification has the same effects as the semiconductor device 1 according to the embodiment of the present invention, even when a plurality of carbon layers 27, 28 are provided in a stacked manner. Note that in the semiconductor device 1 according to the embodiment of the present invention shown in FIG. 2, a plurality of magnetic layers 24 may be arranged in a stacked manner.

[0077] (Other embodiments) As described above, the present invention has been described by the embodiment and the first to seventh modified examples, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0078] For example, in the embodiment and the first to seventh modified examples, the case where the transistor element mounted on the semiconductor chip 3 is a vertical MOSFET has been described, but the present invention is not limited to this. For example, the present invention can be applied to a semiconductor device having a semiconductor chip on which an IGBT is mounted as a transistor element. The present invention can also be applied to a semiconductor device having a semiconductor chip on which a transistor element is mounted and a semiconductor chip on which a rectifier element is mounted.

[0079] In the embodiment and the first to seventh modified examples, the semiconductor device 1 has been described as having a substrate stack 2 in which a wiring substrate 20 is supported via a first conductive post 5a, a second conductive post 5b, and a third conductive post 5c on one insulating circuit substrate 10 on which a semiconductor chip is mounted, but the present invention is not limited thereto. For example, the present invention can be applied to a semiconductor device having a substrate stack in which a wiring substrate is supported via conductive posts on two insulating circuit substrates on which semiconductor chips are mounted.

[0080] In the embodiment and the first to seventh modified examples, the openings 24a, 24b are provided in the magnetic layer 24, and the openings 27a, 27b are provided in the carbon layer 27, thereby avoiding contact with the first conductive post 5a and the second conductive post 5b. However, the present invention is not limited to this, and the openings 24a, 24b of the magnetic layer 24 and the openings 27a, 27b may be omitted from the carbon layer 27, and the magnetic layer 24 and the carbon layer 27 may be brought into contact with the first conductive post 5a and the second conductive post 5b penetrating the wiring board 20. In this case, even if the through-hole wiring 26 is omitted, the magnetic layer 24 and the carbon layer 27 can be made to have the same potential as the first conductive layer 22a and the second conductive layer 23a.

[0081] In addition, the configurations disclosed in the embodiment and the first to seventh modified examples can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the invention-specifying matters related to the claims that are appropriate from the above description. [Explanation of symbols]

[0082] 1...Semiconductor device 2...Substrate laminate 3. Semiconductor chips 3d…Drain electrode 3g: Gate electrode 3s…Source electrode 5a…First conductive post 5b…Second conductive post 5c…Third conductive post 7c…Control terminal 8…Resin sealing body 8a,8b...short side 8c,8d…Long side 10...Insulated circuit board 11...Insulating plate 11a, 11b...short side 11c, 11d...Long side 12...Conductive plate 13...Heat sink 15,16...Joining material 20...Wiring board 20a, 20b...short side 20c, 20d...long side 21...Insulating plate 22a...First conductive layer 22a1…Contour 22b…First gate wiring 23a…Second conductive layer 23a1…Contour 23b…Second gate wiring 24...Magnetic layer 24a, 24b...opening 24m…Contour 25a, 25b...Through hole 26…Through-hole wiring 27, 28…Carbon layer 27a, 27b, 28a...opening 27m, 28m…Contour

Claims

1. a wiring board including: a first insulating layer; a first conductive layer disposed on one main surface side of the first insulating layer; a second conductive layer disposed on the other main surface side of the first insulating layer; a magnetic layer disposed between the first insulating layer and the first or second conductive layer, the magnetic layer having a higher relative magnetic permeability than the first and second conductive layers; and a carbon layer disposed between the first insulating layer and the first or second conductive layer, the carbon layer having a higher thermal conductivity at least in a surface direction than the first and second conductive layers; a semiconductor chip electrically connected to the first and second conductive layers; an insulating circuit board that is disposed apart from the wiring board and has the semiconductor chip mounted thereon; Equipped with A semiconductor device comprising a plurality of carbon layers disposed on either side of the magnetic layer.

2. 2. The semiconductor device according to claim 1, wherein the magnetic layer and the plurality of carbon layers are in contact with each other.

3. the wiring substrate further includes a second insulating layer disposed between the first insulating layer and the second conductive layer; 3. The semiconductor device according to claim 1, wherein the magnetic layer and the plurality of carbon layers are disposed between the first insulating layer and the second insulating layer.

4. 4. The semiconductor device according to claim 3, wherein the wiring board further includes a third insulating layer disposed so as to surround the magnetic layer and the carbon layer.

5. 3. The semiconductor device according to claim 1, wherein the carbon layers are arranged in a plurality of layers so as to be in contact with each other.

6. 6. The semiconductor device according to claim 1, wherein currents flow in the same direction through the first and second conductive layers.

7. 7. The semiconductor device according to claim 1, wherein the first and second conductive layers are made of copper foil or an alloy foil mainly composed of copper.

8. 8. The semiconductor device according to claim 1, wherein the magnetic layer has a relative permeability of 5 or more and 500,000 or less.

9. 9. The semiconductor device according to claim 1, wherein the magnetic layer has a thickness of 10 μm or more and 50 μm or less.

10. 10. The semiconductor device according to claim 1, wherein the magnetic layer is any one selected from the group consisting of stainless steel foil, nickel foil, amorphous foil, permalloy foil, and Finemet (registered trademark) foil.

11. 11. The semiconductor device according to claim 1, wherein the carbon layer is made of graphite or graphene.

12. 12. The semiconductor device according to claim 1, wherein the magnetic layer and the carbon layer each have an outer size smaller than an outer size of the first insulating layer.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that the outlines of the magnetic layer and the carbon layer, when viewed in a plane, are flush with the outlines of the first and second conductive layers, or are located inside the outlines of the first and second conductive layers.

Images