Organic spacers for integrated circuits

Abstract

Embodiments of the present disclosure relate to organic spacers for integrated circuits. Among other things, the organic spacers of embodiments of the present disclosure help provide cost-effective and effective solutions to address issues such as coefficient of thermal expansion (CTE) mismatch, dynamic warpage, and solder joint reliability (SJR). Other embodiments may be described and claimed.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to the field of integrated circuits, and more particularly to organic spacers for integrated circuits. [Background technology]

[0002] Integrated circuits (ICs) are used in a wide variety of applications. Some IC packages may have components with large overhangs relative to other supporting components. In addition, some IC packages may have stress concentrations at the corners due to coefficient of thermal expansion (CTE) mismatch with the substrate. These stress concentrations often cause substrate trace cracks at the die corners. In addition, some IC packages may have relatively large die sizes and unbalanced layouts, resulting in dynamic warpage and solder joint reliability (SJR) issues. [Brief description of the drawings]

[0003] The embodiments can be readily understood from the following detailed description in conjunction with the accompanying drawings, in which like reference numerals refer to like elements and in which: FIG.

[0004] [Figure 1A] 1 illustrates a cross-sectional view of an integrated circuit utilizing organic spacers in accordance with various embodiments. [Figure 1B] 1 illustrates a cross-sectional view of an integrated circuit utilizing organic spacers in accordance with various embodiments. [Figure 1C] 1 illustrates a cross-sectional view of an integrated circuit utilizing organic spacers in accordance with various embodiments.

[0005] [Figure 2A] 1 illustrates additional cross-sectional views of integrated circuits utilizing organic spacers according to various embodiments. [Figure 2B]1 illustrates additional cross-sectional views of integrated circuits utilizing organic spacers according to various embodiments.

[0006] [Diagram 3] FIG. 2 is a flow diagram illustrating an example process associated with providing organic spacers according to some embodiments.

[0007] [Figure 4A] FIG. 4 is an isometric view showing an embodiment of the process of FIG. 3. [Figure 4B] FIG. 4 is an isometric view showing an embodiment of the process of FIG. 3. [Figure 4C] FIG. 4 is an isometric view showing an embodiment of the process of FIG. 3.

[0008] [Diagram 5] 1 illustrates a schematic diagram of an example computing device including an integrated circuit in accordance with various embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments of the present disclosure relate to systems, methods, and apparatuses that utilize organic spacers in IC applications. In particular, the organic spacers of the embodiments of the present disclosure help provide a cost-effective and effective solution to address issues such as CTE mismatch, dynamic warpage, and SJR. In one instance, an IC includes a semiconductor substrate, a silicon die, and a spacer disposed between the silicon die and the semiconductor substrate, the spacer including an organic compound, and the spacer is provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and the silicon die.

[0010] In the following description, various aspects of the implementation example are described using terms that are commonly used by those skilled in the art to convey their work to others skilled in the art. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be implemented using only some of the described aspects. For the purpose of explanation, specific numbers, materials and configurations are described to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be implemented without the specific details. In other cases, well-known features are omitted or simplified so as not to obscure the exemplary implementations.

[0011] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, in which like numerals indicate like parts throughout and which illustrate example embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0012] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), (A) or (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0013] The description may use perspective descriptions such as top / bottom, inside / outside, above / below, etc. Such descriptions are used for ease of description only and are not intended to limit application of the embodiments described herein to any particular orientation.

[0014] The description may use the phrases "in one embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Additionally, terms such as "comprising," "including," and "having," as used with respect to the embodiments of the present disclosure, are synonymous.

[0015] The term "coupled," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following: "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other.

[0016] Some conventional solutions to address this issue include using silicon spacers to elevate the overhanging components and balance the structure of the IC. Some conventional solutions use large silicon spacers at the bottom of the IC package to suppress the board stress and improve the SJR. Additionally, some conventional solutions require tailoring the board core CTE and epoxy molding compound (EMC) CTE to try to reduce the chance of the traces breaking.

[0017] However, the use of silicon spacers is often very expensive to implement. Similarly, tailoring the substrate / EMC CTE requires the formulation and application of special EMC and substrate materials, which are also often costly. Furthermore, the use of large silicon spacers typically only reduces (but does not eliminate) the stress concentration problem.

[0018] In contrast, embodiments of the present disclosure help provide a more cost-effective and effective solution to address such issues using organic spacers. For example, the organic spacers of the present disclosure have a more efficient assembly process flow and can be manufactured at a lower cost than traditional silicon spacers. Furthermore, organic spacers can more effectively solve the dynamic warpage issues discussed above by providing a balanced silicon-to-EMC ratio.

[0019] FIG. 1A illustrates a cross-sectional view of an IC utilizing an organic spacer (in this example, an EMC brick spacer) in accordance with various embodiments. In this example, the organic spacer allows the IC structure to remain unchanged while reducing or minimizing the CTE mismatch between the substrate and the die. Specifically, FIG. 1A illustrates a silicon die structure 100 comprising silicon dies D1, D2, D3, and D4 disposed on a semiconductor substrate 105, where D1, D2, D3, and D4 are stacked on top of each other as shown. As can be seen in FIG. 1A, the dies D3 and D4 extend out of the stacked structure 101 and at least partially overhang a region 115 of the substrate 105.

[0020] In other words, a layout structure of silicon dies D1-D4 is provided, in which silicon die D1 is disposed in contact with substrate 105 but not in contact with silicon die D3 and spacer 102. Silicon die D2 is disposed between silicon die D1 and silicon die D3, but silicon die D3 substantially overhangs silicon die D2 (in region 115), and spacer 102 provides a base for silicon die D3 and D4. In conventional solutions, such an overhang could cause the structure 101 to be slightly unbalanced.

[0021] As shown in FIG. 1A, a spacer 102 is disposed between the silicon die D3 and the semiconductor substrate 105, the spacer including an organic compound, and the spacer is provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate 105 and the silicon die D3. In this example, the spacer 102 includes an organic compound EMC. However, spacers used in conjunction with embodiments of the present disclosure may be formed from other organic compounds, such as organic solder mask materials. In some embodiments, the organic spacer may be formed from two or more different organic compounds.

[0022] 1A, a layout structure 100 of silicon dies D1-D4 can be provided in which silicon die D1 is in contact with substrate 205 but not with silicon die D3 and spacer 102. Silicon die D2 is disposed between silicon die D1 and silicon die D3, but silicon die D3 substantially overhangs silicon die D2, and spacer 102 provides a base for silicon die D3 and D4.

[0023] As shown in FIG. 1A, the spacer 102 is disposed between the silicon die D3 and the semiconductor substrate 105 to reduce or minimize the stress and warpage problems discussed above, and further stabilize the overhanging dies D3 and D4, thus balancing the structure 100. In an embodiment, the spacer 102 includes an organic compound and can reduce the coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate 105 and the silicon die D3. In this example, the spacer 102 includes the organic compound EMC. However, spacers used in conjunction with embodiments of the present disclosure may be formed from other organic compounds, such as organic solder mask materials. In some embodiments, the organic spacer may be formed from two or more different organic compounds.

[0024] 1B and 1C illustrate the use of organic spacers according to embodiments of the present disclosure. FIG. 1B illustrates an example of a layout structure 120 in which a silicon die 121 includes a film layer 122 in contact with a spacer 130. Similarly, silicon dies D1-D4 of FIG. 1A may also include film layers. In FIG. 1A, for example, silicon die D3 includes a film layer 110 in contact with a spacer 102. A film layer 111 on the bottom surface of silicon die D4 also contacts the top surface of silicon die D3. In FIG. 1B, the organic spacer 130 helps to reduce the CTE mismatch between the silicon die 121 and the substrate 105, and thus helps to reduce corner stress concentrations and substrate trace cracks at the corners of the silicon die 121.

[0025] 1C shows an example of an elongated organic spacer 145 (e.g., EMC brick spacer) at the bottom of a silicon die structure 140. Among other things, the elongated organic spacer 145 helps the structure support the large die size in the structure 140, and therefore helps address dynamic warpage and SJR issues.

[0026] In some embodiments, organic spacers can be used to help provide a solution for reducing IC package layout design size. Additionally, the organic spacers of the present disclosure can help to better utilize vertical and horizontal space in IC package layouts by changing the EMC to silicon ratio. For example, in some cases, an IC layout may have no horizontal space between components, but unused space in the vertical direction.

[0027] 2A and 2B show additional cross-sectional views of integrated circuits utilizing organic spacers, according to various embodiments. Specifically, FIG. 2A shows a cross-sectional view of an example IC that increases horizontal spacing between components, according to some embodiments. As shown, structure 200 can use organic spacers 202 (in this example, EMC spacers) disposed between substrate 205 and silicon die D1 to raise the level of silicon die D1 and overhang silicon die D2, increasing horizontal spacing between components.

[0028] 2B illustrates an example of another embodiment. In this example, the layout structure 210 includes a first organic spacer 220 disposed between the substrate 205 and the silicon die D1 to raise the vertical level of the silicon die D1, and a second organic spacer 225 adjacent to the first spacer 220 and disposed between the substrate 205 and the silicon die D2 to raise the vertical level of the silicon die D2. In this way, the spacers 220 and 225 can better utilize the vertical space of the layout structure 210, and the silicon dies D1, D2 can overlap other components without contacting them.

[0029] 3 is a flow diagram illustrating an example of a process 300 for providing an organic spacer according to various embodiments of the present disclosure. A description of the process 300 is provided with reference to the isometric views shown in FIGS. 4A-4C.

[0030] As shown in Figure 3, process 300 includes molding a wafer including organic spacers on a glass carrier at 310, where the organic spacers have a target type and a target thickness. Figure 4A shows an example of this step, where a wafer 400 having a target EMC type and a target thickness 420 is molded on a glass carrier 405. As shown in Figure 4B, the molded wafer 400 can be separated from the glass carrier 405 and placed on a film 410.

[0031] The process 300 further includes, at 320, cutting the wafer to provide one or more organic spacer bricks having a target thickness 420 as shown in FIG. 4C. The organic spacer bricks may be cut to a specific target size for a particular circuit application (e.g., in a grid pattern as shown in FIG. 4C). Thus, the organic spacer bricks may be cut to a target size having a target thickness 420 and any suitable target length and target width. The one or more organic spacer bricks may be disposed on a substrate of an electronic device to reduce a coefficient of thermal expansion (CTE) mismatch between the substrate and the silicon die of the electronic device based on the target type.

[0032] The process 300 further includes, at 330, attaching one or more organic spacer bricks to a substrate of the electronic device to provide a spacer layer between the substrate of the electronic device and the silicon die, the silicon die being or to be disposed on the substrate. The spacer bricks may be attached to the substrate of the device in a variety of configurations, examples of which are shown in Figures 1A-1C and 2A-2B and described above.

[0033] 5 illustrates generally an exemplary computing device that may include an integrated circuit having one or more organic spacers according to various embodiments disclosed herein. The computing device 500 includes a system control logic 508 coupled to one or more processors 504, a memory device 512, one or more communication interfaces 516, and an input / output (I / O) device 520. In some embodiments, for example, an integrated circuit including one or more organic spacers (e.g., as shown in FIGS. 1A-1C and 2A-2B) may be included in the memory device 512 or in another component of the system 500.

[0034] For example, the memory device 512 may include a packaged die 514 coupled to a circuit board 513, the packaged die 514 including a semiconductor substrate, a silicon die, and a spacer disposed between the silicon die and the semiconductor substrate, the spacer including an organic compound, and the spacer provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and the silicon die.

[0035] The memory device 512 may be a non-volatile computer storage chip (e.g., provided on a die). In some embodiments, the memory device 512 includes a package, such as an IC assembly in which the memory device 512 is disposed, driver circuitry (e.g., drivers), input / output connections for electrically coupling the memory device 512 with other components of the computing device 500, and the like. The memory device 512 may be configured to be removably or permanently coupled to the computing device 500. In an embodiment, the memory device 512 includes, for example, a NAND device, such as a 3D SLC, TLC (triple level / cell), QLC (quad level / cell), or SLC NAND device, and the like.

[0036] In some embodiments, memory device 512 includes any suitable persistent memory, e.g., any vertically scaling memory device, such as a write-in-place byte addressable non-volatile memory, that would benefit from embodiments. In some embodiments, memory device 512 may include any suitable memory that stores data by changing the electrical resistance of memory cells. In an embodiment, the memory 512 may include byte-addressable write-in-place three-dimensional cross-point memory devices or other byte-addressable write-in-place NVM devices such as, for example, single or multi-level phase change memory (PCM) or switched phase change memory (PCMS), NVM devices using chalcogenide phase change materials (e.g., chalcogenide glasses), resistive memories including metal oxide-based, oxygen vacancy-based and conductive bridge random access memory (CB-RAM), nanowire memories, ferroelectric random access memories (FeRAM, FRAM®), magnetoresistive random access memories (MRAM) incorporating memristor technology, spin-transfer torque (STT)-MRAM, spintronic magnetic junction memory-based devices, magnetic tunnel junction (MTJ)-based devices, DW (domain wall) and SOT (spin orbit transfer)-based devices, thyristor-based memory devices, or any combination of the above, or other memories.

[0037] The communications interface 516 may provide an interface for the computing device 1200 to communicate over one or more networks and / or with any other suitable devices. The communications interface 516 may include any suitable hardware and / or firmware. The communications interface 516 of an embodiment may include, for example, a network adapter, a wireless network adapter, a telephone modem, and / or a wireless modem. For wireless communication, the communications interface 516 of an embodiment may communicatively couple the computing device 500 to a wireless network using one or more antennas.

[0038] In one embodiment, at least one of the processors 504 may be packaged with logic for one or more controllers of the system control logic 508. In one embodiment, at least one of the processors 504 may be packaged with logic for one or more controllers of the system control logic 508 to form a system-in-package (SiP). In one embodiment, at least one of the processors 504 may be integrated on the same die as logic for one or more controllers of the system control logic 508. In one embodiment, at least one of the processors 504 may be integrated on the same die as logic for one or more controllers of the system control logic 508 to form a system-on-chip (SoC).

[0039] The system control logic 508 of an embodiment may include any suitable interface controller that provides any suitable interface to at least one of the processors 504 and / or to any suitable devices or components that communicate with the system control logic 508. The system control logic 508 may move data to and / or from various components of the computing device 500.

[0040] The system control logic 508 for one embodiment may include a memory controller 824 that provides an interface to the memory device 512 to control various memory access operations. The memory controller 524 may include control logic 528 that may be specifically configured to control access of the memory device 512.

[0041] In various embodiments, the I / O device 520 may include a user interface designed to enable user interaction with the computing device 500, a peripheral component interface designed to enable peripheral component interaction with the computing device 500, and / or a sensor designed to determine environmental conditions and / or location information associated with the computing device 500. In various embodiments, the user interface may include, but is not limited to, a display, e.g., a liquid crystal display, a touch screen display, etc., a speaker, a microphone, one or more digital cameras for taking images and / or videos, a flashlight (e.g., a light emitting diode flash), and a keyboard. In various embodiments, the peripheral component interface may include, but is not limited to, a non-volatile memory port, an audio jack, and a power interface. In various embodiments, the sensors may include, but are not limited to, a gyro sensor, a proximity sensor, an ambient light sensor, and a positioning unit. The positioning unit may additionally / alternatively be part of or interact with the communication interface 516 to communicate with components of a positioning network, e.g., Global Positioning System (GPS) satellites.

[0042] In various embodiments, computing device 500 may be, but is not limited to, a laptop computing device, a tablet computing device, a netbook, a mobile computing device such as a smartphone, a desktop computing device, a workstation, a server, etc. Computing device 500 may have more or fewer components and / or a different architecture. In further implementations, computing device 500 may be any other electronic device that processes data.

[0043] EXAMPLES In accordance with various embodiments, this disclosure describes several examples.

[0044] Example 1 includes an apparatus including a semiconductor substrate, a silicon die, and a spacer disposed between the silicon die and the semiconductor substrate, the spacer including an organic compound, the spacer configured to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and the silicon die.

[0045] Example 2 includes the device of example 1 or any other example herein, wherein the organic compound includes an epoxy molding compound (EMC) or an organic solder mask material.

[0046] Example 3 includes the device of example 1 or any other example herein, wherein the silicon die includes a film layer, the film layer contacting the spacer.

[0047] Example 4 includes the device of example 1 or any other example herein, wherein the silicon die is a first silicon die, and the device further comprises a second silicon die in contact with the semiconductor substrate.

[0048] Example 5 includes the apparatus of example 4 or any other example herein, wherein the second silicon die is not in contact with the first silicon die or the EMC spacer.

[0049] Example 6 includes the device of example 4 or any other example herein, wherein the device further comprises a third silicon die disposed between the first silicon die and the second silicon die.

[0050] Example 7 includes the device of any of Examples 4-6, or any other example herein, where each silicon die includes a film layer.

[0051] Example 8 includes the apparatus of example 1 or any other example herein, wherein the silicon die is a first silicon die, a first side of the first silicon die is in contact with the spacer, and a second side of the first silicon die is in contact with a second silicon die.

[0052] Example 9 includes the device of example 8 or any other example herein, wherein the first silicon die includes a first film layer on the first surface in contact with the spacer, and the second silicon die includes a second film layer in contact with the second surface of the first silicon die.

[0053] Example 10 includes the device of example 1 or any other example herein, wherein the silicon die is a first silicon die, the spacer is a first spacer, and the device further comprises a second silicon die and a second spacer adjacent to the first spacer, the second spacer being disposed between the substrate and the second silicon die.

[0054] Example 11 includes a method comprising: molding a wafer including organic spacers on a glass carrier, the organic spacers having a target type and a target thickness; and cutting the wafer to provide one or more organic spacer bricks having the target thickness, the one or more organic spacer bricks being to be disposed on a substrate of an electronic device to reduce a coefficient of thermal expansion (CTE) mismatch between the substrate and a silicon die of the electronic device based on the target type.

[0055] Example 12 includes the method of example 11 or any other example herein, further comprising attaching the one or more organic spacer bricks to the substrate of the electronic device to provide a spacer layer between the substrate of the electronic device and the silicon die, the silicon die being disposed or to be disposed on the substrate.

[0056] Example 13 includes the method of example 11 or any other example herein, where the organic spacer has a target type that includes an epoxy molding compound (EMC) or an organic solder mask material.

[0057] Example 14 includes the method of example 11 or any other example herein, wherein cutting the wafer includes providing the one or more spacer bricks having a target size, the target size including a target thickness, a target length, and a target width.

[0058] Example 15 includes the method of example 11 or any other example herein, wherein the silicon die is a first silicon die and the electronic device further includes a second silicon die in contact with the substrate.

[0059] Example 16 includes the method of example 15 or any other example herein, wherein the second silicon die is not in contact with the first silicon die or the organic spacer.

[0060] Example 17 includes a computing device comprising a circuit board and a packaged die coupled to the circuit board, the packaged die including a semiconductor substrate, a silicon die, and a spacer disposed between the silicon die and the semiconductor substrate, the spacer including an organic compound, the spacer being provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and the silicon die.

[0061] Example 18 includes the computing device of example 17 or any other example herein, wherein the organic compound includes an epoxy molding compound (EMC) or an organic solder mask material.

[0062] Example 19 includes the computing device of example 17 or any other example herein, wherein the silicon die includes a film layer, the film layer in contact with the spacer.

[0063] Example 20 includes the computing device of example 17 or any other example herein, wherein the silicon die is a first silicon die and the package die further includes a second silicon die in contact with the semiconductor substrate.

[0064] Various embodiments may include any suitable combination of the above-described embodiments, including alternative or multiple embodiments of the embodiments described in the above conjunction (e.g., "and" can be "and / or"). Additionally, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions stored thereon that, when executed, result in the operation of any of the above-described embodiments. Additionally, some embodiments may include an apparatus or system having any suitable means for performing various operations of the above-described embodiments.

[0065] The above description of the illustrated implementations, including those described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the art will recognize.

[0066] These changes may be made to the embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope should be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0067] [Other possible items] What is claimed is: [Item 1] A semiconductor substrate; A silicon die; a spacer disposed between the silicon die and the semiconductor substrate, the spacer including an organic compound, the spacer being provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and the silicon die; An apparatus comprising: [Item 2] Item 1 . The apparatus of item 1 , wherein the organic compound comprises an epoxy molding compound (EMC) or an organic solder mask material. [Item 3] Item 1 , the apparatus of item 1 , wherein the silicon die includes a film layer, the film layer being in contact with the spacer. [Item 4] Item 10. The apparatus of item 1, wherein the silicon die is a first silicon die, the apparatus further comprising a second silicon die in contact with the semiconductor substrate. [Item 5] 5. The apparatus of claim 4, wherein the second silicon die is not in contact with the first silicon die or the EMC spacer. [Item 6] Item 5. The apparatus of item 4, further comprising a third silicon die disposed between the first silicon die and the second silicon die. [Item 7] 7. The apparatus of any one of items 4-6, wherein each silicon die comprises a film layer. [Item 8] 2. The apparatus of claim 1, wherein the silicon die is a first silicon die, a first side of the first silicon die is in contact with the spacer, and a second side of the first silicon die is in contact with a second silicon die. [Item 9] 9. The apparatus of claim 8, wherein the first silicon die includes a first film layer on the first side in contact with the spacer, and the second silicon die includes a second film layer in contact with the second side of the first silicon die. [Item 10] the silicon die is a first silicon die, the spacer is a first spacer, and the apparatus comprises: a second silicon die; and a second spacer adjacent to the first spacer, the second spacer being disposed between the substrate and the second silicon die; Item 1. The apparatus of item 1, further comprising: [Item 11] forming a wafer including organic spacers on a glass carrier, the organic spacers having a target type and a target thickness; cutting the wafer to provide one or more organic spacer bricks having the target thickness, the one or more organic spacer bricks being to be placed on the substrate of the electronic device to reduce a coefficient of thermal expansion (CTE) mismatch between the substrate and a silicon die of the electronic device based on the target type; A method for providing the above. [Item 12] Item 12. The method of item 11, further comprising attaching the one or more organic spacer bricks to the substrate of the electronic device to provide a spacer layer between the substrate of the electronic device and the silicon die, the silicon die being disposed or to be disposed on the substrate. [Item 13] Item 12. The method of item 11, wherein the organic spacer has a target type comprising an epoxy molding compound (EMC) or an organic solder mask material. [Item 14] Item 12. The method of item 11, wherein cutting the wafer comprises providing the one or more spacer bricks having a target size, the target size including a target thickness, a target length, and a target width. [Item 15] Item 12. The method of item 11, wherein the silicon die is a first silicon die and the electronic device further comprises a second silicon die in contact with the substrate. [Item 16] Item 16. The method of item 15, wherein the second silicon die is not in contact with the first silicon die or the organic spacer. [Item 17] A circuit board; a package die coupled to the circuit board, A semiconductor substrate; A silicon die; a spacer disposed between the silicon die and the semiconductor substrate, the spacer including an organic compound, the spacer being provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and the silicon die; and A computing device comprising: [Item 18] Item 18. The computing device of item 17, wherein the organic compound comprises an epoxy molding compound (EMC) or an organic solder mask material. [Item 19] Item 18. The computing device of item 17, wherein the silicon die includes a film layer, the film layer in contact with the spacer. [Item 20] Item 18. The computing device of item 17, wherein the silicon die is a first silicon die and the package die further includes a second silicon die in contact with the semiconductor substrate.

Claims

1. An apparatus coupled to a circuit board, comprising: a semiconductor substrate coupled to the circuit board; A silicon die; a spacer disposed between the silicon die and the semiconductor substrate, the spacer including an organic compound, the spacer being provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and the silicon die; Equipped with The apparatus, wherein the silicon die is a first silicon die, the apparatus further comprising a second silicon die in contact with the semiconductor substrate.

2. The apparatus of claim 1 , wherein the organic compound comprises an epoxy molding compound (EMC) or an organic solder mask material.

3. The apparatus of claim 1 or 2, wherein the silicon die includes a film layer, the film layer being in contact with the spacer.

4. The apparatus of any one of claims 1 to 3, wherein the second silicon die is not in contact with the first silicon die or the spacer.

5. The apparatus of claim 1 , further comprising a third silicon die disposed between the first silicon die and the second silicon die.

6. The apparatus of any one of claims 1 to 5, wherein each silicon die comprises a film layer.

7. 7. The apparatus of claim 1, wherein the silicon die is a first silicon die, a first side of the first silicon die is in contact with the spacer, and a second side of the first silicon die is in contact with a second silicon die.

8. 8. The apparatus of claim 7, wherein the first silicon die includes a first film layer on the first side in contact with the spacer, and the second silicon die includes a second film layer in contact with the second side of the first silicon die.

9. the silicon die is a first silicon die, the spacer is a first spacer, and the apparatus comprises: a second silicon die; a second spacer adjacent to the first spacer, the second spacer being disposed between the semiconductor substrate and the second silicon die; The apparatus of any one of claims 1 to 8, further comprising:

10. forming a wafer including organic spacers on a glass carrier, the organic spacers having a target type and a target thickness; cutting the wafer to provide one or more organic spacer bricks having the target thickness, the one or more organic spacer bricks being to be placed on the substrate of the electronic device to reduce a coefficient of thermal expansion (CTE) mismatch between the substrate and a silicon die of the electronic device based on the target type; Attaching the one or more organic spacer bricks to the substrate of the electronic device to provide a spacer layer between the substrate and the silicon die of the electronic device. Equipped with the substrate of the electronic device is coupled to a circuit board; The method, wherein the silicon die is a first silicon die and the electronic device further comprises a second silicon die in contact with the substrate.

11. The method of claim 10, wherein the silicon die is or is to be disposed on the substrate.

12. 12. The method of claim 10 or 11, wherein the organic spacers have a target type comprising an epoxy molding compound (EMC) or an organic solder mask material.

13. 13. The method of any one of claims 10 to 12, wherein cutting the wafer comprises providing the one or more spacer bricks having a target size, the target size including a target thickness, a target length, and a target width.

14. The method of any one of claims 10 to 13, wherein the second silicon die is not in contact with the first silicon die or the organic spacer.

15. A circuit board; a package die coupled to the circuit board, a semiconductor substrate coupled to the circuit board; A silicon die; a spacer disposed between the silicon die and the semiconductor substrate, the spacer including an organic compound, the spacer being provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and the silicon die; and Equipped with The computing device, wherein the silicon die is a first silicon die, and the package die further includes a second silicon die in contact with the semiconductor substrate.

16. The computing device of claim 15 , wherein the organic compound comprises an epoxy molding compound (EMC) or an organic solder mask material.

17. The computing device of claim 15 or 16, wherein the silicon die includes a film layer, the film layer in contact with the spacer.

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