Semiconductor Device

Abstract

To provide a semiconductor device with a built-in snubber circuit, which is flexibly applicable to various electrical equipment.SOLUTION: A semiconductor device 100, in which a cell region A1 and a peripheral region A2 are defined, comprises: a semiconductor substrate 110 having a drift layer 112, a base region 113, and a source region 114; a source electrode 120; a gate wiring 140 having a first gate wiring part 141 and a second gate wiring part 142 arranged at positions at which the first gate wiring part 141 and the second gate wiring part 142 face each other with the source electrode 120 therebetween; a shield wiring 140 having a first shield wiring part 141 and a second shield wiring part 142 arranged at positions at which the first shield wiring part 141 and the second shield wiring part 142 face each other; a plurality of trenches 151; a gate electrode 153; a shield electrode 154; and an insulation region 155. The shield wiring 140 is electrically connected with the source electrode 120 through a snubber resistance adjustment part 160 having a resistance component.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices having a shielded gate structure in which a gate electrode and a shield electrode for a source potential are formed in a trench are known (see, for example, Patent Document 1). As a semiconductor device having such a shielded gate structure, the following semiconductor device (semiconductor device 900 according to the background art) is considered.

[0003] 11(a), the semiconductor device 900 according to the background art includes a cell region A1 and a peripheral region A2 in plan view. The semiconductor device 900 according to the background art includes a semiconductor substrate 910, a source electrode 920, a gate wiring 930, a shield wiring 940, and a plurality of trenches 951.

[0004] As shown in Fig. 11(b), the semiconductor device 900 according to the related art includes a gate insulating film 952, a gate electrode 953, a shield electrode 954, an insulating region 955, an interlayer insulating film 980, and a drain electrode 990. The semiconductor substrate 910 is an n-type (n + A low resistance semiconductor layer 911 of n-type (n - A p-type drift layer 912, a p-type base region 913 formed on the surface of the drift layer 912 in the cell region A1, and an n-type (n + 9 has a source region 914 of the same type.

[0005] The source electrode 920 is disposed on the surface of the semiconductor substrate 910 in the cell region A1 via an interlayer insulating film 980, and is connected to the semiconductor substrate 910 via a metal plug Pg3. The gate wiring 930 is arranged on the surface of the semiconductor substrate 910 in the peripheral region A2 via an interlayer insulating film 980, and has a first gate wiring portion 931 and a second gate wiring portion 932 arranged opposite each other across the source electrode 920, and a gate pad 933. The shield wiring 940 is arranged on the surface of the semiconductor base 910 in the peripheral region A2 via an interlayer insulating film 980, and has a first shield wiring portion 941 and a second shield wiring portion 942 arranged in opposing positions across the first gate wiring portion 931, the source electrode 920, and the second gate wiring portion 932.

[0006] In the semiconductor device 900 according to the background art, an end of the first shield wiring portion 941 and an end of the second shield wiring portion 942 are electrically connected to the source electrode 920 via a relatively wide connection wiring (see the area surrounded by the dashed dotted line A in FIG. 11(a)). Therefore, the potential of the shield wiring 940 is the same as the potential of the source electrode 920.

[0007] In the semiconductor device 900 according to the background art, the shield electrode 954 is made of polysilicon and has an internal resistance. Also, since there is an insulating region 955 that isolates the drift layer 912 and the shield electrode 954, a parasitic capacitance is present between the shield electrode 954, which is at the source potential, and the drain electrode 990. As a result, a configuration is formed in the semiconductor device between the source electrode 920 and the drain electrode 990, in which the internal resistance of the shield electrode 954 and the parasitic capacitance between the shield electrode 954 and the drift layer 912 are connected in series, and a snubber circuit is secondarily formed. Therefore, the semiconductor device 900 according to the background art is a semiconductor device with a built-in snubber circuit. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 4790908 Summary of the Invention [Problem to be solved by the invention]

[0009] However, in the semiconductor device 900 of the background art, the parasitic capacitance between the shield electrode 954 and the drain electrode 990 and the internal resistance of the shield electrode 954 are determined by the design of the semiconductor device based on the characteristics of the MOSFET, and it is difficult to change the characteristics of the snubber circuit (e.g., the snubber resistance) depending on the electrical equipment to be used. This results in a problem in that it is not possible to provide a semiconductor device with a built-in snubber circuit that can be flexibly applied to various electrical equipment.

[0010] Therefore, the present invention has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device with a built-in snubber circuit that can be flexibly applied to various electric devices. [Means for solving the problem]

[0011] The semiconductor device of the present invention is a semiconductor device in which a cell region and a peripheral region formed in a region surrounding the cell region are defined in a plan view, the semiconductor device comprising: a semiconductor substrate having a first conductivity type drift layer formed in the cell region and the peripheral region, a second conductivity type base region formed on a surface of the drift layer at least in the cell region, and a first conductivity type source region formed in a part of the surface of the base region; a source electrode arranged on the surface of the semiconductor substrate at least in the cell region via an interlayer insulating film; a gate wiring arranged on the surface of the semiconductor substrate in the peripheral region via an interlayer insulating film, the gate wiring having a first gate wiring portion and a second gate wiring portion arranged at positions opposing each other with the source electrode sandwiched therebetween in a plan view; a shield wiring arranged on the surface of the semiconductor substrate in the peripheral region via an interlayer insulating film, the first shield wiring portion and the second shield wiring portion arranged at positions opposing each other with the first gate wiring portion, the source electrode, and the second gate wiring portion sandwiched therebetween in a plan view; the first shield wiring portion and the second shield wiring portion are electrically connected to the source electrode via a snubber resistance adjustment portion having a resistance component, the first shield wiring portion being electrically connected to the source electrode via a gate insulating film formed on an inner surface of the trench inside each of the trenches and a gate electrode being connected to the gate wiring portion in the peripheral region; the second shield wiring portion and the first shield wiring portion being electrically connected to the source electrode via a snubber resistance adjustment portion having a resistance component, the first shield wiring portion and the second shield wiring portion being electrically connected to the source electrode via a snubber resistance adjustment portion having a resistance component, the first shield wiring portion and the second shield wiring portion being electrically connected to the source electrode via a snubber resistance adjustment portion having a resistance component, the first shield wiring portion and the second shield wiring portion being electrically connected to the source electrode via a snubber resistance adjustment portion having a resistance component, the first shield wiring portion and the second shield wiring portion being electrically connected to the source electrode via a snubber resistance adjustment portion having a resistance component, the first shield wiring portion and the second shield wiring portion being electrically connected to the source electrode via a snubber resistance adjustment portion having a resistance component, the first shield wiring portion and the second shield wiring portion being electrically connected to the source electrode via a snubber resistance adjustment portion having a resistance component, Effect of the Invention

[0012] According to the semiconductor device of the present invention, the shield wiring is electrically connected to the source electrode via a snubber resistance adjuster having a resistance component, so that a resistance component other than the resistance component determined by the design of the semiconductor device based on the characteristics of the MOSFET can be added to the current path between the drain electrode and the source electrode. Therefore, by adjusting the resistance component of the snubber resistance adjuster, it is possible to change the snubber resistance and, ultimately, the characteristics of the snubber circuit according to the electrical device in which the semiconductor device is used, without changing the characteristics of the MOSFET. As a result, a semiconductor device with a built-in snubber circuit can be flexibly applied to various electrical devices. [Brief description of the drawings]

[0013] [Figure 1] 1A and 1B are diagrams for explaining a semiconductor device 100 according to embodiment 1. Fig. 1A is a plan view of the semiconductor device 100, Fig. 1B is a cross-sectional view taken along line AA in Fig. 1A, and Fig. 1C is a cross-sectional view taken along line BB in Fig. 1A. [Diagram 2] FIG. 2 is a cross-sectional view taken along line CC of FIG. [Diagram 3] 1 is an enlarged plan view of a main portion shown for explaining a snubber resistance adjuster 160 in the embodiment 1. Note that the peripheral trench structure 170 is not shown except for the outermost peripheral trench structure 170b. [Figure 4] 4A and 4B are diagrams for explaining a snubber circuit of the semiconductor device 100 according to the embodiment 1. Fig. 4A is an equivalent circuit of the semiconductor device 100, Fig. 4B is a diagram for explaining the capacitance of the snubber circuit, and Fig. 4C is a diagram for explaining the resistance of the snubber circuit. [Diagram 5] 11 is an enlarged plan view of a main portion shown for explaining a snubber resistance adjuster 160a in the second embodiment. FIG. [Figure 6] 13 is an enlarged plan view of a main portion shown for explaining a snubber resistance adjuster 160b in the third embodiment. FIG. [Figure 7] 13 is an enlarged plan view of a main portion shown for explaining a snubber resistance adjuster 160c in the fourth embodiment. FIG. [Figure 8] 13 is an enlarged plan view of a main portion shown for explaining a snubber resistance adjuster 160d in the fifth embodiment. FIG. [Figure 9] 9A and 9B are diagrams for explaining a semiconductor device 105 according to an embodiment 6. Fig. 9A is a plan view of the semiconductor device 105, and Fig. 9B is an enlarged plan view of a main part of the semiconductor device 105. [Figure 10] 10A and 10B are diagrams for explaining a snubber resistance adjuster 160e in embodiment 6. Fig. 10A is an enlarged plan view of a main part for explaining the snubber resistance adjuster 160e in the semiconductor device 105, and Fig. 10B is a DD cross-sectional view of Fig. 10A. Fig. 10A shows the state of the semiconductor substrate 110 in the same region as that shown in Fig. 9B. [Figure 11] 11A and 11B are diagrams for explaining a semiconductor device 900 according to the background art, and are a plan view of the semiconductor device 900 and an E-E cross-sectional view of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The semiconductor device of the present invention will be described below based on the embodiments shown in the drawings. Note that each drawing is a schematic diagram and does not necessarily strictly reflect the actual dimensions. Each embodiment described below does not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in each embodiment are necessarily essential to the solution of the present invention. In each embodiment, the same reference numerals are used across embodiments for configurations and elements (including components that are not completely identical in shape, etc.) that have the same basic configuration, features, functions, etc., and repeated explanations may be omitted.

[0015] [Embodiment 1] 1. Configuration of the semiconductor device 100 according to the first embodiment 1(a), the semiconductor device 100 according to the first embodiment is a trench-gate type semiconductor device (MOSFET) including a cell region A1 and a peripheral region A2 defined in a region surrounding the cell region A1. The cell region A1 is a region in which a source electrode 120 is disposed on one surface (hereinafter simply referred to as the surface) of a semiconductor substrate 110, and a vertical MOSFET is formed.

[0016] 1(a), the semiconductor device 100 according to the first embodiment includes a semiconductor substrate 110, a source electrode 120, a gate wiring 130, a shield wiring 140, a plurality of trenches 151, connection trenches 157 and 158, a snubber resistance adjustment section 160, and a peripheral trench structure 170 (170b). The semiconductor substrate 110 has a rectangular shape in plan view that is composed of long sides X1 and X2 and short sides X3 and X4. The plurality of trenches 151 extend from the long side X1 side toward the long side X2 side. Moreover, the semiconductor device 100 according to the first embodiment includes an interlayer insulating film 180 and a drain electrode 190, as shown in FIGS.

[0017] As shown in FIG. 1(a) to FIG. 1(c), the semiconductor substrate 110 is + a n-type low resistance semiconductor layer 111 and a n-type - a p-type drift layer 112, a p-type base region 113 formed on the surface of the drift layer 112 in at least the cell region A1, and an n-type base region 113 formed on the surface of the base region 113 and having a higher impurity concentration than the drift layer 112. + The semiconductor device has a p-type source region 114, and in the peripheral region A2, a p-type peripheral diffusion region 115 formed on the surface of the drift layer 112 in each region between a plurality of shield side connections 143, 144 and a plurality of source electrode side connections 121, 122, which will be described later.

[0018] The low-resistance semiconductor layer 111 has a thickness of 50 μm to 500 μm (for example, 350 μm), and an impurity concentration of 1×10 18 cm -3 ~1×1021 cm -3 (For example, 1×10 19 cm -3 The thickness of the drift layer 112 in the region where the trench 151 is not formed is 3 μm to 50 μm (for example, 15 μm), and the impurity concentration of the drift layer 112 is 1×10 14 cm -3 ~1×10 19 cm -3 (For example, 1×10 15 cm -3 The depth of the base region 113 and the peripheral diffusion region 115 is 0.5 μm to 10 μm (for example, 5 μm), and the impurity concentration of the base region 113 and the peripheral diffusion region 115 is 1×10 16 cm -3 ~1×10 19 cm -3 (For example, 1×10 17 cm -3 ).

[0019] 1(a), the source electrode 120 covers the entire cell region A1 and has a generally rectangular shape extending along an axis from the short side X3 to the short side X4 to a region overlapping with the peripheral region A2 on the short side X4 side. In other words, the source electrode 120 extends to a region overlapping with the peripheral region A2 along a direction (from the short side X3 side toward the short side X4) different from the direction (long side X1 side) in which a first shield wiring portion 141 and a first gate wiring portion 131 described later are arranged and the direction (long side X2 side) in which a second shield wiring portion 142 and a second gate wiring portion 132 are arranged, as viewed from the source electrode 120. The source electrode 120 has, in the peripheral area A2 extending toward the short side X4, five source electrode side connection portions 121 protruding toward the long side X1 side (the first shield wiring portion 141 side) and five source electrode side connection portions 122 protruding toward the long side X2 side (the second shield wiring portion 142 side).

[0020] The source electrode 120 is disposed on the surface of the semiconductor substrate 110 via an interlayer insulating film 180, as shown in Figures 1(b) and 1(c). In the cell region A1, the source electrode 120 is in contact with the source region 114 and the base region 113 via a metal plug Pg3 in a contact hole formed in the interlayer insulating film 180, as shown in Figure 1(c). In the peripheral region A2, the source electrode 120 is in contact with the polysilicon layer 173 in the peripheral trench 171 in the peripheral trench structure 170b on the outermost side (short side X4 side) of the peripheral trench structure 170, at the end on the short side X3 side, as shown in Figure 2, via a metal plug Pg4 in a contact hole formed in the interlayer insulating film 180.

[0021] As shown in FIG. 1(a), the gate wiring 130 includes a first gate wiring portion 131 (first gate finger) arranged on the long side X1 side of the source electrode 120 on the surface of the semiconductor substrate 110 in the peripheral region A2 and extending from the short side X3 side toward the short side X4 side, a second gate wiring portion 132 (second gate finger) arranged on the long side X2 side of the source electrode 120 at a position opposite the first gate wiring portion 131 across the source electrode 120 and extending from the short side X3 side toward the short side X4 side, and a gate pad 133 connected to the ends of the short side X3 side of the first gate wiring portion 131 and the second gate wiring portion 132, and arranged in an approximately central region on the short side X3 side of the source electrode 120.

[0022] 1(b), the gate wiring 130 is disposed on the surface of the semiconductor substrate 110 via an interlayer insulating film 180. In the peripheral region A2, the first gate wiring portion 131 is in contact with one end (the end on the long side X1 side) of the gate electrode 153 via a metal plug Pg1 in a contact hole formed in the interlayer insulating film 180, and the second gate wiring portion 132 is in contact with the other end (the end on the long side X2 side) of the gate electrode 153 via a metal plug Pg1 in a contact hole formed in the interlayer insulating film 180.

[0023] 1(a), on the surface of the semiconductor base 110 in the peripheral region A2, the shield wiring 140 includes a first shield wiring portion 141 arranged on the long side X1 of the first gate wiring portion 131 and extending from the short side X4 side toward the short side X3 side along the long side X1, and a second shield wiring portion 142 arranged on the long side X2 of the second gate wiring portion 132 and extending from the short side X4 side toward the short side X3 side along the long side X2. The second shield wiring portion 142 is arranged at a position opposite to the first shield wiring portion 141 with the first gate wiring portion 131, the source electrode 120, and the second gate wiring portion 132 in between.

[0024] The first shield wiring portion 141 has five shield side connection portions 143 provided at positions facing the five source electrode side connection portions 121 of the source electrode 120, respectively, protruding toward each source electrode side connection portion 121, in a portion on the short side X4 side. The second shield wiring portion 142 has five shield side connection portions 144 provided at positions facing the five source electrode side connection portions 122 of the source electrode 120, respectively, protruding toward each source electrode side connection portion 122, in a portion on the short side X4 side. The total width of the five shield side connection portions 143 or the total width of the five shield side connection portions 144 is narrower than the width of the first shield wiring portion 141 or the second shield wiring portion 142.

[0025] As shown in FIG. 1B, the shield wiring 140 is disposed on the surface of the semiconductor substrate 110 via an interlayer insulating film 180. As shown in FIG. 1B and FIG. 3, the first shield wiring portion 141 is in contact with one end (end on the long side X1 side) of the shield electrode 154 via a metal plug Pg2 in a rectangular contact hole formed in the interlayer insulating film 180 and extending from the short side X3 toward the short side X4, and the second shield wiring portion 142 is in contact with the other end (end on the long side X2 side) of the shield electrode 154 via a metal plug Pg2 in a rectangular contact hole formed in the interlayer insulating film 180 and extending from the short side X3 toward the short side X4. Also, as shown in FIG. 3, the shield wiring 140 is connected to the semiconductor substrate 110 via a metal plug Pg5 in a contact hole formed in the interlayer insulating film 180 in a region between adjacent trenches 151.

[0026] The source electrode 120, the gate wiring 130, and the shield wiring 140 can be formed collectively by depositing a metal film with predetermined locations masked. The source electrode 120, the gate wiring 130, and the shield wiring 140 are made of, for example, an Al film or an Al alloy film (for example, an AlSi film), and have a thickness of 1 μm to 10 μm (for example, 3 μm).

[0027] 1(b) and 1(c), the drain electrode 190 is formed on the other surface side (on the surface of the low-resistance semiconductor layer 111) of the semiconductor substrate 110. The drain electrode 190 is made of a laminated film in which Ti, Ni, and Au (or Ag) are laminated in this order, and the thickness of the drain electrode 190 is 0.2 μm to 1.5 μm (for example, 1 μm).

[0028] Each of the multiple trenches 151 is formed on the surface of the semiconductor substrate 110, and extends in a stripe shape from a region overlapping with the first shield wiring part 141 on the long side X1 side in a plan view across the cell region A1 to a region overlapping with the second shield wiring part 142 on the long side X2 side, as shown in Fig. 1(a). The ends of the multiple trenches 151 on the long side X1 side are connected to a connection trench 157 extending from the short side X3 toward the short side X4 along the long side X1, and the ends of the multiple trenches 151 on the long side X2 side are connected to a connection trench 158 extending from the short side X3 toward the short side X4 along the long side X2. Therefore, in the first embodiment, the multiple trenches 151 and the connection trenches 157, 158 form a lattice-like trench.

[0029] As shown in FIG. 1(c), the multiple trenches 151 are formed to a depth that reaches the drift layer 112 in the cell region A1. The semiconductor device 100 according to the first embodiment includes, in each trench 151, a gate insulating film 152, a gate electrode 153, a shield electrode 154, and an insulating region 155, as shown in FIGS. 1(b) and 1(c).

[0030] The gate electrode 153 is disposed on the upper side of each of the trenches 151 and extends in a stripe shape along the trenches 151 in a plan view. The gate electrode 153 is disposed via a gate insulating film 152 formed on the inner surface of the upper sidewall of the trench 151, and the gate electrode 153 faces the base region 113 via the gate insulating film 152. The gate electrode 153 is made of polysilicon. The bottom of the gate electrode 153 is located deeper than the position of the pn junction between the drift layer 112 and the base region 113.

[0031] The shield electrode 154 is disposed on the lower side inside each of the multiple trenches 151, and extends in a stripe shape along the trenches 151 in a plan view. The shield electrode 154 is disposed apart from the inner surfaces (bottom and side walls) of the trenches 151 and the gate electrode 153. The shield electrode 154 is connected to the first shield wiring portion 141 via a metal plug Pg2 at the end on the long side X1 side, and is connected to the second shield wiring portion 142 via a metal plug Pg2 at the end on the long side X2 side. The shield electrode 154 is formed of polysilicon.

[0032] The insulating region 155 spreads between the gate electrode 153 and the shield electrode 154 inside each of the multiple trenches 151 to separate the shield electrode 154 from the gate electrode 153, and also spreads between the inner surface of the trench 151 and the shield electrode 154 to separate the shield electrode 154 from the inner surface of the trench 151. The insulating region 155 is a CVD oxide film formed by the CVD method, but may be a thermal oxide film, an oxide film in which both are laminated, or an insulating film other than an oxide film.

[0033] 1(a), the snubber resistance adjustment unit 160 is formed between the end of the first shield wiring unit 141 on the short side X4 side and the source electrode 120, and between the end of the second shield wiring unit 142 on the short side X4 side and the source electrode 120. In the snubber resistance adjustment unit 160, as shown in FIG. 3, shield side connection units 143, 144 and source electrode side connection units 121, 122 are formed, and strip-shaped peripheral diffusion regions 115 are formed on the surface of the drift layer between the plurality of source electrode side connection units 121, 122 and the plurality of shield side connection units 143, 144. The peripheral diffusion regions 115 are p-type semiconductor regions formed on the surface of the drift layer 112. The multiple source electrode side connections 121, 122 are connected to the peripheral diffusion region 115 via metal plugs Pg6 in contact holes formed in the interlayer insulating film 180, and the multiple shield side connections 143, 144 are connected to the peripheral diffusion region 115 via metal plugs Pg7 in contact holes formed in the interlayer insulating film 180. In the first embodiment, all of the five shield side connections 143, 144 are connected to the corresponding five source electrode side connections 121, 122 via the peripheral diffusion region 115.

[0034] In snubber resistance adjuster 160, shield side connecting parts 143, 144 and source electrode side connecting parts 121, 122 are formed, and the current conduction path between source electrode 120 and shield wiring 140 is narrow, making it difficult for a current to flow. In addition, p-type peripheral diffusion region 115 has a lower electrical conductivity than the metals constituting source electrode 120 and shield wiring 140, making it difficult for a current to flow. For these reasons, snubber resistance adjuster 160 becomes a resistance component.

[0035] In the first embodiment, in one snubber resistance adjustment unit, all five shield side connection parts 143, 144 are connected to the corresponding source electrode side connection parts 121, 122 via the peripheral diffusion region 115, but there may be some shield side connection parts 143, 144 that are not connected to the peripheral diffusion region 115. The snubber resistance can be adjusted by determining or changing the number of parts that are connected via the peripheral diffusion region 115 and the number that are not connected depending on the electric device to be used.

[0036] 2, the peripheral trench structures 170 are composed of peripheral trenches 171 formed on one surface of the semiconductor substrate 110 and a polysilicon layer 173 embedded in each of the peripheral trenches 171 via a peripheral insulating region 172. The peripheral trench structures 170 are formed at least in a region where the source electrode 120 and the peripheral region A2 overlap. In the first embodiment, the peripheral trench structures 170 are formed to the same depth as the trench 151. The peripheral insulating region 172 is made of, for example, an oxide film.

[0037] Of the multiple peripheral trench structures 170, in the peripheral trench structure 170a closest to the cell region A1, the polysilicon layer 173 is connected to the shield wiring 140 via a metal plug (not shown) in a contact hole formed in the interlayer insulating film 180, and of the multiple peripheral trench structures 170, in the peripheral trench structure 170b farthest from the cell region A1, the polysilicon layer 173 is connected to the source electrode 120 via a metal plug Pg4 in a contact hole formed in the interlayer insulating film 180. The peripheral trench structure 170b is arranged so as to go around the outer periphery of the semiconductor substrate 110.

[0038] 2. Snubber circuit in the semiconductor device 100 according to the first embodiment 1(a) and 1(b), the semiconductor device 100 according to the first embodiment is connected to the shield electrode 154 via the source electrode 120, the snubber resistance adjuster 160, the shield wiring 140, and the metal plug Pg2. Therefore, the shield electrode 154 has a potential close to that of the source electrode 120 (strictly speaking, a potential lower than that of the source electrode 120 by the combined resistance R1 of the internal resistances of the shield electrodes 154 and the resistance R2 of the snubber resistance adjuster 160). In addition, as shown in Figures 1(b) and (c), the shield electrode 154 faces the drift layer 112 via an insulating region 155, and the drift layer 112 is connected to the drain electrode 190 via the low-resistance semiconductor layer 111. Therefore, as shown in FIG. 4B, a capacitance C DS1 There will be a

[0039] On the other hand, in the semiconductor device 100 according to the first embodiment, the capacitance C DS2 exists.

[0040] That is, in the semiconductor device 100 according to the first embodiment, a capacitance C DS1 (The capacitance C between each shield electrode 154 and the source region 114 DS1 (composite capacitance of ) and capacitance C DS2 are arranged, and their capacitance (parasitic capacitance) forms a capacitor C between the source electrode 120 and the drain electrode 190 (see FIG. 4(a)).

[0041] The shield electrode 154 is made of polysilicon containing a predetermined concentration of impurities, and has an internal resistance. In addition, since the shield electrode 154 is disposed in a trench 151 formed in a stripe shape in a plan view (see FIG. 1(a)), the cross-sectional area of ​​the current conduction path is relatively small and the length of the current conduction path is relatively long. Therefore, the internal resistance of the shield electrode 154 has a resistance value that cannot be ignored. Therefore, each shield electrode 154 has a resistance component, and the combined resistance of the internal resistances of each shield electrode 154 constitutes a resistance R1 between the shield wiring 140 and the drain electrode 190 (see FIGS. 4(a) and (c)). The cross-sectional area refers to the area of ​​a cross section perpendicular to the current path.

[0042] Moreover, the snubber resistance adjuster 160 is a resistance component, and constitutes a resistance R2 between the drain electrode 190 and the source electrode 120 (see FIGS. 4(a) and 4(c)).

[0043] Therefore, the semiconductor device 100 becomes a semiconductor device (MOSFET) incorporating an RC snubber circuit in which a capacitor C and a resistor R (a combined resistance of resistors R1 and R2) are connected in series (see FIG. 4(a)).

[0044] Here, since the resistance R2 of the snubber resistance adjustment unit 160 can be changed regardless of the characteristics of the MOSFET, the semiconductor device 100 of embodiment 1 can easily adjust the resistance value of the snubber circuit, making it a highly flexible semiconductor device.

[0045] 3. Effects of the semiconductor device 100 according to the first embodiment According to the semiconductor device 100 of the first embodiment, the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjuster 160 having a resistance component, so that a resistance component other than the resistance component determined by the design of the semiconductor device based on the characteristics of the MOSFET can be added to the current path between the drain electrode 190 and the source electrode 120. Therefore, by adjusting the resistance component of the snubber resistance adjuster 160, it is possible to change the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electric device using the semiconductor device, without changing the characteristics of the MOSFET. As a result, a semiconductor device with a built-in snubber circuit can be flexibly applied to various electric devices.

[0046] Furthermore, according to the semiconductor device 100 of the first embodiment, in the snubber resistance adjustment section 160, the first shield wiring section 141 and the second shield wiring section 142 are connected to the source electrode 120 via the p-type peripheral diffusion region 115 formed on the surface of the drift layer 112, so that the source electrode 120 and the shield wiring 140 can be electrically connected to each other, and the resistance value between the shield wiring 140 and the source electrode 120 can be easily adjusted by adjusting the width, depth, length, impurity concentration, etc. of the peripheral diffusion region 115. This provides a semiconductor device in which the snubber resistance can be easily adjusted.

[0047] Moreover, according to the semiconductor device 100 of the first embodiment, the first shield wiring part 141 and the second shield wiring part 142 each have a plurality of shield side connecting parts 143, 144, and the source electrode 120 has a plurality of source electrode side connecting parts 121, 122 provided at positions facing the plurality of shield side connecting parts 143, 144. Therefore, the cross-sectional area of ​​the connection can be made smaller than when the shield wiring 140 and the source electrode 120 are directly connected, and this can contribute to the resistance component of the snubber resistance. Furthermore, the plurality of shield side connecting parts 143, 144 are connected to the corresponding source electrode side connecting parts 121, 122 via the peripheral diffusion region 115. Therefore, the snubber resistance can be adjusted by adjusting the number of contacts between the plurality of shield side connecting parts 143, 144 and the peripheral diffusion region 115. This results in a semiconductor device in which the snubber resistance can be adjusted even more easily.

[0048] Furthermore, according to the semiconductor device 100 of embodiment 1, since it has multiple peripheral trench structures 170, when a reverse bias is applied, the depletion layer can be extended to the peripheral region A2. Furthermore, since the relative dielectric constant of the oxide film (peripheral insulating region) is higher than the relative dielectric constant of silicon, the oxide film is less likely to be destroyed even when a large voltage is applied to it, and therefore the withstand voltage in the peripheral region A2 can be increased.

[0049] Furthermore, according to the semiconductor device 100 of the first embodiment, in the peripheral trench structure 170a closest to the cell region A1, the polysilicon layer 173 is connected to the shield wiring 140 via a metal plug (not shown) in a contact hole formed in the interlayer insulating film 180, so that a depletion layer extends from each of the p-type base region 113, the trench 151 closest to the peripheral region A2, and the peripheral trench structure 170 closest to the cell region A1 between the trench 151 closest to the peripheral region A2 and the peripheral trench structure 170 closest to the cell region A1, and the depletion layer is easily extended by using the pinch-off effect. Therefore, the breakdown voltage in this region is increased.

[0050] Generally, the polysilicon layer 173 in the peripheral trench 171 is connected to the shield wiring 140, and the shield wiring 140 is directly electrically connected to the source electrode 120, so that the polysilicon layer 173 is at the source potential. Therefore, when the source electrode 120 becomes 0V, the shield wiring 140 also becomes 0V. However, in the semiconductor device 100 according to the first embodiment, the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjustment unit 160 having a resistance component, so that the shield wiring 140 has a potential different from that of the source electrode 120. Therefore, even if the source electrode 120 becomes 0V, the shield wiring 140 does not become 0V, and the polysilicon layer 173 has a potential. Since such a potential is small, it is unlikely that it will affect the potential distribution in the semiconductor base 110 and cause a malfunction. However, in the semiconductor device 100 according to the first embodiment, in the peripheral trench structure 170b farthest from the cell region A1 among the multiple peripheral trench structures 170, the polysilicon layer 173 is connected to the source electrode 120 via the metal plug Pg4 in the contact hole formed in the interlayer insulating film 180, and the polysilicon layer 173 in the outermost peripheral trench 171 becomes the source potential, so that it is possible to more reliably prevent the potential distribution in the semiconductor base from being affected and causing a malfunction.

[0051] [Embodiment 2] The semiconductor device 101 according to the second embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the snubber resistance adjuster is different from that of the semiconductor device 100 according to the first embodiment. That is, in the semiconductor device 101 according to the second embodiment, in the snubber resistance adjuster 160a, a plurality of shield side connecting portions 143, 144 are connected to corresponding source electrode side connecting portions 121, 122 via metallic connecting wiring 162 instead of the peripheral diffusion region 115 (see FIG. 5).

[0052] The connection wiring 162 may be a metal film formed collectively with the source electrode 120 and the shield wiring 140, which has been thinned by etching or the like. In this case, the snubber resistance can be adjusted by cutting the connection wiring 162 by, for example, locally irradiating it with a laser. The connection wiring 162 may be a wire or connector made of a conductive material (for example, made of metal). The total width (cross-sectional area) of the connection wiring 162 is narrower (smaller) than the width (cross-sectional area) of the first shield wiring part 141 or the second shield wiring part 142, so that a current does not easily flow and becomes a resistance component.

[0053] As described above, the semiconductor device 101 according to the second embodiment has a different configuration of the snubber resistance adjuster from that of the semiconductor device 100 according to the first embodiment. However, as in the semiconductor device 100 according to the first embodiment, the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjuster 160a having a resistance component, so that a resistance component other than the resistance component determined by the design of the semiconductor device based on the characteristics of the MOSFET can be added to the current path between the drain electrode 190 and the source electrode 120. Therefore, by adjusting the resistance component of the snubber resistance adjuster 160a, it is possible to change the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical device using the semiconductor device without changing the characteristics of the MOSFET. As a result, a semiconductor device with a built-in snubber circuit is obtained that can be flexibly applied to various electrical devices.

[0054] Furthermore, according to the semiconductor device 101 of the second embodiment, the multiple shield side connecting portions 143, 144 are connected to the corresponding source electrode side connecting portions 121, 122 via the connecting wiring 162 made of a conductive material (for example, made of metal), so that the source electrode 120 and the shield wiring 140 can be electrically connected, and the resistance value between the shield wiring 140 and the source electrode 120 can be easily adjusted by adjusting the cross-sectional area, length, material, etc. of the connecting wiring 162. This results in a semiconductor device in which the snubber resistance can be easily adjusted.

[0055] Furthermore, according to the semiconductor device 101 of the second embodiment, the multiple shield side connecting portions 143, 144 are connected to the corresponding source electrode side connecting portions 121, 122 via the connecting wiring 162, and therefore can be formed collectively with the source electrode 120, the gate wiring 130, and the shield wiring 140. In this case, even at the end of the manufacturing process of the semiconductor device, for example, after the source electrode 120, the gate wiring 130, and the shield wiring 140 are formed, the snubber resistance can be adjusted by cutting off the connection of some of the connecting wirings 162 with a laser or the like.

[0056] In addition, the semiconductor device 101 of embodiment 2 has a configuration similar to that of the semiconductor device 100 of embodiment 1 except for the configuration of the snubber resistance adjustment section, and therefore has the corresponding effects among the effects of the semiconductor device 100 of embodiment 1.

[0057] [Embodiment 3] The semiconductor device 102 according to the third embodiment basically has the same configuration as the semiconductor device 101 according to the second embodiment, but the configuration of the snubber resistance adjuster is different from that of the semiconductor device 101 according to the second embodiment. That is, in the snubber resistance adjuster 160b of the semiconductor device 102 according to the third embodiment, a predetermined number of the multiple shield side connecting portions 143, 144 (two in the snubber resistance adjuster between the first shield wiring portion 141 and the source electrode 120 in the third embodiment) are connected to the source electrode side connecting portions 121, 122 via the metallic connecting wiring 162, and the rest are not connected (see FIG. 6).

[0058] As described above, the semiconductor device 102 according to the third embodiment has a different configuration of the snubber resistance adjuster from that of the semiconductor device 100 according to the first embodiment. However, as in the semiconductor device 101 according to the second embodiment, the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjuster 160b having a resistance component, so that a resistance component other than the resistance component determined by the design of the semiconductor device based on the characteristics of the MOSFET can be added to the current path between the drain electrode 190 and the source electrode 120. Therefore, by adjusting the resistance component of the snubber resistance adjuster 160b, it is possible to change the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical device that uses the semiconductor device, without changing the characteristics of the MOSFET. As a result, a semiconductor device with a built-in snubber circuit is obtained that can be flexibly applied to various electrical devices.

[0059] Furthermore, in the semiconductor device 102 according to the third embodiment, some of the multiple shield side connecting portions 143, 144 in the snubber resistance adjuster 160b are not connected to the source electrode side connecting portions 121, 122, and therefore the resistance value between the source electrode 120 and the shield wiring 140 becomes larger. Therefore, a wider range of resistance values ​​of the snubber resistors can be selected, resulting in a semiconductor device with a built-in snubber circuit that can be flexibly applied to a wider range of electric devices.

[0060] In addition, the semiconductor device 102 of embodiment 3 has a configuration similar to that of the semiconductor device 101 of embodiment 2 except for the configuration of the snubber resistance adjustment section, and therefore has the corresponding effects among the effects of the semiconductor device 101 of embodiment 2.

[0061] [Embodiment 4] The semiconductor device 103 according to the fourth embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the snubber resistance adjustment section is different from that of the semiconductor device 100 according to the first embodiment. That is, in the snubber resistance adjustment section 160c of the semiconductor device 103 according to the fourth embodiment, a predetermined number of the multiple shield side connection sections 143, 144 (two in the snubber resistance adjustment section between the first shield wiring section 141 and the source electrode 120 in the fourth embodiment) are connected to the corresponding source electrode side connection sections 121, 122 via the metallic connection wiring 162, and the remaining ones (three in the snubber resistance adjustment section between the first shield wiring section 141 and the source electrode 120 in the fourth embodiment) are connected to the corresponding source electrode side connection sections 121, 122 via the peripheral diffusion region 115 (see FIG. 7).

[0062] As described above, the semiconductor device 103 according to the fourth embodiment has a different configuration of the snubber resistance adjuster from that of the semiconductor device 100 according to the first embodiment. However, as in the semiconductor device 100 according to the first embodiment, the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjuster 160c having a resistance component, so that a resistance component other than the resistance component determined by the design of the semiconductor device based on the characteristics of the MOSFET can be added to the current path between the drain electrode 190 and the source electrode 120. Therefore, by adjusting the resistance component of the snubber resistance adjuster 160c, it is possible to change the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical device using the semiconductor device without changing the characteristics of the MOSFET. As a result, a semiconductor device with a built-in snubber circuit is obtained that can be flexibly applied to various electrical devices.

[0063] Furthermore, according to the semiconductor device 103 of embodiment 4, of the multiple shield side connection parts 143, 144, a predetermined number are connected to the corresponding source electrode side connection parts 121, 122 via the metallic connection wiring 162, and the remainder are connected to the corresponding source electrode side connection parts 121, 122 via the peripheral diffusion region 115. Therefore, by adjusting the number of wires connected to the metallic connection wiring 162 and the number of wires connected to the peripheral diffusion region 115, the resistance value between the source electrode 120 and the shield electrode 30 can be adjusted widely and in detail, resulting in a semiconductor device with an internal snubber circuit that can be flexibly applied to a wider range of electrical devices.

[0064] In addition, the semiconductor device 103 of embodiment 4 has a configuration similar to that of the semiconductor device 100 of embodiment 1 except for the configuration of the snubber resistance adjustment section, and therefore has the corresponding effects among the effects of the semiconductor device 100 of embodiment 1.

[0065] [Embodiment 5] The semiconductor device 104 according to the fifth embodiment has a configuration similar to that of the semiconductor device 103 according to the fourth embodiment, but the configuration of the snubber resistance adjustment section is different from that of the semiconductor device 103 according to the fourth embodiment. That is, in the snubber resistance adjustment section 160d of the semiconductor device 104 according to the fifth embodiment, among the multiple shield side connection sections 143, 144, a predetermined number (two in the snubber resistance adjustment section between the first shield wiring section 141 and the source electrode 120 in the fifth embodiment) are connected to the corresponding source electrode side connection sections 121, 122 via the metallic connection wiring 162, a predetermined number (two in the snubber resistance adjustment section between the first shield wiring section 141 and the source electrode 120 in the fifth embodiment) are connected to the corresponding source electrode side connection sections 121, 122 via the peripheral diffusion region 115, and the remaining ones are not connected to the source electrode side connection sections 121, 122 (see FIG. 8).

[0066] The peripheral diffusion region 115 is formed all between the multiple (five in the fifth embodiment) shield side connection parts 143, 144 and the multiple (five in the fifth embodiment) source electrode side connection parts 121, 122. With this configuration, it is possible to select whether the shield side connection parts 143, 144 and the source electrode side connection parts 121, 122 are connected by the connection wiring 162, connected by the peripheral diffusion region 115, or not connected at all.

[0067] As described above, the semiconductor device 104 according to the fifth embodiment has a different configuration of the snubber resistance adjuster from that of the semiconductor device 103 according to the fourth embodiment. However, as in the semiconductor device 103 according to the fourth embodiment, the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjuster 160d having a resistance component, so that a resistance component other than the resistance component determined by the design of the semiconductor device based on the characteristics of the MOSFET can be added to the current path between the drain electrode 190 and the source electrode 120. Therefore, by adjusting the resistance component of the snubber resistance adjuster 160d, it is possible to change the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical device using the semiconductor device without changing the characteristics of the MOSFET. As a result, a semiconductor device with a built-in snubber circuit is obtained that can be flexibly applied to various electrical devices.

[0068] In addition, the semiconductor device 104 of embodiment 5 has a configuration similar to that of the semiconductor device 103 of embodiment 4 except for the configuration of the snubber resistance adjustment section, and therefore has the corresponding effects among the effects of the semiconductor device 103 of embodiment 4.

[0069] [Embodiment 6] The semiconductor device 105 according to the sixth embodiment basically has the same configuration as the semiconductor device 104 according to the fifth embodiment, but the configuration of the snubber resistance adjuster is different from that of the semiconductor device 104 according to the fifth embodiment. That is, the snubber resistance adjuster 160e of the semiconductor device 105 according to the sixth embodiment is formed between adjacent trenches 151, not outside the lattice-shaped trenches 151, 157, and 158. In the sixth embodiment, the first shield wiring portion 141 and the second shield wiring portion 142 are separated from the source electrode 120 (see FIGS. 9 and 10).

[0070] The snubber resistance adjustment portion 160e is a region in which the first shield wiring portion 141 and the second shield wiring portion 142 are electrically connected to the source electrode 120 via a diffusion region 116, which will be described later.

[0071] The semiconductor substrate 110a has a p-type diffusion region 116 formed on the surface of the drift layer 112 between (sandwiched) adjacent trenches 151 in the peripheral region A2, from a region where the first shield wiring part 141 or the second shield wiring part 142 is connected to the semiconductor substrate 110a to a region where the source electrode 120 is connected to the semiconductor substrate 110a (see FIG. 10). The diffusion region 116 is connected to the source electrode 120 via a metal plug Pg3 in a contact hole formed in the interlayer insulating film 180. The diffusion region 116 is also connected to the shield wiring 140 via a metal plug Pg5 in a contact hole formed in the interlayer insulating film 180.

[0072] The diffusion region 116 has a region that is narrower than the length between adjacent trenches 151 in a part between the region where the first shield wiring part 141 or the second shield wiring part 142 is connected to the semiconductor base 110a and the region where the source electrode 120 is connected to the semiconductor base 110a in a plan view. That is, the diffusion region 116 is formed only in a part near the center separated from the trenches 151 in a plan view, and the drift layer 112 is exposed on the surface between the diffusion region 116 and each trench 151. Since the diffusion region 116 is formed collectively with the base region 113, it has the same depth as the base region 113.

[0073] The diffusion region 116 is a region doped with p-type impurities, and therefore has an internal resistance. The snubber resistance can be changed by adjusting the width and depth of the diffusion region 116 and the impurity concentration of the p-type impurity, resulting in a highly flexible semiconductor device.

[0074] As described above, the semiconductor device 105 according to the sixth embodiment has a different configuration of the snubber resistance adjuster from that of the semiconductor device 100 according to the first embodiment. However, as in the semiconductor device 100 according to the first embodiment, the shield wiring 140 is electrically connected to the source electrode 120 via the snubber resistance adjuster 160e having a resistance component, so that a resistance component other than the resistance component determined by the design of the semiconductor device based on the characteristics of the MOSFET can be added to the current path between the drain electrode 190 and the source electrode 120. Therefore, by adjusting the resistance component of the snubber resistance adjuster 160e, it is possible to change the snubber resistance and, in turn, the characteristics of the snubber circuit according to the electrical device using the semiconductor device without changing the characteristics of the MOSFET. As a result, a semiconductor device with a built-in snubber circuit is obtained that can be flexibly applied to various electrical devices.

[0075] Furthermore, according to the semiconductor device 105 of the sixth embodiment, the semiconductor body 110a has, between adjacent trenches 151 in the peripheral region A2, a p-type diffusion region 116 formed from a region where the first shield wiring portion 141 or the second shield wiring portion 142 is connected to the semiconductor body 110a to a region where the source electrode 120 is connected to the semiconductor body 110a, and the snubber resistance adjuster 160e is a region where the first shield wiring portion 141 and the second shield wiring portion 142 are electrically connected to the source electrode 120 via the diffusion region 116. Therefore, the area occupied by the snubber resistance adjuster 160e is smaller than that in the case where the snubber resistance adjuster is formed outside the region where the trenches 151 are formed, and a miniaturized semiconductor device can be obtained.

[0076] Furthermore, in the semiconductor device 105 of the sixth embodiment, the diffusion region 116 has a region between the region overlapping with the first shield wiring part 141 or the second shield wiring part 142 and the region overlapping with the source electrode 120, where the width of the diffusion region 116 is narrower than the length between adjacent trenches. This makes it possible to increase the resistance value of the snubber resistor, resulting in a semiconductor device that is easily compatible with electrical devices that can be used.

[0077] In addition, the semiconductor device 105 of embodiment 6 has a configuration similar to that of the semiconductor device 100 of embodiment 1 except for the configuration of the snubber resistance adjustment section, and therefore has the corresponding effects among the effects of the semiconductor device 100 of embodiment 1.

[0078] Although the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment. It can be embodied in various forms without departing from the spirit of the present invention, and for example, the following modifications are also possible.

[0079] (1) The shapes, positions, sizes, etc. described in the above embodiments (including the modified examples; the same applies below) are merely examples and may be modified without impairing the effects of the present invention. In addition, the embodiments and modified examples may be combined.

[0080] (2) In the above embodiments 1 to 5, a shield side connection portion protruding toward the source electrode 120 is provided, but the present invention is not limited to this. A shield side connection portion that does not protrude toward the source electrode 120 may be provided. In addition, a plurality of source electrode side connection portions protruding toward the first shield wiring portion 141 or the second shield wiring portion 142 are provided, but the present invention is not limited to this. A source electrode side connection portion that does not protrude toward the first shield wiring portion 141 or the second shield wiring portion 142 may be provided.

[0081] (3) In each of the above embodiments, the number of source electrode side connection parts and shield side connection parts may be any number. In addition, the number of source electrode side connection parts connected to the shield side connection parts via connection wiring and the number of source electrode side connection parts connected via the peripheral diffusion region may also be any number.

[0082] (4) In the sixth embodiment, the diffusion region 116 has a narrow region, but the present invention is not limited to this. The diffusion region 116 does not have to be narrow. Even in this case, the electrical conductivity of the diffusion region 116 is smaller than that of metal, and it becomes a resistance component.

[0083] (5) In the sixth embodiment, the diffusion region 116 has the same depth as the base region, but the present invention is not limited to this. The diffusion region may have a shallower region than the base region, or may have a deeper region than the base region.

[0084] (6) In the sixth embodiment, the diffusion region 116 has the same impurity concentration as the base region, but the present invention is not limited to this. The diffusion region may have a different impurity concentration than the base region. Also, the impurity in the diffusion region 116 may be a different type of impurity than the impurity in the base region.

[0085] (7) In the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this. The first conductivity type may be p-type and the second conductivity type may be n-type. [Explanation of symbols]

[0086] 100, 101, 102, 103, 104, 105...semiconductor device, 110, 110a...semiconductor substrate, 111...low-resistance semiconductor layer, 112...drift layer, 113...base region, 114...source region, 115...peripheral diffusion region, 116...diffusion region, 120...source electrode, 121, 122...source electrode side connection portion, 130...gate wiring, 131...first gate wiring portion, 132...second gate wiring portion, 140...shield wiring, 141...first shield wiring portion, 142...second shield wiring portion, 143, 144...shield side Connection portion, 151... trench, 152... gate insulating film, 153... gate electrode, 154... shield electrode, 155... insulating region, 157, 158... connection trench, 160, 160a, 160b, 160c, 160d, 160e... snubber resistance adjustment portion, 162... connection wiring, 170, 170a, 170b... peripheral trench structure, 171... peripheral trench, 172... peripheral insulating region, 173... polysilicon layer, 180... interlayer insulating film, 190... drain electrode, A1... cell region, A2... peripheral region, Pg1 to Pg7... metal plugs

Claims

1. A semiconductor device in which a cell region and a peripheral region formed in a region surrounding the cell region are defined in a plan view, a semiconductor substrate including a drift layer of a first conductivity type formed in the cell region and the peripheral region, a base region of a second conductivity type formed on a surface of the drift layer in at least the cell region, and a source region of the first conductivity type formed on a part of a surface of the base region; a source electrode disposed on a surface of the semiconductor substrate in at least the cell region via an interlayer insulating film; a gate wiring having a first gate wiring portion and a second gate wiring portion disposed on a surface of the semiconductor substrate in the peripheral region via an interlayer insulating film and opposed to each other across the source electrode in a plan view; a shield wiring arranged on the surface of the semiconductor substrate in the peripheral region via an interlayer insulating film, the shield wiring having a first shield wiring portion and a second shield wiring portion arranged at positions facing each other with the first gate wiring portion, the source electrode, and the second gate wiring portion interposed therebetween in a plan view; a plurality of trenches formed in parallel on a surface of the semiconductor substrate, extending from a region overlapping with the first shield wiring portion in a plan view across the cell region to a region overlapping with the second shield wiring portion, and formed to a depth reaching the drift layer in the cell region; a gate electrode disposed within each of the trenches via a gate insulating film formed on an inner surface of the trench, the gate electrode being connected to the gate wiring in the peripheral region; a shield electrode disposed inside each of the plurality of trenches and spaced apart from an inner surface of the trench and the gate electrode, and connected to the first shield wiring portion and the second shield wiring portion in the peripheral region; an insulating region extending between the gate electrode and the shield electrode within each of the plurality of trenches to separate the shield electrode from the gate electrode, and extending between an inner surface of the trench and the shield electrode to separate the shield electrode from the inner surface of the trench; The semiconductor device according to the present invention is characterized in that the shield wiring is electrically connected to the source electrode via a snubber resistance adjustment portion having a resistance component.

2. 2. The semiconductor device according to claim 1, wherein in the snubber resistance adjustment portion, the first shield wiring portion and the second shield wiring portion are connected to the source electrode via at least one of a connection wiring having a cross-sectional area smaller than the cross-sectional area of ​​either the first shield wiring portion or the second shield wiring portion, and a peripheral diffusion region of a second conductivity type formed on a surface of the drift layer.

3. In the peripheral region, the first shield wiring portion and the second shield wiring portion each have a plurality of shield-side connecting portions, the source electrode has a plurality of source electrode side connection portions provided at positions facing the plurality of shield side connection portions, a plurality of the peripheral diffusion regions each formed in a strip shape are formed on a surface of the drift layer between the plurality of shield side connection portions and the plurality of source electrode side connection portions in a plan view, 3. The semiconductor device according to claim 2, wherein in the snubber resistance adjustment portion, at least one of the plurality of shield side connection portions is connected to a corresponding one of the plurality of source electrode side connection portions via the peripheral diffusion region.

4. In the peripheral region, the first shield wiring portion and the second shield wiring portion each have a plurality of shield-side connecting portions, the source electrode has a plurality of source electrode side connection portions provided at positions facing the plurality of shield side connection portions, 3. The semiconductor device according to claim 2, wherein in the snubber resistance adjustment portion, at least one of the plurality of shield side connection portions is connected to a corresponding one of the plurality of source electrode side connection portions via the connection wiring.

5. In the peripheral region, the first shield wiring portion and the second shield wiring portion each have a plurality of shield-side connecting portions, the source electrode has a plurality of source electrode side connection portions provided at positions facing the plurality of shield side connection portions, 3. The semiconductor device according to claim 2, wherein in the snubber resistance adjustment portion, at least one of the plurality of shield side connection portions is connected to the corresponding source electrode side connection portion via the connection wiring or the peripheral diffusion region, and at least one of the plurality of shield side connection portions is not connected to the source electrode side connection portion.

6. the first shield wiring portion and the second shield wiring portion are spaced apart from the source electrode, the semiconductor body further includes a diffusion region of a second conductivity type formed on a surface of the drift layer between the trenches adjacent to each other in the peripheral region, the diffusion region being between a region where the first shield wiring portion or the second shield wiring portion and the semiconductor body are connected to a region where the source electrode and the semiconductor body are connected; 2. The semiconductor device according to claim 1, wherein in the snubber resistance adjustment section, the first shield wiring section and the second shield wiring section are electrically connected to the source electrode via the diffusion region.

7. 7. The semiconductor device according to claim 6, further comprising a region between a region where the first shield wiring portion or the second shield wiring portion and the semiconductor body are connected to a region where the source electrode and the semiconductor body are connected, in which the width of the diffusion region is narrower than the length between adjacent trenches.

8. 7. The semiconductor device according to claim 6, further comprising a region in which the diffusion region is shallower than the base region, between a region in which the first shield wiring portion or the second shield wiring portion and the semiconductor body are connected to a region in which the source electrode and the semiconductor body are connected.

9. 7. The semiconductor device according to claim 6, further comprising a region between a region where the first shield wiring portion or the second shield wiring portion and the semiconductor body are connected to a region where the source electrode and the semiconductor body are connected, the region having an impurity concentration of the diffusion region lower than that of the base region.

10. the source electrode extends, as viewed from the source electrode, to a region overlapping the peripheral region along a direction different from a direction in which the first shield wiring portion and the first gate wiring portion are arranged and a direction in which the second shield wiring portion and the second gate wiring portion are arranged; In the region where the source electrode and the peripheral region overlap, A plurality of peripheral trench structures are provided on one surface of the semiconductor substrate, the peripheral trench structures having a plurality of peripheral trenches and a polysilicon layer embedded in each of the plurality of peripheral trenches via a peripheral insulating region formed therein; Among the plurality of peripheral trench structures, in a peripheral trench structure closest to the cell region, the polysilicon layer is connected to the shield wiring, 10. The semiconductor device according to claim 1, wherein, in a peripheral trench structure farthest from the cell region among the plurality of peripheral trench structures, the polysilicon layer is connected to the source electrode.

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