Semiconductor structure and manufacturing method thereof, memory chip, electronic device

Abstract

The embodiments of the present disclosure relate to a semiconductor field, and provide a semiconductor structure and its manufacturing method, a memory chip, and an electronic device, the semiconductor structure includes a substrate and a plurality of lead posts, a stack structure is provided on the substrate, the stack structure includes a plurality of memory cell groups arranged in a first direction, the memory cell group includes a plurality of layers of memory cells arranged in a second direction, and at least two of the lead posts are respectively connected to the memory cells of different layers in the different memory cell groups. The embodiments of the present disclosure can at least improve the integration degree of the semiconductor structure.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on June 21, 2022, entitled "Semiconductor structure and manufacturing method thereof, memory chip, and electronic device" and bearing application number 202210723121.3, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD The embodiments of the present disclosure are in the field of semiconductors, and in particular, relate to semiconductor structures and methods for fabricating same, memory chips, and electronic devices. [Background technology]

[0003] A semiconductor structure includes a number of memory cells, which need to be connected to peripheral circuits to perform memory functions. The higher the integration density of a semiconductor structure, the more memory cells it can accommodate, and the better the performance of the semiconductor structure. However, in current semiconductor structures, a lot of space is wasted. In addition, due to limitations in physical properties, the volume of memory cells has reached a scaling limit, and due to limitations in process factors, it is also difficult to increase the number of stacked memory cells.

[0004] Therefore, there is an urgent need for a semiconductor structure having a new architecture that can increase the integration density of the semiconductor structure. Summary of the Invention

[0005] SUMMARY OF THE DISCLOSURE The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a memory chip, and an electronic device that can improve the integration density of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, one aspect of the embodiments of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes a substrate and a plurality of lead posts, a stacked structure is provided on the substrate, the stacked structure includes a plurality of memory cell groups arranged in a first direction, the memory cell groups include a plurality of layers of memory cells arranged in a second direction, and at least two of the lead posts are respectively connected to memory cells of different layers in different memory cell groups.

[0007] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, the method for manufacturing the semiconductor structure including: providing a substrate; forming a stacked structure on the substrate, the stacked structure including a plurality of memory cell groups arranged in a first direction, the memory cell group including a plurality of layers of memory cells arranged in a second direction; and forming a plurality of lead posts, at least two of the lead posts being respectively connected to memory cells of different layers in different memory cell groups.

[0008] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a semiconductor structure, wherein the semiconductor structure includes a substrate and a plurality of lead posts, a stacked structure is provided on the substrate, the stacked structure includes a plurality of memory cell groups arranged in a first direction, the memory cell group includes a plurality of layers of memory cells arranged in a second direction, and at least two of the lead posts are connected to different memory cells in the same memory cell group.

[0009] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a memory chip, the memory chip comprising the above semiconductor structure.

[0010] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides an electronic device, the electronic device including the above-mentioned memory chip.

[0011] The technical solutions provided in the embodiments of the present disclosure have at least the following advantages:

[0012] In the semiconductor structure provided in the embodiment of the present disclosure, at least two lead posts are connected to memory cells in different layers in a memory cell group, i.e., at least two lead posts are directly connected to the memory cells, which reduces the number of steps or eliminates the need to arrange a separate step region, and helps to improve the integration density of the semiconductor structure. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is an overhead view of a semiconductor structure. [Diagram 2] FIG. 2 is an enlarged view of a portion of FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along the line A-A1 in FIG. [Figure 4] FIG. 2 is a schematic diagram of a laminate structure provided in an embodiment of the present disclosure. [Diagram 5] 1 is a top view of one of seven different semiconductor structures provided in embodiments of the present disclosure. [Figure 6] 1 is a top view of one of seven different semiconductor structures provided in embodiments of the present disclosure. [Figure 7] 1 is a top view of one of seven different semiconductor structures provided in embodiments of the present disclosure. [Figure 8] 1 is a top view of one of seven different semiconductor structures provided in embodiments of the present disclosure. [Figure 9] 1 is a top view of one of seven different semiconductor structures provided in embodiments of the present disclosure. [Figure 10] 1 is a top view of one of seven different semiconductor structures provided in embodiments of the present disclosure. [Figure 11] 1 is a top view of one of seven different semiconductor structures provided in embodiments of the present disclosure. [Figure 12] FIG. 2 is a schematic diagram of a memory cell group provided in an embodiment of the present disclosure. [Figure 13] 1 is a partial side view of a semiconductor structure provided in an embodiment of the present disclosure. [Figure 14] FIG. 2 is a schematic diagram of another memory cell group provided in an embodiment of the present disclosure. [Figure 15] 2 is a local side view of another semiconductor structure provided in accordance with an embodiment of the present disclosure. [Figure 16] 11 is a schematic diagram of yet another group of memory cells provided in accordance with an embodiment of the present disclosure. [Figure 17] 1 is a partial side view of yet another semiconductor structure provided in accordance with an embodiment of the present disclosure. [Figure 18] FIG. 2 is a schematic diagram of one of four different memory cell groups provided in an embodiment of the present disclosure. [Figure 19] FIG. 2 is a schematic diagram of one of four different memory cell groups provided in an embodiment of the present disclosure. [Figure 20] FIG. 2 is a schematic diagram of one of four different memory cell groups provided in an embodiment of the present disclosure. [Figure 21] FIG. 2 is a schematic diagram of one of four different memory cell groups provided in an embodiment of the present disclosure. [Figure 22] FIG. 2 is a schematic diagram of a structural module provided in an embodiment of the present disclosure. [Diagram 23] 1A to 1C are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. [Figure 24] 1A to 1C are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. [Diagram 25] 1A to 1C are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. [Figure 26] 1A to 1C are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. [Figure 27] 1A to 1C are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. [Figure 28]1A to 1C are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. [Figure 29] 1A to 1C are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. [Diagram 30] 1A to 1C are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. [Diagram 31] 1A to 1C are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. [Diagram 32] 3A-3C are schematic structural diagrams corresponding to steps in a method for manufacturing another semiconductor structure provided in an embodiment of the present disclosure. [Diagram 33] 3A-3C are schematic structural diagrams corresponding to steps in a method for manufacturing another semiconductor structure provided in an embodiment of the present disclosure. [Diagram 34] 3A-3C are schematic structural diagrams corresponding to steps in a method for manufacturing another semiconductor structure provided in an embodiment of the present disclosure. [Diagram 35] 3A-3C are schematic structural diagrams corresponding to steps in a method for manufacturing another semiconductor structure provided in an embodiment of the present disclosure. [Diagram 36] 11 is a schematic diagram of yet another group of memory cells provided in accordance with an embodiment of the present disclosure. [Figure 37] FIG. 1 is a top view of one of two different semiconductor structures provided in embodiments of the present disclosure; [Figure 38] 1A-1C are top-down views of two different semiconductor structures provided in embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The above drawings are incorporated in and constitute a part of this specification, and the above drawings illustrate embodiments according to the present disclosure, and are used together with the specification to explain the principles of the present disclosure. It is obvious that the following drawings are merely some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0015] FIG. 1 is a bird's-eye view of the semiconductor structure, FIG. 2 is an enlarged view of the step in the dotted circle in FIG. 1, and FIG. 3 is a cross-sectional view in the A-A1 direction in FIG. 2. Referring to FIG. 1 to FIG. 3, the semiconductor structure includes a memory cell region 100 and a step region 200. A plurality of layers of memory cells are provided in the memory cell region 100. A plurality of steps are provided in the step region 200, and each step and each layer of memory cell are provided in one-to-one correspondence. A connection layer (not shown) may be provided in the step, and a lead post 300 may be provided on the step. The lead post 300 is electrically connected to the memory cell via the connection layer in the step, and thus the memory cell can be connected to a peripheral circuit by drawing out the memory cell. However, as the number of stacked memory cells increases, the area occupied by the step region 200 increases. For example, if there are a total of 64 layers of memory cells, 64 steps are required, and the area of ​​the step increases toward the lower step. If the area of ​​the step in the top step is 0.25 μm 2 If so, the area of ​​the bottom step is 64*0.25=16μm 2 3, the connection layer under each step is only used for support and electrical connection, resulting in a waste of space underneath. Therefore, there is a need to further improve the integration density of semiconductor structures.

[0016] An embodiment of the present disclosure provides a semiconductor structure, in which at least two of the plurality of lead posts are connected to memory cells in different layers in different memory cell groups, i.e., at least two lead posts are directly connected to memory cells, which reduces the number of steps or eliminates the need for a separate step region, and helps to improve space utilization and improve the integration degree of the semiconductor structure.

[0017] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. However, as can be understood by those skilled in the art, although many technical details are disclosed in each embodiment of the present disclosure to allow readers to better understand the embodiments of the present disclosure, the technical solutions claimed in the embodiments of the present disclosure can be realized without these technical details or various changes and modifications based on the following embodiments.

[0018] As shown in Figures 4 to 22, an embodiment of the present disclosure provides a semiconductor structure, which includes a substrate 11 (see Figure 23) and a plurality of lead posts 5, and a stacked structure is provided on the substrate 11, the stacked structure includes a plurality of memory cell groups TC0 arranged in a first direction X, the memory cell group TC0 includes a plurality of layers of memory cells TC arranged in a second direction Z, and at least two lead posts 5 are respectively connected to memory cells TC of different layers in different memory cell groups TC0.

[0019] That is, the number of steps can be reduced by stacking the memory cells TC in multiple layers and directly connecting at least two lead posts 5 to the memory cells TC. If all the lead posts 5 are directly connected to the memory cells TC, there is no need to provide a separate step region. That is, the orthogonal projection of the lead posts 5 connected to the storage unit memory cells TC on the surface of the substrate 11 falls within the orthogonal projection of the stacked structure on the surface of the substrate 11, thereby improving the utilization rate of the surface of the substrate 11 and improving the integration degree of the semiconductor structure. Furthermore, at least two lead posts 5 are connected to memory cells TC of different layers in different memory cell groups TC0, which means that at least two lead posts 5 can utilize the spatial positions of different memory cell groups TC0.

[0020] The semiconductor structure will now be described in detail with reference to the drawings.

[0021] In some embodiments, referring to FIGS. 4-5 and 8-22, all memory cells TC in the same memory cell group TC0 are connected to at most one lead post 5. That is, each memory cell group TC0 only needs to have one connection position between the lead post 5 and the memory cell TC. Since the number of connection positions in the same memory cell group TC0 is relatively small, the connection methods in different memory cell groups TC0 are relatively unified, which helps to unify the connection process between different lead posts 5 and memory cells TC, thereby reducing the manufacturing cost. It should be noted that in order to connect the lead posts 5 to different memory cells TC, at least some of the lead posts 5 may penetrate at least one memory cell TC by removing a part of the structure in the memory cell TC, or the lead posts 5 may be provided on the sidewall of the memory cell TC to penetrate the memory cell TC.

[0022] In some other embodiments, referring to FIG. 6 and FIG. 7, the memory cells TC connected to at least two lead posts 5 are located in the same memory cell group TC0. That is, each memory cell group TC0 may have multiple connection positions between the lead posts 5 and the memory cells TC. It should be noted that in order to connect the lead posts 5 and the memory cells TC, it is usually necessary to remove a part of the structure in the memory cell TC, thereby providing the spatial position required by the lead posts 5. After removing the part of the structure in the memory cell TC, the memory cell TC may no longer perform a memory function. When multiple lead posts 5 are located in the same memory cell group TC0, this helps to reduce the number of ineffective memory cells TC, which can improve the space utilization rate and the integration degree in the semiconductor structure.

[0023] Specifically, memory cells TC connected to at least two lead posts 5 being located in the same memory cell group TC0 may include two situations: at least two lead posts 5 located in the same memory cell group TC0 are connected to memory cells TC in the same layer, or at least two lead posts 5 located in the same memory cell group TC0 are connected to memory cells TC in different layers.

[0024] Referring to FIG. 6, at least two lead posts 5 located in the same memory cell group TC0 can be arranged along the first direction X, and referring to FIG. 7, at least two lead posts 5 located in the same memory cell group TC0 can be arranged along the third direction Y.

[0025] In some embodiments, referring to FIG. 4, the number of lead posts 5 is greater than or equal to the number of layers of memory cells TC, and each layer includes at least a memory cell TC connected to a lead post 5. That is, the memory cell TC of each layer can be directly connected to the lead post 5 without providing a separate step region. Furthermore, the memory cell TC of each layer may be led out by one or more lead posts 5. If the memory cell TC of each layer is led out by one lead post 5, it is helpful to simplify the manufacturing process, and if the memory cell TC of each layer is led out by multiple lead posts 5, it is helpful to increase the contact area, thereby reducing the contact resistance.

[0026] It should be noted that since the memory cell group TC0 has various different structures, if the number of lead posts 5 connected to the same memory cell group TC0 is too large, the spatial positions required by the lead posts 5 will be large, and different lead posts 5 may be connected to different structures in the memory cell group TC0, and different connection processes are usually required for different structures. In some embodiments, the number of lead posts 5 connected to the same memory cell group TC0 is less than the number of layers of memory cells TC in the memory cell group TC0, and by controlling the number of lead posts 5 connected to the same memory cell group TC0, the number can be kept within an appropriate range, thereby simplifying the connection process between the lead posts 5 and the memory cells TC.

[0027] 6, 8 and 9, in some embodiments, the lead posts 5 are arranged in a row along the first direction X. That is, in the first direction X, the multiple lead posts 5 are roughly aligned, which makes it easier to connect the multiple lead posts 5 to the same structure in the memory cells TC, which helps to unify the connection process between the lead posts 5 and the memory cells TC and reduce manufacturing costs.

[0028] For example, referring to Fig. 8, the lead posts 5 are arranged in series along the first direction X. In other words, the lead posts 5 are arranged on the same straight line, and both ends of the multiple lead posts 5 are aligned in the first direction X, which is helpful to simplify the process and improve the uniformity of the semiconductor structure. Furthermore, referring to Fig. 9, the lead posts 5 may be slightly offset from each other, that is, both ends of the multiple lead posts 5 may not be aligned in the first direction X, which can reduce the facing area of ​​the lead posts 5 and reduce the parasitic capacitance between adjacent lead posts 5.

[0029] 4 and 12 to 22, at least one lead post 5 extends in the second direction Z and penetrates at least one memory cell TC of the memory cell group TC0, and in this case, the orthogonal projection of the at least one lead post 5 on the surface of the substrate 11 is located within the orthogonal projection of the memory cell TC on the surface of the substrate 11. In the following, this will be described in detail, and for ease of understanding, the lead post 5 is divided into a contact portion 51 and an extension portion 52, which are stacked. The contact portion 51 is connected to the memory cell TC, and the memory cell TC connected to the contact portion 51 is called the memory cell TC of the corresponding layer.

[0030] Specifically, at least two lead posts 5 are respectively connected to memory cells TC of different layers of different memory cell groups TC0, which means that at least one lead post 5 is connected to a memory cell TC of a non-top layer. The lead post 5 connected to the memory cell TC of a non-top layer needs to occupy the spatial position of the memory cell TC above the corresponding layer in addition to the spatial position of the memory cell TC of the corresponding layer. For example, referring to FIG. 12, FIG. 14 and FIG. 16, when the second top layer is used as the corresponding layer and the contact portion 51 of the lead post 5 is connected to the memory cell TC of the second top layer, the extension portion 52 of the lead post 5 needs to penetrate the memory cell TC of the top layer. The penetrated memory cell TC and the memory cell TC connected to the lead post do not have a memory function. In other words, the spatial position can be provided for the extension portion 52 of the lead post 5 by directly removing a part of the structure of the memory cell TC above the corresponding layer, thus simplifying the manufacturing process.

[0031] It should be explained that in some other embodiments, the extension 52 of the lead post 5 may not occupy the spatial position of the memory cell TC above the corresponding layer, but may occupy the spatial position between the adjacent memory cells TC. Specifically, referring to FIG. 10, a part of the contact portion 51 of the lead post 5 protrudes from the position of the memory cell TC of the corresponding layer and is provided in the space between the adjacent memory cells TC, thereby allowing the extension 52 of the lead post 5 to be drawn upward from the gap between the adjacent memory cells TC without penetrating the memory cell TC above the corresponding layer, thereby reducing the number of invalid memory cells TC. Alternatively, referring to FIG. 11, the contact portion 51 and the extension 52 of the lead post 5 are provided in the space between the adjacent memory cells TC, and the contact portion 51 contacts the sidewall of the memory cell TC of the corresponding layer, thereby allowing the extension 52 of the lead post 5 to be drawn upward from the gap between the adjacent memory cells TC without penetrating the memory cell TC above the corresponding layer, thereby reducing the number of invalid memory cells TC.

[0032] Referring to Figure 4, in the case of a lead post 5 connected to a memory cell TC in the top layer, the lead post 5 only needs to use the spatial position of the memory cell TC in the corresponding layer and does not need to occupy the spatial position of other memory cells TC, and therefore does not need to penetrate memory cells TC other than the corresponding layer.

[0033] It should be noted that in some embodiments, referring to Figures 4, 12 and 13, the lead post 5 may penetrate the memory cell TC of the corresponding layer, i.e., by removing a portion of the structure of the memory cell TC of the corresponding layer, a spatial location is provided for the contact portion 51 of the lead post 5, in which case at least a portion of the side of the lead post 5 is connected to the memory cell TC.

[0034] In some other embodiments, the lead post 5 may not penetrate into the memory cell TC of the corresponding layer. For example, referring to Fig. 14 and Fig. 15, the lead post 5 is embedded in the memory cell TC of the corresponding layer, and in this case, the bottom surface and some side surfaces of the lead post 5 are connected to the memory cell TC. Furthermore, referring to Fig. 16 and Fig. 17, the bottom surface of the lead post 5 is connected to the top surface of the memory cell TC of the corresponding layer.

[0035] 4, 13, 15 and 17, the number of memory cells TC that are penetrated by at least two lead posts 5 is different from each other. That is, at least two lead posts 5 are connected to memory cells TC in different layers, thereby drawing out memory cells TC in different layers. In this way, at least two steps can be reduced, and the volume of the semiconductor structure can be reduced.

[0036] 12, 14, 16, 18-21, the semiconductor structure further includes a dielectric layer 6 between the lead post 5 and the penetrating memory cell TC. The dielectric layer 6 can separate the lead post 5 from the upper memory cell TC of the corresponding layer. It should be noted that when the lead post 5 further penetrates the memory cell TC of the corresponding layer, the dielectric layer 6 is located between the lead post 5 and the upper memory cell TC of the corresponding layer, and exposes the sidewall of the lead post 5 located in the memory cell TC of the corresponding layer, so that the lead post 5 is connected to the memory cell TC of the corresponding layer through the sidewall.

[0037] 4, two adjacent lead posts 5 are spaced apart by at least one memory cell group TC0, that is, two adjacent lead posts 5 are not connected to adjacent memory cell groups TC0, and thus the distance between the adjacent lead posts 5 can be increased to reduce parasitic capacitance.

[0038] Specifically, in some examples, the number of memory cell groups TC0 between two adjacent lead posts 5 is the same, that is, the distance between the adjacent lead posts 5 is fixed, thereby improving the uniformity of the semiconductor structure. In other examples, the facing area of ​​two adjacent lead posts 5 is directly proportional to the number of memory cell groups TC0 between the two adjacent lead posts 5. It can be understood that the parasitic capacitance between adjacent lead posts 5 is also related to the facing area between them, and the larger the facing area between them, the corresponding number of memory cell groups TC0 between them can be increased to increase the distance between them, thereby reducing the parasitic capacitance. Exemplarily, two lead posts 5 connected to memory cells TC in the bottom layer and the second lower layer are provided adjacent to each other, and five memory cell groups TC0 are provided between the two lead posts 5, and two lead posts 5 connected to memory cells TC in the top layer and the second upper layer are provided adjacent to each other, and one memory cell group TC0 is provided between the two lead posts 5.

[0039] In some other embodiments, referring to FIGS. 8 and 9, two adjacent lead posts 5 may be located in adjacent memory cell groups TC0, with no memory cell group TC0 provided between them.

[0040] The laminated structure will now be described in detail.

[0041] 4, the semiconductor structure has a first direction X, a second direction Z, and a third direction Y. The first direction X is parallel to the surface of the substrate 11, the second direction Z is perpendicular to the surface of the substrate 11, and the third direction Y is parallel to the surface of the substrate 11. The third direction Y is different from the first direction X. Exemplarily, the third direction Y may be perpendicular to the first direction X.

[0042] 4, the stacked structure further includes a plurality of parallel signal lines 3 and a plurality of vertical signal lines 4, the plurality of parallel signal lines 3 are arranged in the second direction Z and extend along the first direction X, the parallel signal lines 3 are connected to one layer of memory cells TC, and the vertical signal lines 4 extend in the second direction Z and are connected to multiple layers of memory cells TC of the same memory cell group TC0. The lead posts 5 are electrically connected to the parallel signal lines 3.

[0043] That is, the parallel signal lines 3 are laminated on the substrate 11 and need to be drawn out through the lead posts 5 in order to achieve electrical connection between the parallel signal lines 3 and the peripheral circuitry in the subsequent steps. The vertical signal lines 4 are provided perpendicular to the substrate 11 and therefore do not need to be drawn out through the lead posts 5. In some embodiments, the lead posts 5 are directly connected to the parallel signal lines 3, thereby achieving electrical connection between the lead posts 5 and the parallel signal lines 3, and in other embodiments, the lead posts 5 are electrically connected to the parallel signal lines 3 through conductive structures in the memory cells TC. These will be described in detail below.

[0044] 4 to 22, in some embodiments, the memory cell TC may include a transistor T and a capacitor C arranged in a third direction Y, and the parallel signal line 3 and the vertical signal line 4 are connected to the transistor T. Exemplarily, in a dynamic random access memory (DRAM), the memory cell TC includes one transistor T and one capacitor C. In other embodiments, the memory cell TC may include only the transistor T, for example, in a static random access memory (SRAM), the memory cell TC is composed of six transistors T, and as another example, in a capacitorless double gate quantum well single transistor DRAM (1T DRAM), the memory cell TC is composed of one double gate transistor T.

[0045] The transistor T includes a channel region 22 and a source drain doped region 21 arranged in a third direction Y, and the source drain doped region 21 is located on both sides of the channel region 22. One of the parallel signal line 3 and the vertical signal line 4 is a bit line BL, and the other is a word line WL. The bit line BL is connected to the source drain doped region 21, and the word line WL is connected to the channel region 22. Exemplarily, the source drain doped region 21 includes a first source drain doped region 211 and a second source drain doped region 212, and the first source drain doped region 211 is located between the bit line BL and the channel region 22, and the second source drain doped region 212 is located on the side of the channel region 22 away from the first source drain doped region 211. The first source drain doped region 211 and the second source drain doped region 212 can function as a source electrode and a drain electrode of the transistor T, respectively. Furthermore, the second source drain doped region 21 may further include a lightly doped drain (LDD) structure, which is located between the channel region and the drain electrode.

[0046] The specific positional relationship between the lead post 5 and the memory cell TC and the parallel signal line 3 will be described in detail below.

[0047] When the parallel signal lines 3 are bit lines BL and the vertical signal lines 4 are word lines WL, the positional relationship between the lead posts 5 and the memory cells TC and parallel signal lines 3 is specifically as follows.

[0048] In the first example, referring to Fig. 4, Fig. 12 to Fig. 17, the bottom surface of at least one lead post 5 is located in the source drain doped region 21. That is, the orthogonal projection of the lead post 5 on the surface of the substrate 11 overlaps with the orthogonal projection of the source drain doped region 21 on the surface of the substrate 11, and the lead post 5 can realize an electrical connection with the bit line BL by using the spatial position of the source drain doped region 21. It should be noted that Fig. 13, Fig. 15 and Fig. 17 are all schematic local side views, and the channel region, the vertical signal line and the capacitor are not shown.

[0049] Specifically, at least one lead post 5 is connected to the first source drain doped region 211 of the corresponding layer. Since the first source drain doped region 211 is closer to the bit line BL than the second source drain doped region 212, when the spatial position of the first source drain doped region 211 is used to realize the electrical connection between the lead post 5 and the bit line BL, the distance between the lead post 5 and the bit line BL can be reduced, which helps to reduce the resistance and simplify the manufacturing process. When the lead post 5 is used to realize the electrical connection between the lead post 5 and the bit line BL using the spatial position of the second source drain doped region 212, the channel region 22 and the first source drain doped region 211 can be subjected to a conductorization process to reduce the resistance of both.

[0050] In some embodiments, referring to Figures 4, 12 and 13, at least one lead post 5 penetrates the source drain doped region 21 of at least one memory cell TC. The orthogonal projection of the lead post 5 on the surface of the substrate at least partially overlaps with the orthogonal projection of the memory cell TC (e.g., the first source drain doped region 211) on the surface of the substrate. Specifically, at least one lead post 5 penetrates the source drain doped region 21 of the corresponding layer, for example, the lead post 5 can penetrate the first source drain doped region 211 of the memory cell TC of the corresponding layer. In this case, the lead post 5 can be directly connected to the bit line BL via a sidewall.

[0051] 14 and 15, in some other embodiments, the bottom surface of the lead post 5 is embedded in the source drain doped region 21. That is, the lower end of the lead post 5 is located in the source drain doped region 21 but does not completely penetrate the source drain doped region 21. In this case, the lead post 5 may be directly connected to the bit line BL or may be indirectly electrically connected to the bit line BL via the source drain doped region 21.

[0052] 16 and 17, in some further embodiments, the bottom surface of the lead post 5 is located on the top surface of the source drain doped region 21, for example, the bottom surface of the lead post 5 is located on the top surface of the first source drain doped region 211. In this case, the lead post 5 is not directly connected to the bit line BL, but is electrically connected to the bit line BL via the source drain doped region 21. In order to reduce the resistance of the source drain doped region 21, a conductorization process can be performed on the source drain doped region 21, for example, a metal silicide can be formed in the source drain doped region 21 by a metal silicide process, or a heavy doping process can be performed on the source drain doped region 21.

[0053] It should be noted that, for memory cells TC connected to a non-top layer, the lead post 5 may penetrate the source-drain doped region 21 above the corresponding layer. For the lead post 5 connected to the memory cells TC in the top layer, the lead post 5 does not need to penetrate other source-drain doped regions 21 than the corresponding layer.

[0054] 18, in a second example, the memory cell TC further includes a bit line contact region 23, which connects the bit line BL and the source drain doped region 21. The bit line contact region 23 can reduce the contact resistance between the bit line BL and the source drain doped region 21. Exemplarily, the bit line contact region 23 may be heavily doped polysilicon or metal silicide.

[0055] A bottom surface of at least one lead post 5 is located in the bit line contact region 23. That is, the lead post 5 can be electrically connected to the bit line BL using the spatial position of the bit line contact region 23. For example, the at least one lead post 5 penetrates the bit line contact region 23 in one memory cell TC. Alternatively, the at least one lead post 5 is embedded in the bit line contact region 23 of the corresponding layer. Alternatively, the bottom surface of the at least one lead post 5 is connected to an upper surface of the bit line contact region 23 of the corresponding layer.

[0056] When the parallel signal lines 3 are word lines WL and the vertical signal lines 4 are bit lines BL, the positional relationship between the lead posts 5 and the memory cells TC and parallel signal lines 3 is specifically as follows.

[0057] 19, in a first example, the bottom surface of at least one lead post 5 is located in the channel region 22. That is, the orthogonal projection of the lead post 5 on the surface of the substrate 11 overlaps with the orthogonal projection of the channel region 22 on the surface of the substrate 11, and the lead post 5 can realize an electrical connection with the word line WL using the spatial position of the channel region 22.

[0058] It should be noted that there are various positional relationships between the word lines WL and the channel regions 22. For example, the word lines WL may cover the entire channel regions 22, or the word lines WL may be connected to the top and / or bottom surfaces of the channel regions 22.

[0059] In the following, the positional relationship between the lead post 5 and the word line WL will be described, taking as an example a case in which the word line WL covers at least the upper surface of the channel region 22.

[0060] 19, when a lead post 5 is connected to a memory cell TC of a non-top layer, the lead post 5 is electrically connected to the word line WL on the memory cell TC of the corresponding layer and penetrates the channel region 22 and the word line WL located above the corresponding layer. The orthogonal projection of the lead post 5 on the surface of the substrate at least partially overlaps with the orthogonal projection of the channel region 22 of the memory cell TC on the surface of the substrate. It should be noted that the lead post 5 penetrates the word line WL but does not completely cut the word line WL. For example, the lead post 5 penetrates the center of the word line WL. A dielectric layer 6 is further provided between the lead post 5 and the word line WL above the corresponding layer, thereby avoiding electrical connection between the lead post 5 and the word line WL above the corresponding layer.

[0061] When the lead post 5 is connected to the memory cell TC in the uppermost layer, the lead post 5 is electrically connected to the word line WL in the uppermost layer and does not need to pass through any word lines WL and channel regions 22 .

[0062] Since the semiconductor structure includes at least lead posts 5 connected to memory cells TC of different layers, at least one lead post 5 is connected to a memory cell TC of a non-top layer, and therefore at least one lead post 5 penetrates a channel region 22 of at least one memory cell TC.

[0063] It should be noted that if the word line WL does not cover the top surface of the channel region 22 but covers the bottom surface of the channel region 22, the lead post 5 connected to the top layer memory cell TC must penetrate at least one channel region 22 in order to be connected to the word line WL at the bottom surface of the channel region 22.

[0064] In the second example, referring to FIG. 20 and FIG. 21, the bottom surface of at least one lead post 5 is located in the source drain doped region 21, and a part of the side surface of the lead post 5 is connected to the word line WL of the corresponding layer. Furthermore, the word line WL further penetrates the source drain doped region 21 above the corresponding layer. That is, the lead post 5 can realize an electrical connection with the word line WL using the position of the source drain doped region 21. Specifically, referring to FIG. 20, the bottom surface of at least one lead post 5 is located in the first source drain doped region 211, and a part of the side surface of the lead post 5 is connected to the word line WL of the corresponding layer, and the orthogonal projection of the lead post 5 on the surface of the substrate at least partially overlaps with the orthogonal projection of the first source drain doped region 211 of the memory cell TC on the surface of the substrate. Referring to FIG. 21, the bottom surface of at least one lead post 5 is located in the second source drain doped region 212, a portion of the side of the lead post 5 is connected to the word line WL of the corresponding layer, and the orthogonal projection of the lead post 5 on the surface of the substrate at least partially overlaps with the orthogonal projection of the second source drain doped region 212 of the memory cell TC on the surface of the substrate.

[0065] It should be noted that the bottom surface of the lead post 5 is located in the source drain doped region 21 but is electrically insulated from the source drain doped region 21, for example, an insulating layer (not shown) may be formed on the bottom surface of the lead post 5, or a passivation process can be performed on the surface of the source drain doped region 21 of the corresponding layer before forming the lead post 5.

[0066] The structural modules are described in detail below.

[0067] Referring to FIG. 22, there are a plurality of laminated structures, and the plurality of parallel signal lines 3 of the same laminated structure include first to Nth (N is a positive integer greater than 1) parallel signal lines arranged sequentially in the second direction Z.

[0068] The two laminated structures constitute a structural module, which further includes a plurality of conductive wires 7, each of which is connected to two lead posts 5 of different laminated structures, in other words, two lead posts 5 located in different laminated structures are connected to one conductive wire 7, and the sum of sequence numbers of two parallel signal lines 3 electrically connected to the two lead posts 5 is N+1.

[0069] That is, two parallel signal lines 3 whose sum of sequence numbers is N+1 are electrically connected via the lead post 5 and the conductor 7. The two electrically connected parallel signal lines 3 can constitute a parallel signal line group. Since they have the same potential, the two parallel signal lines 3 in the parallel signal line group may be regarded as one parallel signal line 3.

[0070] For example, the parallel signal lines 3 include first to fifth parallel signal lines, where the first parallel signal line of the laminated structure is connected to the fifth parallel signal line of another laminated structure, the second parallel signal line of the laminated structure is connected to the fourth parallel signal line of another laminated structure, and the third parallel signal line of the laminated structure is connected to the third parallel signal line of another laminated structure. The first parallel signal line is located in the top layer, and the fifth parallel signal line is located in the bottom layer.

[0071] It should be explained that since the lead posts 5 penetrate the memory cells TC, the penetrated memory cells TC no longer perform a memory function. Since the lead posts 5 are connected to the memory cells TC of different layers, the number of available memory cells TC in different layers in the semiconductor structure is different. For example, there are five layers of memory cells TC in total, the first layer is the top layer, the first layer is missing five memory cells TC, the second layer is missing four memory cells TC, the third layer is missing three memory cells TC, the fourth layer is missing two memory cells TC, and the fifth layer is used as the bottom layer, the fifth layer is missing one memory cell TC. Due to the action of the conductive wires 7, the number of memory cells TC connected to different parallel signal line groups is the same.

[0072] In addition, the lengths of the lead posts 5 connected to the memory cells TC of different layers are different, resulting in different resistances. Due to the RC delay effect, the delay times of different memory cells TC are different. Due to the action of the conductive wire 7, two lead posts 5 form one lead post 5 group, and the total lengths of each lead post 5 group are roughly the same, thus helping to unify the delay times, thereby improving the performance of the semiconductor structure.

[0073] Furthermore, the contact areas of the memory cells TC and the lead posts 5 in different layers can be made consistent, so that the contact resistances can be matched and different delay times can be prevented. For example, the contact areas of the memory cells TC and the lead posts 5 in different layers are all within the range of 0.036 to 0.054 μm. 2 It is.

[0074] In some embodiments, the two lead posts 5 connected to the conductor 7 are provided directly opposite each other, and the extension direction of the conductor 7 is perpendicular to the first direction X. In this way, it is helpful to reduce the distance between the two lead posts 5, and thus the length of the conductor can be shortened. The shorter the length of the conductor, the lower the resistance, the lower the power consumption, and the shorter the delay time. In some other embodiments, referring to FIG. 22, the two lead posts 5 connected to the conductor 7 may be arranged in a staggered manner.

[0075] In the same structural module, the transistor T of one stack is arranged opposite the transistor T of the other stack. That is, the stack capacitor C has two opposite sides arranged in the third direction Y, of which the side facing another stack is the inside and the side facing away from another stack is the outside. Arranging the transistors T opposite each other means that the two transistors are located inside the stack to which they belong. In this way, it helps to shorten the distance between the two transistors T and the distance between the two lead posts 5, thereby shortening the length of the conductor 7.

[0076] As shown in FIG. 22, in some other embodiments, in the same structural module, the transistor T of one stacked structure is arranged in the same direction as the transistor T of the other stacked structure. Alternatively, in the same structural module, the transistor T of one stacked structure is arranged in the opposite direction to the transistor T of the other stacked structure. Arranging the transistors T in the same direction means that the transistor T of one stacked structure is located inside the capacitor C, and the transistor T of the other stacked structure is located outside the capacitor C. Arranging the transistors T in the opposite direction means that both of the transistors T of the two stacked structures are located outside the capacitor C.

[0077] In summary, the embodiment of the present disclosure improves the utilization of the surface area of ​​the substrate 11 by integrating at least two lead posts 5 from the step region into the region where the memory cells TC are located. Providing all the lead posts 5 in the region where the memory cells TC are located eliminates the need to separate the step region, which can improve the integration density of the semiconductor structure and help increase the number of memory cells TC.

[0078] As shown in Fig. 23 to Fig. 35, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure is used to manufacture a semiconductor structure provided in the above embodiment, and the detailed description of the semiconductor structure can be referred to the above embodiment. It should be noted that, in order to conveniently describe and clearly show the steps of the method for manufacturing a semiconductor structure, Fig. 23 to Fig. 35 are schematic local structure views of the semiconductor structure, where Fig. 23, Fig. 25, Fig. 26, Fig. 28 to Fig. 30 are local side views with the channel region, vertical signal line and capacitor omitted, and Fig. 24, Fig. 27 and Fig. 31 are local overhead views with the insulating layer 12 omitted. Fig. 32 and Fig. 34 are cross-sectional views in the first direction X, and Fig. 33 and Fig. 34 are local overhead views with the insulating layer 12 omitted.

[0079] 23, a substrate 11 is provided, and a stacked structure is formed on the substrate 11, the stacked structure including a plurality of memory cell groups TC0 (see FIG. 1) arranged in a first direction X, and the memory cell group TC0 includes a plurality of layers of memory cells TC arranged in a second direction Z. The plurality of memory cells TC of the same memory cell group TC0 include a first memory cell to an Nth memory cell arranged in sequence. The first memory cell is located in the top layer, and the Nth memory cell is located in the bottom layer.

[0080] Exemplarily, the memory cell TC may include a transistor T and a capacitor C.

[0081] Specifically, the step of forming the transistor T may include forming a plurality of spaced apart active layers, each active layer including a plurality of active structures, performing a doping process on the active structures to form source drain doped regions 21 and a channel region 22, and forming a gate dielectric layer on a surface of the channel region 22. That is, the memory cell TC includes the channel region 22 and the source drain doped regions 21 arranged in a third direction Y, the source drain doped regions 21 being located on both sides of the channel region 22, and the third direction Y being parallel to the surface of the substrate 11.

[0082] Furthermore, it is necessary to form an insulating layer 12 between the transistors T of adjacent layers to isolate the adjacent transistors T.

[0083] The step of forming the capacitor C may include forming a capacitor support layer and a capacitor hole located in the capacitor support layer, forming a lower electrode on an inner wall of the capacitor hole, forming a capacitor dielectric layer on a surface of the lower electrode, and forming an upper electrode on a surface of the capacitor dielectric layer. The lower electrode, the capacitor dielectric layer, and the upper electrode constitute the capacitor C.

[0084] The method for manufacturing the semiconductor structure further includes forming a plurality of parallel signal lines 3 and a plurality of vertical signal lines 4 (see FIG. 4), where the parallel signal lines 3 are arranged in a second direction Z and extend along a first direction X, and each parallel signal line 3 is connected to one layer of memory cells TC, and the vertical signal lines 4 extend in the second direction Z and are connected to multiple layers of memory cells TC of the same memory cell group TC0. The first direction X is parallel to the surface of the substrate 11, and the second direction Z is perpendicular to the surface of the substrate 11.

[0085] One of the vertical signal line 4 and the parallel signal line 3 is a bit line BL, and the other is a word line WL. The bit line BL is connected to a source / drain doped region 21, and the word line WL is connected to a channel region 22 as a gate electrode.

[0086] A method for forming the vertical signal line 4 may include forming an isolation structure, etching the isolation structure to form a fill hole in the isolation structure, the fill hole extending in the second direction Z, and depositing a conductive material in the fill hole to form the vertical signal line 4.

[0087] The step of forming the parallel signal lines 3 may include depositing a conductive material on the surface of the active structures such that the conductive material covers the active structures in the same layer, followed by forming an isolation structure between adjacent parallel signal lines 3.

[0088] 23 to 35, a plurality of lead posts 5 are formed, where at least two lead posts 5 are each connected to memory cells TC in different layers in different memory cell groups TC0.

[0089] The steps for forming the lead posts 5 will be described in detail below.

[0090] When the parallel signal lines 3 are bit lines BL and the vertical signal lines 4 are word lines WL, the steps for forming the lead posts 5 are specifically as follows.

[0091] First, it should be explained that the multiple source drain doped regions 21 of the same memory cell group TC0 include a first layer of source drain doped regions to an Nth layer of source drain doped regions (N is a positive integer) arranged in sequence. The first layer of source drain doped regions is located in the top layer, and the Nth layer of source drain doped regions is located in the bottom layer.

[0092] 23 and 24, a mask layer 71 is formed, and N openings 72 are provided in the mask layer 71, where N is a positive integer, and the openings 72 are located above the source drain doped region 21 (e.g., above the first source drain doped region 211). Exemplarily, the mask layer 71 may be a photoresist layer, and the photoresist layer is photoetched to form the openings 72. Alternatively, the mask layer 71 may be a hard mask layer and a photoresist layer that are stacked together, and the photoresist layer is photoetched and then the hard mask layer is photoetched to form the openings 72.

[0093] 25, the first memory cell is etched along the opening 72 to form a plurality of first sub-through holes 811, where one first sub-through hole 811 is used as the first through hole 81. Specifically, the source-drain doped region 21 is etched along the opening 72. Also, before etching the first memory cell, the insulating layer 12 above the first memory cell needs to be etched.

[0094] 26 and 27, a sacrificial layer 73 is formed to fill the first sub-through-hole 8. Exemplarily, a low dielectric constant material such as silicon oxide is deposited in the first sub-through-hole 8 and used as the sacrificial layer 73.

[0095] 26 and 27, the mask layer 71 is patterned such that the mask layer 71 has N-1 openings 72. Specifically, a photoresist layer may be spin-coated again and the photoresist layer may be photo-etched to form the openings 72.

[0096] 28, the sacrificial layer 73 and the second memory cell are etched along the opening 72 to form N-1 second sub-through holes 821, where one second sub-through hole 821 is used as the second through hole 82. After etching the sacrificial layer 73, the insulating layer 72 on the second memory cell needs to be etched.

[0097] 29, the steps of forming sacrificial layer 73, patterning mask layer 71, and etching are repeated until the source drain doped region of the Nth layer is penetrated. In some other embodiments, the steps of forming sacrificial layer 73, patterning mask layer 71, and etching are repeated until the N-1th memory cell is penetrated and the Nth memory cell is exposed, or until the N-1th memory cell is penetrated and a partial thickness of the Nth memory cell is removed.

[0098] At this time, the through holes 8 can be formed based on Figs. 23 to 29, and the through holes 8 include a first through hole to an N-th through hole. Exemplarily, referring to Fig. 29, a first through hole 81, a second through hole 82, a third through hole 83, a fourth through hole 84, and a fifth through hole 85 can be formed. In some embodiments, the first through hole 81 can penetrate the source drain doped region of the first layer, and the N-th through hole can penetrate the source drain doped region of the first layer to the source drain doped region 21 of the N-th layer. In other embodiments, the first through hole 8 exposes the source drain doped region 21 of the first layer, and the N-th through hole penetrates the source drain doped region of the first layer to the source drain doped region of the N-1th layer and exposes the source drain doped region 21 of the N-th layer. In some other embodiments, the bottom of the first through hole 8 is embedded in the source drain doped region 21 of the first layer, the Nth through hole penetrates the source drain doped region of the first layer to the source drain doped region of the N-1th layer, and the bottom of the Nth through hole is embedded in the source drain doped region of the Nth layer. It should be noted that the depths of the first through hole 81, the second through hole 82, the third through hole 83, the fourth through hole 84, and the fifth through hole 85 arranged in sequence in the first direction X gradually increase. In other embodiments, the depths of the first through hole 81, the second through hole 82, the third through hole 83, the fourth through hole 84, and the fifth through hole 85 arranged in sequence in the first direction X do not gradually increase or decrease, but alternately change, thereby preventing the parasitic capacitance between the deep lead posts 5 among the subsequently formed lead posts 5 from becoming too large.

[0099] 30 and 31, a dielectric layer 6 is formed to cover the sidewall of the through hole 8, and a lead post 5 is formed to fill the through hole 8, and the lead post 5 contacts the corresponding source drain doped region 21.

[0100] Specifically, when the Nth through hole penetrates the source drain doped region 21 of the Nth layer, or the Nth through hole penetrates the source drain doped region 21 of the N-1th layer and its bottom is embedded in the source drain doped region 21 of the Nth layer, the step of forming the dielectric layer 6 and the lead post 5 may include the following steps.

[0101] A contact portion 51 is formed at the bottom of the through hole 8, and the contact portion 51 is connected to the memory cell TC of the corresponding layer. After the contact portion 51 is formed, a dielectric layer 6 is formed on the side wall of the through hole 8. Exemplarily, an initial dielectric layer is formed on the side wall of the through hole 8 and the surface of the contact portion 51 by a chemical vapor deposition process, the initial dielectric layer located on the surface of the contact portion 51 is removed, and the initial dielectric layer located on the side wall of the through hole 8 is used as the dielectric layer 6. After the dielectric layer 6 is formed, an extension portion 52 is formed to fill the through hole 8. The extension portion 52 and the contact portion 51 constitute the lead post 5.

[0102] When the N-th through-hole 8 penetrates the source drain doped region of the N-1th layer and exposes the source drain doped region of the N-th layer, the step of forming the dielectric layer 6 and the lead post 5 may include forming the dielectric layer 6 on the inner wall of the through-hole 8, and forming the lead post 5 to fill the through-hole 8 after forming the dielectric layer 6. In this case, a metal silicide can be formed in the source drain doped region 21 of the corresponding layer by a metal silicide process, thereby reducing the contact resistance. Specifically, a metal layer is deposited on the inner wall of the through-hole 8, and the metal layer is reacted with the source drain doped region 21 by performing a heat treatment, and then the unreacted metal layer is removed, and the unreacted metal layer is mainly located on the side wall of the through-hole 8, and then the dielectric layer 6 and the lead post 5 are formed.

[0103] When the parallel signal lines 3 are word lines WL and the vertical signal lines 4 are bit lines BL, the steps for forming the lead posts 5 are specifically as follows.

[0104] First, it should be explained that the channel regions 22 of the same memory cell group TC0 include a first channel region to an Nth channel region (N is a positive integer) arranged in sequence. The first channel region is located in the top layer, and the Nth channel region is located in the bottom layer.

[0105] 32 and 33, through holes 8 are formed, and the through holes 8 include a first through hole 81 to an Nth through hole. The first through hole 8 exposes a word line WL connected to the first channel region, and the Nth through hole 8 exposes a word line WL that passes through the first channel region 22 to the N-1th channel region and is connected to the Nth channel region. For the step of forming the through holes 8, the above detailed description can be referred to.

[0106] 34 and 35, a dielectric layer 6 is formed to cover the sidewall of the through hole 8. Specifically, an initial dielectric layer is formed on the inner wall of the through hole 8, and the initial dielectric layer located on the bottom wall of the through hole 8 is removed to expose the word line WL of the corresponding layer, and the initial dielectric layer located on the sidewall of the through hole 8 is used as the dielectric layer 6.

[0107] 34 and 35, a lead post 5 is formed to fill the through hole 8, and the lead post 5 contacts the corresponding word line WL. Exemplarily, a metal such as copper, aluminum, titanium, or tungsten is deposited in the through hole 8 to be used as the lead post 5.

[0108] It should be noted that the above method for forming the lead post 5 is merely an illustrative example, and the method for forming the lead post 5 is not limited thereto, and the method for forming the lead post 5 can be adjusted according to the specific structure of the lead post 5.

[0109] In short, in the embodiment of the present disclosure, the memory cell TC is etched to form a through hole 8, and a dielectric layer and a lead post 5 are formed to fill the through hole 8. In this manner, the lead post 5 is directly electrically connected to the memory cell TC using the spatial position of the memory cell TC, which can reduce the number of steps or eliminate the need to form a separate step region, thus helping to improve the integration density of the semiconductor structure.

[0110] 36 to 38, another embodiment of the present disclosure further provides a semiconductor structure, which is substantially the same as the semiconductor structure in the above embodiment, with a main difference being that at least two lead posts 5 of the semiconductor structure are connected to different memory cells TC of the same memory cell group TC0. For parts of the semiconductor structure that are the same or similar to those of the semiconductor structure in the above embodiment, reference may be made to the detailed description of the above embodiment, and will not be repeated here.

[0111] The semiconductor structure includes a substrate 11 (see FIG. 34) and a plurality of lead posts 5, and a stacked structure is provided on the substrate 11, the stacked structure includes a plurality of memory cell groups TC0 arranged in a first direction X, the memory cell group TC0 includes a plurality of layers of memory cells TC arranged in a second direction Z, and at least two lead posts 5 are connected to different memory cells TC in the same memory cell group TC0.

[0112] Compared with the case where different lead posts 5 are located in different memory cell groups TC0, at least two lead posts 5 can use spatial positions of the same memory cell group TC0, thereby improving the spatial utilization rate in the same memory cell group TC0 and increasing the number of available memory cells TC. For example, when two lead posts 5 are connected to memory cells TC in the top layer and the second highest layer, respectively, if the two lead posts 5 are located in different memory cell groups TC0, three memory cells TC are disabled, and if they are located in the same memory cell group TC0, two memory cells TC are disabled.

[0113] It should be noted that the above two schemes may be combined in the same semiconductor structure, for example, the semiconductor structure includes at least four lead posts 5, where at least two lead posts 5 are respectively connected to memory cells TC in different layers of different memory cell groups TC0, and at least two lead posts 5 are respectively connected to memory cells TC in different layers of the same memory cell group TC0.

[0114] Continuing to refer to Figures 36 to 38, at least two lead posts 5 connected to different memory cells TC of the same memory cell group TC0 are arranged along the first direction X, thus unifying the connection positions between the lead posts 5 and the memory cells TC and helping to simplify the connection process.

[0115] In some embodiments, the stacked structure further includes a plurality of parallel signal lines 3 and a plurality of vertical signal lines 4, the plurality of parallel signal lines 3 are arranged in the second direction Z and extend along the first direction X, the parallel signal lines 3 are connected to one layer of memory cells TC, and the vertical signal lines 4 extend in the second direction Z and are connected to multiple layers of memory cells TC of the same memory cell group TC0. The lead posts 5 are electrically connected to the parallel signal lines 3.

[0116] In some embodiments, the lead posts 5 connected to different memory cells TC of the same memory cell group TC0 are arranged in a line along the first direction X. That is, the lead posts 5 are roughly aligned in the first direction X. In this way, the distances between the multiple lead posts 5 and the parallel signal lines 3 are roughly the same, which helps to balance the contact resistance between the multiple lead posts 5 and the parallel signal lines 3. In addition, it also helps to simplify the process and improve the uniformity of the semiconductor structure. For example, referring to FIG. 37, both ends of the multiple lead posts 5 are aligned in the first direction X, which helps to simplify the process. Referring to FIG. 38, both ends of the multiple lead posts 5 in the first direction X are slightly offset to reduce the facing area, which reduces the parasitic capacitance.

[0117] In short, in the embodiment of the present disclosure, at least two lead posts 5 are integrated from the step region into the region where the memory cells TC are arranged, thereby improving the utilization rate of the surface area of ​​the substrate 11. Furthermore, the at least two lead posts 5 are connected to memory cells TC of different layers in the same memory cell group TC0, which means that the at least two lead posts 5 can use the spatial positions of the same memory cell group TC0, which helps to reduce the number of invalid memory cells TC and improves the integration degree of the semiconductor structure.

[0118] An embodiment of the present disclosure further provides a memory chip including the semiconductor structure provided in the above embodiment.

[0119] The memory chip is a storage unit for storing programs and various data information. Exemplarily, the memory chip may be a random access memory chip or a read-only memory chip, for example, the random access memory chip may include dynamic random access memory or static random access memory. The high integration of the above semiconductor structure helps to realize the ultra-miniaturization of the memory chip.

[0120] An embodiment of the present disclosure further provides an electronic device including the memory chip provided in the above embodiment.

[0121] Exemplarily, the electronic device may be a device such as a television, a computer, a mobile phone, or a tablet computer. The electronic device may include a circuit board and a package structure, and the memory chip is welded onto the circuit board and protected by the package structure. In addition, the electronic device may further include a power supply for supplying an operating voltage to the memory chip.

[0122] In the present description, the description of terms such as "some embodiments," "exemplary," and the like means that the specific features, structures, materials, or characteristics described with reference to the embodiments or examples are included in at least one embodiment or example of the present disclosure. In the present description, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, unless conflicting, a person skilled in the art may integrate or combine different embodiments or examples described herein and features of different embodiments or examples.

[0123] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and transformations to the above embodiments within the scope of the present disclosure, and therefore, the changes and modifications made according to the claims and specifications of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. 1. A semiconductor structure comprising: a substrate and a plurality of lead posts; a stacked structure is provided on the substrate, the stacked structure including a plurality of memory cell groups arranged in a first direction, the memory cell groups including a plurality of layers of memory cells arranged in a second direction; At least two of the lead posts are directly connected to memory cells in different layers in different memory cell groups, respectively, and the number of memory cells that are penetrated by the at least two lead posts is different from each other; The first direction is parallel to a surface of the substrate and the second direction is perpendicular to the surface of the substrate.

2. The lead posts are arranged in a line along the first direction, and The lead posts are arranged in series along the first direction. The semiconductor structure of claim 1 .

3. All the memory cells in the same memory cell group are connected to a maximum of one of the lead posts. The semiconductor structure of claim 1 .

4. the number of said lead posts is greater than or equal to the number of layers of said memory cells, each layer including at least said memory cells connected to said lead posts; The semiconductor structure of claim 1 .

5. the number of lead posts connected to the same memory cell group is less than the number of layers of the memory cells in the memory cell group; The semiconductor structure of claim 1 .

6. The stacked structure further includes a plurality of parallel signal lines and a plurality of vertical signal lines, the plurality of parallel signal lines being arranged in a second direction and extending along the first direction, the parallel signal lines being connected to one layer of the memory cells, and the vertical signal lines being extended along the second direction and connected to the memory cells of the same memory cell group in multiple layers; the lead posts are electrically connected to the parallel signal lines; The semiconductor structure of claim 1 .

7. The memory cell includes a channel region and a source / drain doped region arranged in a third direction, the source / drain doped regions being located on both sides of the channel region, the third direction being parallel to a surface of the substrate and perpendicular to the first direction. The semiconductor structure of claim 6.

8. the parallel signal lines are bit lines and the vertical signal lines are word lines; the bit line is connected to the source drain doped region and the word line is connected to the channel region; At least one of the lead posts penetrates the source-drain doped region of at least one of the memory cells; the source drain doped region includes a first source drain doped region and a second source drain doped region, the first source drain doped region being located between the bit line and the channel region, and the second source drain doped region being located on a side of the channel region away from the first source drain doped region; the lead post penetrates the first source drain doped region; 8. The semiconductor structure of claim 7.

9. the parallel signal lines are word lines and the vertical signal lines are bit lines; the bit line is connected to the source drain doped region and the word line is connected to the channel region; At least one of the lead posts penetrates the channel region of at least one of the memory cells.

8. The semiconductor structure of claim 7.

10. The parallel signal lines are bit lines, and the memory cells further include bit line contact regions, the bit line contact regions connecting the bit lines and the source drain doped regions; At least one of the lead posts passes through the bit line contact region of one of the memory cells.

8. The semiconductor structure of claim 7.

11. two adjacent lead posts are spaced apart by at least one of the memory cell groups; the number of the memory cell groups between two adjacent lead posts is the same, or the facing area of ​​the two adjacent lead posts is directly proportional to the number of the memory cell groups between the two adjacent lead posts; The semiconductor structure of claim 1 .

12. the number of the laminated structures is plural, and the parallel signal lines of the same laminated structure include first to N-th parallel signal lines (N is a positive integer greater than 1) sequentially arranged in a second direction; The two laminated structures constitute a structural module, and the structural module further includes a plurality of conductive wires, the conductive wires connecting the two lead posts connecting the different laminated structures, and the sum of sequence numbers of the two parallel signal lines electrically connected to the two lead posts is N+1. The semiconductor structure of claim 6.

13. 1. A method for manufacturing a semiconductor structure, comprising the steps of: Providing a substrate; forming a stack structure on the substrate, the stack structure including a plurality of memory cell groups arranged in a first direction, the memory cell groups including a plurality of layers of memory cells arranged in a second direction; forming a plurality of lead posts, at least two of the lead posts being directly connected to memory cells in different layers in different memory cell groups, and the number of memory cells through which the at least two lead posts penetrate is different from each other; the first direction is parallel to a surface of the substrate and the second direction is perpendicular to a surface of the substrate.

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