Encoder, decoder and corresponding method using high level flag that DCT2 is valid - Patents.com

Abstract

To provide a video coding method that switches to a pure Discrete Cosine Transform Type 2 (DCT2) transform core.SOLUTION: A video coding method of blocks of images includes the steps of obtaining a resulting residual signal from the inter or intra image prediction, inferring the use of a DCT2 transform core for the sequence of the residual signal, and processing the block's transformation using the inferred transformation core.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 791,674, filed January 11, 2019, the disclosure of which is incorporated herein by reference in its entirety.

[0002] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to the field of image processing, and more specifically to high-level control of transform type selection adapted to block shapes. [Background technology]

[0003] Video coding (video encoding and decoding) is used in a wide range of digital video applications, such as broadcast digital TV, video transmission over the Internet and mobile networks, or real-time interactive applications such as video chat, video conferencing, DVDs and Blu-ray Discs, video content acquisition and editing systems, and camcorders in security applications.

[0004] The amount of video data required even to show a relatively short video can be substantial, which can result in difficulties when the data is to be streamed or otherwise communicated over a communication network with limited bandwidth capacity. Thus, video data is typically compressed before being communicated over modern telecommunication networks. The size of the video can also be an issue when the video is stored on a storage device, since memory resources may be limited. Video compression devices often use software and / or hardware at the source to code the video data before transmission or storage, thereby reducing the amount of data required to represent a digital video image. The compressed data is then received at the destination by a video decompression device that decodes the video data. In view of limited network resources and an ever-increasing demand for higher video quality, improved compression and decompression techniques are desired that improve compression ratios with little to no sacrifice in image quality.

[0005] In JVET-L1001, a draft text of VVC Draft3.0, MTS can be enabled at the sequence level for inter-slice and intra-slice individually. When MTS is off, DCT2 is assumed to be used as the transform core. However, in prior art such as JVET-M0303, JVET-M0140 or JVET-M0102, an inferred DST7 / DCT8 transform is introduced. There is no possibility to switch to a pure DCT2 transform in all cases. This disclosure addresses the above problems.

[0006] In view of the above-mentioned problems, the present disclosure provides a solution that alleviates or even eliminates the above-mentioned problems.

[0007] Embodiments of the present disclosure are defined by the features of the independent claims and further advantageous implementations of the embodiments by the features of the dependent claims.

[0008] The present disclosure provides the following:

[0009] 1. A method of video coding a block of an image, comprising the steps of: for a sample from a plurality of samples of the block, obtaining a residual signal resulting from an inter or intra image prediction; inferring the use of a Discrete Cosine Transform type 2, DCT2, transform core for the sequence of residual signals; using the inferred transform core to process the transform of the block; A method comprising:

[0010] That is, the present disclosure introduces an additional DCT2 enable flag that is used to infer whether only the DCT2 transform core is used for all cases in the sequence when the DCT2 enable flag is false, and then the sequence level MTS enable flag is further signaled. If the DCT2 enable flag is true, it is assumed that only the DCT2 transform core is used. Introducing the additional DCT2 enable flag in the SPS allows switching to DCT2 when the inferred MST tool is on.

[0011] As such, in a possible implementation of the method according to the aforementioned aspect, the use of DCT2 is inferred from a sequence level DCT2 enable flag in the sequence parameter set, SPS.

[0012] Therefore, the embodiment of the present disclosure introduces a switchable DCT2 effective sequence level indicator that provides the possibility to switch to a pure DCT2 transform core with an inferred transform tool for the whole sequence or slice. DCT2 is a case where the calculation is relatively simple and the memory bandwidth is low compared to other transform cores. In the prior art, the possibility to use a simple DCT2 transform is blocked by the inferred transform core, and the current indicator provides the flexibility of switching between low cost / complexity and high performance for both the encoder and the decoder. In the embodiment, both low-level and high-level change possibilities are provided, which ensures the consistency and coding performance of the code with multiple variants.

[0013] As such, in a possible implementation of the method according to the aforementioned aspect, the sequence-level DCT2 enabled flag is represented as sps_dct2_enabled_flag.

[0014] In any of the above implementations of the above two aspects or as such a possible implementation of the method according to the above aspect, a sequence level DCT2 validity flag is included in the SPS level syntax as follows:

[0015] [Table 1]

[0016] Here, sps_dct2_enabled_flag represents the sequence level DCT2 enabled flag.

[0017] In a possible implementation form of the method according to any of the above-mentioned implementations of the above-mentioned aspects as such, sps_mts_intra_enabled_flag equal to 1 specifies that tu_mts_flag may be present in the residual coding syntax of the intra-coding unit, sps_mts_intra_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of the intra-coding unit, and if sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0018] In any of the above implementations of the two above aspects or possible implementations of the method according to the above aspect as such, sps_mts_inter_enabled_flag specifies that tu_mts_flag may be present in the residual coding syntax of the inter coding unit, sps_mts_inter_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of the inter coding unit, and if sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0019] In any of the above-mentioned implementations of the above-mentioned five aspects or possible implementations of the method according to the above-mentioned aspects as such, A sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used for the transformation.

[0020] In any of the above implementations of the above six aspects or possible implementations of the method according to the above aspects as such, A sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transformation.

[0021] In any of the above implementations of the seven above aspects or possible implementations of the method according to the above aspect as such, a sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for both horizontal and vertical transforms.

[0022] In any of the above implementations of the above eight aspects or possible implementations of the method according to the above aspect as such, a sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for the sub-block transform.

[0023] As such, in a possible implementation of the method according to the aforementioned aspect, if one side of the residual transform unit, tu, is greater than 32, the corresponding transform is set as DCT2.

[0024] In any of the above-mentioned implementations of the ten aspects or possible implementations of the method according to the above-mentioned aspects as such, if a sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transform, then both the sub-block transform as well as the multiple transform selection, MTS, transform are inferred to be off.

[0025] In any of the above implementations of the above eleven aspects or possible implementations of the method according to the above aspects as such, A sequence level DCT2 enable flag equal to 0 specifies that a transform core other than the DCT2 is used for the transformation.

[0026] As such, in a possible implementation of the method according to the above aspect, It is derived using the discrete sine transform type 7, DST7, and / or the discrete cosine transform type 8, DCT8, for the transformation.

[0027] In any of the above implementations of the two above aspects or as such a possible implementation of the method according to the above aspect, a sequence level DCT2 valid flag equal to 0 may be Specifies that it is inferred using DST7 / DCT8 only for conversion.

[0028] DCT2 may be highly desirable for both encoder and decoder designs. In other words, switchability between DCT2, inferred DST7 or DCT8, and MTS (RDO Select Transform Core) is one of the goals of this disclosure.

[0029] In any of the above-mentioned implementations of the three above-mentioned aspects or possible implementations of the method according to the above-mentioned aspects as such, If the sequence level DCT2 enabled flag is equal to 0, then it is determined whether multiple transform selection for the sequence parameter set has been enabled via the flag.

[0030] As such, in a possible implementation of the method according to the above aspect, If sps_mts_intra_enabled_flag is present, sps_mts_intra_enabled_flag is equal to 1 to specify that the transform unit, TU, multiple transform selection, MTS flag, represented as tu_mts_flag, is present in the residual coding syntax for the intra coding unit; sps_mts_intra_enabled_flag is equal to 0, it specifies that tu_mts_flag is not present in the residual coding syntax of the intra coding unit; Here, if sps_mts_intra_enabled_flag is not present, then sps_mts_intra_enabled_flag is inferred to be 0.

[0031] The present disclosure further provides an encoder comprising processing circuitry for performing any of the above-mentioned implementations of the above-mentioned aspects or a method according to the above-mentioned aspects as such.

[0032] The present disclosure further provides a decoder comprising processing circuitry for performing any of the above-mentioned implementations of the above-mentioned aspects or a method according to the above-mentioned aspects as such.

[0033] The present disclosure further comprises: an obtaining unit configured to obtain a residual signal resulting from an inter or intra image prediction; an inference unit configured to infer the use of a Discrete Cosine Transform type 2, DCT2, transform core on the sequence of residual signals; a processing unit configured to process the transformation of the block using the inferred transform core; A decoder comprising:

[0034] As such, in a possible implementation of a decoder according to the aforementioned aspect, the inference unit is configured to infer the use of DCT2 from a sequence level DCT2 enable flag in a sequence parameter set, SPS.

[0035] As such, in a possible implementation of a decoder according to the above aspect, the sequence-level DCT2 enabled flag is represented as sps_dct2_enabled_flag.

[0036] In any of the above implementations of the above two aspects or as such a possible implementation of a decoder according to the above aspect, a sequence level DCT2 significance flag is included in the SPS level syntax as follows:

[0037] [Table 2]

[0038] Here, sps_dct2_enabled_flag represents the sequence level DCT2 enabled flag.

[0039] As such, in a possible implementation of a decoder according to the above aspect, sps_mts_intra_enabled_flag equal to 1 specifies that tu_mts_flag may be present in the residual coding syntax of the intra coding unit, sps_mts_intra_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of the intra coding unit, and if sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0040] In any of the above implementations of the above two aspects or as such a possible implementation of a decoder according to the above aspect, sps_mts_inter_enabled_flag specifies that tu_mts_flag may be present in a residual coding syntax of an inter coding unit; sps_mts_inter_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of the inter coding unit; if sps_mts_intra_enabled_flag is not present, then sps_mts_intra_enabled_flag is inferred to be 0.

[0041] In any of the above-mentioned implementations of the above-mentioned five aspects or as such a possible implementation of a decoder according to the above-mentioned aspects, A sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used for the transformation.

[0042] In any of the above implementations of the six above aspects or as such a possible implementation of a decoder according to the above aspects, A sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transformation.

[0043] In any of the above implementations of the seven above aspects or possible implementations of a decoder according to the above aspects as such, a sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for both horizontal and vertical transforms.

[0044] In any of the above implementations of the eight above aspects or a possible implementation of a decoder according to the above aspect as such, a sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for sub-block transform.

[0045] As such, in a possible implementation of a decoder according to the aforementioned aspect, if one side of the residual transform unit, tu, is greater than 32, the corresponding transform is set as DCT2.

[0046] In any of the above implementations of the above ten aspects or possible implementations of a decoder according to the above aspects as such, if a sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transform, then both the sub-block transform as well as the multiple transform selection, MTS, transform are inferred to be off.

[0047] In any of the above implementations of the eleven above aspects or as such a possible implementation of a decoder according to the above aspects, A sequence level DCT2 enable flag equal to 0 specifies that a transform core other than the DCT2 is used for the transformation.

[0048] As such, in a possible implementation of a decoder according to the above aspect, The inference unit is configured to infer using a discrete sine transform type 7, DST7, and / or a discrete cosine transform type 8, DCT8, for the transformation.

[0049] In any of the above implementations of the above two aspects or as such a possible implementation of a decoder according to the above aspect, a sequence level DCT2 valid flag equal to 0 may be Specifies that it is inferred using DST7 / DCT8 only for conversion.

[0050] In any of the above-mentioned implementations of the three above-mentioned aspects or as such a possible implementation of a decoder according to the above-mentioned aspects, If the sequence level DCT2 enabled flag is equal to 0, then it is determined whether multiple transform selection for the sequence parameter set has been enabled via the flag.

[0051] As such, in a possible implementation of a decoder according to any of the above-mentioned implementations of the above-mentioned aspects, If sps_mts_intra_enabled_flag is present, sps_mts_intra_enabled_flag is equal to 1 to specify that the transform unit, TU, multiple transform selection, MTS flag, represented as tu_mts_flag, is present in the residual coding syntax for the intra coding unit; sps_mts_intra_enabled_flag is equal to 0, it specifies that tu_mts_flag is not present in the residual coding syntax of the intra coding unit; Here, if sps_mts_intra_enabled_flag is not present, then sps_mts_intra_enabled_flag is inferred to be 0.

[0052] The present disclosure further comprises: an obtaining unit configured to obtain a residual signal resulting from an inter or intra image prediction; an inference unit configured to infer the use of a Discrete Cosine Transform type 2, DCT2, transform core on the sequence of residual signals; a processing unit configured to process the transformation of the block using the inferred transform core; The present invention provides an encoder comprising:

[0053] As such, in a possible implementation of the encoder according to any of the above-mentioned implementations of the above-mentioned aspects, the inference unit is configured to infer the use of DCT2 from a sequence-level DCT2 enable flag in a sequence parameter set, SPS.

[0054] As such, in a possible implementation of an encoder according to any of the above-mentioned implementations of the above-mentioned aspects, the sequence-level DCT2 enabled flag is represented as sps_dct2_enabled_flag.

[0055] In any of the above implementations of the above two aspects or as such a possible implementation of an encoder according to the above aspect, a sequence level DCT2 significance flag is included in the SPS level syntax as follows:

[0056] [Table 3]

[0057] Here, sps_dct2_enabled_flag represents the sequence level DCT2 enabled flag.

[0058] As such, in a possible implementation of an encoder according to the above aspect, sps_mts_intra_enabled_flag equal to 1 specifies that tu_mts_flag may be present in the residual coding syntax of the intra coding unit, sps_mts_intra_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of the intra coding unit, and if sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0059] In any of the above implementations of the two above aspects or possible implementations of an encoder according to the above aspect as such, sps_mts_inter_enabled_flag specifies that tu_mts_flag may be present in the residual coding syntax of the inter coding unit, sps_mts_inter_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of the inter coding unit, and if sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0060] In any of the above implementations of the above five aspects or as such a possible implementation of an encoder according to the above aspect, A sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used for the transformation.

[0061] In any of the above implementations of the six above aspects or as such a possible implementation of an encoder according to the above aspect, A sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transformation.

[0062] In any of the above implementations of the seven above aspects or possible implementations of an encoder according to the above aspects as such, a sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for both horizontal and vertical transforms.

[0063] In any of the above implementations of the eight above aspects or possible implementations of an encoder according to the above aspect as such, a sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for the sub-block transform.

[0064] As such, in a possible implementation of an encoder according to the aforementioned aspect, if one side of the residual transform unit, tu, is greater than 32, the corresponding transform is set as DCT2.

[0065] In any of the above implementations of the above ten aspects or possible implementations of an encoder according to the above aspects as such, if a sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transform, then both the sub-block transform and the multiple transform selection, MTS, transform are inferred to be off.

[0066] In any of the above implementations of the eleven above aspects or possible implementations of an encoder according to the above aspects as such, A sequence level DCT2 enable flag equal to 0 specifies that a transform core other than the DCT2 is used for the transformation.

[0067] As such, in a possible implementation of an encoder according to any of the above-mentioned implementations of the above-mentioned aspects, The inference unit is configured to infer using a discrete sine transform type 7, DST7, and / or a discrete cosine transform type 8, DCT8, for the transformation.

[0068] In any of the above implementations of the above two aspects or as such a possible implementation of an encoder according to the above aspect, a sequence-level DCT2 valid flag equal to 0 may be Specifies that it is inferred using DST7 / DCT8 only for conversion.

[0069] In any of the above implementations of the three above aspects or as such a possible implementation of an encoder according to the above aspect, If the sequence level DCT2 enable flag is equal to 0, then it is determined whether multiple transform selection for the sequence parameter set has been enabled via the flag.

[0070] As such, in a possible implementation of an encoder according to any of the above-mentioned implementations of the above-mentioned aspects, If sps_mts_intra_enabled_flag is present, sps_mts_intra_enabled_flag is equal to 1 to specify that the transform unit, TU, multiple transform selection, and MTS flags, represented as tu_mts_flag, are present in the residual coding syntax for the intra coding unit; sps_mts_intra_enabled_flag is equal to 0, it specifies that tu_mts_flag is not present in the residual coding syntax of the intra coding unit; Here, if sps_mts_intra_enabled_flag is not present, then sps_mts_intra_enabled_flag is inferred to be 0.

[0071] The present disclosure further provides a computer program product comprising program code for performing any of the above-mentioned implementations of the above-mentioned aspects or the method according to the above-mentioned aspects as such.

[0072] The present disclosure further comprises: one or more processors; a non-transitory computer-readable storage medium coupled to a processor and storing programming for execution by the processor, the programming, when executed by the processor, configuring a decoder to perform any of the aforementioned implementations of the aforementioned aspects or a method according to the aforementioned aspects as such; A decoder comprising:

[0073] The present disclosure further comprises: one or more processors; a non-transitory computer-readable storage medium coupled to a processor and storing programming for execution by the processor, the programming, when executed by the processor, configuring the encoder to perform any of the aforementioned implementations of the aforementioned aspects or a method according to the aforementioned aspects as such; The present invention provides an encoder comprising:

[0074] The present disclosure further provides a computer-readable non-transitory medium storing a program including instructions that, when executed on a processor, cause the processor to perform any of the above-mentioned implementations of the above-mentioned aspects or a method according to the above-mentioned aspects as such. [Brief description of the drawings]

[0075] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. [Figure 1A] FIG. 1 is a block diagram illustrating an example of a video coding system configured to implement embodiments of the present disclosure. [Figure 1B] 2 is a block diagram illustrating another example of a video coding system configured to implement embodiments of the present disclosure. [Diagram 2] FIG. 2 is a block diagram illustrating an example of a video encoder configured to implement embodiments of the present disclosure. [Diagram 3] 2 is a block diagram illustrating an example structure of a video decoder configured to implement embodiments of the present disclosure. [Figure 4] 1 is a block diagram showing an example of an encoding device or a decoding device; [Diagram 5] FIG. 2 is a block diagram showing another example of an encoding device or a decoding device. [Figure 6] FIG. 2 is a block diagram illustrating an example of horizontal and vertical transformations for each SBT position. [Figure 7] FIG. 13 is a block diagram showing another example of horizontal and vertical transformations for each SBT position. [Figure 8] 1 illustrates a method for video coding of a block of an image according to the present disclosure. [Figure 9] Indicates the encoder. [Figure 10] In the following, unless expressly specified otherwise, identical reference signs refer to identical or at least functionally equivalent features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0076] In the following description, reference is made to the accompanying drawings, which form a part of this disclosure and show by way of example specific aspects of the disclosed embodiments or specific aspects in which the disclosed embodiments may be used. It is understood that the disclosed embodiments may be used in other ways and may include structural or logical changes not shown in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0077] For example, it is understood that disclosure related to a described method may also apply to a corresponding device or system configured to perform the method, and vice versa. For example, when one or more steps of a particular method are described, the corresponding device may include one or more units, e.g., functional units, performing one or more steps of the described method, even if such one or more units are not explicitly described or shown in the figures. On the other hand, for example, when a particular apparatus is described based on one or more units, e.g., functional units, the corresponding method may include one step performing the function of one or more units, even if such one or more steps are not explicitly described or shown in the figures (e.g., one step performing the function of one or more units, or multiple steps each performing the function of one or more units). Furthermore, it is understood that features of various exemplary embodiments and / or aspects described herein may be combined with each other, unless specifically noted otherwise.

[0078] Video coding typically refers to the processing of a series of images forming a video or a video sequence. Instead of the term "image", the terms "frame" or "image" may be used as synonyms in the video coding field. Video coding (or coding in general) includes two parts: video encoding and video decoding. Video encoding is performed on the source side and typically involves processing (e.g., by compression) the original video image to reduce the amount of data required to represent the video image (for more efficient storage and / or transmission). Video decoding is performed on the destination side and typically involves the reverse processing compared to the encoder to reconstruct the video image. The embodiments referring to "coding" of a video image (or images in general) shall be understood to relate to "encoding" or "decoding" of the video image or the respective video sequence. The combination of the encoding and decoding parts is also referred to as a codec (Coding and Decoding).

[0079] In the case of lossless video coding, the original video image can be reconstructed, i.e. the reconstructed video image is of the same quality as the original video image (assuming there is no transmission loss or other data loss during storage or transmission). In the case of lossy video coding, further compression, e.g. by quantization, is performed to reduce the amount of data representing the video image, which cannot be completely reconstructed at the decoder, i.e. the quality of the reconstructed video image is reduced or degraded compared to the quality of the original video image.

[0080] Some video coding standards belong to the group of "lossy hybrid video codecs" (i.e., they combine spatial and temporal prediction in the sample domain with 2D transform coding to apply quantization in the transform domain). Each image of a video sequence is typically partitioned into a set of non-overlapping blocks, and coding is typically performed at the block level. In other words, in the encoder, the video is typically processed, i.e., encoded, at the block (video block) level, for example, by generating a predictive block using spatial (intra-image) prediction and / or temporal (inter-image) prediction, subtracting the predictive block from a current block (the block currently being / to be processed) to obtain a residual block, transforming the residual block and quantizing the residual block in the transform domain to reduce (compress) the amount of data to be transmitted, while in the decoder, the inverse process is applied to the encoded or compressed block compared to the encoder to reconstruct the current block for representation. Furthermore, the encoder repeats the decoder processing loop, resulting in both generating the same predictions (e.g., intra- and inter-predictions) and / or reconstructions for processing, i.e., coding, of subsequent blocks.

[0081] In the following, embodiments of a video coding system 10, a video encoder 20, and a video decoder 30 are described based on FIGS.

[0082] 1A is a schematic block diagram illustrating an example coding system 10 that may utilize techniques of the present application, such as video coding system 10 (or coding system 10 for short). A video encoder 20 (or encoder 20 for short) and a video decoder 30 (or decoder 30 for short) of video coding system 10 represent examples of devices that may be configured to perform techniques in accordance with various examples described herein.

[0083] As shown in FIG. 1A, coding system 10 includes a source device 12 configured to provide (13) encoded image data 21 to a destination device 14, for example, for decoding the encoded image data.

[0084] The source device 12 comprises an encoder 20 and may additionally, i.e. optionally, comprise an image source 16 , a pre-processor (or pre-processing unit) 18 , for example an image pre-processor 18 , and a communication interface or unit 22 .

[0085] Image source 16 may include or be any type of image capture device, such as a camera that captures real-world images, and / or any type of image generation device, such as a computer graphics processor that generates computer-animated images, or any type of other device that obtains and / or provides real-world images, computer-generated images (e.g., screen content, virtual reality (VR) images), and / or any combination thereof (e.g., augmented reality (AR) images). Image source may be any type of memory or storage that stores any of the aforementioned images.

[0086] To distinguish from the pre-processor 18 and the processing performed by the pre-processing unit 18 , the image or image data 17 may also be referred to as raw image or raw image data 17 .

[0087] The pre-processor 18 is configured to receive the (raw) image data 17 and perform pre-processing on the image data 17 to obtain a pre-processed image 19 or pre-processed image data 19. The pre-processing performed by the pre-processor 18 may include, for example, cropping, color format conversion (e.g., from RGB to YCbCr), color correction, or noise removal. It can be understood that the pre-processing unit 18 may be an optional component.

[0088] Video encoder 20 is configured to receive pre-processed image data 19 and provide encoded image data 21 (further details are described below, eg, with reference to FIG. 2).

[0089] The communications interface 22 of the source device 12 may be configured to receive the encoded image data 21 and to transmit the encoded image data 21 (or any further processed version thereof) via the communications channel 13 to another device, such as the destination device 14 or any other device, for storage or direct reconstruction.

[0090] The destination device 14 comprises a decoder 30 (eg, a video decoder 30), and may additionally, i.e. optionally, comprise a communications interface or unit 28, a post-processor 32 (or post-processing unit 32), and a display device 34.

[0091] The communications interface 28 of the destination device 14 is configured to receive the encoded image data 21 (or any further processed version thereof), for example directly from the source device 12 or from any other source, for example a storage device, for example an encoded image data storage device, and to provide the encoded image data 21 to a decoder 30.

[0092] Communications interface 22 and communications interface 28 may be configured to transmit or receive (13) encoded image data 21 or encoded data via a direct communications link between source device 12 and destination device 14, such as a direct wired or wireless connection, or via any type of network, such as a wired or wireless network or any combination thereof, or any type of private and public network, or any type of combination thereof.

[0093] The communications interface 22 may be configured, for example, to package the encoded image data 21 into an appropriate format, for example into packets, and / or to process the encoded image data using any type of transmission encoding or processing for transmission over a communications link or network.

[0094] Communications interface 28, forming a counterpart to communications interface 22, may be configured, for example, to receive the transmitted data and process the transmitted data using any type of corresponding transmission decoding or processing and / or depackaging to obtain encoded image data 21.

[0095] Both communication interface 22 and communication interface 28 may be configured as unidirectional communication interfaces, as indicated by the arrow of communication channel 13 pointing from source device 12 to destination device 14 in FIG. 1A, or as bidirectional communication interfaces, e.g., configured to send and receive messages, e.g., set up connections, and confirm and exchange communications links and / or any other information related to data transmission, e.g., transmission of encoded image data.

[0096] The decoder 30 is configured to receive the encoded image data 21 and provide decoded image data 31 or a decoded image 31 (further details are explained below, e.g. based on FIG. 3 or FIG. 5). The post-processor 32 of the destination device 14 is configured to post-process the decoded image data 31 (also called reconstructed image data), e.g. the decoded image 31, to obtain post-processed image data 33, e.g. the post-processed image 33. The post-processing performed by the post-processing unit 32 may include, e.g., color format conversion (e.g., from YCbCr to RGB), color correction, cropping or resampling, or any other processing, e.g. with the purpose of preparing the decoded image data 31 for display, e.g. by a display device 34.

[0097] A display device 34 of the destination device 14 is configured to receive the post-processed image data 33 for displaying the image, for example to a user or viewer. The display device 34 may be or include any type of display for displaying the reconstructed image, for example an integrated or external display or monitor. The display may include, for example, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro LED display, a liquid crystal on silicon (LCoS), a digital light processor (DLP), or any type of other display.

[0098] 1A illustrates source device 12 and destination device 14 as separate devices, an embodiment of the devices may include both or both of their functionality, i.e., source device 12 or corresponding functionality and destination device 14 or corresponding functionality. In such an embodiment, source device 12 or corresponding functionality and destination device 14 or corresponding functionality may be implemented using the same hardware and / or software or by separate hardware and / or software or any combination thereof.

[0099] As will be clear to those skilled in the art based on this description, the presence and (exact) division of functions of different units or functions within source device 12 and / or destination device 14 as shown in FIG. 1A may vary depending on the actual device and application.

[0100] The encoder 20 (e.g., video encoder 20) or the decoder 30 (e.g., video decoder 30) or both the encoder 20 and the decoder 30 may be implemented via processing circuitry as shown in FIG. 1B, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, hardware, dedicated to video coding, or any combination thereof. The encoder 20 may be implemented via processing circuitry 46 to embody various modules described in connection with the encoder 20 of FIG. 2 and / or any other encoder system or subsystem described herein. The decoder 30 may be implemented via processing circuitry 46 to embody various modules described in connection with the decoder 30 of FIG. 3 and / or any other decoder system or subsystem described herein. The processing circuitry may be configured to perform various operations as described below. If the techniques are implemented partially in software, as shown in FIG. 5, the device may store instructions for the software in a suitable non-transitory computer-readable storage medium and may execute the instructions using one or more processors in hardware to perform the techniques of this disclosure. Either video encoder 20 and video decoder 30 may be integrated as part of a combined encoder / decoder (codec) in a single device, for example, as shown in FIG. 1B.

[0101] Source device 12 and destination device 14 may comprise any of a wide range of devices, including any type of handheld or stationary device, such as a notebook or laptop computer, a mobile phone, a smartphone, a tablet or tablet computer, a camera, a desktop computer, a set-top box, a television, a display device, a digital media player, a video gaming console, a video streaming device (such as a content service server or a content delivery server), a broadcast receiver device, a broadcast transmitter device, etc., and may use no operating system or any type of operating system. In some cases, source device 12 and destination device 14 may be enabled for wireless communication. Thus, source device 12 and destination device 14 may be wireless communication devices.

[0102] In some cases, the video coding system 10 shown in FIG. 1A is merely an example, and the techniques of the present application may be applied to video coding settings (e.g., video encoding or video decoding) that do not necessarily include any data communication between an encoding device and a decoding device. In other examples, data may be retrieved from local memory, streamed over a network, etc. A video encoding device may encode and store data in memory, and / or a video decoding device may retrieve data from memory and decode it. In some examples, encoding and decoding are performed by devices that do not communicate with each other but simply encode data in memory and / or retrieve data from memory and decode it.

[0103] For ease of explanation, embodiments of the present disclosure are described herein with reference to, for example, reference software for High Efficiency Video Coding (HEVC) or Versatile Video Coding (VVC), a next-generation video coding standard developed by the ITU-T Video Coding Experts Group (VCEG) and the ISO / IEC Moving Picture Experts Group (MPEG) Joint Working Group on Video Coding (JCT-VC). Those skilled in the art will appreciate that embodiments of the present disclosure are not limited to HEVC or VVC.

[0104] [Encoder and encoding method]

[0105] FIG. 2 shows a schematic block diagram of an exemplary video encoder 20 configured to implement the techniques of the present application. In the example of FIG. 2, the video encoder 20 includes an input 201 (or an input interface 201), a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a loop filter unit 220, a decoded picture buffer (DPB) 230, a mode selection unit 260, an entropy encoding unit 270, and an output 272 (or an output interface 272). The mode selection unit 260 may include an inter prediction unit 244, an intra prediction unit 254, and a partitioning unit 262. The inter prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown). The video encoder 20 shown in FIG. 2 may also be referred to as a hybrid video encoder or a video encoder with a hybrid video codec.

[0106] The residual calculation unit 204, the transform processing unit 206, the quantization unit 208, and the mode selection unit 260 may be referred to as forming a forward signal path of the encoder 20, while the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, the inter prediction unit 244, and the intra prediction unit 254 may be referred to as forming a backward signal path of the video encoder 20. The backward signal path of the video encoder 20 corresponds to the signal path of the decoder (see the video decoder 30 of FIG. 3). The inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded picture buffer (DPB) 230, the inter prediction unit 244, and the intra prediction unit 254 may also be referred to as forming a "built-in decoder" of the video encoder 20.

[0107] [Images and Image Segmentation (Images and Blocks)]

[0108] The encoder 20 may be configured to receive, for example, via an input 201, an image 17 (or image data 17), for example an image of a sequence of images forming a video or a video sequence. The received image or image data may be a preprocessed image 19 (or preprocessed image data 19). For the sake of brevity, the following description refers to the image 17. The image 17 may also be referred to as the current image or the image to be coded (particularly in video coding, to distinguish the current image from other images, for example previously encoded and / or decoded images of the same video sequence, i.e. a video sequence which also includes the current image).

[0109] A (digital) image is or may be considered as a two-dimensional array or matrix of samples with intensity values. The samples in the array may also be called pixels (short for picture element) or pels. The number of samples in the horizontal and vertical directions (or axes) of the array or image defines the size and / or resolution of the image. To represent color, typically three color components are used, i.e. an image may be represented by or may contain three sample arrays. In an RBG format or color space, an image contains corresponding red, green, and blue sample arrays. However, in video coding, each pixel is typically represented in a luminance and chrominance format or color space, e.g. YCbCr, which includes a luminance component denoted Y (sometimes L is used instead) and two chrominance components denoted Cb and Cr. The luminance (or luma for short) component Y represents the brightness or intensity of a gray level (e.g., as in a grayscale image), while the two chrominance (or chroma for short) components Cb and Cr represent the chromaticity or color information components. Thus, an image in YCbCr format includes a luminance sample array of luminance sample values ​​(Y) and two chrominance sample arrays of chrominance values ​​(Cb and Cr). An image in RGB format can be converted or transformed into YCbCr format and vice versa, a process also known as color conversion or transformation. If the image is monochrome, the image may include only a luminance sample array. Thus, an image may be, for example, an array of luma samples in monochrome format, or an array of luma samples and two corresponding arrays of chroma samples in 4:2:0, 4:2:2, and 4:4:4 color formats.

[0110] An embodiment of the video encoder 20 may comprise an image partitioning unit (not shown in FIG. 2 ) configured to partition an image 17 into multiple (typically non-overlapping) image blocks 203. These blocks may also be referred to as root blocks, macroblocks (H.264 / AVC) or coding tree blocks (CTBs) or coding tree units (CTUs) (H.265 / HEVC and VVC). The image partitioning unit may be configured to partition each image into corresponding blocks using the same block size for all images of a video sequence and a corresponding grid defining the block size, or to vary the block size between images or subsets or groups of images.

[0111] In a further embodiment, the video encoder may be configured to directly receive a block 203 of the image 17, e.g. one, some or all of the blocks forming the image 17. The image block 203 may also be referred to as a current image block or an image block to be coded.

[0112] Here as well as in the image 17, the image block 203 is or can be considered as a two-dimensional array or matrix of samples with intensity values ​​(sample values), although with smaller dimensions than the image 17. In other words, the block 203 may comprise, for example, one sample array (for example a luma array in case of a monochrome image 17, or a luma or chroma array in case of a color image), or three sample arrays (for example a luma and two chroma arrays in case of a color image 17), or any other number and / or type of arrays depending on the color format applied. The number of samples in the horizontal and vertical directions (or axes) of the block 203 defines the size of the block 203. The block may thus be, for example, an M×N (M columns×N rows) array of samples, or an M×N array of transformation coefficients.

[0113] The embodiment of video encoder 20 shown in FIG. 2 may be configured to encode image 17 block-by-block, eg, encoding and prediction are performed for each block 203 .

[0114] The embodiment of video encoder 20 shown in FIG. 2 may further be configured to partition and / or encode an image using slices (also referred to as video slices), where an image may be partitioned or encoded using one or more slices (typically non-overlapping), and each slice may include one or more blocks (e.g., CTUs).

[0115] The embodiment of video encoder 20 shown in FIG. 2 may be further configured to partition and / or encode an image using tile groups (also referred to as video tile groups) and / or tiles (also referred to as video tiles), where an image may be partitioned or encoded using one or more tile groups (typically non-overlapping), where each tile group may, for example, include one or more blocks (e.g., CTUs) or one or more tiles, where each tile may, for example, be rectangular in shape and include one or more blocks (e.g., CTUs), e.g., full or fractional blocks.

[0116] [Residual calculation]

[0117] The residual calculation unit 204 may be configured to calculate the residual block 205 (also referred to as residual 205) based on the image block 203 and the prediction block 265 (further details regarding the prediction block 265 are provided later), for example, by subtracting sample values ​​of the prediction block 265 from sample values ​​of the image block 203 on a sample-by-sample (pixel-by-pixel) basis to obtain the residual block 205 in the sample domain.

[0118] [conversion]

[0119] The transform processing unit 206 may be configured to apply a transform, such as a discrete cosine transform (DCT) or a discrete sine transform (DST), to the sample values ​​of the residual block 205 to obtain transform coefficients 207 in a transform domain. The transform coefficients 207 may also be referred to as transform residual coefficients and represent the residual block 205 in the transform domain.

[0120] The transform processing unit 206 may be configured to apply an integer approximation of a DCT / DST, such as the transform specified in H.265 / HEVC. Compared to an orthogonal DCT transform, such an integer approximation is typically scaled by a certain factor. To preserve the norm of the residual block processed by the forward transform and the inverse transform, an additional scaling factor is applied as part of the transform process. The scaling factor is typically selected based on certain constraints, such as a scaling factor that is a power of two of the shift operation, a bit depth of the transform coefficients, a trade-off between accuracy and implementation cost, etc. For example, a certain scaling factor may be specified for the inverse transform, e.g., by the inverse transform processing unit 212 (and a corresponding inverse transform, e.g., by the inverse transform processing unit 312 in the video decoder 30), and a corresponding scaling factor for the forward transform, e.g., by the transform processing unit 206 in the encoder 20, may be specified accordingly.

[0121] An embodiment of video encoder 20 (respectively transformation processing unit 206) may be configured to encode or compress and then output transformation parameters, e.g., one or more types of transformation, e.g., directly or via entropy encoding unit 270, so that, for example, video decoder 30 may receive and use the transformation parameters for decoding.

[0122] [Quantization]

[0123] The quantization unit 208 may be configured to quantize the transform coefficients 207, for example by applying scalar quantization or vector quantization, to obtain quantized coefficients 209. The quantized coefficients 209 may also be referred to as quantized transform coefficients 209 or quantized residual coefficients 209.

[0124] The quantization process may reduce the bit depth associated with some or all of the transform coefficients 207. For example, an n-bit transform coefficient may be rounded to an m-bit transform coefficient during quantization, where n is greater than m. The degree of quantization may be changed by adjusting a quantization parameter (QP). For example, in the case of scalar quantization, different scaling may be applied to achieve finer or coarser quantization. A smaller quantization step size corresponds to finer quantization, while a larger quantization step size corresponds to coarser quantization. The applicable quantization step sizes may be indicated by a quantization parameter (QP). The quantization parameter may, for example, be an index to a predefined set of applicable quantization step sizes. For example, a small quantization parameter may correspond to fine quantization (small quantization step size) and a large quantization parameter may correspond to coarse quantization (large quantization step size), or vice versa. Quantization may include division by a quantization step size, and corresponding and / or inverse dequantization, e.g., by the inverse quantization unit 210, may include multiplication by the quantization step size. Some standards, e.g., HEVC, may be configured to use a quantization parameter to determine the quantization step size. In general, the quantization step size may be calculated based on the quantization parameter using a fixed-point approximation of an equation that includes a division. To restore the norm of the residual block, an additional scaling factor may be introduced in the quantization and dequantization, which may change due to the scaling used in the fixed-point approximation of the quantization step size and quantization parameter equations. In one implementation, the scaling of the inverse transform and dequantization may be combined. Alternatively, customized quantization tables may be used and signaled, e.g., in the bitstream, from the encoder to the decoder. Quantization is a lossy operation, and the loss increases with increasing quantization step size.

[0125] An embodiment of video encoder 20 (respectively quantization unit 208) may be configured to encode and then output a quantization parameter (QP), e.g., directly or via entropy encoding unit 270, so that video decoder 30, for example, may receive and apply the quantization parameter for decoding.

[0126] [Dequantization]

[0127] Inverse quantization unit 210 is configured to apply the inverse quantization of quantization unit 208 to the quantized coefficients, e.g., by applying the inverse of the quantization scheme applied by quantization unit 208 based on or using the same quantization step size as quantization unit 208, to obtain dequantized coefficients 211. The dequantized coefficients 211 may also be referred to as dequantized residual coefficients 211, and correspond to the transform coefficients 207, although they are typically not identical to the transform coefficients due to losses due to quantization.

[0128] [Inverse Transformation]

[0129] The inverse transform processing unit 212 is configured to apply an inverse transform of the transform applied by the transform processing unit 206, such as an inverse discrete cosine transform (DCT) or an inverse discrete sine transform (DST) or other inverse transform, to obtain a reconstructed residual block 213 (or corresponding dequantized coefficients 213) in the sample domain. The reconstructed residual block 213 may also be referred to as a transform block 213.

[0130] [Rebuild]

[0131] The reconstruction unit 214 (e.g., an adder or summator 214) is configured to add the transform block 213 (i.e., the reconstructed residual block 213) to the prediction block 265, e.g., by adding, sample by sample, sample values ​​of the reconstructed residual block 213 and sample values ​​of the prediction block 265 to obtain a reconstructed block 215 in the sample domain.

[0132] [filtering]

[0133] The loop filter unit 220 (or "loop filter" 220 for short) is configured to filter the reconstructed block 215 to obtain a filtered block 221, or in general, to filter the reconstructed samples to obtain filtered samples. The loop filter unit is configured to, for example, smooth pixel transitions or otherwise improve video quality. The loop filter unit 220 may comprise one or more loop filters, such as a deblocking filter, a sample adaptive offset (SAO) filter, or one or more other filters, such as a bilateral filter, an adaptive loop filter (ALF), a sharpening, smoothing filter, or a collaborative filter, or any combination thereof. Although the loop filter unit 220 is illustrated in FIG. 2 as being within the loop filter, in other configurations the loop filter unit 220 may be implemented as a post-loop filter. The filtered block 221 may also be referred to as a filtered reconstructed block 221.

[0134] An embodiment of video encoder 20 (respectively loop filter unit 220) may be configured to encode and then output loop filter parameters (e.g., sample adaptive offset information), e.g., directly or via entropy encoding unit 270, so that decoder 30, for example, may receive and apply the same loop filter parameters or respective loop filters for decoding.

[0135] [Decoded image buffer]

[0136] The decoded picture buffer (DPB) 230 may be a memory that stores reference pictures, or generally reference image data, for encoding video data by the video encoder 20. The DPB 230 may be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous dynamic random access memory (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. The decoded picture buffer (DPB) 230 may be configured to store one or more filtered blocks 221. The decoded picture buffer 230 may further be configured to store other previously filtered blocks, e.g., previously reconstructed and filtered blocks 221, of the same current picture or a different picture, e.g., a previously reconstructed picture, and / or may provide a previously reconstructed, i.e., decoded, complete picture (and corresponding reference blocks and samples) and / or a partially reconstructed current picture (and corresponding reference blocks and samples), e.g., for inter prediction. The decoded picture buffer (DPB) 230 may be configured to store, for example, one or more unfiltered reconstructed blocks 215 if the reconstructed blocks 215 have not been filtered by the loop filter unit 220, or, in general, unfiltered reconstructed samples, or any other further processed version of the reconstructed blocks or samples.

[0137] [Mode Selection (Segmentation and Prediction)]

[0138] The mode selection unit 260 comprises a partitioning unit 262, an inter prediction unit 244 and an intra prediction unit 254 and is configured to receive or obtain original image data, e.g. original block 203 (current block 203 of current image 17), and reconstructed image data, e.g. filtered and / or unfiltered reconstructed samples or blocks of the same (current) image and / or from one or more previously decoded images, e.g. from a decoded image buffer 230 or other buffer (e.g. line buffer, not shown). The reconstructed image data is used as reference image data for prediction, e.g. inter prediction or intra prediction, to obtain a prediction block 265 or predictor 265.

[0139] The mode selection unit 260 may be configured to determine or select a partitioning for a current block prediction mode (not including partitioning) and a prediction mode (e.g., intra or inter prediction mode), and to generate a corresponding prediction block 265, which is used for calculating the residual block 205 and for reconstructing the reconstructed block 215.

[0140] An embodiment of the mode selection unit 260 may be configured to select a partitioning and prediction mode (e.g., from those supported by or available to the mode selection unit 260) that provides the best match, or in other words, the smallest residual (smallest residual means better compression rate for transmission or storage), or the smallest signaling overhead (smallest signaling overhead means better compression rate for transmission or storage), or a consideration or balance of both. The mode selection unit 260 may be configured to determine the partitioning and prediction mode based on rate-distortion optimization (RDO), i.e., to select the prediction mode that provides the smallest rate-distortion. Terms such as "best", "minimum", "optimum", etc. in this context do not necessarily refer to the overall "best", "minimum", "optimum", etc., but may refer to the achievement of a termination or selection criterion, such as a value exceeding or falling below a threshold or other constraint, potentially leading to a "suboptimal selection", but with reduced complexity and processing time.

[0141] In other words, the partitioning unit 262 may be configured to partition the block 203 into smaller block partitions or sub-blocks (again forming blocks), e.g., using quadtree partitioning (QT), binary tree partitioning (BT), or ternary tree partitioning (TT) or any combination thereof repeatedly, and to perform, e.g., prediction on each of the block partitions or sub-blocks, where the mode selection includes selecting a tree structure of the partitioned block 203, and a prediction mode is applied to each of the block partitions or sub-blocks.

[0142] The partitioning (eg, by partitioning unit 260) and prediction processes (by inter prediction unit 244 and intra prediction unit 254) performed by exemplary video encoder 20 are described in more detail below.

[0143] [Partitioning]

[0144] The partitioning unit 262 may partition (or divide) the current block 203 into smaller partitions, e.g., smaller blocks of square or rectangular size. These smaller blocks (which may also be referred to as sub-blocks) may be further partitioned into even smaller partitions. This is also referred to as tree partitioning or hierarchical tree partitioning, where a root block, e.g., at root tree level 0 (hierarchical level 0, depth 0), may be recursively partitioned, e.g., into two or more blocks at a node at the next lower tree level, e.g., tree level 1 (hierarchical level 1, depth 1), which may be repartitioned into two or more blocks at the next lower level, e.g., tree level 2 (hierarchical level 2, depth 2), etc., until the partitioning is terminated, e.g., due to a termination criterion being reached, e.g., due to reaching a maximum tree depth or a minimum block size. Blocks that are not further partitioned are also referred to as leaf blocks or leaf nodes of the tree. A tree that uses a partitioning into two partitions is called a binary tree (BT), a tree that uses a partitioning into three partitions is called a ternary tree (TT), and a tree that uses a partitioning into four partitions is called a quad tree (QT).

[0145] As mentioned above, the term "block" as used herein may be a portion of an image, in particular a square or rectangular portion. For example, with reference to HEVC and VVC, a block may be or correspond to a coding tree unit (CTU), a coding unit (CU), a prediction unit (PU), and a transform unit (TU), and / or a corresponding block, such as a coding tree block (CTB), a coding block (CB), a transform block (TB), or a prediction block (PB).

[0146] For example, a coding tree unit (CTU) may be or include a CTB of luma samples, two corresponding CTBs of chroma samples of an image with three sample arrays, or a CTB of samples of an image coded using three separate color planes and syntax structures used to code a monochrome image or sample. Correspondingly, a coding tree block (CTB) may be an N×N block of samples of some value N, such that the division of components into CTBs is partitioning. A coding unit (CU) may be or include a coding block of luma samples, two corresponding coding blocks of chroma samples of an image with three sample arrays, or a coding block of samples of an image coded using three separate color planes and syntax structures used to code a monochrome image or sample. Correspondingly, a coding block (CB) may be an M×N block of samples of some values ​​M and N, such that the division of a CTB into coding blocks is partitioning.

[0147] For example, in an embodiment according to HEVC, a coding tree unit (CTU) may be divided into CUs by using a quadtree structure represented as a coding tree. The decision of whether to code an image area using inter-image (temporal) prediction or intra-image (spatial) prediction is made at the CU level. Each CU can be further divided into one, two, or four PUs according to the partition type of the PU. Inside one PU, the same prediction process is applied, and related information is sent to the decoder on a PU basis. After obtaining the residual block by applying the prediction process based on the partition type of the PU, the CU can be partitioned into transform units (TUs) according to another quadtree structure similar to the coding tree of the CU.

[0148] For example, in an embodiment according to the latest video coding standard currently under development, called Versatile Video Coding (VVC), for example, a combined quad-tree and binary tree (QTBT) partitioning is used to partition the coding block. In the QTBT block structure, the CU can be either square or rectangular in shape. For example, the coding tree unit (CTU) is first partitioned by a quad-tree structure. The leaf nodes of the quad-tree are further partitioned by a ternary (or triple) tree structure. The leaf nodes of the partitioning tree are called coding units (CUs), whose segmentation is used for prediction and transformation processes without any further partitioning. That is, the CUs, PUs, and TUs have the same block size in the QTBT coding block structure. In parallel, multiple partitionings, for example, ternary tree partitioning, can be used with the QTBT block structure.

[0149] In one example, mode selection unit 260 of video encoder 20 may be configured to perform any combination of the partitioning techniques described herein.

[0150] As described above, video encoder 20 may be configured to determine or select a best or optimal prediction mode from a (e.g., predetermined) set of prediction modes, which may include, for example, intra-prediction modes and / or inter-prediction modes.

[0151] [Intra prediction]

[0152] The set of intra prediction modes may include 35 different intra prediction modes, e.g., non-directional modes such as DC (or average) mode and planar mode, or directional modes as defined in HEVC, or may include 67 different intra prediction modes, e.g., non-directional modes such as DC (or average) mode and planar mode, or directional modes as defined for VVC.

[0153] The intra prediction unit 254 is configured to generate an intra prediction block 265 according to an intra prediction mode from a set of intra prediction modes using reconstructed samples of neighboring blocks of the same current image.

[0154] The intra prediction unit 254 (or generally, the mode selection unit 260) is further configured to output intra prediction parameters (or generally, information indicating the intra prediction mode selected for the block) to the entropy encoding unit 270 in the form of syntax element 266 to be included in the encoded image data 21, so that, for example, the video decoder 30 may receive and use the prediction parameters for decoding.

[0155] [Inter prediction]

[0156] The set (or possible) inter prediction modes depends on the available reference images (i.e., previously at least partially decoded images, e.g., stored in DBP230) and other inter prediction parameters, such as, for example, whether the entire reference image or only a portion of it is used to search for the best matching reference block, such as, for example, a search window area around the area of ​​the current block in the reference image, and / or whether pixel interpolation, e.g., half-pel and / or quarter-pel interpolation, has been applied.

[0157] In addition to the above prediction modes, skip mode and / or direct mode may be applied.

[0158] The inter prediction unit 244 may include a motion estimation (ME) unit and a motion compensation (MC) unit (both not shown in FIG. 2). The motion estimation unit may be configured to receive or obtain the image block 203 (the current image block 203 of the current image 17) and the decoded image 231, or at least one or more previously reconstructed blocks, e.g., reconstructed blocks of one or more other / different previously decoded images 231, for motion estimation. For example, a video sequence may include the current image and the previously decoded image 231, or in other words, the current image and the previously decoded image 231 may be part of or form a series of images forming a video sequence.

[0159] The encoder 20 may be configured to, for example, select a reference block from multiple reference blocks of the same or different ones of multiple other images, and provide the reference image (or reference image index) and / or an offset (spatial offset) between the position (x, y coordinates) of the reference block and the position of the current block to the motion estimation unit as an inter prediction parameter. This offset is also called a motion vector (MV).

[0160] The motion compensation unit is configured to obtain, e.g., receive, inter prediction parameters, and perform inter prediction based on or using the inter prediction parameters to obtain an inter prediction block 265. The motion compensation performed by the motion compensation unit may involve fetching or generating a prediction block based on a motion / block vector determined by motion estimation, possibly performing interpolation up to sub-pixel accuracy. Interpolation filtering may generate additional pixel samples from known pixel samples, thus potentially increasing the number of candidate prediction blocks that can be used to code the image block. Upon receiving a motion vector for the PU of the current image block, the motion compensation unit may locate the prediction block to which the motion vector points in one of the reference image lists.

[0161] The motion compensation unit may generate syntax elements associated with blocks and video slices for use by video decoder 30 in decoding image blocks of the video slices. In addition to or in the alternative to slices and their respective syntax elements, tile groups and / or tiles and their respective syntax elements may be generated or used.

[0162] [Entropy coding]

[0163] The entropy encoding unit 270 is configured to, for example, apply an entropy encoding algorithm or scheme (e.g., a variable length coding (VLC) scheme, a context-adaptive VLC scheme (CAVLC), an arithmetic coding scheme, binarization, context-adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or another entropy encoding method or technique) or bypass (no compression) to the quantized coefficients 209, the inter-prediction parameters, the intra-prediction parameters, the loop filter parameters, and / or other syntax elements to obtain encoded image data 21 that can be output via an output unit 272, for example in the form of an encoded bitstream 21, so that, for example, the video decoder 30 may receive and use the parameters for decoding. The encoded bitstream 21 may be transmitted to the video decoder 30 or may be stored in a memory for later transmission or retrieval by the video decoder 30.

[0164] Other structural variations of the video encoder 20 may be used to encode the video stream. For example, a non-transform-based encoder 20 may quantize the residual signal directly, without using the transform processing unit 206 for a particular block or frame. In another implementation, the encoder 20 may have the quantization unit 208 and the inverse quantization unit 210 combined into a single unit.

[0165] [Decoder and decoding method]

[0166] 3 illustrates an example of a video decoder 30 configured to implement the techniques of the present application. The video decoder 30 is configured to receive encoded image data 21 (e.g., encoded bitstream 21), e.g., encoded by encoder 20, to obtain a decoded image 331. The encoded image data or bitstream includes information for decoding the encoded image data, e.g., data representing image blocks (and / or tile groups or tiles) of encoded video slices and associated syntax elements.

[0167] In the example of Figure 3, the decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g., summer 314), a loop filter 320, a decoded picture buffer (DBP) 330, a mode application unit 360, an inter prediction unit 344, and an intra prediction unit 354. The inter prediction unit 344 may be or include a motion compensation unit. The video decoder 30 may, in some examples, perform a generally inverse decoding pass relative to the encoding pass described in connection with the video encoder 100 of Figure 2.

[0168] As described with respect to the encoder 20, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded picture buffer (DPB) 230, the inter prediction unit 344, and the intra prediction unit 354 are also referred to as forming a "built-in decoder" of the video encoder 20. Thus, the inverse quantization unit 310 may be functionally identical to the inverse quantization unit 110, the inverse transform processing unit 312 may be functionally identical to the inverse transform processing unit 212, the reconstruction unit 314 may be functionally identical to the reconstruction unit 214, the loop filter 320 may be functionally identical to the loop filter 220, and the decoded picture buffer 330 may be functionally identical to the decoded picture buffer 230. Thus, the description provided for the respective units and functions of the video encoder 20 correspondingly applies to the respective units and functions of the video decoder 30.

[0169] [Entropy Decoding]

[0170] The entropy decoding unit 304 is configured to parse the bitstream 21 (or the encoded image data 21 in general) and, for example, perform entropy decoding on the encoded image data 21 to obtain, for example, quantization coefficients 309 and / or decoded coding parameters (not shown in FIG. 3), for example, any or all of inter prediction parameters (e.g., reference image index and motion vectors), intra prediction parameters (e.g., intra prediction mode or index), transform parameters, quantization parameters, loop filter parameters, and / or other syntax elements. The entropy decoding unit 304 may be configured to apply a decoding algorithm or scheme corresponding to the encoding schemes described with respect to the entropy encoding unit 270 of the encoder 20. The entropy decoding unit 304 may be further configured to provide the inter prediction parameters, intra prediction parameters, and / or other syntax elements to the mode application unit 360 and other parameters to other units of the decoder 30. The video decoder 30 may receive syntax elements at a video slice level and / or a video block level. In addition to or in the alternative to slices and their respective syntax elements, tile groups and / or tiles and their respective syntax elements may be received and / or used.

[0171] [Dequantization]

[0172] Inverse quantization unit 310 may be configured to receive a quantization parameter (QP) (or, in general, information related to inverse quantization) and quantization coefficients from encoded image data 21 (e.g., by parsing and / or decoding, e.g., by entropy decoding unit 304) and apply inverse quantization to the decoded quantized coefficients 309 based on the quantization parameter to obtain dequantized coefficients 311, which may also be referred to as transform coefficients 311. The inverse quantization process may involve use of a quantization parameter determined by video encoder 20 for each video block within a video slice (or tile or group of tiles) to determine the degree of quantization, and thus the degree of inverse quantization to be applied.

[0173] [Inverse Transformation]

[0174] The inverse transform processing unit 312 may be configured to receive the dequantized coefficients 311, also referred to as transform coefficients 311, and apply a transform to the dequantized coefficients 311 to obtain the reconstructed residual block 213 in the sample domain. The reconstructed residual block 213 may also be referred to as a transform block 313. The transform may be an inverse transform, for example an inverse DCT, an inverse DST, an inverse integer transform, or a conceptually similar inverse transform process. The inverse transform processing unit 312 may further be configured to receive transform parameters or corresponding information from the encoded image data 21 (e.g., by parsing and / or decoding, for example, by the entropy decoding unit 304) and determine a transform to be applied to the dequantized coefficients 311.

[0175] [Rebuild]

[0176] The reconstruction unit 314 (e.g., an adder or summator 314) is configured to add the reconstructed residual block 313 to the prediction block 365, for example by adding sample values ​​of the reconstructed residual block 313 and sample values ​​of the prediction block 365, to obtain a reconstructed block 315 in the sample domain.

[0177] [filtering]

[0178] A loop filter unit 320 (either in the coding loop or after the coding loop) is configured to filter the reconstructed block 315 to obtain a filtered block 321, e.g., to smooth pixel transitions or otherwise improve video quality. The loop filter unit 320 may comprise one or more loop filters, such as a deblocking filter, a sample adaptive offset (SAO) filter, or one or more other filters, e.g., a bilateral filter, an adaptive loop filter (ALF), a sharpening, smoothing filter, or a collaborative filter, or any combination thereof. Although the loop filter unit 320 is illustrated in FIG. 3 as being in the loop filter, in other configurations the loop filter unit 320 may be implemented as a post-loop filter.

[0179] [Decoded image buffer]

[0180] The decoded video blocks 321 of the image are then stored in a decoded image buffer 330, which stores the decoded image 331 as a reference image for subsequent motion compensation of other images and / or output of the respective display.

[0181] The decoder 30 is arranged to output a decoded image 311 for presentation or display to a user, for example via an output 312.

[0182] [prediction]

[0183] The inter prediction unit 344 may be identical to the inter prediction unit 244 (in particular the motion compensation unit), and the intra prediction unit 354 may be functionally identical to the inter prediction unit 254, performing the partitioning or partitioning decision and prediction based on the partitioning and / or prediction parameters or respective information received (e.g. by analysis and / or decoding, e.g. by the entropy decoding unit 304) from the encoded image data 21. The mode application unit 360 may be configured to perform prediction (intra prediction or inter prediction) for each block based on the reconstructed image, block or respective sample (filtered or unfiltered) to obtain a prediction block 365.

[0184] If the video slice is coded as an intra-coded (I) slice, the intra prediction unit 354 of the mode application unit 360 is configured to generate a prediction block 365 for an image block of the current video slice based on the signaled intra prediction mode and data from a previously decoded block of the current image. If the video image is coded as an inter-coded (i.e., B or P) slice, the inter prediction unit 344 (e.g., a motion compensation unit) of the mode application unit 360 is configured to generate a prediction block 365 for a video block of the current video slice based on the motion vector and other syntax elements received from the entropy decoding unit 304. For inter prediction, the prediction block may be generated from one of a number of reference images included in one of a number of reference image lists. The video decoder 30 may construct the reference frame lists, List 0 and List 1, based on the reference images stored in the DPB 330 using a default construction technique. The same or similar techniques may be applied to or from embodiments that use tile groups (e.g., video tile groups) and / or tiles (e.g., video tiles) in addition to or instead of slices (e.g., video slices). For example, video may be coded using I, P, or B tile groups and / or tiles.

[0185] Mode application unit 360 is configured to determine prediction information for video blocks of the current video slice by analyzing motion vectors or related information and other syntax elements, and uses the prediction information to generate predictive blocks for the current video block being decoded. For example, mode application unit 360 uses some of the received syntax elements to determine a prediction mode (e.g., intra prediction or inter prediction) used to code the video blocks of the video slice, an inter prediction slice type (e.g., B slice, P slice, or GPB slice), construction information regarding one or more of the reference image lists for the slice, a motion vector for each inter encoded video block of the slice, an inter prediction status for each inter coded video block of the slice, and other information for decoding video blocks in the current video slice. The same or similar techniques may be applied to or in addition to embodiments that use tile groups (e.g., video tile groups) and / or tiles (e.g., video tiles) in addition to or instead of slices (e.g., video slices). For example, video may be coded using I, P, or B tile groups and / or tiles.

[0186] The embodiment of video decoder 30 shown in FIG. 3 may be configured to partition and / or decode an image using slices (also referred to as video slices), where an image may be partitioned or decoded using one or more slices (typically non-overlapping), and each slice may include one or more blocks (e.g., CTUs).

[0187] The embodiment of video decoder 30 shown in FIG. 3 may be configured to partition and / or decode an image using tile groups (also referred to as video tile groups) and / or tiles (also referred to as video tiles), where an image may be partitioned or decoded using one or more tile groups (typically non-overlapping), where each tile group may include, for example, one or more blocks (e.g., CTUs) or one or more tiles, where each tile may be, for example, rectangular in shape and may include one or more blocks (e.g., CTUs), e.g., full or fractional blocks.

[0188] Other variations of the video decoder 30 may be used to decode the encoded image data 21. For example, the decoder 30 may generate an output video stream without using a loop filtering unit 320. For example, a non-transform-based decoder 30 may inverse quantize the residual signal directly, without using an inverse transform processing unit 312 for a particular block or frame. In another implementation, the video decoder 30 may have the inverse quantization unit 310 and the inverse transform processing unit 312 combined into a single unit.

[0189] It should be understood that in the encoder 20 and the decoder 30, the processing result of the current stage may be further processed and then output to the next stage. For example, after the interpolation filtering, the motion vector derivation or the loop filtering, further operations such as clipping or shifting may be performed on the processing result of the interpolation filtering, the motion vector derivation or the loop filtering.

[0190] It should be noted that further operations may be applied to the derived motion vector of the current block (including but not limited to control point motion vector in affine mode, sub-block motion vector in affine, planar, ATMVP mode, temporal motion vector, etc.). For example, the value of the motion vector is restricted to a predefined range according to its representation bit. If the representation bit of the motion vector is bitDepth, its range is -2^(bitDepth-1) to 2^(bitDepth-1)-1, where "^" means exponentiation. For example, if bitDepth is set equal to 16, its range is -32768 to 32767, and if bitDepth is set equal to 18, its range is -131072 to 131071. For example, the value of the derived motion vector (e.g., MV of four 4x4 sub-blocks in one 8x8 block) is restricted so that the maximum difference between the integer parts of the four 4x4 sub-block MVs is less than or equal to N pixels, e.g., less than or equal to 1 pixel. Here we provide two methods to constrain motion vectors according to bitDepth.

[0191] Method 1: Remove the overflow MSB (most significant bit) by the following calculation:

number

number

[0192] Method 2: Remove the overflow MSB by clipping the value.

number

number

[0193] 4 is a schematic diagram of a video coding device 400 according to an embodiment of the present disclosure. The video coding device 400 is suitable for implementing the disclosed embodiments described herein. In an embodiment, the video coding device 400 may be a decoder, such as the video decoder 30 of FIG. 1A, or an encoder, such as the video encoder 20 of FIG. 1A.

[0194] Video coding device 400 comprises an ingress port 410 (or input port 410) and a receiver unit (Rx) 420 for receiving data, a processor, logic unit, or central processing unit (CPU) 430 for processing data, a transmitter unit (Tx) 440 and an egress port 450 (or output port 450) for transmitting data, and a memory 460 for storing data. Video coding device 400 may comprise optical / electrical (OE) and electrical / optical (EO) components coupled to ingress port 410, receiver unit 420, transmitter unit 440, and egress port 450 for egress or ingress of optical or electrical signals.

[0195] The processor 430 is implemented by hardware and software. The processor 430 may be implemented as one or more CPU chips, cores (e.g., as a multi-core processor), FPGA, ASIC, and DSP. The processor 430 communicates with the ingress port 410, the receiver unit 420, the transmitter unit 440, the egress port 450, and the memory 460. The processor 430 includes a coding module 470. The coding module 470 implements the disclosed embodiments described above. For example, the coding module 470 implements, processes, prepares, or provides various coding operations. Thus, the inclusion of the coding module 470 provides a significant improvement in the functionality of the video coding device 400, resulting in the transformation of the video coding device 400 into different states. Alternatively, the coding module 470 is implemented as instructions stored in the memory 460 and executed by the processor 430.

[0196] Memory 460 may comprise one or more disks, tape drives, and solid state drives, and may be used as an overflow data storage device to store programs when such programs are selected for execution, and to store instructions and data read during execution of the programs. Memory 460 may be, for example, volatile and / or non-volatile, and may be read only memory (ROM), random access memory (RAM), ternary content addressable memory (TCAM), and / or static random access memory (SRAM).

[0197] FIG. 5 is a simplified block diagram of an apparatus 500 that may be used as either or both of the source device 12 and the destination device 14 according to FIG. 1A in accordance with an exemplary embodiment.

[0198] The processor 502 in the device 500 may be a central processing unit. Alternatively, the processor 502 may be any other type of device or devices now existing or later developed capable of manipulating or processing information. Although implementations of the disclosure may be practiced with a single processor as shown, such as the processor 502, advantages of speed and efficiency may be realized using more than one processor.

[0199] The memory 504 in the apparatus 500 may be, in one implementation, a read-only memory (ROM) device or a random access memory (RAM) device. Any other suitable type of storage device may be used as the memory 504. The memory 504 may include code and data 506 that is accessed by the processor 502 using a bus 512. The memory 504 may further include an operating system 508 and application programs 510, which include at least one program that enables the processor 502 to perform the methods described herein. For example, the application programs 510 may include applications 1-N, which further include a video coding application that performs the methods described herein.

[0200] The apparatus 500 may also include one or more output devices, such as a display 518. The display 518, in one example, may be a touch-sensitive display that combines a display with a touch-sensitive element operable to sense touch input. The display 518 may be coupled to the processor 502 via the bus 512.

[0201] Although shown here as a single bus, bus 512 of device 500 may be comprised of multiple buses. Additionally, secondary storage 514 may be directly coupled to other components of device 500 or may be accessible over a network, and may include a single integrated unit such as a memory card or multiple units such as multiple memory cards. Thus, device 500 may be implemented in a wide variety of configurations.

[0202] In JVET-L1001, a draft text of VVC Draft3.0, MTS can be enabled at the sequence level for inter-slice and intra-slice individually. When MTS is off, DCT2 is assumed to be used as the transform core. However, in prior art such as JVET-M0303, JVET-M0140 or JVET-M0102, an inferred DST7 / DCT8 transform is introduced. There is no possibility to switch to a pure DCT2 transform in all cases. This disclosure addresses the above problems.

[0203] This disclosure introduces an additional DCT2 enable flag that is used to infer whether only the DCT2 transform core is used for all cases in the sequence when the DCT2 enable flag is false, and then the sequence level MTS enable flag is further signaled. If the DCT2 enable flag is true, it is assumed that only the DCT2 transform core is used.

[0204] Introducing an additional DCT2 enabled flag in the SPS allows switching to DCT2 when the inferred MST tool is on.

[0205] [7.3.2.1 Sequence Parameter Set RBSP Syntax]

[0206] [Table 4]

[0207] In JVET-L1001, a draft text of VVC Draft3.0, Multiple Transform Selection (MTS) can be enabled at the sequence level of inter-slice and intra-slice individually. When MTS is off, DCT2 is assumed to be used as the transform core. However, in prior art such as JVET-M0303, JVET-M0140 or JVET-M0102, inferred DST7 / DCT8 transform is introduced. In the case of MTS sequence level off, prior art uses DST7 / DCT8, and DCT2 is adaptively applied according to block shape, position or other features. However, DCT2 is desirable for both encoder and decoder design. In other words, switchability between DCT2, inferred DST7 or DCT8, and MTS (RDO selection transform core) is designed in this disclosure.

[0208] In this disclosure, a DCT2 enable flag is introduced into the high-level syntax to address the issues mentioned in Section 1.1. The additional DCT2 enable flag in the high-level syntax is used to infer whether only the DCT2 transform core is used for all cases in a sequence when the DCT2 enable flag is false, and then the sequence-level MTS enable flag is further signaled to infer whether MTS is enabled for the sequence. If the DCT2 enable flag is true, it is assumed that only the DCT2 transform core is used.

[0209] In the case where the sequence level DCT2 enable flag is disabled, the sequence level MTS flag is also signaled as in the prior art of VVC Draft 3.0 (JVET-L1001). Therefore, the inferred DST7DCT8 or adaptive transform core coding tool such as (JVET-M0303, JVET-M0140, or JVET-M0102) is used as in the prior art.

[0210] In cases where the sequence level DCT enable flag is enabled, it is assumed that only DCT2 is used. Therefore, inferred DST7DCT8 or adaptive transform core coding tools such as (JVET-M0303, JVET-M0140, or JVET-M0102) are either inferred using DCT2 instead of DST7 / DCT8 or are disabled.

[0211] [First embodiment of the present disclosure]

[0212] In the first embodiment, the sequence-level DCT2 enable flag is shown in sps as follows, and the highlighted part is designed according to the present disclosure: The encoder includes the indicator of the DCT2 enable flag in the bitstream, and the decoder parses the indicator of the DCT2 enable flag from the bitstream.

[0213] [7.3.2.1 Sequence Parameter Set RBSP Syntax]

[0214] [Table 5]

[0215] sps_dct2_enabled_flag equal to 1 specifies that only DCT2 transform cores are used for the transform unit. sps_mts_intra_enabled_flag equal to 0 specifies that other transform cores than DCT2 are available for the transform unit.

[0216] sps_mts_intra_enabled_flag equal to 1 specifies that tu_mts_flag may be present in the residual coding syntax of the intra coding unit. sps_mts_intra_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of the intra coding unit. If sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0217] sps_mts_inter_enabled_flag specifies that tu_mts_flag may be present in the residual coding syntax of an inter coding unit. sps_mts_inter_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of an inter coding unit. If sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0218] The DCT2 enabled flag is further used in the low level syntax, e.g. in the case of shape adaptive transform selection (JVET-M0303), where if the MTS flag is indicated as disabled at the sequence level, the inferred DST7 / DCT8 is used for the short edges of rectangular blocks and DST7 is used for square blocks. If sequence level MTS is enabled for a sequence, shape adaptivity is applied when the MTS flag is zero and the VTM uses DCT2 for both horizontal and vertical directions. In the case where the MTS flag is 1, this is followed by the VTM transform selection process. All three transforms used (DCT2, DST7, and DCT8) are the same as those defined in the current VTM.

[0219] In the proposed method, when the DCT2 enable flag is indicated as disabled, the adaptive core selection is kept the same as the prior art. When the DCT2 enable flag is indicated as enabled, only DCT2 can be used. The MTS function is inferred to be turned off. The shape adaptive transform selection can be inferred only using DCT2, which in this embodiment is equivalent to disabling the shape adaptive transform selection. The corresponding low-level syntax is as follows:

[0220] [8.4.4 Transformation process of scaled conversion coefficients]

[0221] [8.4.4.1 General]

[0222] The input to this process is a luma position (xTbY, yTbY) that specifies the top-left sample of the current luma transform block relative to the top-left luma sample of the current picture; A variable nTbW that specifies the width of the current transformation block, A variable nTbH that specifies the height of the current transformation block, A variable cIdx that specifies the color component of the current block, and a (nTbW)×(nTbH) array d[x][y] of scaled transform coefficients, where x=0..nTbW−1, y=0..nTbH−1.

[0223] The output of this process is a (nTbW) x (nTbH) array of residual samples r[x][y], where x=0..nTbW-1, y=0..nTbH-1.

[0224] The variable trTypeHor that specifies the horizontal transformation kernel and the variable trTypeVer that specifies the vertical transformation kernel are derived in Tables 8-11 according to mts_idx[xTbY][yTbY][cIdx]. The variables trAdaptHorEnabled and trAdaptVerEnabled are derived as follows. ‐if sps_dct2_enabled_flag && CuPredMode[xTbY][yTbY] == MODE_INTRA && !(cIdx>0 && IntraPredModeC[xTbY][yTbY]>66): trAdaptSizeMin=4 trAdaptSizeMax=cIdx == 0?16:8 trAdaptHorEnabled=nTbW>=trAdaptSizeMin && nTbW<=trAdaptSizeMax?1:0 trAdaptVerEnabled=nTbH>=trAdaptSizeMin && nTbH<=trAdaptSizeMax?1:0 - Otherwise: trAdaptHorEnabled=0 trAdaptVerEnabled=0

[0225] The variables trAdaptHor and trAdaptVer are derived as follows. -if sps_mts_intra_enabled_flag: trAdaptHor=trAdaptHorEnabled && nTbW <nTbH?1:0 trAdaptVer=trAdaptVerEnabled && nTbH <nTbW?1:0 - Otherwise: trAdaptHor=trAdaptHorEnabled && nTbW<=nTbH?1:0 trAdaptVer=trAdaptVerEnabled && nTbH<=nTbW?1:0

[0226] [Table 8-11 - trTypeHor and trTypeVer specifications according to mts_idx[x][y][cIdx]]

[0227] [Table 6]

[0228] [Second embodiment of the present disclosure]

[0229] In the second embodiment, the sequence-level DCT2 enable flag is shown in sps as follows, and the highlighted part is designed according to the present disclosure: The encoder includes the indicator of the DCT2 enable flag in the bitstream, and the decoder parses the indicator of the DCT2 enable flag from the bitstream.

[0230] [7.3.2.1 Sequence Parameter Set RBSP Syntax]

[0231] [Table 7]

[0232] sps_dct2_enabled_flag equal to 1 specifies that only DCT2 transform cores are used for the transform unit. sps_mts_intra_enabled_flag equal to 0 specifies that other transform cores outside of DCT2 are available for the transform unit.

[0233] sps_mts_intra_enabled_flag equal to 1 specifies that tu_mts_flag may be present in the residual coding syntax of the intra coding unit. sps_mts_intra_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of the intra coding unit. If sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0234] sps_mts_inter_enabled_flag specifies that tu_mts_flag may be present in the residual coding syntax of an inter coding unit. sps_mts_inter_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of an inter coding unit. If sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0235] The DCT2 valid flag is further used for low level syntax, for example in the case of sub-block transform (JVET-M0140), and the inferred DST7 / DCT8 is used depending on the position of the sub-transform block. More specifically, the horizontal and vertical transforms for each SBT position are specified in Figures 6 and 7. For example, the horizontal and vertical transforms for SBT-V position 0 are DCT-8 and DST-7, respectively. If one side of the residual TU is greater than 32, the corresponding transform is set to DCT-2. Thus, the sub-block transform jointly specifies the TU tiling, cbf, and horizontal and vertical transforms of the residual block, which can be considered as a syntax shortcut for the case where the main residual of the block is on one side of the block.

[0236] In the proposed method, when the DCT2 valid flag is indicated as invalid, the sub-block transform selection is kept the same as in the prior art.

[0237] If the DCT2 enable flag is indicated as enabled, only DCT2 may be used. The MTS feature is inferred to be off. The sub-block transform core may only be inferred using DCT2. The corresponding low-level syntax is attached.

[0238] [8.4.4 Transformation process of scaled conversion coefficients]

[0239] [8.4.4.1 General]

[0240] The input to this process is a luma position (xTbY, yTbY) that specifies the top-left sample of the current luma transform block relative to the top-left luma sample of the current picture; A variable nTbW that specifies the width of the current transformation block, A variable nTbH that specifies the height of the current transformation block, A variable cIdx that specifies the color component of the current block, and a (nTbW)×(nTbH) array d[x][y] of scaled transform coefficients, where x=0..nTbW−1, y=0..nTbH−1.

[0241] The output of this process is a (nTbW) x (nTbH) array of residual samples r[x][y], where x=0..nTbW-1, y=0..nTbH-1.

[0242] When cu_sbt_flag[xTbY][yTbY] is equal to 1, the variable trTypeHor specifying the horizontal transformation kernel and the variable trTypeVer specifying the vertical transformation kernel are derived in the table according to cu_sbt_horizontal_flag[xTbY][yTbY] and cu_sbt_pos_flag[xTbY][yTbY].

[0243] Otherwise (cu_sbt_flag[xTbY][yTbY] is equal to 0), the variable trTypeHor specifying the horizontal transformation kernel and the variable trTypeVer specifying the vertical transformation kernel are derived in Table 8-16 according to mts_idx[xTbY][yTbY][cIdx].

[0244] The variables nonZeroW and nonZeroH are derived as follows. nonZeroW=Min(nTbW,32) (8‐810) nonZeroH=Min(nTbH,32) (8‐811)

[0245] The (nTbW)×(nTbH) array r of residual samples is derived as follows: 1. Each (vertical) column of scaled transform coefficients d[x][y], where x=0..nonZeroW-1, y=0..nonZeroH-1, is transformed to e[x][y], where x=0..nonZeroW-1, y=0..nTbH-1, by invoking the 1-D transform process specified in Section 8.4.4.2 for each column x=0..nonZeroW-1 with the height nTbH of the transform block, the non-zero height nonZeroH of the scaled transform coefficients, the list d[x][y], where y=0..nonZeroH-1, and a transform type variable trType set equal to trTypeVer as input; the output is a list e[x][y], where y=0..nTbH-1. 2. The intermediate sample values ​​g[x][y], where x=0..nonZeroW-1, y=0..nTbH-1, are derived as follows: g[x][y]=Clip3(CoeffMin,CoeffMax,(e[x][y]+64)>>7) (8‐812) 3. Each (horizontal) row of the resulting array g[x][y], where x=0..nonZeroW-1, y=0..nTbH-1, is transformed to r[x][y], where x=0..nTbW-1, y=0..nTbH-1, by invoking the 1-dimensional transformation process specified in Section 8.4.4.2 for each row y=0..nTbH-1 with the width nTbW of the transformation block, the non-zero width nonZeroW of the resulting array g[x][y], the list g[x][y], where x=0..nonZeroW-1, and a transformation type variable trType set equal to trTypeHor as input; the output is a list r[x][y], where x=0..nTbW-1.

[0246] [Table 8-15 - trTypeHor and trTypeVer specifications according to cu_sbt_horizontal_flag[x][y] and cu_sbt_pos_flag[x][y]]

[0247] [Table 8]

[0248] [Table 8-16 - trTypeHor and trTypeVer specifications according to mts_idx[x][y][cIdx]]

[0249] [Table 9]

[0250] [Third embodiment of the present disclosure]

[0251] In the third embodiment, the sequence-level DCT2 enable flag is shown in sps as follows, and the highlighted part is designed according to the present disclosure: The encoder includes the indicator of the DCT2 enable flag in the bitstream, and the decoder parses the indicator of the DCT2 enable flag from the bitstream.

[0252] [7.3.2.1 Sequence Parameter Set RBSP Syntax]

[0253] [Table 10]

[0254] sps_dct2_enabled_flag equal to 1 specifies that only DCT2 transform cores are used for the transform unit. sps_mts_intra_enabled_flag equal to 0 specifies that other transform cores outside of DCT2 are available for the transform unit.

[0255] sps_mts_intra_enabled_flag equal to 1 specifies that tu_mts_flag may be present in the residual coding syntax of the intra coding unit. sps_mts_intra_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of the intra coding unit. If sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0256] sps_mts_inter_enabled_flag specifies that tu_mts_flag may be present in the residual coding syntax of an inter coding unit. sps_mts_inter_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of an inter coding unit. If sps_mts_intra_enabled_flag is not present, sps_mts_intra_enabled_flag is inferred to be 0.

[0257] The DCT2 valid flag is further used for low level syntax, for example in the case of sub-block transform (JVET-M0140), and the inferred DST7 / DCT8 is used depending on the position of the sub-transform block. More specifically, the horizontal and vertical transforms for each SBT position are specified in FIG. 6. For example, the horizontal and vertical transforms for SBT-V position 0 are DCT-8 and DST-7, respectively. If one side of the residual TU is greater than 32, the corresponding transform is set to DCT-2. Thus, the sub-block transform jointly specifies the TU tiling, cbf, and horizontal and vertical transforms of the residual block, which can be considered as a syntax shortcut for the case where the main residual of the block is on one side of the block.

[0258] In the proposed method, if the DCT2 enable flag is indicated as invalid, the sub-block transform selection is kept the same as in the prior art. If the DCT2 enable flag is indicated as valid, only DCT2 may be used. The MTS function is inferred to be off. The sub-block transform is inferred to be off since no possible inferred MTS transform core is available.

[0259] The corresponding syntax changes at the top of JVET-M0140 are as follows:

[0260] [7.3.2.1 Sequence Parameter Set RBSP Syntax]

[0261] [Table 11]

[0262] The embodiments of the present disclosure introduce a switchable DCT2 effective sequence level indicator that provides the possibility to switch to a pure DCT2 transform core using an inferred transform tool for the whole sequence or slice. DCT2 is a case where the computation is relatively simple and memory bandwidth is low compared to other transform cores. In the prior art, the possibility to use a simple DCT2 transform is blocked by the inferred transform core, and the current indicator provides the flexibility of switching between low cost / complexity and high performance for both the encoder and the decoder. In the embodiments, both low-level and high-level change possibilities are provided, which ensures the consistency and coding performance of the code with multiple variants.

[0263] In other words, the present disclosure provides: a method for video coding a block of an image, comprising the steps of obtaining a residual signal resulting from inter or intra image prediction for a sample from a plurality of samples of the block, inferring the use of a Discrete Cosine Transform type 2, DCT2, transform core for the sequence of residual signals, and processing a transform of the block using the inferred transform core.

[0264] That is, the present disclosure introduces an additional DCT2 enable flag that is used to infer whether only the DCT2 transform core is used for all cases in the sequence when the DCT2 enable flag is false, and then the sequence level MTS enable flag is further signaled. If the DCT2 enable flag is true, it is assumed that only the DCT2 transform core is used. Introducing the additional DCT2 enable flag in the SPS allows switching to DCT2 when the inferred MST tool is on.

[0265] This is further illustrated in Fig. 8, in which in step 1601 an image having a block is provided. In step 1602 a residual signal resulting from inter or intra image prediction for a sample from a plurality of samples of the block of the image is obtained. In step 1603 the use of a Discrete Cosine Transform type 2, DCT2, transform core for the sequence of residual signals is inferred, said residual signals being obtained in step 1602. In step 1604 the transform of the block is processed using the inferred transform core.

[0266] In the method according to the present disclosure, and as shown according to FIG. 8, the use of DCT2 can be inferred from a sequence-level DCT2 enable flag in the sequence parameter set, SPS.

[0267] In the method according to the present disclosure and as shown in accordance with FIG. 8, the sequence-level DCT2 enabled flag is represented as sps_dct2_enabled_flag.

[0268] The present disclosure further provides an encoder 20 as shown in FIG. 9. The encoder 20 as shown in FIG. 9 comprises an acquisition unit 22. The acquisition unit 22 may be configured to acquire a residual signal resulting from an inter or intra image prediction. FIG. 9 further shows that the encoder 20 also comprises an inference unit 24. The inference unit 24 may be configured to infer the use of a Discrete Cosine Transform Type 2, DCT2, transform core for a sequence of residual signals, where the residual signals may be acquired by the acquisition unit 22. The encoder 20 as shown in FIG. 9 further comprises a processing unit 26. The processing unit 26 may be configured to process a transformation of a block using an inferred transform core. The transform core may be inferred by the inference unit 24.

[0269] As shown in FIG. 9, in an encoder 20 according to the present disclosure, inference unit 24 may be configured to infer the use of DCT2 from a sequence-level DCT2 enable flag in a sequence parameter set, SPS.

[0270] As shown in accordance with FIG. 9, in the encoder 20 according to the present disclosure, the sequence-level DCT2 enabled flag may be represented as sps_dct2_enabled_flag.

[0271] The present disclosure further provides a decoder 30 shown in FIG. 10. The decoder 30 shown in FIG. 10 comprises an acquisition unit 32. The acquisition unit 32 may be configured to acquire a residual signal resulting from inter or intra image prediction. FIG. 10 further shows that the decoder 30 also comprises an inference unit 34. The inference unit 34 may be configured to infer the use of a Discrete Cosine Transform Type 2, DCT2, transform core for a sequence of residual signals, where the residual signals may be acquired by the acquisition unit 32. The decoder 30 shown in FIG. 10 further comprises a processing unit 36. The processing unit 36 ​​may be configured to process a transformation of the block using an inferred transform core. The transform core may be inferred by the inference unit 34.

[0272] As shown in FIG. 10, in a decoder 30 according to the present disclosure, an inference unit 34 may be configured to infer the use of DCT2 from a sequence-level DCT2 enable flag in a sequence parameter set, SPS.

[0273] As shown in accordance with FIG. 10, in a decoder 30 according to the present disclosure, the sequence-level DCT2 enabled flag may be represented as sps_dct2_enabled_flag.

[0274] [Mathematical operators]

[0275] The mathematical operators used in this application are similar to those used in the C programming language. However, the results of integer division and arithmetic shift operations are more precisely defined, and additional operations such as exponentiation and real-valued division are defined. Numbering and counting conventions generally start at 0, e.g., "first" corresponds to the 0th, "second" corresponds to the 1st, etc.

[0276] [Arithmetic operators]

[0277] The following arithmetic operators are defined as follows: [Table 12]

[0278] [Logical Operators]

[0279] The following logical operators are defined as follows: x&&y The Boolean logic "and" of x and y x||y The Boolean "or" of x and y ! Boolean logic "not" x?y:zIf x is true or not equal to 0, then evaluate the value of y, else evaluate the value of z.

[0280] [Relational Operator]

[0281] The following relational operators are defined as follows: > Greater than >= Greater than or equal to < Less than <= Less than or equal = = equal to != not equal to

[0282] When a relational operator is applied to a syntax element or variable that has been assigned the value "na" (not applicable), the value "na" is treated as the distinct value of that syntax element or variable. The value "na" is considered not equal to any other value.

[0283] [Bitwise Operators]

[0284] The following bitwise operators are defined as follows: & Bitwise "and". When operating on integer terms, the operation is performed on the two's complement representation of the integer value. When operating on a binary term that contains fewer bits than another term, the shorter term is extended by appending its more significant bits equal to zero. | Bitwise "or". When performing an operation on an integer term, the operation is performed on the two's complement representation of the integer value. When performing an operation on a binary term that contains fewer bits than another term, the shorter term is extended by adding higher-order bits equal to 0. ^ Bitwise "exclusive or". When performing an operation on an integer term, the operation is performed on the two's complement representation of the integer value. When performing an operation on a binary term that contains fewer bits than another term, the shorter term is extended by adding higher-order bits equal to 0. x>>y Arithmetic right shift of the two's complement integer representation of x by the number of bits in y. This function is defined only for non-negative integer values of y. The bit shifted into the most significant bit (MSB) as a result of the right shift has a value equal to the MSB of x before the shift operation. x<<y Arithmetic left shift of the two's complement integer representation of x by the number of bits in y. This function is defined only for non-negative integer values of y. The bit shifted into the least significant bit (LSB) as a result of the left shift has a value equal to 0.

[0285] [Assignment operator]

[0286] The following arithmetic operators are defined as follows. = Assignment operator ++ Increment, i.e., x++ is equivalent to x=x+1, and when used in an array index, evaluates the value of the variable before the increment operation. -- Decrement, i.e., x-- is equivalent to x=x-1, and when used in an array index, evaluates the value of the variable before the decrement operation. += Increment by the specified amount, i.e., x+=3 is equivalent to x=x+3. x+=(-3) is equivalent to x=x+(-3). -= Decrement by the specified amount, i.e., x-=3 is equivalent to x=x-3. x-=(-3) is equivalent to x=x-(-3).

[0287] [Range notation]

[0288] The following notation is used to specify ranges of values: x=y..zx takes integer values ​​starting from y up to z (inclusive), where x, y, and z are integers and z is greater than y.

[0289] [Mathematical Functions]

[0290] The following mathematical functions are defined:

number

number

number

number

number

number

number

number

[0291] [Order of precedence of operations]

[0292] If the order of precedence in an expression is not explicitly indicated through the use of parentheses, the following rules apply: -An operation with higher precedence is evaluated before any operation with lower precedence. -Operations of equal precedence are evaluated sequentially from left to right.

[0293] The following table specifies the precedence of operations from highest to lowest. A higher position in the table indicates a higher priority.

[0294] For operators that are also used in the C programming language, the order of precedence used herein is the same as that used in the C programming language.

[0295] Table: Operation precedence from highest (top of table) to lowest (bottom of table)

[0296] [Table 13]

[0297] [Textual explanation of logical operations]

[0298] In the text, logical statements are mathematically explained in the following form:

number

[0299] Each "If...Otherwise, if...Otherwise,..." statement in the text is introduced by a "...as follows" or "...the following applies" immediately followed by "If...". The last condition in an "If...Otherwise, if...Otherwise,..." is always "Otherwise,...". Interleaved "If...Otherwise, if...Otherwise,..." statements can be identified by matching "...as follows" or "...the following applies" that ends with "Otherwise,...".

[0300] In the text, logical statements are mathematically explained in the following form:

number

[0301] In the text, logical statements are mathematically explained in the following form:

number

[0302] Although the embodiments of the present disclosure have been described primarily based on video coding, it should be noted that the coding system 10, encoder 20, and decoder 30 (and correspondingly, system 10) embodiments described herein, as well as other embodiments, may also be configured for still image processing or coding, i.e., processing or coding of an individual image independent of any previous or subsequent images as in video coding. In general, when image processing coding is limited to a single image 17, only the inter prediction units 244 (encoder) and 344 (decoder) may not be available. All other functions (also referred to as tools or techniques) of the video encoder 20 and video decoder 30 may be equally used for still image processing, e.g., residual calculation 204 / 304, transform 206, quantization 208, inverse quantization 210 / 310, (inverse) transform 212 / 312, partitioning 262 / 362, intra prediction 254 / 354, and / or loop filtering 220, 320, as well as entropy coding 270 and entropy decoding 304.

[0303] The embodiments of, e.g., the encoder 20 and the decoder 30, and the functions described herein with reference to, e.g., the encoder 20 and the decoder 30, may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on a computer-readable medium or transmitted over a communication medium as one or more instructions or code and executed by a hardware-based processing unit. A computer-readable medium may include a computer-readable storage medium corresponding to a tangible medium, such as a data storage medium, or a communication medium including any medium that facilitates transfer of a computer program from one place to another, e.g., according to a communication protocol. Thus, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium, or (2) a communication medium, such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to obtain instructions, code, and / or data structures for implementation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.

[0304] By way of example, and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is referred to as a computer-readable medium, as appropriate. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but instead cover non-transitory tangible storage media. Disk and disc as used herein includes compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where a disk typically reproduces data magnetically and a disc typically reproduces data optically by a laser. Combinations of the above should also be included within the scope of computer readable media.

[0305] The instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor" as used herein may refer to any of the foregoing structures, or any other structure suitable for implementing the techniques described herein. In addition, in some aspects, the functionality described herein may be provided in dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into a combined codec. Also, the techniques may be implemented entirely in one or more circuit or logic elements.

[0306] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chipset). Although various components, modules, or units are described in this disclosure to highlight functional aspects of devices configured to perform the disclosed techniques, realization by different hardware units is not necessarily required. Rather, as described above, the various units may be combined into a codec hardware unit, or may be provided by a collection of interoperable hardware units including one or more processors, as described above, in conjunction with suitable software and / or firmware. [Other possible items] [Item 1] 1. A method for video coding a block of an image, comprising the steps of: obtaining a residual signal resulting from an inter or intra image prediction; inferring the use of a Discrete Cosine Transform type 2, DCT2, transform core for said sequence of residual signals; processing said transform of said block using said inferred transform core; A method comprising: [Item 2] The method according to item 1, in which the use of DCT2 is inferred from a sequence-level DCT2 enable flag in the sequence parameter set, SPS. [Item 3] The method described in item 2, wherein the sequence level DCT2 enabled flag is represented as sps_dct2_enabled_flag. [Item 4] The sequence level DCT2 enable flag is included in the SPS level syntax as follows: [Table 14] The method according to item 2 or 3, wherein sps_dct2_enabled_flag represents the sequence level DCT2 enabled flag. [Item 5] The sps_mts_intra_enabled_flag equal to 1 specifies that tu_mts_flag may be present in the residual coding syntax of an intra-coding unit; sps_mts_intra_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the above residual coding syntax for an intra-coding unit; The method described in item 4, wherein if the sps_mts_intra_enabled_flag is not present, the sps_mts_intra_enabled_flag is inferred to be 0. [Item 6] The method described in item 4 or 5, wherein the sps_mts_inter_enabled_flag specifies that tu_mts_flag may be present in the residual coding syntax of an inter-coding unit, and sps_mts_inter_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of an inter-coding unit, and if the sps_mts_intra_enabled_flag is not present, it is inferred that the sps_mts_intra_enabled_flag is 0. [Item 7] 7. The method according to any one of items 2 to 6, wherein the sequence level DCT2 valid flag equal to 1 specifies that a DCT2 transform core is used for the transform. [Item 8] 8. The method according to any one of items 2 to 7, wherein the sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transform. [Item 9] 9. The method according to any one of items 2 to 8, wherein the sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for both horizontal and vertical transforms. [Item 10] 10. The method according to any one of items 2 to 9, wherein the sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for the sub-block transform. [Item 11] Item 11. The method according to item 10, wherein if one side of the residual transform unit, tu, is greater than 32, the corresponding transform core is set to DCT2. [Item 12] 12. The method of any one of items 2 to 11, wherein if the sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transform, then both the sub-block transform and multiple transform selection, MTS, transform are inferred to be off. [Item 13] 11. The method according to any one of items 2 to 10, wherein the sequence level DCT2 valid flag equal to 0 specifies that a transform core other than DCT2 is used for the transform. [Item 14] Item 14. The method according to item 13, wherein the other transform core comprises a Discrete Sine Transform type 7, DST7 and / or a Discrete Cosine Transform type 8, DCT8. [Item 15] The sequence level DCT2 valid flag equal to 0 means 15. The method according to item 13 or 14, specifying that the transformation is inferred using at least one of DST7 or DCT8. [Item 16] 16. The method according to any one of items 13 to 15, wherein if the sequence level DCT2 enable flag is equal to 0, it is determined whether multiple transform selection for the sequence parameter set is enabled via a flag. [Item 17] If the sps_mts_intra_enabled_flag above exists, When the sps_mts_intra_enabled_flag is equal to 1, it is specified that a transform unit, TU, multiple transform selection, MTS flag represented as tu_mts_flag is present in the residual coding syntax of an intra coding unit; If the sps_mts_intra_enabled_flag is equal to 0, it is specified that the tu_mts_flag is not present in the residual coding syntax of the intra coding unit; 17. The method of claim 16, wherein if the sps_mts_intra_enabled_flag is not present, the sps_mts_intra_enabled_flag is inferred to be 0. [Item 18] 18. An encoder (20) comprising processing circuitry for carrying out the method according to any one of items 1 to 17. [Item 19] 18. A decoder (30) comprising processing circuitry for carrying out the method according to any one of items 1 to 17. [Item 20] an obtaining unit configured to obtain a residual signal resulting from an inter or intra image prediction; an inference unit configured to infer the use of a Discrete Cosine Transform type 2, DCT2, transform core on said sequence of residual signals; a processing unit configured to process the transformation of the block using the inferred transform core; A decoder (20) comprising: [Item 21] 21. The decoder of claim 20, wherein the inference unit is configured to infer the use of DCT2 from a sequence level DCT2 enable flag in the sequence parameter set, SPS. [Item 22] 22. The decoder according to item 21, wherein the sequence level DCT2 enabled flag is represented as sps_dct2_enabled_flag. [Item 23] The sequence level DCT2 enable flag is included in the SPS level syntax as follows: [Table 15] 23. The decoder according to item 21 or 22, wherein sps_dct2_enabled_flag represents the sequence level DCT2 enable flag. [Item 24] A decoder as described in item 21, wherein the sps_mts_intra_enabled_flag equal to 1 specifies that tu_mts_flag may be present in the residual coding syntax of an intra-coding unit, and the sps_mts_intra_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of an intra-coding unit, and when the sps_mts_intra_enabled_flag is not present, the sps_mts_intra_enabled_flag is inferred to be 0. [Item 25] The sps_mts_inter_enabled_flag specifies that the tu_mts_flag may be present in the residual coding syntax of an inter coding unit; sps_mts_inter_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the above residual coding syntax for an inter coding unit; 23. A decoder according to item 21 or 22, wherein if the sps_mts_intra_enabled_flag is not present, the sps_mts_intra_enabled_flag is inferred to be 0. [Item 26] 26. The decoder of any one of claims 21 to 25, wherein the sequence level DCT2 enable flag equal to 1 specifies that a DCT2 transform core is used for the transform. [Item 27] 27. The decoder of any one of claims 21 to 26, wherein the sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transform. [Item 28] 28. The decoder of any one of items 21 to 27, wherein the sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for both horizontal and vertical transforms. [Item 29] 29. The decoder of any one of items 21 to 28, wherein the sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for sub-block transform. [Item 30] 30. The decoder of claim 29, wherein if one side of the residual transform unit, tu, is greater than 32, the corresponding transform is set to DCT2. [Item 31] 31. The decoder of any one of claims 21 to 30, wherein if the sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transform, then both the sub-block transform and multiple transform selection, MTS, transform are inferred to be off. [Item 32] 30. The decoder of any one of claims 21 to 29, wherein the sequence level DCT2 valid flag equal to 0 specifies that a transform core other than DCT2 is used for the transform. [Item 33] 33. The decoder according to item 32, wherein the inference unit is configured to infer using a discrete sine transform type 7, DST7, and / or a discrete cosine transform type 8, DCT8, for the transform. [Item 34] The sequence level DCT2 valid flag equal to 0 means 34. The decoder of claim 32 or 33, specifying that it is inferred using only DST7 / DCT8 for transformation. [Item 35] 35. The decoder of any one of items 32 to 34, wherein if the sequence level DCT2 enable flag is equal to 0, it is determined whether multiple transform selection for the sequence parameter set is enabled via a flag. [Item 36] If the sps_mts_intra_enabled_flag above exists, When the sps_mts_intra_enabled_flag is equal to 1, it is specified that a transform unit, TU, multiple transform selection, MTS flag represented as tu_mts_flag is present in the residual coding syntax of an intra coding unit; If the sps_mts_intra_enabled_flag is equal to 0, it is specified that the tu_mts_flag is not present in the residual coding syntax of the intra coding unit; Item 36. The decoder of item 35, wherein if the sps_mts_intra_enabled_flag is not present, the sps_mts_intra_enabled_flag is inferred to be 0. [Item 37] an obtaining unit configured to obtain a residual signal resulting from an inter or intra image prediction; an inference unit configured to infer the use of a Discrete Cosine Transform type 2, DCT2, transform core on said sequence of residual signals; a processing unit configured to process the transformation of the block using the inferred transform core; An encoder (20). [Item 38] Item 38. The encoder of item 37, wherein the inference unit is configured to infer the use of DCT2 from a sequence level DCT2 enable flag in the sequence parameter set, SPS. [Item 39] Item 39. An encoder as described in Item 38, wherein the sequence level DCT2 enabled flag is represented as sps_dct2_enabled_flag. [Item 40] The sequence level DCT2 enable flag is included in the SPS level syntax as follows: [Table 16] 40. An encoder according to item 38 or 39, wherein sps_dct2_enabled_flag represents the sequence level DCT2 enable flag. [Item 41] An encoder as described in item 38, wherein the sps_mts_intra_enabled_flag equal to 1 specifies that tu_mts_flag may be present in the residual coding syntax of an intra-coding unit, and the sps_mts_intra_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of an intra-coding unit, and when the sps_mts_intra_enabled_flag is not present, the sps_mts_intra_enabled_flag is inferred to be 0. [Item 42] An encoder as described in item 38 or 39, wherein the sps_mts_inter_enabled_flag specifies that tu_mts_flag may be present in the residual coding syntax of an inter-coding unit, and sps_mts_inter_enabled_flag equal to 0 specifies that tu_mts_flag is not present in the residual coding syntax of an inter-coding unit, and if the sps_mts_intra_enabled_flag is not present, the sps_mts_intra_enabled_flag is inferred to be 0. [Item 43] 43. The encoder of any one of claims 38 to 42, wherein the sequence level DCT2 enable flag equal to 1 specifies that a DCT2 transform core is used for the transform. [Item 44] 44. The encoder of any one of claims 38 to 43, wherein the sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transform. [Item 45] 45. The encoder of any one of items 38 to 44, wherein the sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used in both horizontal and vertical directions in shape adaptive transform selection. [Item 46] Item 46. The encoder of any one of items 38 to 45, wherein the sequence level DCT2 enable flag equal to 1 specifies that DCT2 is used for sub-block transform. [Item 47] Item 47. The encoder of item 46, wherein if one side of the residual transform unit, tu, is greater than 32, the corresponding transform is set to DCT2. [Item 48] 48. An encoder according to any one of claims 38 to 47, wherein if the sequence level DCT2 enable flag equal to 1 specifies that the DCT2 transform core is used only for transform, then both the sub-block transform and the multiple transform selection, MTS, transform are inferred to be off. [Item 49] 47. The encoder of any one of claims 38 to 46, wherein the sequence level DCT2 enable flag equal to 0 specifies that a transform core other than DCT2 is used for the transform. [Item 50] 50. The encoder of claim 49, wherein the inference unit is configured to infer using a discrete sine transform type 7, DST7, and / or a discrete cosine transform type 8, DCT8, for the transform. [Item 51] The sequence level DCT2 valid flag equal to 0 means 51. The encoder of claim 49 or 50, which specifies that it is inferred using DST7 / DCT8 only for transformation. [Item 52] 52. The encoder of any one of items 49 to 51, wherein if the sequence level DCT2 enable flag is equal to 0, it is determined whether multiple transform selection for the sequence parameter set is enabled via a flag. [Item 53] If the sps_mts_intra_enabled_flag above exists, When the sps_mts_intra_enabled_flag is equal to 1, it is specified that a transform unit, TU, multiple transform selection, MTS flag represented as tu_mts_flag is present in the residual coding syntax of an intra coding unit; If the sps_mts_intra_enabled_flag is equal to 0, it is specified that the tu_mts_flag is not present in the residual coding syntax of the intra coding unit; Item 53. The encoder of item 52, wherein if the sps_mts_intra_enabled_flag is not present, the sps_mts_intra_enabled_flag is inferred to be 0. [Item 54] 18. A computer program product comprising a program code for performing the method according to any one of items 1 to 17. [Item 55] A decoder comprising: one or more processors; a non-transitory computer-readable storage medium coupled to said one or more processors and storing programming for execution by said one or more processors, said programming, when executed by said one or more processors, configuring said decoder to perform the method according to any one of items 1 to 17; A decoder comprising: [Item 56] 1. An encoder comprising: one or more processors; a non-transitory computer-readable storage medium coupled to the one or more processors and storing programming for execution by the one or more processors, the programming, when executed by the one or more processors, configuring the encoder to perform the method of any one of items 1 to 17; An encoder comprising: [Item 57] 18. A computer-readable non-transitory medium storing a program comprising instructions which, when executed on a processor, cause said processor to perform the method according to any one of items 1 to 17.

Claims

1. receiving a bitstream, the bitstream having a sequence parameter set (SPS), the SPS including a flag indicating whether a discrete cosine transform type 2 (DCT2) transform core is used for a current block; obtaining a residual signal of the current block; determining whether the DCT2 transform core is to be used for the current block based on the flag; in response to determining that the DCT2 transform core is to be used for the current block, performing an inverse transform on the residual signal of the current block using the DCT2 transform core to obtain a reconstructed residual block; obtaining a reconstructed block based on the reconstructed residual block; Equipped with The flag is represented as sps_dct2_enabled_flag, The SPS further includes sps_mts_intra_enabled_flag and sps_mts_inter_enabled_flag, The SPS has the following structure: 【Table 14】 method.

2. The method of claim 1 , wherein the flag equal to a first value specifies that a DCT2 transform core is used for the inverse transform.

3. The method of claim 1 , wherein the flag equal to a second value specifies that a transform core other than DCT2 is used for the inverse transform.

4. The method of claim 3 , wherein the other transform core comprises a Discrete Sine Transform type 7 (DST7) or a Discrete Cosine Transform type 8 (DCT8).

5. Obtaining the current block; obtaining a residual block corresponding to the current block; determining a transform core for the residual block, the transform core being a Discrete Cosine Transform type 2 (DCT2) transform core or a transform core other than DCT2; performing a transform on the residual block by using the determined transform core to obtain transform coefficients of the current block; generating a bitstream having a sequence parameter set (SPS) and encoded image data obtained based on the transform coefficients, the SPS including a flag indicating whether the DCT2 transform core or the other transform core is used for the current block; Equipped with The flag is represented as sps_dct2_enabled_flag, The SPS further includes sps_mts_intra_enabled_flag and sps_mts_inter_enabled_flag, The SPS has the following structure: 【Table 15】 Video encoding method.

6. 6. The video encoding method of claim 5, wherein the flag equal to a first value specifies that a DCT2 transform core is used for transformation.

7. 6. The video encoding method of claim 5, wherein the flag equal to a second value specifies that a transform core other than DCT2 is used for the transform.

8. 8. The video encoding method of claim 7, wherein the other transform core comprises a Discrete Sine Transform type 7 (DST7) or a Discrete Cosine Transform type 8 (DCT8).

9. 1. A method for storing a bitstream for a video signal, comprising the steps of: receiving a bitstream having a sequence parameter set (SPS) and encoded image data, the encoded image data being obtained based on transform coefficients of a current block, the transform coefficients being obtained by performing a transform on a residual signal of the current block by using a transform core, the transform core being a discrete cosine transform type 2 (DCT2) transform core or another transform core other than DCT2, the SPS including a flag indicating whether the DCT2 transform core or the other transform core is used for the current block, if the DCT2 transform core is used for the current block, the flag is used to determine whether the DCT2 transform core is used for the current block based on the flag, an inverse transform is performed on the residual signal of the current block using the DCT2 transform core to obtain a reconstructed residual block, and a reconstructed block is obtained based on the reconstructed residual block; storing the received bitstream in a storage medium; Preparation, The flag is represented as sps_dct2_enabled_flag, The SPS further includes sps_mts_intra_enabled_flag and sps_mts_inter_enabled_flag, The SPS has the following structure: 【Table 16】 method.

10. 10. The method of claim 9, wherein the flag equal to a first value specifies that a DCT2 transform core is used for the inverse transform.

11. 10. The method of claim 9, wherein the flag equal to a second value specifies that a transform core other than DCT2 is used for the inverse transform.

12. A decoder comprising: one or more processors; a non-transitory computer-readable storage medium coupled to the one or more processors and storing programming for execution by the one or more processors, the programming, when executed by the one or more processors, configuring the decoder to perform the method of any one of claims 1 to 4; A decoder comprising:

13. 1. An encoder comprising: one or more processors; a non-transitory computer readable storage medium coupled to the one or more processors and storing programming for execution by the one or more processors, the programming, when executed by the one or more processors, configuring the encoder to perform the method of any one of claims 5 to 8; An encoder comprising:

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