MEMORY CONTROL DEVICE AND METHOD

Abstract

To reduce operations to read / write data from / to a memory by a method other than DMA when data is transferred by DMA.SOLUTION: A transfer device (230) receives a tag number from a first firmware (112); reads out, from a transmission descriptor table corresponding to the tag number, a plurality of transmission descriptors included in the transmission descriptor table in an order designated by the transmission descriptor table; and successively transfers a plurality of data to be transferred according to descriptions in the plurality of transmission descriptors successively read out.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a memory control device and a control method. [Background technology]

[0002] When data is transferred between central processing units (CPUs) or between a CPU unit and a device unit, the data may be transferred by a direct memory access (DMA) method. For example, the following Patent Document 1 discloses a DMA circuit that checks whether a descriptor is correct when reading it, and determines whether DMA transfer of memory data is possible.

[0003] When transferring data using DMA, it is necessary to prepare a descriptor that describes the data to be transferred and the amount to be transferred in the memory of the sending and / or receiving unit, and have the DMAC (DMA Controller) read this descriptor. One such descriptor is required each time the DMAC transfers a chunk of data (for example, one packet). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2006-178795 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, when multiple transfer target data are collectively transferred as a packet, there is a risk that memory copy associated with packet creation may occur frequently in a control unit (e.g., CPU, MPU, etc.) that controls the transmitting unit. Also, there is a risk that memory copy associated with packet decompression may occur frequently in a control unit that controls the receiving unit.

[0006] Fig. 6 is a diagram showing a typical process of packetizing data in a conventional data transfer method using a DMA system. The memory in the diagram is the memory of the unit that transmits the data (i.e., the transmitting unit).

[0007] When multiple data A to E exist at non-consecutive addresses in memory, the control unit of the transmitting unit first rearranges the data A to E in the order in which they are to be tagged. For example, as shown in FIG. 6, the control unit copies the data A to E to any area in memory so that the data A to E are stored at consecutive addresses (STEP: 1). Next, the CPU generates tag X from the rearranged and stored data A to E, and copies tag X to any area in memory (STEP: 2). For example, if there is another tag Y that is to be packetized together, tag X is copied to an address consecutive to tag Y. Finally, the tags stored at consecutive addresses (tags X and Y in the example of FIG. 6) are combined to generate a packet (STEP: 3).

[0008] In this way, when the storage addresses of the data to be transferred are not consecutive, in order to tag and / or packetize the data, the data must be organized and copied back to memory so that they are stored in consecutive addresses in memory. This causes frequent memory copies in the CPU of the sending unit, which results in a problem of a processing load being placed on the CPU of the sending unit.

[0009] Furthermore, the CPU or MPU of the receiving unit that receives the packet or tag must decompress the packet and / or tag and copy the data contained therein to an appropriate area in memory. Specifically, the control unit of the receiving unit must copy each piece of data to an area in memory that is usable by the application of the receiving unit.

[0010] One aspect of the present invention has been made in view of the above-described problems, and has an object to reduce memory reads and writes by methods other than the DMA method when data transfer is performed by the DMA method. [Means for solving the problem]

[0011] In order to solve the above problems, a memory control device according to one embodiment of the present invention is a memory control device that accesses a transmitting side memory and a receiving side memory using a DMA (Direct Memory Access) method and transfers multiple pieces of transfer target data from the transmitting side memory to the receiving side memory, wherein the transmitting side memory stores at least the multiple pieces of transfer target data and a transmit descriptor table including multiple transmit descriptors, and the memory control device is equipped with an identifier receiving unit that receives an identifier specifying the transmit descriptor table from a transmitting side control unit, a transmit descriptor reading unit that reads multiple transmit descriptors included in the transmit descriptor table from the transmit descriptor table specified by the identifier in an order specified by the transmit descriptor table, and a data reading unit that sequentially reads the multiple pieces of transfer target data from the transmitting side memory in accordance with the descriptions of the multiple transmit descriptors that are sequentially read from the transmitting side memory.

[0012] In order to solve the above problems, a control method of a memory control device according to one embodiment of the present invention is a control method of a memory control device that accesses a transmitting side memory and a receiving side memory using a DMA (Direct Memory Access) method to transfer multiple pieces of transfer target data from the transmitting side memory to the receiving side memory, wherein the transmitting side memory stores at least the multiple pieces of transfer target data and a transmit descriptor table including multiple transmit descriptors, and includes an identifier receiving step of receiving an identifier designating the transmit descriptor table from a transmitting side control unit, a transmit descriptor reading step of reading multiple transmit descriptors contained in the transmit descriptor table from the transmit descriptor table designated by the identifier in an order specified by the transmit descriptor table, and a data reading step of sequentially reading the multiple pieces of transfer target data from the transmitting side memory in accordance with the descriptions of the multiple transmit descriptors that are sequentially read from the transmitting side memory.

[0013] According to the above configuration, the memory control device reads out the transmission descriptors in the order specified by the transmission descriptor table. The memory control device can then sequentially read out the data to be transferred from the transmission-side memory according to the descriptions in those transmission descriptors. Therefore, the memory control device can read out multiple pieces of data to be transferred simply by receiving an identifier from the transmission-side control unit. In other words, the transmission-side control unit does not need to access the transmission-side memory after initially transmitting an identifier to the memory control device. Therefore, according to the above configuration, the frequency with which the transmission-side control unit accesses the transmission-side memory can be reduced.

[0014] Furthermore, the memory control device can read out the transfer target data separately, even if the transfer target data are stored in non-consecutive addresses in the transmission side memory, for example. Therefore, the transmission side control unit does not need to consolidate the transfer target data into one packet or the like in advance. In other words, the transmission side control unit does not need to access the transmission side memory and copy data to generate a packet and / or a tag. Therefore, according to the above configuration, the frequency with which the transmission side control unit accesses the transmission side memory can be reduced, compared to the case in which the transfer target data are consolidated into packets and / or tags and transferred.

[0015] In order to solve the above problems, a memory control device according to one embodiment of the present invention is a memory control device that accesses a transmitting memory and a receiving memory using a DMA (Direct Memory Access) method and transfers multiple transfer target data from the transmitting memory to the receiving memory, wherein at least a receiving descriptor table including multiple receiving descriptors is stored in the receiving memory, and the memory control device is equipped with an identifier receiving unit that receives an identifier designating the receiving descriptor table from a transmitting side control unit, a receiving descriptor reading unit that reads multiple receiving descriptors included in the receiving descriptor table from the receiving descriptor table corresponding to the identifier determined by the transmitting side control unit in an order specified by the receiving descriptor table, and a data writing unit that sequentially writes the multiple transfer target data read from the transmitting side memory to the receiving side memory in accordance with the descriptions of the multiple receiving descriptors that are sequentially read from the receiving side memory.

[0016] In order to solve the above problems, a control method of a memory control device according to one embodiment of the present invention is a control method for a memory control device that accesses a transmitting side memory and a receiving side memory using a DMA (Direct Memory Access) method to transfer multiple transfer target data from the transmitting side memory to the receiving side memory, wherein at least a receiving side memory table including multiple receiving descriptors is stored in the receiving side memory, and includes an identifier receiving step of receiving an identifier designating the receiving side descriptor table from a transmitting side control unit, a receiving descriptor reading step of reading multiple receiving descriptors contained in the receiving side descriptor table from the receiving side control unit corresponding to the identifier determined by the transmitting side control unit in an order specified by the receiving side descriptor table, and a data writing step of sequentially writing the multiple transfer target data read from the transmitting side memory to the receiving side memory in accordance with the descriptions of the multiple receiving descriptors sequentially read from the receiving side memory.

[0017] According to the above configuration, the memory control device reads the receive descriptors in the order specified by the receive descriptor table. The memory control device can then write the data to be transferred to the receive memory in sequence according to the descriptions in the receive descriptors. This allows the receive control unit to write the data to be transferred without accessing the receive memory. Therefore, according to the above configuration, the frequency with which the receive control unit accesses the receive memory can be reduced.

[0018] Also, the memory control device writes the multiple data to be transferred separately. Therefore, for example, specifically, the receiving side control unit does not need to decompress the packet and / or tag that bundles the multiple data to be transferred and recopy each data to an appropriate area. Therefore, according to the above configuration, the frequency with which the receiving side control unit accesses the receiving side memory can be reduced compared to the case where the multiple data to be transferred are bundled and transferred in packets and / or tags, etc.

[0019] The receiving side memory may store at least a receiving descriptor table including a plurality of receiving descriptors, and the identifier may be an identifier specifying the transmitting descriptor table and the receiving descriptor table corresponding to the transmitting descriptor table. The memory control device may include a receiving descriptor reading unit that reads out the plurality of receiving descriptors included in the receiving descriptor table specified by the identifier in an order specified by the receiving descriptor table, and a data writing unit that sequentially writes the plurality of transfer target data read from the transmitting side memory to the receiving side memory in accordance with descriptions of the plurality of receiving descriptors sequentially read from the receiving side memory.

[0020] According to the above configuration, the memory control device receives an identifier specifying a transmission descriptor table and a reception descriptor table from the transmission side control unit. This allows the memory control device to read a reception descriptor paired with a transmission descriptor from the reception descriptor table specified by the identifier in the order specified by the reception descriptor table. Then, the memory control device can write the data to be transferred sequentially to the reception side memory according to the descriptions of those reception descriptors. This allows the reception side control unit to write the data to be transferred without accessing the reception side memory. Therefore, according to the above configuration, it is possible to reduce both the frequency with which the transmission side control unit accesses the transmission side memory and the frequency with which the reception side control unit accesses the reception side memory.

[0021] Also, the memory control device reads out the multiple data to be transferred from the transmitting memory separately and writes them separately. Therefore, the transmitting control unit does not need to access the transmitting memory to generate packets and / or tags, and the receiving control unit does not need to decompress the packets and / or tags that consolidate the multiple data to be transferred and recopy each data to an appropriate area. Therefore, according to the above configuration, it is possible to reduce both the frequency with which the transmitting control unit accesses the transmitting memory and the frequency with which the receiving control unit accesses the receiving memory, compared to the case in which multiple data to be transferred are consolidated into packets and / or tags and transferred.

[0022] In the memory control device, the transmitting memory may be provided in a first device, and the receiving memory may be provided in a second device that is different from the first device and communicates with the first device using a DMA method.

[0023] According to the above configuration, in data transfer between a sending memory and a receiving memory mounted on different devices, it is possible to reduce the frequency of access to the memory by a method other than the DMA method.

[0024] In the memory control device, the sending memory and the receiving memory may be the same. According to the configuration, in data transfer within a certain memory, it is possible to reduce the frequency of access to the memory by a method other than the DMA method. Effect of the Invention

[0025] According to one aspect of the present invention, when data transfer is performed by the DMA method, it is possible to reduce the frequency of access to memory by methods other than the DMA method. [Brief description of the drawings]

[0026] [Figure 1] 1 is a block diagram showing an example of a configuration of a main part of a data transfer system according to a first embodiment. [Diagram 2] 1A and 1B are diagrams illustrating data structures of a tag table and a descriptor table. [Diagram 3] FIG. 2 illustrates the data structures of a transmit descriptor and a receive descriptor. [Figure 4] 4 is a sequence diagram showing a process flow of downstream data transfer in the data transfer system. FIG. [Diagram 5] FIG. 11 is a block diagram showing an example of a configuration of a main part of a data transfer system according to a second embodiment. [Figure 6] FIG. 1 is a diagram illustrating a process for packetizing data in a conventional data transfer method using a DMA (Direct Memory Access) system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] [Embodiment 1] § 1. Examples of Application In this embodiment, as an example, a data transfer system capable of bidirectional data transfer between a first processing device 110 included in a first unit (first device, second device) 100 and a second processing device 210 included in a second unit (first device, second device) 200 will be described.

[0028] In the following description, data transfer from the first processor 110 to the second processor 210 may be referred to as "downstream transfer." Data transfer from the second processor 210 to the first processor 110 may be referred to as "upstream transfer."

[0029] 1 is a block diagram showing an example of a main configuration of a data transfer system 500 according to this embodiment. The data transfer system 500 includes a first unit 100 and a second unit 200. The first unit 100 includes a first processing device 110 and a first memory 120, and the second unit 200 includes a second processing device 210, a second memory 220, and a transfer device 230.

[0030] (1st unit 100) The first unit 100 is, for example, a unit that controls industrial equipment. The first unit 100 can be realized by a PLC (Programmable Logic Controller) or the like. The first processing device 110 is a processor in the first unit 100. The first processing device 110 may be, for example, a CPU (Central Processing Unit). The first memory 120 is a volatile storage device in the first unit 100. The first memory 120 may be, for example, a DRAM (Dynamic Random Access Memory).

[0031] (2nd unit 200) The second unit 200 is, for example, a unit for complementing or expanding the function of the first unit 100. More specifically, the second unit 200 may be a unit that performs functions such as a data statistical function, a router function, or a database function.

[0032] The second processing device 210 is a processor of the second unit 200. The second processing device 210 may be, for example, a Micro Processing Unit (MPU). The second memory 220 is a volatile storage device in the second unit 200. The second memory 220 may be, for example, a DRAM.

[0033] The transfer device 230 is a device for realizing data transfer by the DMA method between the first processing device 110 and the second processing device 210. The transfer device 230 can be realized, for example, by an FPGA (Field-Programmable gate array). Note that, in this embodiment, the transfer device 230 is provided in the second unit 200, but in the data transfer system 500, the transfer device 230 may be provided in the first unit 100.

[0034] In either case, the first processing device 110 and the transfer device 230, and the second processing device 210 and the transfer device 230 are each connected by a bus conforming to the PCIe (Peripheral Component Interconnect Express) standard. This allows the first processing device 110 and the second processing device 210 to communicate with each other via the transfer device 230 using PCIe.

[0035] (Transfer of data) Although details will be described later, in the data transfer system 500, the transmitting unit transmits a certain identifier to the receiving unit. The identifier is information for specifying the transmitting descriptor table to be used in the transmitting unit, and is also information for specifying the receiving descriptor table to be used in the receiving unit.

[0036] The transmit descriptor table contains multiple transmit descriptors. The receive descriptor table contains multiple receive descriptors. Therefore, the above identifier can be said to specify the transmit and receive descriptor groups to be used when transferring multiple pieces of transfer data.

[0037] The transfer device 230 reads a transmission descriptor from a transmission descriptor table in the transmission side memory. The transfer device 230 also reads a reception descriptor from a reception descriptor table in the reception side memory. The transfer device 230 then transfers the data to be transferred from the transmission side memory to the reception side memory according to the description of one set of the transmission descriptor and reception descriptor. The transfer device 230 repeats the reading of the transmission descriptor and reception descriptor and the transfer of the data to be transferred the number of times equal to the number of sets of the transmission descriptor and reception descriptor.

[0038] According to the process shown in Fig. 4, in the data transfer system 500, the transmitting unit only needs to determine an identifier and transmit the identifier to the transfer device 230. Therefore, even if there are multiple pieces of data to be transferred, there is no need to tag and / or packetize the data to be transferred. Furthermore, there is no need to rearrange data in memory in order to tag and / or packetize the data to be transferred. Therefore, according to the data transfer system 500, it is possible to reduce the frequency of memory access by the control unit of the transmitting unit.

[0039] Furthermore, in the data transfer system 500, the receiving unit receives the data to be transferred as is, not the packet or tag. Therefore, the process of writing the packet or tag to memory once and then decompressing it does not occur. In addition, there is no need to move the decompressed data to be transferred again to an appropriate area on the memory. Therefore, according to the data transfer system 500, the frequency of memory access by the control unit of the receiving unit can be reduced.

[0040] §2. Example configuration (1st unit 100) Next, a description will be given of the main configuration of the first unit 100 and the second unit 200 shown in Fig. 1. In the example of Fig. 1, the first unit 100 includes a first processing device 110 and a first memory 120. The first unit 100 may also include an input device, an output device, and a non-volatile storage device such as a ROM (Read Only Memory).

[0041] (First processing device 110) The first processing device 110 (transmission side control unit) is a processor that performs overall control of the first unit 100. The first processing device 110 is realized by, for example, a CPU. The first processing device 110 loads a control program for the first unit 100 stored in a non-volatile storage device (not shown) in a first memory 120. The first processing device 110 then interprets and executes the control program loaded in the first memory 120 to control each component. As a result, as shown in FIG. 1, the first processing device 110 according to this embodiment functions as a first control unit 111, a first firmware (FW) 112, and a first PCIe interface 113.

[0042] The first control unit 111 controls devices (for example, industrial devices) connected to the first unit 100. The first control unit 111 may also periodically communicate with the connected devices and acquire data to be processed in downstream processes from the various devices. For example, the data acquired by the first control unit 111 may be transferred to the second unit 200 and then processed by the second unit 200.

[0043] The first firmware 112 executes various processes related to data transfer between the first unit 100 and the second unit 200. For example, the first firmware 112 determines a tag number for downstream data transfer and notifies the transfer device 230. The tag number will be described later in detail. In addition, the first firmware 112 also performs a process of creating or downloading a tag table, a transmission descriptor table, and a reception descriptor table in advance, and a process of writing the created or downloaded tag table, transmission descriptor table, and reception descriptor table in the first memory 120, before starting data transfer between the first unit 100 and the second unit 200. That is, the first firmware 112 prepares a tag table, a transmission descriptor table, and a reception descriptor table in advance, and stores them in the first memory 120.

[0044] The first PCIe interface 113 is an interface for connecting the first processing device 110 to the transfer device 230 via a PCIe bus using PCIe.

[0045] (First memory 120) The first memory 120 is a volatile storage area (RAM; Random Access Memory). The first memory 120 stores transmission data generated by the first processing device 110, reception data generated by the second processing device 210 to be processed by the first processing device 110, and various programs to be executed by the first processing device 110. The first memory 120 may also be used as a working memory when the first processing device 110 executes various programs. Typically, a DRAM (Dynamic Random Access Memory) can be used as the first memory 120.

[0046] The first memory 120 stores a transmission tag table, a transmission descriptor table, a reception tag table, a reception descriptor table, and data to be transferred (data 1 to m in FIG. 1).

[0047] The transmission descriptor of the first memory 120 is a descriptor that defines a part of the operation for the DMAC 233 (described later) of the transfer device 230 to realize downstream transfer. This enables the first firmware 112 of the first processing device 110 to transmit data to the second firmware 212 of the second processing device 210.

[0048] The receive descriptor of the first memory 120 defines a part of the operation for the DMAC 233 to realize the upstream transfer. This enables the first firmware 112 of the first processing device 110 to receive data transmitted from the second firmware 212 of the second processing device 210.

[0049] (tag and descriptor tables) 2 is a diagram showing the data structures of a tag table and a descriptor table. Note that the basic data structure of a tag table is the same whether it is a transmission tag table or a reception tag table. Also, the basic data structure of a descriptor table is the same whether it is a transmission descriptor table or a reception descriptor table.

[0050] A "tag table" is a list of the first addresses of the storage locations in memory for each of multiple descriptor tables. The transmit tag table is a table used when transmitting data, and is a list of the first addresses of the transmit descriptor tables. The receive tag table is a table used when receiving data, and is a list of the first addresses of the receive descriptor tables.

[0051] For convenience, in Fig. 2, the descriptors specified by the first addresses of a certain descriptor table (descriptor table 1) in the tag table are shown in correspondence with the tag table. However, the tag table and the descriptor table corresponding to the tag table may be stored in non-consecutive addresses in memory. Also, the tag table in Fig. 2 specifies the first addresses of the descriptor tables, and may not include the descriptor tables themselves.

[0052] Also, the order of the top addresses of the descriptor tables in the tag table in Fig. 2 is not particularly limited. For example, in the example in the figure, the top addresses of the X number of descriptor tables are arranged in such a way that they are specified in reverse order from descriptor table X to descriptor table 1, but they may be arranged in such a way that they are specified in order from descriptor table 1 to descriptor table X.

[0053] A "descriptor table" is a data table that stores multiple descriptors in the order in which they are used for data transfer. In the example of FIG. 2, the descriptor table includes descriptor 1 to descriptor i. A transmit descriptor table is a data table that stores multiple transmit descriptors in the order in which they are used for data transfer. A receive descriptor table is a data table that stores multiple receive descriptors in the order in which they are used for data transfer. For example, if the descriptor in FIG. 2 is a transmit descriptor, the transmit descriptors are used in order starting from descriptor 1 when reading data from the transmitting memory. Also, for example, if the descriptor in FIG. 2 is a receive descriptor, the receive descriptors are used in order starting from descriptor 1 when writing data to the receiving memory.

[0054] (Transmit and Receive Descriptors) 3 is a diagram showing the data structures of a transmission descriptor and a reception descriptor. As shown in FIG. 2, the transmission descriptor includes the following (1) to (3).

[0055] (1) The address in memory where the data to be sent is stored (2) The size of the data to be sent (3) Other data Of these, the "other data" shown in (3) includes, for example, a transfer completion flag that is set when the transfer is completed successfully.

[0056] As shown in FIG. 2, the receive descriptor includes the following (4) and (5).

[0057] (4) The address where the data to be received is stored in memory (5) Other data Of these, the "other data" shown in (5) includes, for example, a transfer completion flag that is set when the transfer is completed successfully.

[0058] (2nd unit 200) In the example of FIG. 1, the second unit 200 includes a second processing device 210, a second memory 220, and a transfer device 230.

[0059] (Second processing device 210) The second processing device (transmission side control unit) 210 centrally controls the second unit 200. The second processing device 210 is realized by, for example, an MPU. The second processing device 210 loads a control program for the second unit 200 stored in a non-volatile storage device (not shown) in a second memory 220. The second processing device 210 then interprets and executes the control program loaded in the second memory 220 to control each component. As a result, as shown in FIG. 1, the second processing device 210 according to this embodiment functions as a second control unit 211, a second firmware 212, and a second PCIe interface 213.

[0060] The second control unit 211 executes processes related to various functions carried out by the second unit 200 itself. For example, the second control unit 211 may tally up data acquired from the first unit 100.

[0061] The second firmware 212 executes various processes related to the transfer of data between the second unit 200 and the first unit 100. For example, the second firmware 212 determines a tag number for the upstream data transfer and notifies the transfer device 230. In addition, the second firmware 212 also performs a process of creating or downloading a tag table, a transmission descriptor table, and a reception descriptor table in advance, and a process of writing the created or downloaded transmission descriptor table and reception descriptor table in the second memory 220, before starting the data transfer between the second unit 200 and the first unit 100. That is, the second firmware 212 prepares a tag table, a transmission descriptor table, and a reception descriptor table in advance, and stores them in the second memory 220.

[0062] The second PCIe interface 213 is an interface for connecting the second processing device 210 to the transfer device 230 via a PCIe bus using PCIe.

[0063] (Second memory 220) The second memory 220 is a volatile storage area (RAM). The second memory 220 stores transmission data generated by the second processing device 210, reception data generated by the first processing device 110 to be processed by the second processing device 210, and various programs to be executed by the second processing device 210. The second memory 220 may also be used as a working memory when the second processing device 210 executes various programs. As the second memory 220, a DRAM or the like can typically be used.

[0064] The second memory 220 stores a transmission tag table, a transmission descriptor table, a reception tag table, a reception descriptor table, and data to be transferred, similarly to the first memory 120. The data structures of the tag table and the descriptor table are similar to the data of the same name described in the first memory 120.

[0065] The transmission descriptor of the second memory 220 is a descriptor that defines a part of the operation for the DMAC 233 of the transfer device 230 to realize the upstream transfer. This enables the second firmware 212 of the second processing device 210 to transmit data to the first firmware 112 of the first processing device 110.

[0066] The receive descriptor of the second memory 220 defines a part of the operation for the DMAC 233 to realize the downstream transfer. This enables the second firmware 212 of the second memory 220 to receive data transmitted from the first firmware 112 of the first processing device 110.

[0067] (Transporter 230) The transfer device (memory control device) 230 is a device for communicating with the first processing device 110 and the second processing device 210 via PCIe. The transfer device 230 controls downstream transfer between the first processing device 110 and the second processing device 210, and upstream transfer as necessary.

[0068] The transfer device 230 includes at least a DMAC (Direct Memory Access Controller) 233, a downstream transmit descriptor controller (identifier receiver, transmit descriptor reader) 235, and a downstream receive descriptor controller (receive descriptor reader) 234 to realize downstream transfer.

[0069] The DMAC 233 (data reading unit, data writing unit) controls data transfer from the first memory 120 of the first processor 110 to the second memory 220 of the second processor 210. The DMAC 233 reads data to be transferred in sequence according to the description of the transmit descriptor. The DMAC 233 writes the read data to the second memory 220 according to the description of the receive descriptor.

[0070] The downstream transmit descriptor controller 235 receives from the first firmware 112 a tag number that specifies the transmit and receive descriptor tables to be used in the transfer of the data to be transferred.

[0071] Here, the "tag number" is an identifier that specifies a descriptor table in the tag table. Since the descriptor table contains descriptors, the "tag number" can be said to be an identifier that specifies a group of descriptors to be used in transferring the data to be transferred. In other words, the "tag number" in the transmitting unit is an identifier that specifies a group of transmit descriptors to be used when receiving data. The "tag number" in the receiving unit is an identifier that specifies a group of receive descriptors to be used when receiving data.

[0072] The format of the tag number is not particularly limited. For example, the tag number may be an identifier including at least one of a numerical value, a character string, a code, etc. In this embodiment, the tag number is a value that specifies a specific address in memory.

[0073] The downstream transmit descriptor controller 235 identifies a transmit descriptor table designated by the tag number from among the transmit descriptor tables stored in the first memory 120. The downstream transmit descriptor controller 235 refers to the identified transmit descriptor table and reads out the transmit descriptors in the order stored in the table (i.e., designated in the table). This transmit descriptor is the transmit descriptor related to the address in the first memory 120 where the data to be transferred (i.e., the data to be read from the first memory 120) is stored.

[0074] The downstream receive descriptor controller 234 identifies a receive descriptor table designated by the tag number from among the receive descriptor tables stored in the second memory 220. The downstream receive descriptor controller 234 refers to the identified receive descriptor table and reads out the receive descriptors in the order stored in the table (i.e., designated in the table). This receive descriptor is the receive descriptor related to the address in the second memory 220 where the data to be transferred (i.e., the data to be written to the second memory 220) should be stored.

[0075] The transfer device 230 may further include an upstream transmit descriptor controller (identifier receiver, transmit descriptor reader) 237 and an upstream receive descriptor controller (receive descriptor reader) 236 in order to realize upstream transfer.

[0076] When implementing an upstream transfer, the DMAC (data reading unit, data writing unit) 233 controls data transfer from the second memory 220 of the second processor 210 to the first memory 120 of the first processor 110. The DMAC 233 reads data to be transferred in sequence according to the description of the transmit descriptor. The DMAC 233 writes the read data to the first memory 120 according to the description of the receive descriptor.

[0077] The upstream transmit descriptor controller 237 receives from the second firmware 212 a tag number that specifies the transmit and receive descriptor tables to be used for transferring the data to be transferred.

[0078] The upstream transmission descriptor controller 237 identifies a transmission descriptor table designated by the tag number from among the transmission descriptor tables stored in the second memory 220. The upstream transmission descriptor controller 237 refers to the identified transmission descriptor table and reads out the transmission descriptors in the order stored in the table (i.e., designated in the table). This transmission descriptor is the transmission descriptor related to the address in the second memory 220 where the data to be transferred (i.e., the data to be read from the second memory 220) is stored.

[0079] The upstream receive descriptor controller 236 identifies a receive descriptor table specified by the tag number from among the receive descriptor tables stored in the first memory 120. The upstream receive descriptor controller 236 refers to the identified receive descriptor table and reads the receive descriptors in the order stored in the table (i.e., specified in the table). This receive descriptor is the receive descriptor related to the address in the first memory 120 where the data to be transferred (i.e., the data to be written to the first memory 120) should be stored.

[0080] The first PCIe interface 231 is an interface for connecting the transfer device 230 to the first processing device 110 via a PCIe bus using PCIe.

[0081] The second PCIe interface 232 is an interface for connecting the transfer device 230 to the second memory 220 via a PCIe bus using a PCIe.

[0082] § 3. Processing flow Fig. 4 is a sequence diagram showing the flow of downstream data transfer in the data transfer system 500. Note that, before the series of processes shown in Fig. 4, the first firmware 112 of the first processing device 110 prepares at least a transmission tag table and a transmission descriptor table in the first memory 120 as an initial process. Also, the second firmware 212 of the second processing device 210 prepares at least a reception tag table and a reception descriptor table in the second memory 220. Also, it is assumed that a plurality of transfer target data are stored in the first memory 120.

[0083] When preparation of the various tag tables and descriptor tables is completed, the first firmware 112 of the first processing device 110 transmits the tag number to the downstream transmission descriptor controller 235 of the transfer device 230. The downstream transmission descriptor controller 235 receives the tag number (S100, identifier receiving step) and outputs the tag number to the downstream reception descriptor controller 234 (S101). The downstream reception descriptor controller 234 accepts the input tag number (S201).

[0084] When the notification of the tag number in S101 to S201 is completed, the downstream transmit descriptor controller 235 identifies a transmit descriptor table (transmit DescT) corresponding to the tag number from the transmit tag table in the first memory 120 (S102). The downstream transmit descriptor controller 235 reads out from the first memory 120 the transmit descriptor (transmit Desc) stored in the first position (i.e., the beginning) of the identified transmit descriptor table (S103, transmit descriptor reading step).

[0085] On the other hand, after receiving the tag number (S201), the downstream receive descriptor controller 234 identifies (S202) a receive descriptor table (receive DescT) corresponding to the tag number from the receive tag table in the second memory 220. The downstream receive descriptor controller 234 reads out from the second memory 220 the receive descriptor (receive Desc) stored in the first position (i.e., the beginning) of the identified receive descriptor table (S203, receive descriptor reading step).

[0086] The DMAC 233 reads data (i.e., the first data) from the first memory 120 according to the information described in the transmit descriptor read by the downlink transmit descriptor controller 235 (S301, data read step). The DMAC 233 writes the read data to the second memory 220 according to the information described in the receive descriptor read by the downlink receive descriptor controller 234 (S302, data write step).

[0087] After the writing of the first data to the second memory 220 (S302) is completed, the downstream transmit descriptor controller 235 then reads the next transmit descriptor stored in the transmit descriptor table identified in S102 (i.e., the second transmit descriptor) (S104, transmit descriptor reading step). After the processing of S302 is completed, the downstream receive descriptor controller 234 also reads the next receive descriptor stored in the receive descriptor table identified in S202 (i.e., the second receive descriptor) (S204, receive descriptor reading step).

[0088] The DMAC 233 executes the same processes as S301 to S302 based on the second transmit descriptor and the second receive descriptor. That is, the DMAC 233 reads the second data according to the information described in the second transmit descriptor (S303, data read step), and writes the second data to the second memory 220 based on the second receive descriptor (S304, data write step).

[0089] Thereafter, the downstream transmit descriptor controller 235, downstream receive descriptor controller 234, and DMAC 233 repeat the same process until all the data to be transferred is transferred. That is, the downstream transmit descriptor controller 235 reads the next stored transmit descriptor (the m-th transmit descriptor) from the transmit descriptor table specified in S102 (S105, transmit descriptor reading step). The downstream receive descriptor controller 234 reads the next stored receive descriptor (i.e., the m-th receive descriptor) from the receive descriptor table specified in S202 (S205, receive descriptor reading step).

[0090] The DMAC 233 executes the same process as S301 to S302 based on the m-th transmit descriptor and the m-th receive descriptor. That is, the DMAC 233 reads the m-th data according to the information described in the m-th transmit descriptor (S305, data read step), and writes the m-th data to the second memory 220 based on the m-th receive descriptor (S306, data write step).

[0091] According to the process shown in Fig. 4, the transfer device 230 can reduce the frequency of access from the first processing device 110 to the first memory 120 in data transfer between the first memory 120 and the second memory 220 mounted on different devices. Also, according to the process shown in Fig. 4, the transfer device 230 can reduce the frequency of access from the second processing device 210 to the second memory 220 in data transfer between the first memory 120 and the second memory 220 mounted on different devices. In other words, the transfer device 230 can reduce the frequency of access to the memory by a method other than the DMA method.

[0092] According to the process shown in FIG. 4, the transfer device 230 reads out the transmission descriptors in the order specified by the transmission descriptor table. Then, the transfer device 230 can sequentially read out the data to be transferred from the first memory 120 according to the descriptions of those transmission descriptors. Therefore, the transfer device 230 can read out a plurality of data to be transferred simply by receiving the tag number from the first processing device 110. In other words, the first processing device 110 does not need to access the first memory 120 after first transmitting the tag number to the transfer device 230. Therefore, according to the process shown in FIG. 4, the frequency with which the first processing device 110 accesses the first memory 120 can be reduced.

[0093] Further, the transfer device 230 can read out the transfer target data separately, even if the transfer target data are stored in non-consecutive addresses in the first memory 120. Therefore, the first processing device 110 does not need to collect the transfer target data into one packet or the like in advance. That is, the first processing device 110 does not need to access the first memory 120 and copy the data to generate the packet and / or tag. Therefore, according to the process shown in FIG. 4, the frequency with which the first processing device 110 accesses the first memory 120 can be reduced compared to the case where the transfer target data is collected and transferred into a packet and / or a tag or the like.

[0094] According to the process shown in Fig. 4, the transfer device 230 reads the reception descriptors in the order specified by the reception descriptor table. Then, the transfer device 230 can sequentially write the data to be transferred to the second memory 220 according to the descriptions of those reception descriptors. This allows the second processing device 210 to write the data to be transferred without accessing the second memory 220. Therefore, according to the process shown in Fig. 4, the frequency with which the second processing device 210 accesses the second memory 220 can be reduced.

[0095] Moreover, the transfer device 230 writes a plurality of transfer target data separately. Therefore, for example, specifically, the second processing device 210 does not need to decompress the packet and / or tag that collects a plurality of transfer target data and recopy each transfer target data to an appropriate area. Therefore, according to the process shown in FIG. 4, the frequency with which the second processing device 210 accesses the second memory 220 can be reduced compared to the case where a plurality of transfer target data is collected and transferred in a packet and / or tag, etc.

[0096] The flow of the upstream data transfer in the data transfer system 500 is the same as that of the downstream data transfer, except for the subjects of various processes. Specifically, in the case of the upstream data transfer, the control device and memory on the transmitting side are changed to the second processing device 210 and the second memory 220, and the control device on the receiving side is changed to the first processing device 110 and the first memory 120. In addition, in the case of the upstream data transfer, the processes performed by the downstream transmission descriptor controller 235 and the downstream reception descriptor controller 234 may be respectively executed by the upstream transmission descriptor controller 237 and the upstream reception descriptor controller 236. In addition, the DMAC 233 may write the data read from the second memory 220 to the first memory 120.

[0097] [Embodiment 2] In the present invention, the sending memory and the receiving memory may be the same. That is, the data transfer system according to the present invention may be applied not only to data transfer between two independent devices, but also to data transfer within one memory of one device (i.e., reading and writing data within one memory).

[0098] The second embodiment of the present invention will be described below. For convenience of explanation, the same reference numerals are given to components having the same functions as those described in the previous embodiment, and the explanations thereof will not be repeated. In this embodiment, as an example, a case where data transfer is performed within the device of the third unit 300 will be described.

[0099] 5 is a block diagram showing an example of a main configuration of a data transfer system 600 according to this embodiment. The third unit 300 in the data transfer system 600 includes a first processing device (transmission side control unit) 110, a first memory 120, and a transfer device (memory control device) 330.

[0100] The transfer device 330 includes a DMAC (data reading unit, data writing unit) 331, a receive descriptor controller (receive descriptor reading unit) 332, a transmit descriptor controller (identifier receiving unit, transmit descriptor reading unit) 333, and a PCIe interface 334. The transmit descriptor controller 333 executes the same processes as the downstream transmit descriptor controller 235 and the upstream transmit descriptor controller 237. The receive descriptor controller 332 executes the same processes as the downstream receive descriptor controller 234 and the upstream receive descriptor controller 236.

[0101] The basic flow of the upstream and downstream data transfer in the data transfer system 600 is the same as the flow of the upstream and downstream data transfer in the data transfer system 500 according to the first embodiment. Specifically, in the case of this embodiment, both the transmitting side memory and the receiving side memory are the first memory 120. That is, where information was read and written to the second memory 220 in the process shown in FIG. 4, similar information may be read and written to the first memory 120. Also, in the case of this embodiment, the first firmware 112 of the first processing device 110 determines a tag number that specifies the transmitting descriptor table and the receiving descriptor table used to transfer the data to be transferred, and transmits it to the downstream transmitting descriptor controller 333.

[0102] 4 is executed by a transmit descriptor controller 333. Moreover, the process executed by the downstream receive descriptor controller 234 in Fig. 4 is executed by a receive descriptor controller 332. Moreover, the process executed by the DMAC 233 in Fig. 4 is executed by a DMAC 331.

[0103] According to the above configuration, when data transfer is performed by the DMA method, the frequency with which the first processing unit 110 accesses the first memory 120 can be reduced.

[0104] [Modifications] Although the embodiment of the present invention has been described in detail above, the above description is merely an example of the present invention in every respect. It goes without saying that various improvements and modifications can be made without departing from the scope of the present invention. For example, the following modifications are possible. In the following, the same reference numerals are used for the same components as in the above embodiment, and the description of the same points as in the above embodiment is omitted as appropriate. The following modifications can be combined as appropriate.

[0105] The data transfer system 500 according to the first embodiment may include one first unit 100 and multiple second units 200. In this case, the first unit 100 may include one transfer device 230, or each of the multiple second units 200 may include a transfer device 230. This allows each of the multiple second units 200 to transmit and receive data to and from the first unit 100 via the transfer device 230.

[0106] [Software implementation example] The control blocks of the first processing device 110, the second processing device 210, the transfer device 230, and the transfer device 330 may be realized by a logic circuit (hardware) formed on an integrated circuit (IC chip) or the like, or may be realized by software.

[0107] In the latter case, the first processing device 110, the second processing device 210, the transfer device 230, and the transfer device 330 are provided with a computer that executes instructions of a program, which is software that realizes each function. This computer is provided with, for example, one or more processors, and also with a computer-readable recording medium that stores the above program. Then, in the above computer, the above processor reads the above program from the above recording medium and executes it, thereby achieving the object of the present invention. For example, the above processor can be a CPU (Central Processing Unit). For the above recording medium, in addition to a "non-transient tangible medium", for example, a ROM (Read Only Memory) or the like, a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. In addition, the computer may further include a RAM (Random Access Memory) that expands the above program. In addition, the above program may be supplied to the above computer via any transmission medium (such as a communication network or a broadcast wave) that can transmit the program. Note that one aspect of the present invention may also be realized in the form of a data signal embedded in a carrier wave, in which the above program is embodied by electronic transmission.

[0108] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of symbols]

[0109] 100 1st unit (1st device, 2nd device) 110 First processing device (transmission side control unit) 111 First Control Section 112 1st Firmware 113, 213, 231, 232, 334 Interface 120 First memory (sender memory, receiver memory) 200 2nd unit (1st device, 2nd device) 210 Second processing device (transmission side control unit) 211 Second Control Section 212 2nd Firmware 220 Second memory (sender memory, receiver memory) 230, 330 Transfer device (memory control device) 233, 331 DMAC (data read unit, data write unit) 234 Downstream Receive Descriptor Controller 235 Downstream transmission descriptor controller (identifier receiver, transmission descriptor reader) 236 Upstream receive descriptor controller (receive descriptor reader) 237 Upstream transmit descriptor controller (identifier receiver, transmit descriptor reader) 332 Receive Descriptor Controller (Receive Descriptor Reader) 333 Transmit Descriptor Controller (Identifier Receiver, Transmit Descriptor Reader) 300 3rd Unit 500, 600 Data Transfer System

Claims

1. A memory control device that accesses a transmitting side memory and a receiving side memory by a DMA (Direct Memory Access) method and transfers a plurality of transfer target data from the transmitting side memory to the receiving side memory, the transmitting side memory stores at least the plurality of transfer target data and a transmission descriptor table including a plurality of transmission descriptors; an identifier receiving unit that receives an identifier designating one of the plurality of transmission descriptor tables from a transmission side control unit; a transmission descriptor reading unit that reads out a plurality of transmission descriptors included in the transmission descriptor table specified by the identifier in an order specified by the transmission descriptor table; a data reading unit that sequentially reads the plurality of transfer target data from the transmission side memory in accordance with descriptions of the plurality of transmission descriptors that are sequentially read from the transmission side memory.

2. A memory control device that accesses a transmitting side memory and a receiving side memory by a DMA (Direct Memory Access) method and transfers a plurality of transfer target data from the transmitting side memory to the receiving side memory, the receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors; an identifier receiving unit that receives an identifier designating the reception descriptor table from a transmission side control unit; a reception descriptor reading unit that reads out a plurality of reception descriptors included in the reception descriptor table corresponding to the identifier determined by the transmission side control unit in an order specified by the reception descriptor table; a data writing unit that sequentially writes the multiple transfer target data read from the transmitting side memory to the receiving side memory in accordance with the descriptions of the multiple receiving descriptors that are sequentially read from the receiving side memory.

3. the receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors; the identifier is an identifier for specifying the transmission descriptor table and the reception descriptor table corresponding to the transmission descriptor table, a reception descriptor reading unit that reads, from the reception descriptor table designated by the identifier, a plurality of reception descriptors included in the reception descriptor table in an order designated by the reception descriptor table; 2. The memory control device according to claim 1, further comprising: a data writing unit that sequentially writes the plurality of transfer target data read from the transmitting side memory to the receiving side memory in accordance with descriptions of the plurality of receiving descriptors that are sequentially read from the receiving side memory.

4. the sending memory is provided in a first device; 4. The memory control device according to claim 3, wherein the receiving memory is provided in a second device which is a device different from the first device and which communicates with the first device by a DMA method.

5. 4. The memory control device according to claim 3, wherein said sending memory and said receiving memory are the same.

6. 1. A control method for a memory control device that accesses a transmitting memory and a receiving memory by a DMA (Direct Memory Access) method to transfer a plurality of transfer target data from the transmitting memory to the receiving memory, comprising the steps of: the transmitting side memory stores at least the plurality of transfer target data and a transmission descriptor table including a plurality of transmission descriptors; an identifier receiving step of receiving an identifier designating one of the plurality of transmission descriptor tables from a transmission side control unit; a transmission descriptor reading step of reading, from the transmission descriptor table designated by the identifier, a plurality of transmission descriptors included in the transmission descriptor table in an order designated by the transmission descriptor table; a data reading step of sequentially reading the plurality of transfer target data from the transmitting side memory in accordance with descriptions of the plurality of transmission descriptors sequentially read from the transmitting side memory.

7. 1. A control method for a memory control device that accesses a transmitting memory and a receiving memory by a DMA (Direct Memory Access) method to transfer a plurality of transfer target data from the transmitting memory to the receiving memory, comprising the steps of: the receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors; an identifier receiving step of receiving an identifier designating the reception descriptor table from a transmission side control unit; a reception descriptor reading step of reading, from the reception descriptor table corresponding to the identifier determined by a transmission side control unit, a plurality of reception descriptors included in the reception descriptor table in an order specified by the reception descriptor table; a data writing step of sequentially writing the multiple transfer target data read from the transmitting side memory to the receiving side memory in accordance with the descriptions of the multiple receiving descriptors sequentially read from the receiving side memory.

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