Solid state drive and method for accessing metadata thereof

Abstract

To provide a solid-state drive of which operation performance has improved and a method of accessing metadata thereof.SOLUTION: A solid state drive disclosed herein comprises first and second memory units 610, 620 of different types, and a memory controller 500 configured to control the first and second memory units. The memory controller receives a metadata access request from a host, lets a condition checker 520 thereof determine conditions of the first and second memory units in response to the metadata access request to select at least one of the memory units, and accesses the memory unit(s) selected by the condition checker.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a solid-state drive and a metadata access method thereof. [Background technology]

[0002] A solid state drive (SSD) is a storage device that stores information using NAND flash memory, a memory semiconductor. It has the advantages of being faster than a hard disk drive (HDD), with less mechanical delay, failure rate, heat generation, and noise, as well as being compact and lightweight. Unlike a hard disk drive, it has no physical driving device, so it is quiet and has a fast data processing speed.

[0003] However, new solid-state drives are being developed that add a different type of memory, such as a NAND flash memory, to existing solid-state drives to form a composite solution. Such composite solution devices can have better operating performance by operating according to the characteristics of the different memories. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a solid state drive with improved operating performance.

[0005] Another problem to be solved by the present invention is to provide a metadata access method for a solid-state drive with improved performance.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] To solve the above problem, a solid state drive according to some embodiments of the present invention includes first and second memories of different types, and a memory controller that controls the first and second memories, wherein the memory controller includes a condition checker that receives a metadata access request from a host, determines conditions of the first and second memories in response to the metadata access request, and selects at least one of them, and accesses the memory selected by the condition checker.

[0008] To solve the above problem, a solid state drive according to some embodiments of the present invention includes a first memory in which first metadata is stored, a second memory in which second metadata identical to the first metadata is stored and which is a different type from the first memory, and a memory controller that controls the first and second memories, the memory controller including a condition checker that judges conditions of the first and second memories and selects a memory in a better condition, and the memory controller receives a metadata read request from a host, and reads the metadata stored in the memory selected by the condition checker from the first and second metadata in response to the metadata read request.

[0009] To solve the other problems, a metadata access method for a solid state drive according to some embodiments of the present invention includes receiving a metadata read request from a host, determining conditions of first and second memories of different types to select one of the first and second memories, and reading metadata of the selected memory of the first and second memories. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating a solid-state drive system according to some embodiments of the present invention. [Diagram 2]FIG. 2 is a block diagram for explaining the solid-state drive of FIG. [Diagram 3] FIG. 3 is a block diagram for explaining the memory controller and memory of FIG. 2 in detail. [Figure 4] 4 is an example of a characteristic table for explaining in detail the operation of the condition checker of FIG. 3. [Diagram 5] FIG. 4 is a block diagram for explaining the memory controller of FIG. 3 from the viewpoint of an interface. [Figure 6] 4 is a block diagram for explaining in detail the structure of the second memory of FIG. 3; FIG. [Figure 7] 7 is an exemplary equivalent circuit diagram for a memory block of the second memory of FIG. 6. [Figure 8] 7 is an exemplary perspective view of a memory block of the second memory of FIG. 6. [Figure 9] FIG. 2 is an illustrative perspective view of a memory block of a second memory of a solid-state drive according to some embodiments of the invention. [Figure 10] 4 is a time diagram illustrating a program operation of a solid-state drive according to some embodiments of the present invention. [Figure 11] FIG. 1 is a block diagram illustrating a solid-state drive according to some embodiments of the present invention. [Figure 12] FIG. 1 is a block diagram illustrating a solid-state drive according to some embodiments of the present invention. [Figure 13] FIG. 1 is a block diagram illustrating a solid-state drive according to some embodiments of the present invention. [Figure 14] 4 is a time diagram illustrating a program operation of a solid-state drive according to some embodiments of the present invention. [Figure 15] 4 is a time diagram illustrating a program operation of a solid-state drive according to some embodiments of the present invention. [Figure 16]4 is a time diagram illustrating a program operation of a solid-state drive according to some embodiments of the present invention. [Figure 17] 1 is a flow chart illustrating a metadata access method for a solid state drive according to some embodiments of the present invention. [Figure 18] 1 is a flow chart illustrating a metadata access method for a solid state drive according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Semiconductor devices according to some embodiments of the present invention will be described below with reference to FIGS.

[0012] 1 is a block diagram for explaining a solid-state drive system according to some embodiments of the present invention. Referring to FIG. 1, the solid-state drive system according to some embodiments of the present invention includes a host (HOST) 10 and a solid-state drive 20.

[0013] The host 10 may be coupled to the solid-state drive 20 outside the solid-state drive 20. The host 10 may be connected to the solid-state drive 20 via a host interface. The host 10 may control data processing operations of the solid-state drive 20 (e.g., a program operation, an erase operation, and a read operation).

[0014] The host 10 may be implemented as, but is not limited to, a host processor, an integrated circuit (IC), a motherboard, a system on chip (SoC), an application processor (AP), a mobile AP, a web server, a data server, or a database server.

[0015] The solid-state drive 20 may exchange commands and / or data with the host 10 via a host interface. The solid-state drive 20 may be implemented as, but is not limited to, a flash based storage. For example, the solid-state drive 20 may be implemented as, but is not limited to, a solid-state drive or solid-state disk (SSD) or an embedded SSD (eSSD).

[0016] The host 10 and the solid state drive 20 can be connected to each other to realize a data processing system, which can be realized by, for example, but not limited to, a personal computer (PC), a workstation, a data center, an internet data center (IDC), a direct attached storage (DAS) system, a storage area network (SAN) system, a network attached storage (NAS) system, a redundant array of inexpensive disks (RAID), or a mobile device.

[0017] Furthermore, the mobile device may be, but is not limited to, a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, a mobile internet device (MID), a wearable computer, an internet of things (IoT) device, an internet of everything (IoE) device, a drone, or an e-book.

[0018] Fig. 2 is a block diagram for explaining the solid-state drive of Fig. 1. Referring to Fig. 2, the solid-state drive according to some embodiments of the present invention includes a host interface 300, a processing core 100, a volatile memory 200, a power control module 400, a memory controller 500, and a non-volatile memory 600.

[0019] The host interface 300 may be a path for transmitting commands and / or data between the host 10 and the solid-state drive 20. Depending on the embodiment, the host interface 300 may be implemented as, but is not limited to, a serial advanced technology attachment (SATA) interface, a SATA express (SATAe) interface, a serial attached small computer system interface (SCSI) (SAS) interface, a peripheral component interconnect express (PCIe) interface, a non-volatile memory express (NVMe) interface, an advanced host controller interface (AHCI) interface, or a multimedia card (MMC) interface.

[0020] Depending on the embodiment, host interface 300 may transmit electrical or optical signals.

[0021] The processing core 100 may perform operations of the solid-state drive 20 within the solid-state drive 20. Specifically, the processing core 100 may perform operations on data processing commands transmitted by the host 10, refresh operations of the non-volatile memory 600, and the like.

[0022] The processing core 100 may include a first core (core 1) 101 and a second core (core 2) 102. The first core 101 and the second core 102 may be the same type of core or different types of cores. The first core 101 and the second core 102 may perform a plurality of tasks separately.

[0023] 2, the processing core 100 is shown with two processing cores, a first core 101 and a second core 102, but is not limited thereto. In some embodiments of the present invention, the number of processing cores may be one, or three or more.

[0024] The volatile memory 200 may work with the processing core 100 on data processing instructions and refresh the non-volatile memory 600. The volatile memory 200 may be, for example, a dynamic random access memory (DRAM). The volatile memory 200 may act as a buffer memory for performing the above operations.

[0025] A power control module 400 may control the power supplied to the solid-state drive 20. The power control module 400 may be powered by and control the host (10 in FIG. 1), or the power control module 400 may be powered by an internally located battery.

[0026] The memory controller 500 may control the non-volatile memory 600. The memory controller 500 may access the non-volatile memory 600 upon request from the host (10 in FIG. 1). Thus, the memory controller 500 may control the transmission or processing of instructions and / or data provided to the non-volatile memory 600.

[0027] Specifically, the memory controller 500 may perform program, read, and erase operations on the non-volatile memory 600. The memory controller 500 will be described in more detail below.

[0028] The non-volatile memory 600 programs data therein or reads data stored therein in response to a request from a host. The non-volatile memory 600 may include a first memory 610 and a second memory 620.

[0029] The first memory 610 and the second memory 620 may be different types from each other. For example, the first memory 610 and the second memory 620 may be any one of a Phase-change Random Access Memory (PRAM), a Resistive Random Access Memory (RRAM), a Magnetic Random Access Memory (MRAM), and a NAND flash memory. For convenience, it is assumed below that the first memory 610 is a PRAM and the second memory 620 is a NAND flash memory.

[0030] 2, the first memory 610 is connected to the first channel Ch1, and the second memory 620 is multiple and can be connected to the second channel Ch2, the third channel Ch3, and the fourth channel Ch4. That is, the second memory 620 can include a first channel memory 621 connected to the second channel Ch2, a second channel memory 622 connected to the third channel Ch3, and a third channel memory 623 connected to the fourth channel Ch4.

[0031] 2 is merely an example, and the memories may be arranged in any other manner. That is, the first memory 610 may be multiple and connected to multiple channels, and the second memory 620 may be single and connected to one channel. Also, the total number of memories is not limited.

[0032] As discussed above, the second memory 620 may include a three-dimensional NAND flash memory array. The second memory 620 may be monolithically formed in one or more physical levels of an array of memory cells having active areas disposed over a silicon substrate and circuitry associated with the operation of the memory cells. The circuitry associated with the operation of the memory cells may be located in or on the substrate. The term monolithically means that the layers of each level of the three-dimensional array are deposited directly on the layers of the lower level of the three-dimensional array.

[0033] In an exemplary embodiment according to the inventive concept, a three-dimensional memory array includes vertical NAND strings having a vertical orientation, with at least one memory cell located above another memory cell. At least one memory cell includes a charge trapping layer. Each vertical NAND string may include at least one select transistor located above the memory cell. The at least one select transistor may have the same structure as the memory cell and may be monolithically formed with the memory cell, as will be described in more detail below.

[0034] A system bus 700 may connect between the host interface 300, the volatile memory 200, the processing core 100, the memory controller 500 connected to the non-volatile memory 600, and the power control module 400. That is, data and requests are transferred via the system bus 700.

[0035] FIG. 3 is a block diagram for explaining the memory controller and memory of FIG. 2 in detail, and FIG. 4 is an example diagram of a characteristic table for explaining the operation of the condition checker of FIG. 3 in detail.

[0036] Referring to FIG. 3, the memory controller 500 may include a flash translation layer 510, a condition checker 520, and a characteristic table 530.

[0037] The flash translation layer 510 can translate a logical address into a physical address and provide the address to the non-volatile memory 600 in response to a data access request from the host (10 in FIG. 1).

[0038] The flash translation layer 510 may also perform management operations on various cell regions (e.g., chip-by-chip, block-by-page, etc.) of the non-volatile memory 600. For example, the flash translation layer 510 may perform garbage collection and bad block management operations on multiple blocks of the non-volatile memory 600.

[0039] The flash translation layer 510 may also perform wear leveling. Wear leveling means distributing work among cells of a NAND flash memory. If a cell of a NAND flash memory goes through a program and erase process too frequently, it becomes unusable (wearing off). Therefore, the work is distributed among cells of the NAND flash memory so that each block reaches the program / erase cycle limit at the same time.

[0040] The condition checker 520 may check the condition of each memory, i.e., the condition checker 520 may determine what the current condition of the first memory 610 and the second memory 620 is.

[0041] The first memory 610 and the second memory 620 may each contain the same metadata, i.e., the first memory 610 may store first metadata MD1 and the second memory 620 may store second metadata MD2.

[0042] The first metadata MD1 and the second metadata MD2 may be mirror data having the same contents as each other. The metadata may be important data for initial operation of the solid-state drive 20. That is, the metadata may include data for security authentication, data for initial operation of the firmware, and data for firmware debugging.

[0043] A solid-state drive 20 according to some embodiments of the present invention protects against metadata corruption by mirroring such metadata and storing it in different types of memory.

[0044] The memory controller 500 receives the metadata access request, i.e., the metadata read request, from the host 10, and in response, the condition checker 520 can determine which of the first memory 610 and the second memory 620 has a better condition.

[0045] The condition checker 520 may determine a current condition of the first memory 610 and may determine a current condition of the second memory 620. The condition checker 520 may compare the condition of the first memory 610 with the condition of the second memory 620 and select the memory having the better condition.

[0046] There are various methods for the condition checker 520 to compare the memory conditions. For example, the condition checker 520 may refer to the characteristic table 530. Although the characteristic table 530 is located outside the condition checker 520 in FIG. 3, the present invention is not limited to this. That is, the characteristic table 530 may be located inside the condition checker 520, or may be stored in another memory outside the memory controller 500 from the beginning. That is, the location of the characteristic table 530 is not particularly limited as long as the condition checker 520 can refer to it.

[0047] The characteristic table 530 may include a characteristic table for the first memory 610 and a characteristic table for the second memory 620. The characteristic table 530 may include a condition point corresponding to a status value.

[0048] The condition value may be a value for a current memory state. The condition value may be at least one of a temperature, a P / E cycle, a program retention time, and an erase retention time. However, the present embodiment is not limited thereto, and condition scores for other condition values ​​may be stored in the characteristic table 530.

[0049] At higher temperatures, NAND flash memory is in better condition than PRAM. If the first memory 610 is a PRAM and the second memory 620 is a NAND flash memory, the condition checker 520 may give a higher score to the second memory 620 at higher temperatures.

[0050] That is, the state value of the first memory 610 may be t2 among t1 to t4, and the corresponding condition score may be a2. In contrast, the state value of the second memory 620 may be t3, and the corresponding condition score may be b3 among b1 to b4, which are different from a1 to a4. In this case, b1 to b4 may be different from a1 to a4. This may be due to the difference in characteristics between PRAM and NAND flash memory.

[0051] The more P / E cycles the NAND flash memory has, the more its reliability deteriorates, and condition scores reflecting this can be stored in the characteristic table 530. The program retention time means the time left after the most recent programming, and the erase retention time means the time left after the most recent erasing. When the program retention time and erase retention time are large, the distribution of the NAND flash memory becomes wider due to the action of electrons / holes in the cells of the NAND flash memory. In other words, the longer the program retention time or erase retention time is, the lower the reliability of the second memory 620, which is a NAND flash memory.

[0052] The characteristic table 530 may store condition scores corresponding to the respective condition values ​​reflecting the above-mentioned characteristics. The condition checker 520 may receive current condition information from the first memory 610 and the second memory 620. At this time, the current condition information may include the condition values.

[0053] The condition value may be applied in a plurality of ways. For example, when temperature and P / E cycles are both taken into consideration, the condition score according to temperature and the condition score according to P / E cycles may be added together to compare the condition scores of the first memory 610 and the second memory 620.

[0054] The condition checker 520 may select the memory having the higher condition score among the first memory 610 and the second memory 620. That is, the condition checker 520 may select the memory having the better condition among the heterogeneous memories.

[0055] The memory controller 500 reads metadata of a memory selected by the condition checker 520 in response to a metadata read request from the host (10 in FIG. 1). That is, if the condition checker 520 selects the first memory 610, the memory controller 500 reads the first metadata MD1 of the first memory 610, and in contrast, if the condition checker 520 selects the second memory 620, the memory controller 500 reads the second metadata MD2 of the second memory 620.

[0056] This embodiment may thereby access metadata in better condition, greatly improving the operational performance and reliability of the solid-state drive 20.

[0057] Fig. 5 is a block diagram for explaining the memory controller of Fig. 3 from the viewpoint of an interface. Referring to Fig. 5, a memory controller 500 may include a volume interface 501. The volume interface 501 may include a security volume 502, a firmware volume (F / W Volume) 503, a debug volume (Debug Volume) 504, and a user volume (User Volume) 505.

[0058] The security volume 502 may be an area for security authentication of the solid state drive 20. The firmware volume 503 may be an area for firmware driving of the solid state drive 20. The debug volume 504 may be an area for debugging the solid state drive 20. The user volume 505 may be an area for direct use by the user.

[0059] Such an area must ultimately be accessed from either the first memory 610 or the second memory 620, but one of the first memory 610 and the second memory 620 can be selected and accessed by a dynamic selector 506. The dynamic selector 506 can enable selective access depending on the operation of the condition checker 520 of FIG.

[0060] Since the first memory 610 is a PRAM and the second memory 620 is a NAND flash memory, there may be a PRAM interface 507 for accessing the first memory 610 and a NAND interface 508 for accessing the second memory 620.

[0061] The PRAM interface 507 may provide access to a first memory 610, and the NAND interface 508 may provide access to a second memory 620.

[0062] Hereinafter, the structure of a NAND flash memory constituting the second memory 620 of the solid-state drive 20 according to some embodiments of the present invention will be described in detail with reference to FIGS.

[0063] Fig. 6 is a block diagram for explaining in detail the structure of the second memory of Fig. 3, and Fig. 7 is an exemplary equivalent circuit diagram of a memory block of the second memory of Fig. 6. Fig. 8 is an exemplary perspective view of the memory block of the second memory of Fig. 6.

[0064] 6 shows only the first channel memory 621 of the second memory 620 for convenience. The second channel memory 622 and the third channel memory 623 may have the same or similar structure as the first channel memory 621.

[0065] 6, the first channel memory 621 includes a plurality of memory blocks (BLK1 to BLKz, where z is an integer equal to or greater than 2). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of pages (Page1 to Pagem, where m is an integer equal to or greater than 2).

[0066] 7, a memory block (BLK) includes strings (Strings) connected to a plurality of bit lines (BL1 to BLn, n is an integer of 2 or more). Here, each string includes at least one string selection transistor SST, a plurality of memory cells (MC1 to MCm, m is an integer of 2 or more), and at least one ground selection transistor GST, which are connected in series between the bit line and a common source line (CSL).

[0067] Each of the memory cells MC1 to MCm may store at least one bit of data. Although not shown in the drawing, each of the strings may further include at least one dummy cell between the string selection transistor SST and the memory cells MC1 to MCm, and at least one dummy cell between the memory cells MC1 to MCm and the ground selection transistor GST.

[0068] Referring to Fig. 8, four sub-blocks are formed on a substrate. Each sub-block is formed by stacking at least one ground selection line GSL, a plurality of word lines WLs, and at least one string selection line SSL in a plate shape between word line cuts (WL cuts) on a substrate. Here, at least one string selection line SSL is separated by a string selection line cut. Meanwhile, although string selection line cuts are present in Fig. 8, the memory block of the present invention is not limited thereto. The memory block (BLKa) of the present invention may be realized without the string selection line cuts.

[0069] The first direction 1st and the second direction 2nd may intersect with each other, and the third direction 3rd may intersect with the first direction 1st and the second direction 2nd. The first direction 1st, the second direction 2nd, and the third direction 3rd may be, for example, orthogonal directions that are perpendicular to each other.

[0070] The ground select lines GSL, the word lines WLs, and the string select lines SSL may extend in the second direction 2nd and be spaced apart from one another in the first direction 1st by the word line cuts and the string select line cuts. Also, the ground select lines GSL, the word lines WLs, and the string select lines SSL may be stacked sequentially in the third direction 3rd.

[0071] In some embodiments of the present invention, at least one dummy word line may be stacked in a plate shape between the ground selection line GSL and the word line WLs, or at least one dummy word line may be stacked in a plate shape between the word line WLs and the string selection line SSL.

[0072] Although not shown in the drawing, each word line cut includes a common source line (CSL). In an embodiment, the common source lines CSL included in each word line cut are commonly connected. A pillar connected to a bit line penetrates at least one ground selection line GSL, a plurality of word lines WLs, and at least one string selection line SSL to form a string.

[0073] 8, the target between the word line cuts is shown as a sub-block, but the present invention is not necessarily limited to this. In the sub-block of the present invention, the target between the word line cut and the string selection line cut is named a sub-block.

[0074] The block (BLKa) according to the embodiment of the present invention may be realized in a structure in which two word lines are merged into one, in other words, in a merged wordline structure.

[0075] FIG. 9 is an exemplary perspective view of a memory block of a second memory of a solid-state drive according to some embodiments of the invention.

[0076] The structure of the block BLKb in Fig. 9 is different from the structure of the block (BLKa) in Fig. 8. Referring to Fig. 9, for the convenience of explanation, the memory block BLKb is shown to have four layers of word lines, but is not limited thereto. The memory block BLKb can be realized as a pipe-shaped bit cost scalable (PBiCS) structure in which the lower ends of adjacent serially connected memory cells are connected by a pipe.

[0077] The memory block BLKb includes m×n (m and n are natural numbers) strings NS. In FIG. 9, m=6 and n=2 are shown. Each string NS includes memory cells MC1 to MC8 connected in series. Here, first upper ends of the memory cells MC1 to MC8 are connected to the string selection transistor SST, second upper ends of the memory cells MC1 to MC8 are connected to the ground selection transistor GST, and lower ends of the memory cells MC1 to MC8 are connected to the pipe.

[0078] The word lines WL1 to WL8 may extend in a first direction 1st, and the strings NS may extend in a second direction. The word lines WL1 to WL8 and the strings NS may be spaced apart from each other in a third direction 3rd.

[0079] The memory cells constituting the string NS are formed by stacking a plurality of semiconductor layers. Each string NS includes a first pillar PL11, a second pillar PL12, and a pillar coupling portion PL13 that couples the first pillar PL11 and the second pillar PL12. The first pillar PL11 is connected to a bit line (e.g., BL1) and the pillar coupling portion PL13, and is formed by penetrating between the string selection line SSL and the word lines WL5 to WL8. The second pillar PL12 is connected to a common source line CSL and the pillar coupling portion PL13, and is formed by penetrating between the ground selection line GSL and the word lines WL1 to WL4. As shown in FIG. 9, the string NS is realized in the form of a U-shaped pillar.

[0080] In this case, the first pillar PL11 and the second pillar PL12 may extend in the third direction, and the pillar connection part PL13 may be connected in the second direction 2nd.

[0081] In some embodiments of the present invention, the back gate BG is formed on a substrate, and the pillar connection portion PL13 may be realized inside the back gate BG. In the embodiment, the back gate BG may be common to the block BLKb. The back gate BG may be a structure separated from the back gates of other blocks.

[0082] FIG. 10 is a time diagram illustrating a program operation of a solid-state drive according to some embodiments of the present invention.

[0083] 3 and 10, the method of programming the solid-state drive 20 according to some embodiments of the present invention may differ from the method of reading.

[0084] The memory controller 500 receives a metadata program request from the host (10 in FIG. 1). When the memory controller 500 receives the metadata program request, the condition checker 520 checks the conditions of the first memory 610 and the second memory 620.

[0085] The condition checker 520 may select the memory having the better condition from among the first memory 610 and the second memory 620 in the same manner as described above. As a result, the memory controller 500 programs the metadata into the memory selected by the condition checker 520 first.

[0086] Assuming that the condition checker 520 selects the first memory 610, the memory controller 500 programs the first metadata MD1 into the first memory 610 at a first time point t1.

[0087] The memory controller 500 may not program the second metadata MD2 into the second memory 620 that is not selected by the condition checker 520 immediately after the first metadata MD1 is programmed.

[0088] The condition checker 520 dynamically checks the condition of the second memory 620 that is not selected by the condition checker 520, and programs the second metadata MD2 into the second memory 620 at a second time t2 when the condition is better than the first time t1. The second time t2 may be a time after the first time t1.

[0089] At this time, the point when the condition becomes good means the point when the condition score derived by the condition checker 520 with reference to the characteristic table 530 is equal to or greater than a preset specific value.

[0090] Although the first metadata MD1 and the second metadata MD2 are stored at different times, they may be mirrored data of the same content, in order to store the metadata in a redundant manner so that the metadata can be read in a better condition of memory at a later time.

[0091] Hereinafter, a solid state drive according to some embodiments of the present invention will be described with reference to Fig. 11. Portions that overlap with the above description will be omitted or simplified.

[0092] 11 is a block diagram for explaining a solid state drive according to some embodiments of the present invention. Referring to FIG. 11, in the solid state drive according to some embodiments of the present invention, metadata mirrored not only in the first channel memory 621 but also in the second channel memory 622 and the third channel memory 623 may exist.

[0093] Specifically, the second channel memory 622 connected to the third channel Ch3 may store the third metadata MD3, and the third channel memory 623 connected to the fourth channel Ch4 may store the fourth metadata MD4.

[0094] This allows the condition checker 520 to not simply compare the condition scores of the first memory 610 and the second memory 620, but to compare the first memory 610, the first channel memory 621, the second channel memory 622, and the third channel memory 623 together and select one of them.

[0095] Here, the first metadata MD1, the second metadata MD2, the third metadata MD3 and the fourth metadata MD4 may be mirrored metadata having the same content.

[0096] In the solid state drive 20 according to this embodiment, since state values ​​such as temperature, PE cycles, program retention time, and erase retention time may differ even between the same type of memory in different channels, the solid state drive 20 selects the memory in the best condition among the same type of memory and reads the metadata.

[0097] This allows the metadata to be read undamaged and the overall operational performance of the solid-state drive 20 can be greatly improved.

[0098] Hereinafter, a solid state drive according to some embodiments of the present invention will be described with reference to Fig. 12. Portions that overlap with the above description will be omitted or simplified.

[0099] 12 is a block diagram illustrating a solid-state drive according to some embodiments of the present invention. Referring to FIG. 12, a memory controller 500 of a solid-state drive according to some embodiments of the present invention may include characteristic parameters 531.

[0100] The characteristic parameters 531 may include characteristic parameters for the first memory 610 and characteristic parameters for the second memory 620. The characteristic parameters 531 may be parameters by which the state values ​​are multiplied.

[0101] For example, the condition checker is y=a 1 X 1 +a 2 X 2 +a 3 X 3 where y is the condition score and X 1 , X 2 , X 3a can be a temperature state value, a P / E cycle state value, and a program retention time state value, respectively. 1 , a 2 , a 3 are X 1 , X 2 , X 3 , which may be stored in characteristic parameters 531.

[0102] The parameters are stored for each memory and used by the condition checker 520 to derive a condition score for each memory.

[0103] In this case, the formula may be a polynomial having a higher degree instead of the linear formula as described above. This may be appropriately modified in consideration of memory characteristics. For example, it is possible to use linear terms for certain state values ​​and quadratic terms for other state values.

[0104] Hereinafter, a solid state drive according to some embodiments of the present invention will be described with reference to Fig. 13. Portions that overlap with the above description will be omitted or simplified.

[0105] 13 is a block diagram illustrating a solid-state drive according to some embodiments of the present invention. Referring to FIG. 13, the solid-state drive according to some embodiments of the present invention may further include a third memory 630.

[0106] The third memory 630 may be a different type of memory than the first memory 610 and the second memory 620. If the first memory 610 is a PRAM and the second memory 620 is a NAND flash memory, the third memory 630 may be an RRAM.

[0107] The third memory 630 may be connected to the memory controller 500 via a fifth channel Ch5. The third memory 630 may include fifth metadata MD5 in which the first metadata MD1 and the second metadata MD2 are mirrored. That is, the fifth metadata MD5 may be metadata having the same content as the first metadata MD1 and the second metadata MD2.

[0108] The condition checker 520 may derive condition scores for the first memory 610, the second memory 620, and the third memory 630, respectively.

[0109] The condition checker 520 may refer to a characteristic table 530. The characteristic table 530 may include separate characteristic tables for the first memory 610, the second memory 620, and the third memory 630.

[0110] The condition checker 520 may compare the condition scores of the first memory 610, the second memory 620, and the third memory 630 to select the memory in the best condition.

[0111] This causes the memory controller 500 to read the metadata of the memory selected by the condition checker 520.

[0112] The solid-state drive according to the present embodiment compares the conditions of three different types of memory and reads the metadata of the best memory, thereby providing a more stable and reliable solid-state drive.

[0113] Although three types of memory are shown in FIG. 13, the present embodiment is not limited thereto. That is, the solid-state drive according to some embodiments of the present invention may include four or more types of memory, and the condition of each of these may be judged to select the memory in the best condition.

[0114] Hereinafter, solid state drives according to some embodiments of the present invention will be described with reference to Figures 1, 13, and 14. Portions that overlap with the above description will be omitted or simplified.

[0115] FIG. 14 is a time diagram illustrating a program operation of a solid-state drive according to some embodiments of the present invention.

[0116] 1, 13 and 14, a method for programming a solid state drive according to some embodiments of the present invention programs the remaining memories, excluding the memory in the worst condition, first.

[0117] The memory controller 500 receives a metadata program request from the host 10 , and the condition checker 520 checks the conditions of the first memory 610 , the second memory 620 and the third memory 630 .

[0118] The condition checker 520 may select the memory having the better condition from among the first memory 610, the second memory 620, and the third memory 630 in the same manner as described above, except that the condition checker 520 may select multiple memories instead of just one.

[0119] Specifically, the condition checker 520 may select the remaining two memories excluding the memory with the worst condition from the three memories in total, and the memory controller 500 may then program the metadata into the memory selected by the condition checker 520 first.

[0120] Assuming that the condition checker 520 selects the first memory 610 and the third memory 630, the memory controller 500 programs the first metadata MD1 into the first memory 610 at a first point in time t1 and programs the fifth metadata MD5 into the third memory 630 at the same first point in time t1.

[0121] The memory controller 500 may not program the second metadata MD2 into the second memory 620 not selected by the condition checker 520 immediately after the first metadata MD1 and the fifth metadata MD5 are programmed.

[0122] The condition checker 520 dynamically checks the condition of the second memory 620 that is not selected by the condition checker 520, and programs the second metadata MD2 into the second memory 620 at a second time t2 when the condition is better than the first time t1. The second time t2 may be a time after the first time t1.

[0123] In this case, the point in time when the condition becomes good may refer to the point in time when the condition score derived by the condition checker 520 with reference to the characteristic table 530 is equal to or greater than a preset specific value.

[0124] Although the first metadata MD1, the fifth metadata MD5, and the second metadata MD2 may be mirrored data of the same content, although they were created at different times. This may be to store the metadata in duplicate so that the metadata can be read in a better condition of memory at a later time.

[0125] This embodiment can prevent metadata from being damaged by not immediately programming metadata into memory in poor conditions, but by programming the metadata later when conditions become better.

[0126] Hereinafter, solid state drives according to some embodiments of the present invention will be described with reference to Figures 1, 13, and 15. Portions that overlap with the above description will be omitted or simplified.

[0127] FIG. 15 is a time diagram illustrating a program operation of a solid-state drive according to some embodiments of the present invention.

[0128] 1, 13 and 15, a method for programming a solid-state drive according to some embodiments of the present invention programs the memory in the best condition first, and then programs the remaining memories sequentially.

[0129] The condition checker 520 may select the memory having the best condition from among the first memory 610, the second memory 620, and the third memory 630 in the same manner as described above.

[0130] Specifically, the condition checker 520 may select the memory with the best condition from the total of three memories, and the memory controller 500 may program the metadata into the memory selected by the condition checker 520 first.

[0131] Assuming that the condition checker 520 selects the first memory 610, the memory controller 500 programs the first metadata MD1 into the first memory 610 at a first time point t1.

[0132] The memory controller 500 may not immediately program the second metadata MD2 and the fifth metadata MD5 into the second memory 620 and the third memory 630, respectively, that are not selected by the condition checker 520, once the first metadata MD1 has been programmed.

[0133] The condition checker 520 may dynamically check the conditions of the second memory 620 and the third memory 630 that are not selected by the condition checker 520. The fifth metadata MD5 is then programmed into the third memory 630 at a second time t2 when the condition of the third memory 630 is better than the first time t1. The second time t2 may be a time after the first time t1.

[0134] Similarly, the condition checker 520 may further dynamically check the condition of the unprogrammed second memory 620. Then, the second metadata MD2 is programmed into the second memory 620 at a third time t3 when the condition of the second memory 620 is better than the first time t1 and the second time t2. The third time t3 may be a time after the first time t1 and the second time t2.

[0135] At this time, the point when the condition becomes good means the point when the condition score derived by the condition checker 520 with reference to the characteristic table 530 is equal to or greater than a preset specific value.

[0136] Although they are generated at different times, the first metadata MD1, the fifth metadata MD5 and the second metadata MD2 may be mirrored versions of each other and have the same content.

[0137] This embodiment can prevent metadata damage much more easily by having each memory program its metadata when conditions are good, i.e., the reliability of all metadata is very high since each memory is programmed when conditions are good.

[0138] Hereinafter, solid state drives according to some embodiments of the present invention will be described with reference to Figures 1, 13, and 16. Portions that overlap with the above description will be omitted or simplified.

[0139] FIG. 16 is a time diagram illustrating a program operation of a solid-state drive according to some embodiments of the present invention.

[0140] 1, 13 and 16, a method for programming a solid-state drive according to some embodiments of the present invention programs metadata in all but the most poorly conditioned memory.

[0141] The condition checker 520 may select the remaining memory from among the first memory 610, the second memory 620, and the third memory 630, excluding the memory having the worst condition, in the same manner as described above.

[0142] Specifically, the condition checker 520 may select two memories excluding the memory with the worst condition from the total of three memories, and the memory controller 500 may then program the metadata into the memory selected by the condition checker 520 first.

[0143] Assuming that the condition checker 520 selects the first memory 610 and the third memory 630, the memory controller 500 programs the first metadata MD1 into the first memory 610 and the fifth metadata MD5 into the third memory 630 at a first time point t1.

[0144] The memory controller 500 may not program metadata into the second memory 620 that is not selected by the condition checker 520. Of course, the first metadata MD1 and the fifth metadata MD5 may be data having the same content that is mirrored to each other.

[0145] In this embodiment, since the metadata is stored in duplicate even when only one of a plurality of memories is removed, it is possible to eliminate the need to program the memory in the worst condition under the premise that the reliability of the metadata can be sufficiently improved.

[0146] Since the operation of continuously and dynamically checking the condition of the second memory 620 that is not selected by the condition checker 520 after the first time point t1 and the operation of programming metadata into the second memory 620 consume a lot of resources, the present embodiment can maintain high operating performance of the solid state drive by excluding these operations and saving resources. At the same time, the solid state drive of the present embodiment can maintain high reliability of the metadata because two pieces of metadata are programmed into two memories, respectively.

[0147] Hereinafter, a metadata access method for a solid state drive according to some embodiments of the present invention will be described with reference to Figures 1, 3, and 17. Portions that overlap with the above description will be omitted or simplified.

[0148] 17 is a flow chart illustrating a method for accessing metadata in a solid state drive according to some embodiments of the present invention. Referring to FIG 17, a request to read metadata is received (S100).

[0149] Specifically, referring to FIGS. 1 and 3, the memory controller 500 may receive a metadata read request from the host 10.

[0150] Referring again to FIG. 17, the memory condition is determined and a memory is selected (S200).

[0151] 1 and 3, the condition checker 520 may determine a current condition of the first memory 610 and may determine a current condition of the second memory 620. The condition checker 520 may compare the condition of the first memory 610 with the condition of the second memory 620 and select the memory having a better condition. For example, the condition checker 520 may determine the conditions of the first memory 610 and the second memory 620 by referring to the characteristic table 530.

[0152] Referring again to FIG. 17, if the first memory is selected, the first metadata is read (S300).

[0153] Specifically, referring to Figures 1 and 3, since the first memory 610 is in better condition than the second memory 620, the first metadata MD1 in the first memory 610 may have higher reliability than the second metadata MD2 in the second memory 620.

[0154] Referring again to FIG. 17, if the second memory is selected, the second metadata is read (S400).

[0155] Specifically, referring to FIG. 1 and FIG. 3, since the second memory 620 is in a better condition, the second metadata MD2 may have higher reliability.

[0156] A method of memory access in a solid-state drive according to some embodiments of the present invention can improve the reliability of the solid-state drive by storing mirrored metadata in heterogeneous memories and reading the metadata from the memory having better conditions.

[0157] Hereinafter, a metadata access method for a solid state drive according to some embodiments of the present invention will be described with reference to Figures 1, 3, 10, and 18. Portions that overlap with the above description will be omitted or simplified.

[0158] 18 is a flow chart illustrating a method for accessing metadata in a solid state drive according to some embodiments of the present invention. Referring to FIG 18, a metadata program request is received (S1100).

[0159] Specifically, referring to FIGS. 1, 3 and 10, the memory controller 500 may receive a metadata program request from the host 10.

[0160] Referring again to FIG. 18, the memory condition is determined and a memory is selected (S1200).

[0161] 1, 3, and 10, when the memory controller 500 receives a metadata program request, the condition checker 520 checks the conditions of the first memory 610 and the second memory 620. The condition checker 520 may select the memory having the better condition from the first memory 610 and the second memory 620 in the same manner as described above.

[0162] Referring again to FIG. 18, if the first memory is selected, the metadata is programmed into the first memory (S1300).

[0163] 1, 3, and 10, since the first memory 610 is in a better condition than the second memory 620, programming metadata only in the first memory 610 may be a way to prevent possible damage to the metadata. In this case, if the metadata is programmed in the second memory 620, the metadata to be programmed in the memory in a worse condition may be damaged.

[0164] Referring again to FIG. 18, the condition of the second memory is determined (S1500).

[0165] Specifically, referring to Figures 1, 3 and 10, since metadata has already been programmed into the first memory 610, the condition checker 520 can dynamically check the condition of the second memory 620 in which metadata has not been programmed.

[0166] If the condition of the second memory 620 is not good, the metadata may not be programmed and the second memory 620 may wait until the condition of the second memory 620 is good.

[0167] Referring again to FIG. 18, when the condition of the second memory becomes good, metadata is programmed into the second memory (S1700).

[0168] That is, the condition checker 520 dynamically checks the condition of the second memory 620 that is not selected by the condition checker 520, and programs the second metadata MD2 into the second memory 620 at a second time t2 when the condition is better than the first time t1. The second time t2 may be a time after the first time t1.

[0169] At this time, the point when the condition becomes good means the point when the condition score derived by the condition checker 520 with reference to the characteristic table 530 is equal to or greater than a preset specific value.

[0170] Referring again to FIG. 18, if the second memory 620 is selected, metadata is programmed into the second memory 620 (S1400), the condition of the unselected first memory 610 is determined (S1600), and the metadata is programmed into the first memory 610 when the condition of the first memory 610 improves (S1800).

[0171] In the above description, the metadata may be mirrored data in each memory, i.e. data containing the same content, so that a later metadata read operation will read the metadata from the memory in better condition.

[0172] In this embodiment, if the condition of a particular memory is not good, the metadata is not programmed immediately, but is programmed when the condition of the particular memory improves, thereby preventing damage to the mirrored metadata.

[0173] Although only two types of memory are illustrated in the above embodiment, this is merely an example, and the metadata access method for a solid state drive according to the present embodiment can also be applied to a solid state drive including three or more types of memory. In this case, step S1200 can select at least one memory instead of simply selecting one memory.

[0174] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0175] 10 Host 20 Solid State Drive 500 Memory Controller 510 Flash Translation Layer 520 Condition Checker 530 Characteristics Table 531 Characteristic parameters 600 Non-volatile Memory 610 First Memory 620 Second Memory 621 1st channel memory 622 Second Channel Memory 623 3rd Channel Memory 630 3rd Memory

Claims

1. First and second memories of different types; a memory controller for controlling the first and second memories; Both the first and second memories are configured to store the same metadata, the metadata being important data for initial operation of the solid-state drive; The memory controller includes: Receives a metadata access request from a host, a condition checker that determines conditions of the first and second memories in response to the metadata access request and selects at least one of the first and second memories; The metadata access request is a metadata read request, the first and second memories each store the same metadata; the condition checker selects one of the first and second memories; the memory controller reads the metadata from a memory selected by the condition checker out of the first and second memories; Solid state drive.

2. 2. The solid state drive of claim 1, wherein the condition checker determines the condition of the first and second memories by taking into account at least one of a temperature, a P / E cycle, a program retention time, and an erase retention time.

3. 3. The solid state drive of claim 1, wherein the first and second memories are any one of a NAND flash memory, a PRAM, a RRAM, and an MRAM.

4. First and second memories of different types; a memory controller for controlling the first and second memories; Both the first and second memories are configured to store the same metadata, the metadata being important data for initial operation of the solid-state drive; The memory controller includes: Receives a metadata access request from a host, a condition checker that determines conditions of the first and second memories in response to the metadata access request and selects at least one of the first and second memories; the metadata access request is a metadata program request, the memory controller first programs metadata into one of the first and second memories selected by the condition checker; When a condition of the memory not selected by the condition checker among the first and second memories becomes good, the metadata is programmed into the memory not selected by the condition checker. Solid state drive.

5. The solid-state drive of claim 1 , wherein the second memory includes first and second channel memories connected to the memory controller via different channels.

6. 6. The solid state drive of claim 5, wherein the condition checker determines conditions of the first memory, the first channel memory, and the second channel memory in response to the metadata access request, and selects one of the first memory, the first channel memory, and the second channel memory.

7. first to third memories different from each other; a memory controller that controls the first to third memories; The first, second and third memories are configured to store the same metadata, the metadata being important data for initial operation of the solid state drive; The memory controller includes: Receives a metadata access request from a host, a condition checker that checks conditions of the first, second, and third memories in response to the metadata access request and selects at least one of the first, second, and third memories; the metadata access request is a metadata program request, the condition checker selects the remaining memory except for one of the first memory, the second memory, and the third memory; the memory controller first programs metadata into a memory selected by the condition checker among the first, second, or third memories; When a condition of the memory not selected by the condition checker among the first, second, or third memories becomes good, the metadata is programmed into the memory not selected by the condition checker. Solid state drive.

8. The solid-state drive of claim 1 , wherein the metadata includes at least one of security metadata, firmware metadata, and debug metadata.

9. A first memory in which first metadata, which is important data for initial operation of a solid state drive, is stored; a second memory in which second metadata identical to the first metadata is stored and which is of a different type than the first memory; a memory controller for controlling the first and second memories, the memory controller including a condition checker for determining conditions of the first and second memories and selecting a memory having a superior condition; The memory controller receives a metadata read request from a host, and reads metadata stored in a memory selected by the condition checker from the first and second metadata in response to the metadata read request.

10. the condition checker receives current state information of the first and second memories and determines conditions of the first and second memories based on the current state information; 10. The solid state drive of claim 9, wherein the current state information includes at least one of a temperature, a P / E cycle, a program retention time, and an erase retention time of the first and second memories.

11. The solid-state drive of claim 10 , wherein the condition checker includes a characteristic table in which characteristic values ​​corresponding to the current state information for each of the first and second memories are stored.

12. The solid-state drive of claim 10 , wherein the condition checker includes characteristic parameters corresponding to the current state information for each of the first and second memories.

13. Receive a metadata read request from the host, determining conditions of first and second memories of different types in which the same metadata is stored, and selecting one of the first and second memories, the metadata being important data for initial operation of the solid state drive; A method of accessing metadata in a solid state drive, comprising: reading metadata from a selected one of the first and second memories.

14. receiving a metadata program request from the host; determining a condition of each of the first and second memories to select at least one of the first and second memories; 14. The method of claim 13, further comprising programming the metadata into selected ones of the first and second memories.

15. 15. The method of claim 14, further comprising: after programming the metadata into a selected one of the first and second memories, when a condition of the unselected one of the first and second memories becomes good, programming the metadata into the unselected one of the first and second memories.

16. the second memory includes first and second channel memories for different channels; determining conditions of the first and second memories and selecting one of the first and second memories when the metadata program request is received; 15. The method of claim 14, further comprising: determining a condition of each of the first memory, the first channel memory, and the second channel memory, and selecting one of the first and second channel memories.

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