Determining and using a byte error location signal - Patents.com

Abstract

To provide determination and use of byte error position signals.SOLUTION: At least one byte error is identified in a binary sequence comprising a plurality of bytes, where the binary sequence in an error-free case is a code word of an error code, and each of at least two byte error position signals is determined using components of an error syndrome of the error code. The at least two byte error position signals indicate whether or not a byte of the binary sequence associated with the byte error position signals is erroneous. The invention relates to correcting at least one byte error in a binary sequence comprising a plurality of bytes, where at least one byte error position signal is determined using components of an error syndrome of an error code. The at least one byte error position signal allows determination of whether a byte of the binary sequence is erroneous. At least one byte error correction value is determined for at least one correct byte on the basis of the byte error correction value.SELECTED DRAWING: None

Description

[Background technology]

[0001] It is known to recognize and correct errors in data present in the form of bytes, byte by byte, where a byte may contain at least two bits. At least one error in at least one bit of a byte is called a byte error. If at least one bit of a byte is erroneous, then a byte error exists. If only at least one bit of a byte is erroneous, then this is a single byte error.

[0002] Correction of one-byte errors is described, for example, in (Non-Patent Document 1).

[0003] If bits in two different bytes are in error, then this is a double byte error. Thus, when bits in k bytes are in error (i.e., at least one bit in each of the k bytes has an error), then we say that there is a k-byte error.

[0004] The general motivation is to perform error correction of potentially erroneous bytes quickly. This is the case, for example, when data in the form of bytes is provided in parallel, read in parallel from a memory. In such a scenario, it may be advantageous to also perform error correction in parallel.

[0005] "Parallel" here means in particular that error correction or parts of error correction for at least two bytes are performed at least partly simultaneously (eg also at least partly overlapping in time).

[0006] Byte error correction can be performed, for example, by Reed-Solomon codes.

[0007] OKANO (Patent Document 2) describes a circuit configuration for correcting double-byte errors using a Reed-Solomon code. Here, the double-byte error correction described in OKANO has the disadvantage that it is relatively slow. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Bossen, D.: b-Adjacent Error Correction, IBM J. Res.Dev., July 1970, pp. 402-408. [Non-Patent Document 2] Okano, H., Imai, H.: A Construction Method of High-Speed ​​Decoders Using ROM's for Bose-Chaudhuri-Hocquengiem and Reed-Solomon Codes, IEEE TRANSACTIONS ON COMPUTERS, VOL. C-36, NO. 10, OCTOBER 1987, pp. 1165-1171. [Non-Patent Document 3] Lin, S., Costello, D.: Error Control Coding, Prentice Hall, 1983, pp. 170-177. [Non-Patent Document 4] Wicker, S.: Error Control Systems for Digital Communication and Storage, Prentice Hall, 1995, pp. 214-224. [Non-Patent Document 5] Fujiwara, E.: Code Design for Dependable Systems, Wiley, 2006, 65 pages. Summary of the Invention [Problem to be solved by the invention]

[0009] The object of the invention is to overcome the disadvantages of known solutions for correcting byte errors and in particular to make it possible to carry out error correction of errors within several bytes as quickly as possible.

[0010] In particular, one challenge is to provide error correction for m byte errors (m≧2) for memory cells, such as MRAM memory cells or RRAM memory cells, thereby increasing the reliability of data read from the memory cells. [Means for solving the problem]

[0011] This problem is solved according to the features of the independent claims. Preferred embodiments emerge in particular from the dependent claims.

[0012] In order to solve the above problem, there is provided a circuit arrangement for determining at least two byte error location signals, comprising: Identifying at least one byte error in a binary string containing multiple bytes; - if the binary string is not erroneous, it is a codeword of the error code; the circuitry is designed to be able to determine at least two respective byte error location signals using components of the error syndrome of the error code, each of the at least two byte error location signals indicating whether a byte of the binary sequence associated with that byte error location signal is erroneous or not; at least two byte error location signals are determined in parallel, A circuit configuration is proposed.

[0013] It should be noted that one byte error location signal can be determined for each byte of the binary string. Thus, with each byte of the binary string there is associated or associated a byte error location signal. The value of the byte error location signal indicates whether the byte associated with the byte error location signal has an error or not.

[0014] The error code may be, for example, an error correcting and / or error recognizing code. For example, a Reed-Solomon code may be used as the error code.

[0015] In this context, "parallel" in particular means that the values ​​are determined at least partially parallel to one another, ie for example simultaneously in time or at least partially simultaneously in time.

[0016] In one variant, the circuitry is capable of determining a byte error location signal using components of the error syndrome of the error code, the byte error location signal being designed to indicate that there is a correctable error for at least two of the bytes of the binary string.

[0017] In one variant, the error code is a t-byte error correcting code, and at least (t+1) byte error location signals are determined in parallel.

[0018] In one variant, the binary string has two byte errors.

[0019] In one variant, each byte of the binary string has m bits, where m≧2.

[0020] In one variant, the error code is -t byte error correction code, or -t byte error correcting and (t+1) byte error detecting code where t≧2.

[0021] In one variant, the binary string comprises at least (t+1) correctable bytes.

[0022] In one variant, the error syndrome has at least 2 t components s1, s2, ..., s 2t where each component contains m bits, m≧2.

[0023] A correctable byte is a byte in which, if there is a byte error in that byte, error correction is performed when the byte error can be corrected by the byte error correcting code.

[0024] In one variation, the byte error location signal has a first value if the byte associated with the byte error location signal is erroneous and has a second value if the byte associated with the byte error location signal is not erroneous.

[0025] In one variant, at least one of the byte error location signals is determined for at least one corrected byte.

[0026] In one variant, the binary string comprises data bytes and check bytes, the data bytes and / or the check bytes constituting the correctable bytes.

[0027] In particular, it is possible to correct only the data bytes, or only the check bytes, or a combination of data bytes and check bytes, where the data bytes may be the usage data and the check bytes may be additional check information that can be used to correct the usage data.

[0028] In order to solve the above problem, a circuit configuration for correcting at least one byte error in a binary string including a plurality of bytes is provided, the binary string being a codeword of an error code if it is not erroneous, the circuit configuration comprising: determining at least one byte error location signal using components of the error syndrome of the error code, and being able to determine whether a byte of the binary string is erroneous or not by means of the byte error location signal; determining at least one byte error correction value and being able to correct erroneous byte positions identified by the byte error position signal based on the byte error correction value; - designed such that at least one byte error correction value is determined for at least one correct byte, A circuit configuration is proposed.

[0029] In a variant, at least one byte error location signal and / or at least one byte error correction value are determined in parallel.

[0030] In particular, at least two byte error correction values ​​can be determined in parallel.

[0031] In one variant, the error code is a t-byte error correcting code, and at least (t+1) byte error location signals are determined in parallel.

[0032] In one variant, the error code is a t-byte error correcting code, and at least (t+1) byte error correcting values ​​are determined in parallel.

[0033] In one variation, the at least (t+1) byte error correction values ​​are determined using up to three Galois field multipliers, where t≧2.

[0034] In one variant, the circuitry is designed to correct one of the byte errors by computing the byte error location signal with a byte error correction value for the erroneous byte.

[0035] In one variation, the circuitry is designed to correct t byte errors, where t≧2.

[0036] In one variation, the circuitry is further designed to correct one byte errors.

[0037] In one variation, the circuitry is further designed to correct τ byte errors, where t≧τ>2.

[0038] In one variant, in the case of a double byte error, the i-th byte is a correctable byte, the byte error location signal for the i-th byte is

number

number

[0039] In one variant, in case of a double byte error, the byte error correction value of the i-th byte is

number

[0040] The circuitry may be divided into individual subcircuitry, and in particular the circuitry described herein may be realised in one component or in multiple components.

[0041] Furthermore, the circuit configuration can be realized using synthesis tools.

[0042] In one variant, in case of a double byte error, the correction of the correctable bytes is determined depending on the three components of the error syndrome and the byte error location signal.

[0043] Also provided is a method for determining at least two byte error location signals, comprising: Identifying at least one byte error in a binary string containing multiple bytes; - if the binary string is not erroneous, it is a codeword of the error code; - each of at least two byte error location signals is determined using components of an error syndrome of the error code to indicate whether a byte of the binary string associated with the byte error location signal is erroneous or not; at least two byte error location signals are determined in parallel, A method is presented.

[0044] There is further provided a method for correcting at least one byte error in a binary string comprising a plurality of bytes, the binary string being, if not erroneous, a codeword of an error code, the method comprising: - determining at least one byte error location signal using components of the error syndrome of the error code, such that it is possible to determine whether a byte of the binary string is erroneous or not by means of the at least one byte error location signal; determining at least one byte error correction value, based on which erroneous byte positions identified by the byte error position signal are corrected; At least one byte error correction value is determined for the at least one correct byte. A method is presented.

[0045] The above-mentioned characteristics, features and advantages of the present invention, as well as the manner in which they are achieved, will now be described in connection with a schematic description of exemplary embodiments, which will now be described in more detail with reference to the drawings, in which, for ease of understanding, identical elements or elements having identical functions may be provided with the same reference numerals. [Brief description of the drawings]

[0046] [Figure 1] FIG. 13 illustrates an exemplary circuit configuration for generating byte error location signals for two byte errors in parallel. [Diagram 2] FIG. 2 shows an alternative form of the circuit configuration shown in FIG. [Diagram 3] FIG. 2 shows a further configuration of the circuit arrangement shown in FIG. 1 having a central circuit portion. [Figure 4] FIG. 4 illustrates an alternative exemplary implementation of the central circuit portion shown in FIG. 3. [Diagram 5] FIG. 13 is a diagram showing an example of a circuit configuration for byte error correction regarding a double-byte error. [Figure 6] FIG. 6 shows an example of an implementation of the sub-circuit shown in FIG. 5 for generating a byte error correction value. [Figure 7] 6 shows a further example of an implementation of the sub-circuit shown in FIG. 5 for generating a byte error correction value. [Figure 8]FIG. 13 is a diagram showing an example of a correction circuit for one-byte errors and two-byte errors that uses a circuit configuration for generating a byte error location signal for a two-byte error. [Figure 9] FIG. 1 illustrates an exemplary correction circuit for 1 byte error, 2 byte errors, and so on up to t byte errors using circuitry to generate a byte error location signal for 2 byte errors. [Figure 10] FIG. 9 illustrates an exemplary embodiment of the subcircuit shown in FIG. 8. [Figure 11] FIG. 2 is a diagram illustrating an error recognition circuit. [Figure 12] FIG. 13 is a diagram showing an error recognition circuit for recognizing a three-byte error. [Figure 13] FIG. 1 is a table illustrating various representation forms of elements of a Galois field GF(2m), where m=5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] As an example, we describe below the correction of byte errors using Reed-Solomon codes, where a byte can contain multiple bits.

[0048] For each correctable byte position, a signal (also called a byte error location signal) is specified that makes it possible to determine whether the byte is erroneous or not, for example the byte error location signal has a value of 1 if the byte is erroneous and a value of 0 if the byte is not erroneous.

[0049] The byte error location signal is preferably determined by the value of a locator polynomial. In the case of a byte error correcting code, one locator polynomial can be used for each number of errors.

[0050] It is therefore particularly proposed to determine a byte error position signal with respect to a correctable byte position of a byte error correcting code, where the byte error correcting code is particularly capable of correcting at least two byte errors.

[0051] Here, the correctable byte position is a byte position where a correction is made when an error that can be corrected by the byte error correcting code occurs.

[0052] The bytes may be, for example, data bytes, a combination of data bytes and check bytes, or a subset thereof. The data bytes preferably contain usage data.

[0053] For a byte position, a byte error correction value can be determined, and based on the byte error correction value, the byte position is corrected when an error occurs there. The byte error location signal indicates whether an error occurs for a byte, and the byte error correction value can correct this error. The byte error location signal can also be used to mask individual byte positions, in which case no correction is performed.

[0054] In particular, it is an option to multiply a byte error correction value that is not used for correction at a byte position (e.g. because the byte position is not in error) by 0. To that extent, multiplying a byte error correction value by 0 also corresponds to not using a byte error correction value at the byte position.

[0055] A general description of Reed-Solomon codes Below we explain some concepts and properties of Reed-Solomon codes.

[0056] for example, -t byte error correction code, -t byte error correction and (t+1) byte recognition code In particular, consider the cases t=2 and t=1.

[0057] For example, a Reed-Solomon code, known as a byte error correcting code, can be used. For more information on the Reed-Solomon code, see, for example, Patent Document 3 or Patent Document 4.

[0058] One-byte error correcting and two-byte error recognizing Reed-Solomon codes are written using the H matrix

number

number

[0059] Here, α i is in the Galois field GF(2 m ) element of the Galois field GF(2 m ) can be a primitive element of α j The exponent j of m It can be interpreted as -1.

[0060] From the H matrix in equation (1), the following H matrix can be derived:

number

[0061] For 2-byte error correcting and 3-byte error detecting codes, the following H matrix is ​​used:

number

[0062] Each column of the H matrix expressed by equation (3) corresponds to one byte.

[0063] If the length of the code is N bytes or m N bits (where each byte has m bits), then only N columns of the H matrix according to (1) or (3) are used. For example, the remaining (last) 2 m -2-N columns can be deleted.

[0064] In general, for a t-byte error correcting and t+1-byte error detecting code, the H matrix can be expressed as:

number

[0065] As an example, consider below a code that can correct two-byte errors and recognize three-byte errors.

[0066] If an error occurs, the correct vector v=v 0 ,…,v N-1 is disturbed, and the incorrect vector v ’ =v ’0 ,…,v ’N-1 become.

[0067] Component v of vector v 0 ,…,v N-1 are bytes each containing m bits, so that for i=0,…,N-1,

number

number

[0068] The m-bit bytes are stored in the Galois field GF(2 m ) elements.

[0069] In the case of a byte error, only one byte is in error, ie, for a particular i∈{0,...,N-1}, the associated i-th byte is in error.

[0070] The correct i-th byte

number

number

[0071] A byte error in the i-th byte is - the erroneous byte position i, and - The byte error value can be expressed as follows:

number

number

[0072] The position of the i-th byte is α i It can also be expressed as:

[0073] A byte error is a byte error value e at byte position i. i If the i-th byte is corrected by , then for byte position i, a byte error correction value can be determined that is equal to the byte error value.

[0074] In this example, for a byte error to be corrected, the byte error value is equal to the byte error correction value; to that extent the concepts "byte error value" and "byte error correction value" can be used synonymously.

[0075] To avoid confusing the subscript numbers, hereafter the byte error values ​​will be represented by the alphabetic letters a, b, and c.

[0076] The byte error correction value for the i-th byte may also be represented as a(i).

[0077] The byte position is i,j,k,…, or α i ,α j ,α k , …, where α is a function of the Galois field GF(2 m ) is a generating element of

[0078] The error syndrome s has syndrome components (also called components, error syndrome components, partial error syndromes, or partial syndromes) s1, s2, s3, s4, and s5, which are determined in terms of the H matrix according to equation (3) as follows: s1=(α 0 ,α 0 ,…,α 0 )·(v ’0 ,v ’1 ,…,v ’N-1 ) T , s2=(α 0 ,α 1 ,…,α N-1 )·(v ’0 ,v ’1 ,…,v ’N-1 ) T , s3=(α 0 ,α 2 ,…,α 2(N-1) )·(v ’0 ,v ’1 ,…,v ’N-1 ) T , s4=(α 0 ,α 3 ,…,α 3(N-1) )·(v ’0 ,v ’1 ,…,v ’N-1 ) T , s5=(α 0 ,α 4 ,…,α 4(N-1) )·(v ’0 ,v ’1 ,…,v ’N-1 ) T

[0079] Here, (v ’0 ,…,v ’N-1 ) T is the component v ’0 ,…,v ’N-1 is a column vector with the row vector (v ’0 ,…,v ’N-1 ) can also be called the transpose vector.

[0080] The syndrome components s1, s2, s3, s4, and s5 each constitute a byte having m bits.

[0081] If there are no errors, It holds that s1=s2=s3=s4=s5=0.

[0082] If there is a byte error with a byte error value α at the i-th byte error location, then the following equation holds: s1=α 0 a=a s2=a i a s3=a 2i a s4=a 3i a s5=a 4i a (4)

[0083] If there are two byte errors at byte error locations i and j with byte error values ​​a and b, then the following holds: s1=α 0 A+α 0 b=a+b s2=a i ·a+α j b s3=a 2i ·a+α 2j b s4=a 3i ·a+α 3j b s5=a 4i ·a+α 4j b (5)

[0084] If there are three byte errors with byte error values ​​a, b, and c at byte error locations i, j, and k, then the following holds: s1=α 0 A+α 0 b+α 0 c=a+b+c s2=a i ·a+α j ·b+α k ·c s3=a 2i ·a+α 2j ·b+α 2k ·c s4=a 3i ·a+α 3j ·b+α 3k ·c s5=a 4i ·a+α 4j ·b+α 4k c (6)

[0085] For the considered errors the following relations are satisfied: 1.1 Regarding byte errors, s1=a≠0 (7) and

number

number

number

number

[0086] Byte error position α i and α j In the case of a double-byte error in the i-th and j-th bytes, the formula

number

number

[0087] Correspondingly, the byte error location for a single byte error is determined by the zero locations of the first order locator polynomial, which is generally given by: 1≦t≦t For t, the erroneous byte locations in the τ byte errors for the t byte error correcting code are determined by the zero locations of the τ degree locator polynomial.

[0088] If a codeword consists of N m bits, and hence N bytes, then there are N distinct byte positions that may be considered as byte error positions, whereas in the corresponding bit-correcting code there are m N bit positions that may be in error.

[0089] For one byte error a first order locator polynomial is used, and for two byte errors a second order locator polynomial is used.

[0090] Additional explanation of Reed-Solomon codes In the case of a double byte error, the byte error correction value a(i) for the i-th byte can be determined depending only on the syndrome components s1, s2, s3 and the byte position i.

[0091] Here, it is an advantage that multiple byte error correction values ​​can be determined in parallel, for example for at least three correctable bytes.

[0092] For example, assume there are two byte errors. A byte error correction value for each byte position can be determined in parallel based on the provided syndrome components s1, s2, s3 and the known positions of the correctable bytes. A byte error correction value is determined for both bytes that are erroneous and for at least the non-erroneous bytes.

[0093] The byte error correction value determined for the i-th byte position coincides with the byte error value at this i-th position.

[0094] A similarly (possibly in parallel) determined byte error location signal determines whether there is a byte error in the byte of interest and whether correction is to be performed using the byte error correction value. If the byte error location signal indicates that there is no byte error in the corresponding position, then no correction is performed using the byte error correction value determined for this position.

[0095] In other words, the byte error location signal determines at which byte location correction using the provided byte error correction value is performed: if the byte error location signal for a byte location indicates a byte error, then correction using the byte error correction value is performed; if the byte error location signal for this byte location does not indicate a byte error, then no correction is performed.

[0096] Given t byte error correcting codes, corresponding byte error correction values ​​for more than t correctable byte positions can be determined, and then a byte error location signal for (all or a portion of) the byte positions can be determined. The byte error correction values ​​can also be determined in parallel with the byte error location signal.

[0097] If there is no byte error in the i-th byte, the byte error correction value determined for this i-th byte is not used for correction based on the value of the byte error location signal. In this case, no correction is performed based on the byte error location signal, so the byte error correction value determined for this non-erroneous byte is

number

number

[0098] When there are two byte errors, for the byte error position i, the byte error correction value a(i) of the i-th byte is expressed by the formula:

number

[0099] For two byte errors, if the byte position i where the byte error occurs is known, then based on equation (13), the byte error correction value a(i) for the erroneous byte position i is determined by a value α i is determined by.

[0100] For byte position k, the byte error correction value a(k) is

number

[0101] If the byte error location signal indicates that there is a byte error at byte location k, then error correction of the kth byte is performed by the byte error correction value a(k) determined for this byte location k.

[0102] If the byte error location signal indicates that there is no byte error at byte position k, then no error correction of the kth byte is performed and the byte error correction value a(k) determined for this byte position k is not used for error correction. Optionally, the byte error correction value can be set to 0.

[0103] Thus, the byte error correction value for a byte position already exists before it is determined whether an error has actually occurred at this byte position.

[0104] Corresponding byte error correction values ​​may be determined in parallel for various byte positions, in particular for all correctable byte positions or for a subset of the correctable byte positions.

[0105] If a byte error correcting code can correct up to t erroneous bytes, then more than t byte error correction values ​​can be determined in parallel, e.g. for all correctable byte positions, or for at least a subset of t+1 correctable byte positions, regardless of whether the byte positions have a byte error or not.

[0106] The value of the byte error location signal determines whether the byte error correction value is used to correct the corresponding byte.

[0107] The correctable byte positions may be, for example, all data bytes, a subset of the data bytes, check bytes, all bytes of a codeword of the t-byte error correcting code, or a subset of the bytes of a codeword of the t-byte error correcting code.

[0108] Here, the byte error location signal can be determined, for example, with respect to a byte location, to take a first value if the byte at the byte location is erroneous, and to take a second value different from the first value if the byte at the byte location is not erroneous.

[0109] The byte error location signal can be determined using the corresponding locator polynomial.

[0110] Byte error location signal for 1 byte error For one byte error, the first order locator polynomial is x s1 = s2 (15), and the solution or zero position

number

[0111] The byte error correction value a(i) for the erroneous byte position i is a(i)=s1(17) It is.

[0112] For each kth byte, the byte error correction value a(k)=s1=a (18) is determined.

[0113] If the error in the i-th byte has a byte error correction value a, and thus s1=a, then for each byte k, a byte error correction value a(k)=a is determined according to equation (18), and the byte error correction value a(k)=a is used for the i-th byte that should actually be corrected, and is masked (e.g., set to zero) for the bytes that should not be corrected. The decision of whether a byte is corrected or not is made based on the value of the corresponding byte error location signal.

[0114] For each byte, in the case of one byte error, the byte error location signal is determined using equation (15). The byte error location signal for byte location i is -α i is 1 if it is a zero of the locator polynomial according to equation (15), -α i is 0 if it is not a zero position of the locator polynomial according to equation (15).

[0115] The correction of the i-th byte is α i This is done only if θ is a zero of the locator polynomial according to equation (15).

[0116] Byte error location signal for two-byte errors The function of the byte error location signal in correcting a double byte error will now be described based on an example.

[0117] When t-byte error correcting codes are used, where t≧2, in the case of a two-byte error, the erroneous byte positions are determined by the two zero positions of the quadratic locator polynomial according to equation (12).

[0118] If the erroneous byte positions are positions i and j, the byte error position signal is, for example, α i and α j is 1 if is a zero of the quadratic locator polynomial according to equation (12), and 0 in all other cases.

[0119] For each byte position k, the byte error correction value

number

[0120] The value of the byte error location signal for byte position k determines whether or not a correction is made at this byte position k. If the byte error location signal is 1, a correction is made, and if the byte error location signal is 0, no correction is made.

[0121] For byte position k=i, a byte error correction value a(i) is determined such that the i-th byte that is erroneous is corrected by the byte error correction value a(i). Similarly, for byte position k=j, a byte error correction value a(j) is determined such that the j-th byte that is erroneous is corrected by the byte error correction value a(j).

[0122] For all other byte positions k, where k≠i,j, there is no byte error and therefore no correction is performed for these byte positions. Even when the byte error correction value a(k) is determined to be non-zero, it is not used for correction because the byte error position signal takes the value 0 for this byte position and therefore no correction is required for this byte position.

[0123] Handling 1-byte error, 2-byte error, and 3-byte error In the following, we will explain how byte errors can be recognized and distinguished from one another. For example, consider a 2-byte error correcting code. As a supplement, we will also discuss 3-byte error recognition.

[0124] 1. Start with the case where there is only one or two byte errors. In such an example, for two byte errors, according to equation (9),

number

number

[0125] Furthermore, it is possible to distinguish the case where neither a single byte error nor a double byte error occurs. Since s1=0, it can be concluded that neither a single byte error nor a double byte error occurs.

[0126] As the probability of a 3-byte error is extremely small, it can be concluded that no errors have occurred in this case.

[0127] 2. Now consider the case where there is only 1 byte error, only 2 byte errors, or only 3 byte errors. For 3 byte errors, according to equation (11),

number

[0128] Correspondingly, for a 2-byte error or a 1-byte error,

number

[0129] If there are two byte errors, then equation (9)

number

[0130] For a single byte error, equations (7) and (8)

number

[0131] Since the condition in equation (9) also holds for 3-byte errors, it cannot be concluded from this condition alone that there are 2-byte errors.

[0132] Correcting double byte errors can be done as follows: For each byte position i, where i∈{0,1,…,N-1}, we find the value L(α i ) is determined according to the following formula:

number

[0133] L(α i If L(α )=0, the i-th byte is corrected. i If )≠0, the i-th byte is not corrected. i The byte error location signal BPs indicates whether or not correction of each byte is performed. i For example,

number

[0134] Galois field GF(2 m) circuit configurations employ, for example, multipliers, constant multipliers, squarers, power (cube) generators, etc. The circuit-technical implementation of each such operation is known. In the following, by way of example, it is described how a multiplier, a squarer, a cube generator, and a constant multiplier can be realized in a Galois field that is determined, for example, by a remainder polynomial. For example, it is assumed that m=5, a byte consists of m=5 bits, and the corresponding Galois field is GF(2 5 ).

[0135] Galois field GF(2 m ) Example For example, m=5 is chosen and the underlying Galois field GF(2 m )=GF(2 5 )=GF(32) contains a total of 32 elements.

[0136] The elements of the Galois field GF(32) are shown in various representations in Figure 13. The remainder polynomial in the Galois field GF(32) is the polynomial p(x)=1+x 2 +x 5 It is.

[0137] The first column of the table shown in FIG. 13 is the exponential representation (also called the exponential function representation) of GF(2 5 ) element α i ≠ 0. The zero element of the field does not have an exponential representation. In the second column of the table, all elements are listed with their polynomial representation with respect to the associated remainder polynomial p(x). The third column of the table lists all elements in GF(2 5 ), the vector representation of the elements of the polynomial representation can be read directly from the polynomial representation, where the five components of the vector representation are, from left to right, the coefficients of the associated power in the polynomial representation. x 0 ,x 1 ,x 2 ,x 3 ,x 4 Corresponds to.

[0138] The corresponding polynomial expression is [x i mod (1+x 2 +x 5 )], the power expression α i For example, the polynomial expression for α5 is x 5 mod (1+x 2 +x 5 )=1+x 2 Since this is true, 1+x 2 It is.

[0139] Multiplication of two elements of a Galois field can be done in exponential or polynomial representation. In the Galois field GF(2 m )=GF(2 5 ) are expressed as exponential expressions α i and α j Then, their product is: α i α j = α k Where: k = (i + j) mod (2 m -1)=(i+j) mod 31

[0140] When the elements to be multiplied in the Galois field are vector expressions or polynomial expressions, their multiplication can be performed by a Galois field multiplier. In the following, we will take the multiplication of two elements in polynomial expressions as an example. In the Galois field GF(2 m )=GF(2 5 ), one can multiply two elements of each other in the usual way, directly, and determine the result as the remainder of the remainder polynomial.

[0141] For example, the polynomial 1+x 2 +x 3 and x+x 3 , which gives us their direct multiplication (1+x 2 +x 3 )(x+x3 )=x+x 4 +x 5 +x 6 is obtained.

[0142] x 5 =1+x 2 mod (1+x 2 +x 5 ) and x 6 =x+x 3 mod (1+x 2 +x 5 ) Due to x+x 4 +x 5 +x 6 =x+x 4 +1+x 2 +x+x 3 =1+x 2 +x 3 +x 4 It becomes.

[0143] Therefore, as a result, (1+x 2 +x 3 )·(x+x 3 )=1+x 2 +x 3 +x 4 holds true.

[0144] Below, the remainder polynomial m(x)=x 5 +x 2 +1 Galois field GF(2 5 ), the first element a(x) a(x)=a4x 4 +a3x 3 +a2x 2 +a1x+a0 and the second element b(x) b(x)=b4x 4 +b3x 3 +b2x 2 +b1x+b0 When polynomials a(x) and b(x) are multiplied directly, we first obtain an 8th degree polynomial. x 5 mod (1+x 2 +x 5 )=1+x 2 , x 6 mod (1+x 2 +x 5 )=x+x 3 , x 7 mod (1+x 2 +x 5 )=x 2 +x 4 , x 8 mod (1+x 2 +x 5 )=1+x 2 +x 3 This gives us a fourth-order polynomial as follows: c4x 4 +c3x 3 +c2x 2 +c1x 1 +c0=a(x)·b(x) mod m(x)= =(a0b4+a1b3+a2b2+a3b1+a3b4+a4b0+a4b3)·x 4 + +(a0b3+a1b2+a2b1+a2b4+a3b0+a3b3+a4b2+a4b4)·x 3 + +(a0b2+a1b1+a1b4+a2b0+a2b3+a3b2+a3b4+a4b1+a4b3+a4b4)·x 2 + +(a0b1+a1b0+a2b4+a3b3+a4b2)·x 1 + +(a0b0+a1b4+a2b3+a3b2+a4b1+a4b4)

[0145] This relationship is realized by a Galois field multiplier having five first binary inputs, five second binary inputs, and five binary outputs, as described in detail below.

[0146] The first five inputs of the Galois field multiplier are input with binary values ​​a0, a1, a2, a3, a4, the second five inputs are input with binary values ​​b0, b1, b2, b3, b4, and the five binary outputs are output with values ​​c0, c1, c2, c3, c4, where: (a0b0+a1b4+a2b3+a3b2+a4b1+a4b4)=c0, (22) (a0b1+a1b0+a2b4+a3b3+a4b2)=c1(23) (a0b2+a1b1+a1b4+a2b0+a2b3+a3b2+a3b4+a4b1+a4b3+a4b4)=c2(24) (a0b3+a1b2+a2b1+a2b4+a3b0+a3b3+a4b2+a4b4)=c3(25) (a0b4+a1b3+a2b2+a3b1+a3b4+a4b0+a4b3)=c4(26) Here, the sign "+" represents mod 2 addition (XOR operation).

[0147] The implementation of equations (22) to (26) can be performed by a Galois field multiplier, for example, using AND gates and XOR gates (exclusive OR gates). For example, a synthesis tool can be used within the scope of the implementation.

[0148] If an element of a Galois field is squared, the element can be multiplied by itself. a(x)=a0+a1x 1 +a2x 2 +a3x 3 +a4x 4 If given as (a(x)) 2 mod m(x) = =[a0+a1x 2 +a2x 4 +a3x 6 +a4x 8 ] mod (1+x 2 +x 5 )= =(a2)x4 +(a3+a4)x 3 +(a1+a4)x 2 +a3x 1 +(a0+a4) holds true.

[0149] Correspondingly, the Galois field GF(2 5 The squaring of the elements in a can be realized by a squarer having five binary inputs and five binary outputs. The five binary inputs are fed with binary values ​​a0, a1, a2, a3, a4, and the five binary outputs provide binary values ​​d0, d1, d2, d3, d4. a0+a4=d0, (27) a3=d1, (28) a1+a4=d2, (29) a3+a4=d3, (30) a2=d4, (31) where the sign "+" again indicates mod 2 addition (XOR operation).

[0150] Remainder polynomial m(x)=1+x 2 +x 5 Galois field GF(2 5 To realize a squarer in , equations (27)-(31) can be implemented, for example, by XOR gates.

[0151] Galois field GF(2 5 ) to illustrate how we can determine the cube of an element given a polynomial expression.

[0152] polynomial a(x)=a0+a1x 1 +a2x 2 +a3x 3 +a4x 4 cubed(a(x)) 3 is the remainder polynomial m(x)=1+x 2 +x 5 If the remainder of (a(x)) 3mod m(x) = =(a0a2+a0a4+a1a2+a1a3+a1a4+a2a3+a2a4+a3+a3a4)·x 4 + +(a0a4+a1+a2+a2a3+a2a4+a3+a4)·x 3 + +(a0a1+a0a2+a0a4+a1a2+a2a4+a3a4+a4)·x 2 + +(a0a1+a0a3+a2+a3+a3a4+a4)·x 1 + +(a0+a0a4+a1a2+a1a3+a2a3)

[0153] Correspondingly, the Galois field GF(2 5 ) can be realized by a cube generator with five binary inputs and five binary outputs. The five binary inputs are fed with binary values ​​a0, a1, a2, a3, a4, and the five binary outputs provide binary values ​​f0, f1, f2, f3, f4. f0=a0+a0a4+a1a2+a1a3+a2a3(32) f1=a0a1+a0a3+a2+a3+a3a4+a4(33) f2=a0a1+a0a2+a0a4+a1a2+a2a4+a3a4+a4(34) f3=a0a4+a1+a2+a2a3+a2a4+a3+a4(35) f4=a0a2+a0a4+a1a2+a1a3+a1a4+a2a3+a2a4+a3+a3a4(36) holds true.

[0154] For example, the cube generator is the remainder polynomial m(x)=1+x 2 +x 5 Galois field GF(2 5 This can be achieved by simply implementing equations (32)-(36) in

[0155] Alternatively, the cube generator can be realized from a squarer and a Galois field multiplier connected downstream, and higher powers of the element a(x) can be realized in a corresponding manner using appropriate components.

[0156] Galois field GF(2 m ) is described below for m=5 as an example. The remainder polynomial is m(x)=1+x 2 +x 5 It is.

[0157] a∈GF(2 5 ), then any element of the Galois field can be expressed by the following polynomial expression: a(x)=a0+a1x+a2x 2 +a3x 3 +a4x 4 (37)

[0158] For example, α 9 is selected and its polynomial representation is given by: α 9 (x)=x+x 3 +x 4 (38) As a multiplication, a(x) α 9 (x) mod (1+x 2 +x 5 )=b0+b1x+b2x 2 +b3x 3 +b4x 4 (39) is obtained, b0=a1+a2, (40) b1=a0+a2+a3, (41) b2=a2+a3+a4, (42) b3=a0+a3+a4, (43) b4=a0+a1+a4(44) It is.

[0159] The output values b0, …, b4 can be derived from the input values a0, …, a4 corresponding to the relationships represented by formulas (40) to (44), and the output values are determined by the XOR operation from the input values. Here, the symbol “+” indicates modulo 2 addition (XOR operation). Correspondingly, the constant multiplier can be realized by an XOR gate.

[0160] Explanation of the byte error position signal generator for generating the byte error position signal FIG. 1 shows an exemplary circuit configuration for determining the byte error position signal. For example, consider a two-byte error correcting error code having a codeword consisting of n bytes each having m bits.

[0161] The circuit configuration has N byte error position signal generators 10, 11, …, 1i, …, 1N-1, and the byte error position signal generators 10, 11, …, 1i, …, 1N-1 provide byte error position signals BPs0, BPs1, …, BPs i , …, BPs N-1 through their respective 1-bit wide outputs.

[0162] To the 4·m-bit wide inputs of each of the N byte error position signal generators 10, 11, …, 1i, …, 1N-1, an error syndrome s = s1, s2, s3, s4 of 4·m-bit width provided by a syndrome generator (not shown in FIG. 1) is provided, and this error syndrome consists of syndrome components s1, s2, s3, s4 each of m-bit width.

[0163] When all bytes are corrected in the case of one error, N = n holds. When less than n bytes are corrected in the case of one error, N < n holds. For example, in the case of an error, only the data bytes can be corrected. In such an example, the check bytes cannot be corrected.

[0164] The byte error position signal generator 10 is configured, for example, as follows. - The byte error position signal generator 10

number

number

[0165] The byte error position signal generator 11 is configured, for example, as follows. The byte error location signal generator 11

number

number

[0166] The byte error position signal generator 1i is configured, for example, as follows. The byte error location signal generator 1i

number

number

[0167] The byte error position signal generator 1N-1 is configured, for example, as follows. The byte error location signal generator 1N-1

number

number

[0168] where α mod 2 m Each exponent of -1 can be interpreted as:

[0169] If there are two byte errors and the jth byte and the kth byte are erroneous, the byte error location signals BPs for i=j and for i=k are i is 1, and all remaining byte error location signals BPs l is 0, where 0≦i,j,k,l≦N-1, α 0 =1 holds true, 1 is in the Galois field GF(2 m ) is the identity element of

[0170] Byte error location signal generator according to FIG. FIG. 2 shows a circuit arrangement illustrating a possible implementation of the circuit arrangement shown in FIG.

[0171] The byte error location signal generator 10 shown in FIG. a subcircuit 210 having one 4·m-bit wide input for receiving the components s1, s2, s3 and s4 of an error syndrome s=s1, s2, s3, s4 and three m-bit wide outputs, a constant multiplier 220 having a first m-bit wide input, a second m-bit wide input, and one m-bit wide output; a constant multiplier 230 having a first m-bit wide input, a second m-bit wide input, and one m-bit wide output; an XOR circuit 240 having three inputs each having a width of m bits and an output having a width of m bits; a NOR circuit 250 having one m-bit wide input and one 1-bit wide binary output;

[0172] When the error syndrome s is input, the subcircuit 210 performs the following: -The first output outputs s1·s4+s2·s3, - On the second output,

number

number

[0173] A first output of the partial circuit 210 is connected to a first input of a constant multiplier 220. A second input of the constant multiplier 220 is connected to a constant α 0 = 1, so that at the output of the constant multiplier 220, α 0 (s1 s4 + s2 s3) = s1 s4 + s2 s3 is provided.

[0174] The output of the constant multiplier 220 is connected to a first input of the XOR circuit 240 .

[0175] The second output of the partial circuit 210 is connected to a first input of a constant multiplier 230. The second input of the constant multiplier 230 is connected to a constant α 2·0 = α 0 is input, which results in the output of the constant multiplier 230 being:

number

[0176] The output of the constant multiplier 230 is connected to a second input of the XOR circuit 240 .

[0177] A third output of the partial circuit 210 is connected to a third input of the XOR circuit 240 .

[0178] The XOR circuit 240 generates, for example, a component-wise XOR operation of the m-bit wide values ​​input to its three inputs, and outputs the m-bit wide value

number

[0179] The byte error location signal generator 11 shown in FIG. a subcircuit 211 having one 4·m-bit wide input for inputting the components s1, s2, s3 and s4 of the error syndrome s=s1, s2, s3, s4 and three m-bit wide outputs, a constant multiplier 221 having a first m-bit wide input, a second m-bit wide input and one m-bit wide output; a constant multiplier 231 having a first m-bit wide input, a second m-bit wide input and one m-bit wide output; an XOR circuit 241 having three inputs each having a width of m bits and an output having a width of m bits; - a NOR circuit 251 having one m-bit wide input and one 1-bit wide binary output

[0180] When the error syndrome s is input, the partial circuit 211 performs the following: -The first output outputs s1·s4+s2·s3, - On the second output,

number

number

[0181] A first output of the partial circuit 211 is connected to a first input of a constant multiplier 221. A second input of the constant multiplier 221 is connected to a constant α 1 is input, so that at the output of the constant multiplier 221, α 1 (s1 s4 + s2 s3) is provided.

[0182] The output of the constant multiplier 221 is connected to a first input of the XOR circuit 241 .

[0183] The second output of the partial circuit 211 is connected to a first input of a constant multiplier 231. The second input of the constant multiplier 231 is connected to a constant α 2 is input, so that at the output of the constant multiplier 231,

number

[0184] The output of the constant multiplier 231 is connected to a second input of the XOR circuit 241 .

[0185] A third output of the partial circuit 211 is connected to a third input of the XOR circuit 241 .

[0186] The XOR circuit 241 generates, for example, an XOR operation for each component of the m-bit-wide values ​​input to its three inputs, and outputs the m-bit-wide value

number

[0187] The byte error location signal generator 1i shown in FIG. a subcircuit 21i having one 4·m-bit wide input for inputting the components s1, s2, s3 and s4 of the error syndrome s=s1, s2, s3, s4 and three m-bit wide outputs, a constant multiplier 22i having a first m-bit wide input, a second m-bit wide input and one m-bit wide output, a constant multiplier 23i having a first m-bit wide input, a second m-bit wide input and one m-bit wide output, an XOR circuit 24i having three inputs each having a width of m bits and an output having a width of m bits, - a NOR circuit 25i having one m-bit wide input and one 1-bit wide binary output;

[0188] When the error syndrome s is input, the partial circuit 21i performs the following: -The first output outputs s1·s4+s2·s3, - On the second output,

number

number

[0189] The first output of the partial circuit 21i is connected to the first input of the constant multiplier 22i. The second input of the constant multiplier 22i is connected to the constant α iis input, so that at the output of the constant multiplier 22i, α i (s1 s4 + s2 s3) is provided.

[0190] The output of the constant multiplier 22i is connected to a first input of the XOR circuit 24i.

[0191] The second output of the partial circuit 21i is connected to the first input of the constant multiplier 23i. The second input of the constant multiplier 23i is connected to the constant α 2·i is input, so that at the output of the constant multiplier 23i,

number

[0192] The output of the constant multiplier 23i is connected to the second input of the XOR circuit 24i.

[0193] A third output of the partial circuit 21i is connected to a third input of the XOR circuit 24i.

[0194] The XOR circuit 24i generates, for example, an XOR operation for each component of the m-bit-wide value input to its three inputs, and outputs the m-bit-wide value

number

[0195] The byte error location signal generator 1N-1 shown in FIG. a subcircuit 21N-1 having one 4·m-bit wide input for inputting the components s1, s2, s3 and s4 of the error syndrome s=s1, s2, s3, s4 and three m-bit wide outputs, a constant multiplier 22N-1 having a first m-bit wide input, a second m-bit wide input, and one m-bit wide output; a constant multiplier 23N-1 having a first m-bit wide input, a second m-bit wide input, and one m-bit wide output; an XOR circuit 24N-1 having three inputs each having a width of m bits and an output having a width of m bits, - a NOR circuit 25N-1 having one m-bit wide input and one 1-bit wide binary output

[0196] When the error syndrome s is input, the partial circuit 21N-1 performs the following: -The first output outputs s1·s4+s2·s3, - On the second output,

number

number

[0197] A first output of the partial circuit 21N-1 is connected to a first input of a constant multiplier 22N-1. A second input of the constant multiplier 22N-1 is connected to a constant α N-1 is input, so that at the output of the constant multiplier 22N-1, α N-1 (s1 s4 + s2 s3) is provided.

[0198] The output of the constant multiplier 22N-1 is connected to a first input of the XOR circuit 24N-1.

[0199] The second output of the partial circuit 21N-1 is connected to the first input of the constant multiplier 23N-1. The second input of the constant multiplier 23N-1 is connected to the constant α 2·(N-1) is input, so that at the output of the constant multiplier 23N-1,

number

[0200] The output of the constant multiplier 23N-1 is connected to a second input of the XOR circuit 24N-1.

[0201] A third output of the partial circuit 21N-1 is connected to a third input of the XOR circuit 24N-1.

[0202] The XOR circuit 24N-1 generates, for example, an XOR operation for each component of the m-bit-wide values ​​input to its three inputs, and outputs the m-bit-wide value

number

[0203] Exemplary synthesis of subcircuits 2 are functionally identical, and therefore, it is possible to integrate these sub-circuits into the sub-circuit 31.

[0204] 3 shows a sub-circuit 31 that integrates sub-circuits 210, 211, ..., 21i, ..., 21N-1. The remainder of the circuit portion shown in FIG. 3 is identical to FIG.

[0205] For example, the byte error location signal generators 10, 11, . . . , 1i, . . . , 1N-1 according to FIG.

[0206] Exemplary implementation of subcircuit 31 FIG. 4 shows a possible implementation of the subcircuit 31 shown in FIG.

[0207] The subcircuit 31 has four m-bit wide inputs for inputting the components s1, s2, s3, s4 constituting the syndrome s. Furthermore, four multipliers 41, 42, 44, and 47 each having two m-bit wide inputs and one m-bit wide output, two squarers 45 and 48 each having one m-bit wide input and one m-bit wide output, and three XOR circuits 43, 46, and 49 each having two m-bit wide inputs and one m-bit wide output are provided.

[0208] The XOR circuits 43, 46, and 49 each perform a component-wise XOR operation on the m component values ​​input to their respective inputs. m ) and the squarer performs multiplication in the Galois field GF(2 m ) and square it.

[0209] The input delivering the component s1 is connected to a first input of a multiplier 41 and to a first input of a multiplier 44 .

[0210] The input delivering the component s2 is connected to a first input of a multiplier 42, to a first input of a multiplier 47 and to an input of a squarer 45.

[0211] The input delivering component s3 is connected to a second input of multiplier 42, to a second input of multiplier 44 and to an input of squarer 48.

[0212] The input delivering component s 4 is connected to a second input of multiplier 41 and to a second input of multiplier 47 .

[0213] The output of the multiplier 41 is connected to a first input of an XOR circuit 43. The output of the multiplier 42 is connected to a second input of the XOR circuit 43. At the output of the XOR circuit 43 the signal s1s4+s2s3 is provided.

[0214] The output of the multiplier 44 is connected to a first input of an XOR circuit 46. The output of the squarer 45 is connected to a second input of the XOR circuit 46. At the output of the XOR circuit 46, the signal

number

[0215] The output of the multiplier 47 is connected to a first input of an XOR circuit 49. The output of the squarer 48 is connected to a second input of the XOR circuit 49. At the output of the XOR circuit 49, the signal

number

[0216] Byte error correction value for 2 byte errors 5 shows an exemplary circuit for generating byte error correction values ​​for a total of N bytes in the case of two byte errors. The N bytes under consideration are numbered 0 to N-1.

[0217] Byte error correction value a(i) for the i-th byte (0≦i≦N-1) cor is the actual error syndrome s, byte position i, and byte error position signal BPs i Depending on a(i) cor =BPs i a(i) is determined in accordance with

[0218] For example, a byte error correction value is determined for all N byte positions. For byte positions that are not erroneous, the byte error correction value is masked. For example, the masking is performed by multiplying the byte error correction value by a byte error position signal having a value of 0.

[0219] If there are two byte errors in byte positions i and j, then the i-th and j-th bytes can be corrected by denoting the i-th and j-th bytes by the corresponding byte error correction value a(i). cor = a(i) ≠ 0 or a(j) cor This is done by XORing each component with a(j) = a(j) ≠ 0.

[0220] Bytes that are not erroneous are not corrected. For this purpose, for those byte positions, a byte error correction value is set to 0 (e.g., multiplication of the byte error correction value and 0 as described above), and then the bytes to be corrected are component-wise XORed with this value 0. XORing with the value 0 leaves the original value unchanged.

[0221] For the i-th erroneous byte, the byte error location signal is BPs i = 1, a(i) cor =BPs i a(i)=a(i) holds true.

[0222] For the jth erroneous byte, the byte error location signal is BPsj=1; a(j) cor =BPsj·a(j)=a(j) holds true.

[0223] For the kth (k ≠ i, j) non-erroneous byte, the byte error location signal is BPsk = 0, a(k) cor =BPsk·a(k)=0.

[0224] If the kth (k ≠ i,j) byte is not erroneous, then it is not corrected. This can be achieved by component-wise XORing the kth byte with a value of 0, leaving the value of the kth byte unchanged, following the example shown in Figure 5. The byte error location signal thereby masks the byte error correction value to 0, and therefore no correction is made.

[0225] In the case of two byte errors, if the first byte error is in byte position j and the second byte error is in byte position k, then the byte error correction value a(j) cor and a(k) cor is not 0, and the byte error correction value a(i) for i ≠ j, k cor are 0. In this case, BPsj=BPsk=1 and BPs i =0 (for i ≠ j, k) also holds true.

[0226] Figure 5 shows a single 4 m-bit wide (or 4 m-dimensional) input for inputting the error syndrome s, and byte error location signals BPs0, BPs1, …, BPs i , …, BPs N-1 , BPs0, BPs1, ..., BPs i , …, BPs N-1 , 1N-1 for generating N byte error location signal generators 10, 11, . . . , 1i, . . . , 1N-1.

[0227] FIG. 5 further illustrates N byte error correction value generators 510, 511, ..., 51i, ..., 5N-1, which a first 1-bit wide input for receiving a byte error location signal; a second 3 m-bit wide input for inputting the components s1, s2, s3 of the error syndrome s; - the byte error correction value a(0) for the corresponding byte position cor , a(1) cor , …, a(i) cor , …, a(N-1) cor and m-bit wide output for outputting Each of them has:

[0228] 5 further includes N XOR circuits 520, 521, . . . , 52i, . . . , 52N-1, which are - a first input of width m bits for receiving a corresponding byte error correction value; a second m-bit wide input for inputting the corresponding byte to be corrected; and m-bit wide outputs for outputting corrected bytes each m-bit wide.

[0229] The actual error syndrome s is input to a 4·m-bit wide input of the byte error location signal generator 10. A 1-bit wide output of the byte error location signal generator 10, which is connected to a first input of the byte error correction value generator 510, outputs the byte error location signal BPs0.

[0230] A second 3·m-bit wide input of the byte error correction value generator 510 receives the components s1, s2, and s3 of the error syndrome s. The byte error correction value generator 510 outputs a byte error correction value a(0) cor The output of the byte error correction value generator 510 is connected to a first input of an XOR circuit 520. A second input of the XOR circuit 520 provides the byte value of the 0th byte, which may be erroneous.

number

number

number

[0231] The actual error syndrome s is input to a 4·m-bit wide input of the byte error location signal generator 11. A 1-bit wide output of the byte error location signal generator 11, which is connected to a first input of the byte error correction value generator 511, outputs the byte error location signal BPs1.

[0232] The second 3·m-bit wide input of the byte error correction value generator 511 receives the components s1, s2, and s3 of the error syndrome s. The byte error correction value generator 511 outputs a byte error correction value a(1) cor The output of the byte error correction value generator 511 is connected to a first input of an XOR circuit 521. A second input of the XOR circuit 521 is connected to the byte value of the first byte that may be erroneous.

number

number

number

[0233] The actual error syndrome s is input to a 4·m-bit wide input of the byte error location signal generator 1i. A byte error location signal BPs is generated at a 1-bit wide output of the byte error location signal generator 1i, which is connected to a first input of the byte error correction value generator 51i. i will be output.

[0234] The second 3·m-bit wide input of the byte error correction value generator 51i receives the components s1, s2, and s3 of the error syndrome s. The byte error correction value generator 51i outputs a byte error correction value a(i) cor The output of the byte error correction value generator 51i is connected to a first input of an XOR circuit 52i. A second input of the XOR circuit 52i is connected to the byte value of the i-th byte that may be erroneous.

number

number

number

[0235] The actual error syndrome s is input to a 4 m-bit wide input of the byte error location signal generator 1N-1. The byte error location signal BPs is output at a 1-bit wide output of the byte error location signal generator 1N-1, which is connected to a first input of the byte error correction value generator 51N-1. N-1 will be output.

[0236] The second 3·m-bit wide input of the byte error correction value generator 51N-1 receives the components s1, s2, and s3 of the error syndrome s. The byte error correction value generator 51N-1 outputs a byte error correction value a(N-1) corThe output of the byte error correction value generator 51N-1 is connected to a first input of an XOR circuit 52N-1. A second input of the XOR circuit 52N-1 is connected to the byte value of the (N-1)th byte that may be erroneous.

number

number

number

[0237] Thus, the byte corrector 530 includes a byte error location signal generator 10 and a byte error correction value generator 510, the byte corrector 531 includes a byte error location signal generator 11 and a byte error correction value generator 511, the byte corrector 53i includes a byte error location signal generator 1i and a byte error correction value generator 51i, and the byte corrector 53N-1 includes a byte error location signal generator 1N-1 and a byte error correction value generator 51N-1. Correspondingly, the byte correctors 530, 531, ..., 53i, ..., 53N-1 can be referred to as byte correctors for two-byte errors.

[0238] In this example, the byte corrector for the two byte errors outputs a byte error correction value for the two byte positions that are in error. For byte positions that have no error, the byte error correction value is 0.

[0239] For the erroneous byte position i, a(i) cor = a(i) holds true.

[0240] For the non-erroneous byte position j, a(j) cor =0 holds true.

[0241] where a(i) is the byte error correction value of the i-th byte.

[0242] To concretely illustrate that the byte error location signal generator generates a corresponding byte error location signal according to the four components s1, s2, s3, s4 of the error syndrome s, and the byte error correction value generator generates a corresponding byte error correction value according to the three components s1, s2, s3 of this error syndrome s, two input lines are shown by way of example in Fig. 5, namely an input line for inputting the components s1, s2, s3, s4 and a further input line for inputting the components s1, s2, s3. These lines can also be integrated with respect to the components s1, s2, s3.

[0243] For r=0,...,N-1, the byte error correction value generator 51r calculates, in the case of two byte errors, at its m-bit wide output, which is connected to a first m-bit wide input of the XOR circuit 52r,

number

[0244] In the case of a two-byte error, if the j-th and k-th bytes are erroneous, a byte error correction value generator 51j generates a byte error correction value

number

number

[0245] Byte Error Correction Value Generator FIG. 6 shows a possible implementation of a byte error correction value generator 51r, where r can take values ​​from 0 to N-1.

[0246] The byte error correction value generator 51r is - two multipliers 61, 66 each having a first and a second m-bit wide input and an m-bit wide output; - two XOR circuits 63, 64 each having a first m-bit wide input, a second m-bit wide input and an m-bit wide output; a constant multiplier 67 having first and second m-bit wide inputs and an m-bit wide output, the second input being coupled to a constant value α 2r a constant multiplier 67 to which - a squarer 62 having an m-bit wide input and an m-bit wide output; - an inverter circuit 65 having an m-bit wide input and an m-bit wide output; an AND circuit 68 having a first 1-bit wide input, a second m-bit wide input, and an m-bit wide output; Includes.

[0247] The value of component s1 is input to a first input of multiplier 61, and the value of component s3 is input to a second input of multiplier 61. Multiplier 61 is a Galois field GF(2 m ) generates a value s1·s3, and outputs the value s1·s3 at its output. The output of the multiplier 61 is connected to a first input of the XOR circuit 63.

[0248] A second input of the XOR circuit 63 is connected to the output of the squarer 62, to whose input the value of the component s2 is input. Thus, the squarer 62 outputs the value

number

number

[0249] The value of the component s3 is input to a first input of the XOR circuit 64. The value of the component s1 is input to a first input of the constant multiplier 67, and the value of the constant α 2r The constant multiplier 67 is a Galois field GF(2 m ) and the operation α 2r · s1. A constant multiplier can be implemented using, for example, an XOR gate.

[0250] The output of XOR circuit 64 is the value s3+α 2r s1 is provided to the input of inverter 65, which outputs the value

number

[0251] The output of inverter 65 is connected to a first input of multiplier 66, which therefore produces at its output the value

number

[0252] The AND circuit implements a bitwise AND operation of the m bits input to its second input and the byte error location signal BPsr, thereby providing at its output the value

number

[0253] Byte Error Correction Value Generator, Alternative Embodiment Figure 7 shows a further possible form of the byte error correction value generator 51r, described for the rth byte in the same way as in Figure 6, where r can take values ​​from 0 to (N-1).

[0254] The byte error correction value generator 51r shown in FIG. three multipliers 71, 75, 76 each having a first m-bit wide input, a second m-bit wide input and an m-bit wide output; - two XOR circuits 72, 77 each having a first input m bits wide, a second input m bits wide and an output m bits wide; a constant multiplier 78 having a first m-bit wide input, a second m-bit wide input, and an m-bit wide output, the second input being coupled to a constant value α 2r a constant multiplier 78 to which - a squarer 73 having an m-bit wide input and an m-bit wide output; - two inverters 74, 79 having an m-bit wide input and an m-bit wide output; an AND circuit 710 having a first 1-bit wide input, a second m-bit wide input, and an m-bit wide output; Includes.

[0255] The value of component s1 is input to a first input of multiplier 71, and the value of component s3 is input to a second input of multiplier 71. Multiplier 71 is a Galois field GF(2 m ) to generate the value s1·s3 and provide at its output the value s1·s3. The output of the multiplier 71 is connected to a first input of an XOR circuit 72.

[0256] A second input of the XOR circuit 72 is connected to the output of a squarer 73, the input of which receives the value of the component s2. Thus, the squarer 73 outputs the value

number

number

number

[0257] The output of the inverter 74 is connected to a first input of a multiplier 75, and the value of the component s3 is input to a second input of the multiplier 75. Furthermore, the output of the inverter 74 is connected to a first input of a multiplier 76, and the value of the component s1 is input to a second input of the multiplier 76.

[0258] Multiplier 76 has at its output the value

number

number

[0259] Multiplier 75 produces at its output the value

number

[0260] The output of the constant multiplier 78 is connected to a second input of the XOR circuit 77 which outputs the value

number

[0261] Inverter 79 has at its output the value

number

[0262] The value of the byte error location signal BPsr is input to a first input of the AND circuit 710. The AND circuit 710 performs a bitwise AND operation between the m bits input to its second input and the byte error location signal BPsr. As a result, the AND circuit 710 outputs the value

number

[0263] The portion shown in FIG. 7 including multipliers 71, 75, 76, XOR circuit 72, and squarer 73, produces a value at the output of multipliers 75 and 76.

number

number

[0264] It is an option to realize the byte error correction value generator using up to three multiplications for the correctable byte positions, for example for all correctable byte positions or for a portion of the correctable byte positions, where the three multiplications can be implemented using three multipliers. It is also an option to perform a further multiplication by a constant, in particular by a constant multiplier.

[0265] Correcting 1-byte and 2-byte errors, Fig. 8 FIG. 8 shows exemplary circuits for correcting one-byte errors and two-byte errors, where these circuits can be used to determine a byte error location signal for a two-byte error and to correct the two-byte error.

[0266] The circuit shown in FIG. - If there is a 2-byte error, the 2-byte error is corrected, - If there is a 1 byte error, the 1 byte error is corrected, -If there is no error, no correction will be made It is structured as follows.

[0267] For this reason, Fig. 8 N byte error correction value generators 810, ..., 81i, ..., 81N-1 for correcting one byte error, each having a 2 m-bit wide input for inputting the components s1, s2 and an m-bit wide output for outputting an m-bit wide byte error correction value; N byte correctors 530, ..., 53i, ..., 53N-1 for correcting double byte errors (as described in FIG. 5), each having a 4·m-bit wide input for inputting the components s1, s2, s3, s4 and an m-bit wide output for outputting an m-bit wide byte error correction value, - N multiplexers 820, ..., 82i, ... 82N-1, - a first m-bit wide input (0 input), - a second m-bit wide input (1 input), a 1-bit wide control input capable of receiving a binary control signal st, and -m bit wide output N multiplexers 820, ..., 82i, ..., 82N-1 each having N AND circuits 830, ..., 83i, ..., 83N-1 each having a first 1-bit wide input for receiving a binary error signal E, a second m-bit wide input, and an m-bit wide output; N XOR circuits 840, ..., 84i, ..., 84N-1 each having a first m-bit wide input, a second m-bit wide input, and an m-bit wide output; Includes.

[0268] A line 85 carries the components s1, s2 and is connected to the inputs of each of the byte error correction value generators 810, . . . , 81i, . . . , 81N-1.

[0269] A line 86 carries the components s1, s2, s3, s4 and is connected to the inputs of each of the byte correctors 530, . . . , 53i, . . . , 53N-1.

[0270] The byte error correction value generator 810 outputs the 0th byte in error in the case of a 1-byte error at byte position 0.

number

number

number

[0271] A possible implementation of a byte error correction value generator for correcting one byte error is described in relation to FIG.

[0272] Regarding possible implementations of the byte correctors 530 to 53N-1, for example, there may be mentioned the position signal generator described in relation to FIG. 2 and the byte error correction value generator described in relation to FIG. 6 and FIG.

[0273] The output of the byte error correction value generator 810 is connected to a first input of a multiplexer 820. The output of the byte corrector 530 is connected to a second input of the multiplexer 820. If the value of the control signal st is 0, the multiplexer 820 connects its 0 input (first input) to its output. If the value of the control signal st is 1, the multiplexer 820 connects its 1 input (second input) to its output.

[0274] A first input of the AND circuit 830 receives the binary error signal E. An output of the multiplexer 820 is connected to a second input of the AND circuit 830. An output of the AND circuit 830 is connected to a first input of the XOR circuit 840. A second input of the XOR circuit 840 receives a possibly erroneous byte.

number

number

[0275] The AND circuit 830 enables a component-by-component AND operation of an m-digit value input to its second input and an error signal E. If the error signal E=0, the AND circuit 830 outputs an m-component value of 0. If the error signal E=1, the AND circuit 830 outputs the value input to its second input.

[0276] These embodiments apply to the remaining byte positions as well.

[0277] The output of the byte error correction value generator 81i is connected to a first input of the multiplexer 82i. The output of the byte error correction value generator 53i is connected to a second input of the multiplexer 82i. When the value of the control signal st is 0, the multiplexer 82i connects its 0 input (first input) to its output. When the value of the control signal st is 1, the multiplexer 82i connects its 1 input (second input) to its output.

[0278] A binary error signal E is input to a first input of the AND circuit 83i. An output of the multiplexer 82i is connected to a second input of the AND circuit 83i. An output of the AND circuit 83i is connected to a first input of the XOR circuit 84i. A second input of the XOR circuit 84i is connected to a byte that may be erroneous.

number

number

[0279] The AND circuit 83i enables an AND operation for each component between an m-digit value input to its second input and an error signal E. When the error signal E=0, the AND circuit 83i outputs an m-component value of 0. When the error signal E=1, the AND circuit 83i outputs the value input to its second input.

[0280] The output of the byte error correction value generator 81N-1 is connected to a first input of the multiplexer 82N-1. The output of the byte error correction value generator 53N-1 is connected to a second input of the multiplexer 82N-1. When the value of the control signal st is 0, the multiplexer 82N-1 connects its 0 input (first input) to its output. When the value of the control signal st is 1, the multiplexer 82N-1 connects its 1 input (second input) to its output.

[0281] A first input of the AND circuit 83N-1 receives the binary error signal E. An output of the multiplexer 82N-1 is connected to a second input of the circuit 83N-1. An output of the AND circuit 83N-1 is connected to a first input of the XOR circuit 84N-1. A second input of the XOR circuit 84N-1 receives a possibly erroneous byte.

number

number

[0282] The AND circuit 83N-1 enables an AND operation for each component between an m-digit value input to its second input and the error signal E. When the error signal E=0, the AND circuit 83N-1 outputs an m-component value of 0. When the error signal E=1, the AND circuit 83N-1 outputs the value input to its second input.

[0283] The error signal E is - If a 1-byte error or 2-byte error occurs, the value is 1. If no error occurs, it takes the value 0.

[0284] The control signal st is - If a byte error occurs, the value is 0. If a -2 byte error occurs, the value is 1.

[0285] Circuit for correcting three or more byte errors. Figure 9 shows a circuit for correcting 1 byte error, 2 byte error, ..., t byte error, in which the elements described in Figure 8 can be used in a similar manner.

[0286] The circuit shown in FIG. - If there is a 1 byte error, the 1 byte error is corrected, - If there is a 2-byte error, the 2-byte error is corrected, -Similarly, -If there is a t byte error, the t byte error is corrected, -If there is no error, no correction will be made This makes it possible.

[0287] As an example, consider the case where t byte error correcting and (t+1) byte error detecting codes are used, where in particular t>2.

[0288] The circuit according to FIG. N byte error correction value generators 810 to 81N-1 according to FIG. 8; - N byte correctors 530 to 53N-1 according to FIG. 8 (as also described in FIG. 5), and so on -components s1, s2,…, s 2t N byte error correction value generators 910, ..., 91i, ..., 91N-1 for correcting t byte errors, each having a 2·t·m-bit wide input for inputting t byte errors, and an m-bit wide output for outputting an m-bit wide byte error correction value, N multiplexers 920, ..., 92i, ..., 92N-1, - a first m-bit wide input (0 input), - a second m-bit wide input (1 input), - Similarly, the tth m-bit input ((t-1) input), - a control input on which a control signal st is input that can take t different values, and -m bit wide output N multiplexers 920, ..., 92i, ..., 92N-1, each having N AND circuits 930, ..., 93i, ..., 93N-1 each having a first 1-bit wide input for receiving a binary error signal E, a second m-bit wide input, and an m-bit wide output, and N XOR circuits 940, ..., 94i, ..., 94N-1 each having a first m-bit wide input, a second m-bit wide input, and an m-bit wide output; Includes.

[0289] When the control signal st has a value 0, the 0 input of one of the multiplexers 920 to 92N-1 is connected to its output. Correspondingly, the corresponding control signal st can take a value of 0 to (t-1) to establish a connection between one of the inputs 0 to (t-1) and the output. For example, if st=(t-1)=3, then the third input (2 inputs) of the multiplexer is connected to its output.

[0290] A line 95 carries the components s1, s2 and is connected to the inputs of each of the byte error correction value generators 810, . . . , 81i, . . . , 81N-1.

[0291] A line 96 carries the components s1, s2, s3, s4 and is connected to the inputs of each of the byte correctors 530, . . . , 53i, . . . , 53N-1.

[0292] Finally, line 97 is shown, and based on line 97, components s1, s2, ..., s 2t are connected to respective inputs of byte error correction value generators 910, . . . , 91i, . . . , 91N-1.

[0293] The byte error correction value generator 810 outputs the 0th byte in error in the case of a 1-byte error at byte position 0.

number

number

number

[0294] The byte corrector 530, in the case of a two-byte error, outputs the 0th byte that is in error.

number

number

number

[0295] The byte error correction value generator 910 outputs, in the case of t byte errors, the 0th byte that is in error.

number

number

number

[0296] For non-erroneous bytes, the byte error correction values ​​assigned to those byte positions are masked with the value 0, respectively.

[0297] The output of the byte error correction value generator 810 is connected to a first input (0 input) of a multiplexer 920. The output of the byte corrector 530 is connected to a second input (1 input) of the multiplexer 920. Correspondingly, the output of the byte error correction value generator 910 is connected to the t-th input (the (t-1) input) of the multiplexer 920.

[0298] A first input of the AND circuit 930 receives the binary error signal E. An output of the multiplexer 920 is connected to a second input of the AND circuit 930. An output of the AND circuit 930 is connected to a first input of the XOR circuit 940. A second input of the XOR circuit 940 receives a possibly erroneous byte value E.

number

number

[0299] The AND circuit 930 enables a component-by-component AND operation of the m-digit value input to its second input and the error signal E. If the error signal E=0, the AND circuit 930 outputs an m-component value of 0. If the error signal E=1, the AND circuit 930 outputs the value input to its second input.

[0300] These embodiments apply to the remaining byte positions as well.

[0301] The output of the byte error correction value generator 81i is connected to a first input (0 input) of a multiplexer 92i. The output of the byte error correction value generator 53i is connected to a second input (1 input) of the multiplexer 92i. Correspondingly, the output of the byte error correction value generator 91i is connected to the t-th input ((t-1) input) of the multiplexer 92i.

[0302] A first input of the AND circuit 93i is connected to the binary error signal E. An output of the multiplexer 92i is connected to a second input of the AND circuit 93i. An output of the AND circuit 93i is connected to a first input of the XOR circuit 94i. A second input of the XOR circuit 94i is connected to a possibly erroneous byte.

number

number

[0303] The AND circuit 93i enables an AND operation for each component between an m-digit value input to its second input and an error signal E. When the error signal E=0, the AND circuit 93i outputs an m-component value of 0. When the error signal E=1, the AND circuit 93i outputs the value input to its second input.

[0304] The output of the byte error correction value generator 81N-1 is connected to a first input (0 input) of a multiplexer 92N-1. The output of the byte error correction value generator 53N-1 is connected to a second input (1 input) of the multiplexer 92N-1. Correspondingly, the output of the byte error correction value generator 91N-1 is connected to the t-th input ((t-1) input) of the multiplexer 92N-1.

[0305] A first input of the AND circuit 93N-1 receives the binary error signal E. An output of the multiplexer 92N-1 is connected to a second input of the circuit 93N-1. An output of the AND circuit 93N-1 is connected to a first input of the XOR circuit 94N-1. A second input of the XOR circuit 94N-1 receives a possibly erroneous byte value E.

number

number

[0306] The AND circuit 93N-1 enables an AND operation for each component between an m-digit value input to its second input and the error signal E. When the error signal E=0, the AND circuit 93N-1 outputs an m-component value of 0. When the error signal E=1, the AND circuit 93N-1 outputs the value input to its second input.

[0307] The error signal E is If a -1 byte error, 2 byte error, ..., or t byte error occurs, the value is 1. If no error occurs, it takes the value 0.

[0308] The control signal st is - If a byte error occurs, the value is 0. - If a 2-byte error occurs, it takes the value 1. -Similarly, - If a byte error occurs, the value (t-1) Take.

[0309] Byte error corrector for single byte errors FIG. 10 shows an exemplary circuit for a byte error correction value generator 81i for the i-th byte as described in relation to FIG.

[0310] The byte error correction value generator 81i a constant multiplier 101, a first m-bit wide input, -Constant value α i a second m-bit wide input, -m bit wide output A constant multiplier 101 having an XOR circuit 102 having a first m-bit wide input, a second m-bit wide input, and an m-bit wide output; - a NOR circuit 103 having an m-bit input and a 1-bit output; an AND circuit 104 having a first 1-bit wide input, a second m-bit wide input, and an m-bit wide output; Includes.

[0311] Additionally shown in FIG. 10 is multiplexer 82i and byte error correction value generator 53i from FIG. 8 (and FIG. 5).

[0312] The constant multiplier 101, the XOR circuit 102, and the NOR circuit 103 form a byte error location signal generator 105, which generates a byte error location signal indicating whether or not there is a byte error in the i-th byte location, for example.

number

[0313] When a single byte error occurs at byte position i, the output of the AND circuit 104 is the m-dimensional byte error correction value a(i). cor If a byte error occurs at another byte position j different from i, the byte error position signal BPs i =0, and therefore the output of the AND circuit 104 also has the value 0.

[0314] The component s1 is input to a first input of the constant multiplier 101, and the constant α i is input to the constant multiplier 101. The output of the constant multiplier 101 is connected to a first input of the XOR circuit 102. The component s2 is input to a second input of the XOR circuit 102. The output of the XOR circuit 102 is connected to an input of the NOR circuit 103. The output of the NOR circuit 103 is connected to a first input of the AND circuit 104. The component s1 is input to a second input of the AND circuit 104. The output of the AND circuit 104 is connected to a first input of the multiplexer 82i.

[0315] A second input of the multiplexer 82i is connected to the output of the byte error correction value generator 53i.

[0316] Thus, a first input of multiplexer 82i is provided with a byte error correction value for one byte error, and a second input of multiplexer 82i is provided with a byte error correction value for two byte errors.

[0317] Correspondingly, the control signal st for the multiplexer 82i is: - 0 if there is a byte error, connecting the first input (the 0 input) of multiplexer 82i to its output, or -1 if there is a 2 byte error, connecting the second input (1 input) of multiplexer 82i to its output.

[0318] In the absence of errors, the value of the control signal st can be arbitrary, for example it can be set to 0 as described by way of example below.

[0319] In the absence of errors, the value of the error signal E is 0. This was previously explained in relation to figure 8. Based on the downstream connected AND circuit 83i which logically ANDs the signal at the output of the multiplexer 82i component-wise with the error signal E, it is guaranteed that at error signal E=0 (i.e. when there are no errors) the value 0 is provided at the output of the AND circuit 83i, regardless of the signal at the output of the multiplexer 82i. Therefore, no correction of the i-th byte is performed.

[0320] Circuit for determining an error signal FIG. 11 shows an exemplary circuit for determining the error signal E, such as that used in the circuit shown in FIG.

[0321] The configuration shown in FIG. a multiplier 111 having a first m-bit wide input, a second m-bit wide input, and an m-bit wide output; an XOR circuit 113 having a first m-bit wide input, a second m-bit wide input, and an m-bit wide output; a squarer 112 having an m-bit wide input and an m-bit wide output; - an OR circuit 114 having an m-bit wide input and a 1-bit wide output; - an OR circuit 116 having an m-bit wide input and a 1-bit wide output; an OR circuit 115 having a first binary input, a second binary input, and a binary output; Includes.

[0322] The value of component s1 is input to a first input of multiplier 111. The value of component s3 is input to a second input of multiplier 111. The output of multiplier 111 is connected to a first input of XOR circuit 113.

[0323] The component s1 is also input to an input of the OR circuit 116. The output of the OR circuit 116 is connected to a second input of the OR circuit 115.

[0324] The component s2 is input to an input of the squarer 112. The output of the squarer 112 is connected to a second input of the XOR circuit 113.

[0325] An output of the XOR circuit 113 is connected to an input of an OR circuit 114 , and an output of the OR circuit 114 is connected to a first input of an OR circuit 115 .

[0326] At the output of the OR circuit 114, a control signal st is provided, and at the output of the OR circuit 115, an error signal E is provided.

[0327] The control signal st is

number

[0328] Correspondingly, the control signal st is

number

[0329] The error signal E takes the value 0 if the control signal st is 0 and if the value of the component s1 is 0. In this case, there is neither a single byte error nor a double byte error.

[0330] When the value of the control signal st is 1, in the circuit according to FIG. 8, two-byte correction is performed using the byte correctors 530 to 53N-1.

[0331] If the value of the control signal st is 0, then in the circuit according to Fig. 8, first one-byte correction is performed using the byte error correction value generators 810 to 81N-1. If the error signal E is 0, and therefore there is neither one-byte error nor two-byte error, then the AND circuits 830 to 83N-1 all output the value 0, and therefore the byte

number

[0332] If a 3-byte error is recognized, for example, error correction can be discontinued. Such discontinuance of error correction can be done at the system level.

[0333] Circuit for recognizing three-byte errors. FIG. 12 shows an exemplary circuit for recognizing a three-byte error. To this end, the circuit: - four multipliers 121, 122, 123, 124 each having a first m-bit wide input and a second m-bit wide and a third m-bit wide output, three squarers 125, 126, 127 each having an m-bit wide input and an m-bit wide output; three XOR circuits 128, 129, 1210 each having a first m-bit wide input, a second m-bit wide input and an m-bit wide output; - An OR circuit 1211 having an m-bit wide input and a binary output, and the OR circuit 1211 performs an OR operation for each m-bit component input to its input.

[0334] A first input of multiplier 121 and a second input of multiplier 123 receive the value of component s1.

[0335] The value of the component s2 is input to the input of the squarer 126.

[0336] An input of the squarer 125 and a second input of the multiplier 122 receive the value of the component s3.

[0337] The value of the component s4 is input to the input of the squarer 127.

[0338] A second input of the multiplier 121 and a first input of the multiplier 124 receive the value of the component s5.

[0339] An output of the multiplier 121 is connected to a first input of the XOR circuit 128. An output of the squarer 125 is connected to a second input of the XOR circuit 128. An output of the XOR circuit 128 is connected to a first input of the multiplier 122. An output of the multiplier 122 is connected to a first input of the XOR circuit 129.

[0340] The output of the squarer 127 is connected to a first input of the multiplier 123. The output of the multiplier 123 is connected to a first input of the XOR circuit 1210.

[0341] The output of the squarer 126 is connected to a second input of the multiplier 124, the output of which is connected to a second input of the XOR circuit 1210. The output of the XOR circuit 1210 is connected to a second input of the XOR circuit 129. The output of the XOR circuit 129 is connected to an input of an OR circuit 1211, at the output of which a signal Err3 is provided, and based on the signal Err3 a 3-byte error can be determined.

[0342] The signal Err3 is

number

[0343] Correspondingly, the signal Err3 is

number

[0344] 10, 11, ..., 1i, ..., 1N-1 Byte Error Location Signal Generator s1, s2, s3, s4 syndrome components BPs0 Byte error position signal 210 Partial circuit 220 Constant Multiplier 230 Constant Multiplier 240 XOR circuit 250 NOR Circuit

Claims

1. 1. A circuit arrangement for determining at least two byte error location signals, comprising: Identifying at least one byte error in a binary string comprising a plurality of bytes; If the binary string is not erroneous, it is a codeword of an error code; the circuitry is designed to be able to determine, using components of an error syndrome of the error code, each of the at least two byte error location signals, each of the at least two byte error location signals indicating whether a byte of the binary string associated with the byte error location signal is erroneous or not; the at least two byte error location signals are determined in parallel; determining at least one byte error correction value and capable of correcting erroneous byte positions identified by the byte error position signal based on the byte error correction value; a byte error location signal is calculated with a byte error correction value for the erroneous byte to thereby correct one of the byte errors; The error code is t-byte error correcting and (t+1)-byte error detecting codes where t is a natural number, t≧2, the binary string having at least (t+1) correctable bytes; each byte of the binary string has m bits, where m>=2; The circuit configuration is N byte error correction value generators for each k, where k is a natural number ranging from 1 to t, for correcting k byte errors, each byte error correction value generator having a 2·k·m-bit wide input for inputting the error syndrome of 2·k components s 1 , s 2 , ..., s 2k , each component containing m bits, and an m-bit wide output for outputting an m-bit wide byte error correction value; N multiplexers, each of which is a 0 input, which is a first input having a width of m bits for receiving the byte error correction value, which is the output of the byte error correction value generator for correcting one byte error; one input, a second input m bits wide for receiving the byte error correction value, which is the output of the byte error correction value generator for correcting double byte errors; Similarly, a (t-1) input, which is an m-bit wide t-th input for inputting the byte error correction value, which is the output of the byte error correction value generator for correcting t byte errors; a control input for receiving a control signal st that can take t different values; and m-bit wide output N multiplexers each outputting a value at its st input in response to said control signal st; N AND circuits in one-to-one correspondence with the N multiplexers, each of which performs an AND operation on a 1-bit wide first input for inputting a binary error signal E and an m-bit wide second input to which an output of the corresponding multiplexer is connected, to output an m-bit wide output value; N XOR circuits corresponding one-to-one to the N AND circuits, each of which performs an XOR operation on a first input having an m-bit width to which an output of a corresponding AND circuit is connected and a second input having an m-bit width for inputting a byte value of a byte that may be erroneous, and outputs a corrected byte value having an m-bit width; The binary error signal E is - If 1 byte error, 2 byte error, ..., or t byte error occurs, it takes the value 1. - if no error has occurred, it takes the value 0; The control signal st is If a -1 byte error occurs, the value is 0. If a -2 byte error occurs, it takes the value 1. - And so on. A circuit configuration that takes the value (t-1) if a -t byte error occurs.

2. 2. The circuit arrangement of claim 1, wherein the byte error location signal can be determined using components of an error syndrome of the error code, the byte error location signal being designed to indicate that there is a correctable error for at least two of the bytes of the binary string.

3. 3. The circuit arrangement according to claim 1, wherein the binary string has two byte errors.

4. 4. The circuit arrangement of claim 1, wherein the byte error location signal has a first value when a byte associated with the byte error location signal is erroneous, and a second value when the byte associated with the byte error location signal is not erroneous.

5. A circuit arrangement as claimed in any one of claims 1 to 4, wherein at least one of the byte error location signals is determined with respect to at least one correct byte.

6. A circuit arrangement according to any one of claims 1 to 5, wherein the binary string comprises data bytes and check bytes, the data bytes and / or the check bytes constituting correctable bytes.

7. 1. A circuit arrangement for correcting at least one byte error in a binary string comprising a plurality of bytes, the binary string being, if not erroneous, a codeword of an error code, the circuit arrangement comprising: determining at least one byte error location signal using components of an error syndrome of the error code, and being able to determine whether a byte of the binary string is erroneous or not by means of the byte error location signal; determining at least one byte error correction value and capable of correcting erroneous byte positions identified by the byte error position signal based on the byte error correction value; at least one of said byte error correction values ​​is determined for at least one correct byte; a byte error location signal is calculated with a byte error correction value for the erroneous byte to thereby correct one of the byte errors; The at least one byte error location signal and / or the at least one byte error correction value are determined in parallel, The error code is t-byte error correcting and (t+1)-byte error detecting codes where t is a natural number, t≧2, the binary string having at least (t+1) correctable bytes; each byte of the binary string has m bits, where m>=2; The circuit configuration is N byte error correction value generators for each k, where k is a natural number ranging from 1 to t, for correcting k byte errors, each byte error correction value generator having a 2·k·m-bit wide input for inputting the error syndrome of 2·k components s 1 , s 2 , ..., s 2k , each component containing m bits, and an m-bit wide output for outputting an m-bit wide byte error correction value; N multiplexers, each of which is a 0 input, which is a first input having a width of m bits for receiving the byte error correction value, which is the output of the byte error correction value generator for correcting one byte error; one input, a second input m bits wide for receiving the byte error correction value, which is the output of the byte error correction value generator for correcting double byte errors; Similarly, a (t-1) input, which is an m-bit wide t-th input for inputting the byte error correction value, which is the output of the byte error correction value generator for correcting t byte errors; a control input for receiving a control signal st that can take t different values; and m-bit wide output N multiplexers each outputting a value at its st input in response to said control signal st; N AND circuits in one-to-one correspondence with the N multiplexers, each of which performs an AND operation on a 1-bit wide first input for inputting a binary error signal E and an m-bit wide second input to which an output of the corresponding multiplexer is connected, to output an m-bit wide output value; N XOR circuits corresponding one-to-one to the N AND circuits, each of which performs an XOR operation on a first input having an m-bit width to which an output of a corresponding AND circuit is connected and a second input having an m-bit width for inputting a byte value of a byte that may be erroneous, and outputs a corrected byte value having an m-bit width; The binary error signal E is - If 1 byte error, 2 byte error, ..., or t byte error occurs, it takes the value 1. - if no error has occurred, it takes the value 0; The control signal st is If a -1 byte error occurs, the value is 0. If a -2 byte error occurs, it takes the value 1. - And so on. A circuit configuration that takes the value (t-1) if a -t byte error occurs.

8. α is a Galois field GF(2 ｍ ), and s １ , s ２ , s ３ , s ４ are the components of the error syndrome, In the case of a two-byte error, the i-th byte is a correctable byte, The byte error location signal for the i th byte is [0010] If The byte error location signal for the i th byte is [0025] If so, take a second value; the i-th byte is erroneous if a byte error location signal associated with the i-th byte has the first value; 8. The circuit arrangement according to claim 7.

9. α is a Galois field GF(2 ｍ ), and s １ , s ２ , s ３ are the components of the error syndrome, In the case of a two-byte error, the byte error correction value of the i-th byte is [0030] 9. The circuit configuration according to claim 7 or 8, wherein the circuit configuration is determined according to

10. A circuit arrangement according to any one of claims 7 to 9, wherein in case of a double byte error, the correction of a correctable byte is determined depending on three components of the error syndrome and a byte error location signal.

11. A method for determining at least two byte error location signals by a circuit arrangement according to any one of claims 1 to 6, comprising: Identifying at least one byte error in a binary string comprising a plurality of bytes; If the binary string is not erroneous, it is a codeword of an error code; each of the at least two byte error location signals is determined using components of an error syndrome of the error code and indicates whether a byte of the binary string associated with the byte error location signal is erroneous or not; the at least two byte error location signals are determined in parallel; determining at least one byte error correction value and capable of correcting erroneous byte positions identified by the byte error position signal based on the byte error correction value; and correcting one of said byte errors by computing said byte error location signal with said byte error correction value for said erroneous byte.

12. A method for correcting at least one byte error in a binary string comprising a plurality of bytes, the binary string being, if not erroneous, a codeword of an error code, the method comprising: determining at least one byte error location signal using components of an error syndrome of the error code, the byte error location signal being able to determine whether a byte of the binary string is erroneous or not; determining at least one byte error correction value, based on which erroneous byte positions identified by the byte error position signal are corrected; At least one of the byte error correction values ​​is determined for at least one correct byte; correcting one of the byte errors by computing the byte error location signal with the byte error correction value for the erroneous byte; A method, wherein the at least one byte error location signal and / or the at least one byte error correction value are determined in parallel.

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