Semiconductor Device

Abstract

To provide a semiconductor device which can reduce thermal resistance in a heat conduction path while alleviating thermal stress generated in a contact part of a semiconductor chip.SOLUTION: A semiconductor device comprises: a semiconductor chip; and a thermal diffusion member, provided with a first main surface and a second main surface facing each other, which is configured such that the semiconductor chip is directly bonded to the first main surface and that a groove is formed on a portion, of the second main surface, where the semiconductor chip is projected.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, a heat dissipation device has been known in which a stress relaxation member having multiple protrusions is interposed between an insulating substrate bonded to a semiconductor element and a cooler to mitigate the effects of thermal stress generated in the heat dissipation device due to the difference in linear expansion coefficient between the insulating substrate and the cooler when the semiconductor element generates heat (Patent Document 1). The invention described in Patent Document 1 relieves thermal stress by deforming the protrusions of the stress relaxation member when thermal stress occurs in the heat dissipation device. This prevents cracks from occurring in the insulating substrate and at the joint between the insulating substrate and the stress relaxation member, as well as warping on the surface of the cooler facing the insulating substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-19203 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the invention disclosed in Patent Document 1, the contact area between the insulating substrate and the stress relaxation member is reduced due to the protrusions provided on the stress relaxation member, and the heat conduction path from the semiconductor element to the cooler is reduced. In other words, there is a problem that the thermal resistance of the stress relaxation member increases, deteriorating the cooling performance of the semiconductor element.

[0005] The present invention has been made in consideration of the above-mentioned problems, and its object is to provide a semiconductor device that reduces the thermal resistance of the heat conduction path while alleviating the thermal stress generated at the contact portion of a semiconductor chip. [Means for solving the problem]

[0006] The semiconductor device includes a semiconductor chip, and a heat diffusion member having a first main surface and a second main surface opposing each other, the semiconductor chip being directly bonded to the first main surface, and a groove being formed at the location of the semiconductor chip projected onto the second main surface. Effect of the Invention

[0007] According to the present invention, it is possible to reduce the thermal resistance of the heat conduction path while mitigating the thermal stress occurring in the contact portion of the semiconductor chip. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1A is a plan view of the semiconductor device according to the first embodiment. [Figure 1B] FIG. 1B is a cross-sectional view of the semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a plan view showing a modification of the semiconductor device according to the first embodiment. [Figure 3A] FIG. 3A is a plan view of the semiconductor device according to the second embodiment. [Figure 3B] FIG. 3B is a cross-sectional view of the semiconductor device according to the second embodiment. [Figure 4A] FIG. 4A is a plan view of the semiconductor device according to the third embodiment. [Figure 4B] FIG. 4B is a side view of the semiconductor device according to the third embodiment. [Diagram 5] FIG. 5 is a plan view of the semiconductor device according to the fourth embodiment. [Figure 6] FIG. 6 is a plan view of the semiconductor device according to the fifth embodiment. [Figure 7] FIG. 7 is a plan view of the semiconductor device according to the sixth embodiment. [Figure 8] FIG. 8 is a side view of the semiconductor device according to the embodiment including a cooler. [Figure 9] FIG. 9 is a side view of a semiconductor device according to an embodiment including a cooler and an insulating substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments will be described with reference to the drawings. In the description of the drawings, the same parts are given the same reference numerals and the description will be omitted.

[0010] (First embodiment) [Configuration of semiconductor device] The overall configuration of the semiconductor device according to the first embodiment will be described with reference to Figures 1A and 1B. Figure 1A is a plan view of the semiconductor device according to the first embodiment, and Figure 1B is a cross-sectional view of the semiconductor device along line AA' shown in Figure 1A.

[0011] The semiconductor device has a semiconductor chip 1 and a heat diffusion member 2. The semiconductor chip 1 is directly bonded to the heat diffusion member 2, and a groove 3a is formed at a position on the second main surface 5 where the semiconductor chip 1 is projected.

[0012] The heat diffusion member 2 absorbs heat generated by the semiconductor chip 1 through thermal conduction and releases it into the atmosphere, thereby preventing the temperature of the semiconductor chip 1 from rising above a predetermined temperature. The heat diffusion member 2 is made of a material with thermal conductivity, specifically, ceramics with heat dissipation properties such as aluminum oxide (Al2O3), aluminum nitride (AlN), and silicon carbide (SiC).

[0013] The heat diffusion member 2 has a first main surface 4 and a second main surface 5 opposed to each other.

[0014] The semiconductor chip 1 is directly bonded to the first main surface 4. The semiconductor chip 1 and the first main surface 4 are bonded by metal bonding such as solder or sintered metal, or by diffusion bonding. Diffusion bonding is a method in which materials to be bonded are brought into close contact with each other, pressurized and heated in a controlled atmosphere such as a vacuum or an inert gas, and bonded using the diffusion of atoms that occurs at the bonding surface.

[0015] Grooves 3a are formed in the second main surface 5. Grooves 3a are formed by cutting or electric discharge machining. Grooves 3a absorb the thermal expansion of the heat diffusion member 2 caused by heat generation from the semiconductor chip 1, thereby suppressing the thermal expansion of the heat diffusion member 2.

[0016] The groove 3a is formed at a location where the semiconductor chip 1 is projected on the second main surface 5. More specifically, the groove 3a is formed across the side 10 of the semiconductor chip 1 projected onto the second main surface 5. In this embodiment, the groove 3a is formed across the short-side side 10 of the semiconductor chip 1, but the side of the semiconductor chip 1 that the groove 3a spans is not limited to this. The groove 3a may be formed across the long-side side 11 of the semiconductor chip 1, or across both the short-side side 10 and the long-side side 11. The groove 3a is formed perpendicular to the second main surface 5, but may be formed obliquely to the second main surface 5.

[0017] [Effects] As described above, according to the first embodiment, the following advantageous effects can be obtained.

[0018] The heat diffusion member 2 has grooves 3a formed at the location of the second main surface 5 directly below the semiconductor chip 1 where the semiconductor chip 1 is projected, thereby making it possible to alleviate thermal stress occurring at the contact portion between the semiconductor chip 1 and the heat diffusion member 2 due to the difference in linear expansion coefficient between the semiconductor chip 1 and the heat diffusion member 2. The semiconductor chip 1 is directly bonded to the first main surface 4, making it possible to reduce the thermal resistance between the semiconductor chip 1 and the heat diffusion member 2. Therefore, it is possible to reduce the thermal resistance of the heat conduction path while alleviating the thermal stress occurring at the contact portion of the semiconductor chip 1.

[0019] The groove 3a formed in the heat diffusion member 2 is formed across the edge 10 of the semiconductor chip 1 projected onto the second main surface 5, thereby making it possible to relieve thermal stress at the end of the contact portion between the semiconductor chip 1 and the heat diffusion member 2, which is a location where thermal stress is likely to concentrate.

[0020] (Modification of the first embodiment) [Configuration of semiconductor device] A semiconductor device according to a modified example of the first embodiment will be described with reference to Fig. 2. Fig. 2 is a plan view of the semiconductor device according to the modified example of the first embodiment. The difference from the first embodiment is the number of semiconductor chips 1 and the shape of the grooves 3b. Therefore, only the difference will be described, and the description of the other common configurations will be omitted.

[0021] In the semiconductor device according to the modified example of the first embodiment, a plurality of semiconductor chips 1 are bonded to a first main surface 4, and one groove 3b corresponding to the plurality of semiconductor chips 1 is formed at a location where the plurality of semiconductor chips 1 are projected onto the second main surface 5. More specifically, the groove 3b is formed across the sides 12 of the plurality of semiconductor chips 1 projected onto the second main surface 5.

[0022] In this manner, one groove 3b may be formed to correspond to a plurality of semiconductor chips 1. Alternatively, a plurality of semiconductor chips 1 may be arranged to correspond to a single groove 3b. In this embodiment, the plurality of semiconductor chips 1 are arranged in parallel on the first main surface 4, but the arrangement of the semiconductor chips 1 is not limited to this. The semiconductor chips 1 may be arranged anywhere as long as the grooves 3b are formed at the positions where the semiconductor chips 1 are projected on the second main surface 5.

[0023] [Effects] As described above, according to the modified example of the first embodiment, the following advantageous effects can be obtained in addition to the advantageous effects of the first embodiment.

[0024] One groove 3b corresponding to the multiple semiconductor chips 1 is formed at a location on the second main surface 5 where the multiple semiconductor chips 1 are projected, and is formed across the sides 12 of the multiple semiconductor chips 1 projected onto the second main surface 5. This makes it possible for one groove 3b to relieve thermal stress occurring at the contact portion between the multiple semiconductor chips 1 and the heat diffusion member 2. In addition, the number of grooves 3b for the semiconductor chips 1 to be mounted can be reduced, and the number of steps required to form the grooves 3b and the processing costs can be reduced.

[0025] Second embodiment [Configuration of semiconductor device] The configuration of the semiconductor device according to the second embodiment will be described with reference to Figures 3A and 3B. Figure 3A is a plan view of the semiconductor device according to the second embodiment, and Figure 3B is a cross-sectional view of the semiconductor device at AA' shown in Figure 3A. The difference from the first embodiment is the depth of the groove 3c and the contact area between the semiconductor chip 1 and the heat diffusion member 2. Therefore, only the difference will be described, and the description of the other common configurations will be omitted.

[0026] 3B, the depth E of the groove 3c is shorter than the distance F from the first main surface 4 to the second main surface 5. In other words, the groove 3c does not reach the first main surface 4.

[0027] Therefore, the entire contact surface of the semiconductor chip 1 is joined to the heat diffusion member 2, and the contact area between the semiconductor chip 1 and the heat diffusion member 2 is larger than that in the first embodiment in which the grooves 3a penetrate to the first main surface 4.

[0028] [Effects] As described above, according to the second embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0029] The depth E of the groove 3c is shorter than the distance F from the first main surface 4 to the second main surface 5, so that the entire contact surface of the semiconductor chip 1 is bonded to the heat diffusion member 2. This increases the contact area between the semiconductor chip 1 and the heat diffusion member 2, and further reduces the thermal resistance between the semiconductor chip 1 and the heat diffusion member 2.

[0030] Third embodiment [Configuration of semiconductor device] The configuration of the semiconductor device according to the third embodiment will be described with reference to Figures 4A and 4B. Figure 4A is a plan view of the semiconductor device according to the third embodiment, and Figure 4B is a side view of the semiconductor device shown in Figure 4A in the direction of arrow B. The only difference from the second embodiment is the shape of the groove 3d. Therefore, only the shape of the groove 3d will be described, and descriptions of other common configurations will be omitted.

[0031] The groove 3d reaches the side surface 20 connecting the first main surface 4 and the second main surface 5. As a result, the side surface 20 connecting the first main surface 4 and the second main surface 5 of the heat diffusion member 2 is divided by the groove 3d. Note that, in this embodiment, both ends of the groove 3d reach the side surface 20 connecting the first main surface 4 and the second main surface 5, but only one end of the groove 3d may reach the side surface 20 connecting the first main surface 4 and the second main surface 5.

[0032] [Effects] As described above, according to the third embodiment, in addition to the effects of the second embodiment, the following effects can be obtained.

[0033] Groove 3d reaches side surface 20 connecting first main surface 4 and second main surface 5, thereby dividing heat diffusion member 2 and further alleviating thermal stress occurring at the contact portion between semiconductor chip 1 and heat diffusion member 2. Groove 3d also reaches side surface 20 connecting first main surface 4 and second main surface 5, thereby making it possible to easily form groove 3d.

[0034] (Fourth embodiment) [Configuration of semiconductor device] The configuration of the semiconductor device according to the fourth embodiment will be described with reference to Fig. 5. Fig. 5 is a plan view of the semiconductor device according to the fourth embodiment. The difference from the third embodiment is that the groove 3e formed on the second main surface 5 is divided at the location where the semiconductor chip 1 is projected, and two grooves 3e are formed. Therefore, only this difference will be described, and the description of the other common configurations will be omitted.

[0035] 5, a plurality of grooves 3e are formed at locations where the semiconductor chip 1 is projected onto the second main surface 5. More specifically, the plurality of grooves 3e are formed across sides 10 of the semiconductor chip 1 projected onto the second main surface 5.

[0036] In this embodiment, the multiple grooves 3e are formed across the short-side side 10 of the semiconductor chip 1 projected onto the second main surface 5, but the side of the semiconductor chip 1 across which the multiple grooves 3e span is not limited to the short-side direction. The multiple grooves 3e may be formed across the long-side side 11 of the semiconductor chip 1, or across both the short-side side 10 and the long-side side 11. Three or more grooves 3e may be formed.

[0037] [Effects] As described above, according to the fourth embodiment, in addition to the effects of the third embodiment, the following effects can be obtained.

[0038] The grooves 3e are formed in a plurality of locations on the second main surface 5 where the semiconductor chip 1 is projected, thereby increasing the number of locations where the heat diffusion member 2 is divided. This increases the heat dissipation area, thereby reducing the thermal resistance of the heat diffusion member 2.

[0039] Fifth embodiment [Configuration of semiconductor device] The configuration of the semiconductor device according to the fifth embodiment will be described with reference to Fig. 6. Fig. 6 is a plan view of the semiconductor device according to the fifth embodiment. The difference from the fourth embodiment is the thermal characteristics of the heat diffusion member 2 and the arrangement method of the grooves 3f. Therefore, only the difference will be described, and the description of the other common configurations will be omitted.

[0040] The heat diffusion member 2 is made of a heat conductive member having isotropy in heat conduction. The heat conductive member having isotropy in heat conduction is made of the material having the heat conductivity exemplified in the first embodiment, and the crystal structure of the heat conductive member is homogeneous. In other words, the heat conductivity of the heat diffusion member 2 is constant.

[0041] A plurality of grooves 3f are formed, and each groove 3f is formed radially from a position where the intersection point C of the diagonal lines of the semiconductor chip 1 on the second main surface is projected. In this embodiment, the plurality of grooves 3f are formed so that the extension line of each groove 3f passes through the intersection point C and the distance from the intersection point C to each groove 3f is equal, but the position where the plurality of grooves 3f are formed is not limited to this. The grooves 3f may be formed radially from a position where the intersection point C of the diagonal lines of the semiconductor chip 1 on the second main surface 5 is projected. The plurality of grooves 3f may be formed so as to overlap each other.

[0042] [Effects] As described above, according to the fifth embodiment, in addition to the effects of the fourth embodiment, the following effects can be obtained.

[0043] Since the heat diffusion member 2 is made of a heat conductive material having isotropy in heat conduction, the heat conductivity is constant, so that the grooves 3f can be efficiently formed in accordance with the mounting positions and number of the semiconductor chips 1.

[0044] Since the grooves 3f are formed radially from the intersection C of the diagonals of the semiconductor chip 1 on the second main surface 5, the grooves 3f can be formed along the direction of heat diffusion radially from the semiconductor chip 1, thereby increasing the heat dissipation area and reducing the thermal resistance of the heat diffusion member 2.

[0045] Sixth embodiment [Configuration of semiconductor device] The configuration of the semiconductor device according to the sixth embodiment will be described with reference to Fig. 7. Fig. 7 is a plan view of the semiconductor device according to the sixth embodiment. The difference from the fifth embodiment is the thermal characteristics of the heat diffusion member 2 and the arrangement method of the grooves 3g. Therefore, only the difference will be described, and the description of the other common configurations will be omitted.

[0046] The heat diffusion member 2 is composed of a heat conductive member having anisotropy in heat conduction. A heat conductive member having anisotropy in heat conduction is a member having directionality in heat conduction by laminating materials having different thermal conductivities. The heat diffusion member 2 shown in FIG. 7 has a thermal conductivity in the D direction higher than a predetermined reference value, and the D direction is the heat conduction direction. Therefore, more heat is diffused along the heat conduction direction. The predetermined reference value is a thermal conductivity set as a reference value for giving directionality to the heat conduction. The predetermined reference value may be set appropriately according to the material of the heat diffusion member 2 and the directionality of the heat conduction to be set.

[0047] A plurality of grooves 3g are formed, and are formed parallel to the heat conduction direction (direction D) of the heat diffusion member 2 having a thermal conductivity higher than the above-mentioned predetermined reference value. Specifically, the grooves 3g are formed at the positions where the semiconductor chip 1 is projected on the second main surface 5, and are formed parallel to the heat conduction direction across the sides 10 of the semiconductor chip 1 projected on the second main surface 5.

[0048] [Effects] As described above, according to the sixth embodiment, in addition to the effects of the fourth embodiment, the following effects can be obtained.

[0049] The heat diffusion member 2 is made of a heat conductive member having anisotropy in heat conduction, This allows the heat conduction to have directionality, so that the direction of heat conduction can be set in accordance with the mounting positions and number of semiconductor chips 1, and heat can be efficiently diffused in the direction of heat conduction.

[0050] By forming groove 3g parallel to the thermal conduction direction of heat diffusion member 2, groove 3g can be formed along the diffusion direction of heat spreading from semiconductor chip 1 in the thermal conduction direction (direction D), thereby enabling efficient heat diffusion and reducing the thermal resistance of heat diffusion member 2.

[0051] Seventh embodiment [Configuration of semiconductor device] The configuration of the semiconductor device according to the seventh embodiment will be described with reference to Fig. 8. Fig. 8 is a side view of the semiconductor device according to the seventh embodiment. The difference from the other embodiments is that a cooler 6 is further provided. Therefore, only this difference will be described, and the description of the other common configurations will be omitted.

[0052] The semiconductor device includes a cooler 6 thermally joined to the second main surface 5 of the heat diffusion member 2. In Fig. 8, a heat sink is illustrated as the cooler 6, but the cooler 6 may be an air-cooled type including a heat sink, or a water-cooled type. The cooler 6 is directly joined to the second main surface 5 of the heat diffusion member 2 by a known fixing method such as thermally conductive double-sided tape, a push pin, a clip, or a shoulder screw.

[0053] As shown in FIG. 9, an insulating substrate 7 and a metal material 8 may be provided between the heat diffusion member 2 and the cooler 6.

[0054] [Effects] As described above, according to the seventh embodiment, the following advantageous effects can be obtained in addition to the advantageous effects of the other embodiments.

[0055] By providing the cooler 6 thermally joined to the second main surface 5, the heat of the heat diffusion member 2 can be dissipated more efficiently.

[0056] As described above, the embodiment of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting this invention. From this disclosure, various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art. [Explanation of symbols]

[0057] 1. Semiconductor chip 2. Heat diffusion material 3a groove 4 1st main surface 5 Second main surface

Claims

1. A semiconductor chip; a heat diffusion member having a first main surface and a second main surface opposed to each other, the semiconductor chip being directly bonded to the first main surface, and a groove being formed in the second main surface at a position where the semiconductor chip is projected; It has the first main surface and the second main surface are formed with an outline larger than that of the semiconductor chip; The groove is formed across a side of the semiconductor chip projected onto the second main surface. Semiconductor device.

2. A semiconductor chip; a heat diffusion member having a first main surface and a second main surface opposed to each other, the semiconductor chip being directly bonded to the first main surface, and a groove being formed in the second main surface at a position where the semiconductor chip is projected; It has The groove is closed at a side surface connecting the first main surface and the second main surface of the heat diffusion member. Semiconductor device.

3. The depth of the groove is shorter than the distance from the first main surface to the second main surface.

3. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

4. The groove reaches a side surface connecting the first main surface and the second main surface.

4. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

5. The heat diffusion member is a heat conductive member having isotropy in heat conduction.

5. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

6. The heat diffusion member is a heat conductive member having anisotropy in heat conduction.

5. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

7. The groove is formed in plurality.

7. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

8. The groove is formed in plurality, The grooves are formed radially from points where the diagonal intersections of the semiconductor chip on the second main surface are projected.

6. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

9. The groove is formed in plurality, The grooves are formed in parallel along a heat conduction direction of the heat diffusion member having a thermal conductivity higher than a predetermined reference value.

7. The semiconductor device according to claim 1, wherein the first insulating layer is a first insulating layer.

10. a cooler thermally bonded to the second main surface of the heat diffusion member; 10. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

11. A semiconductor chip; a heat diffusion member having a first main surface and a second main surface opposed to each other, the semiconductor chip being directly bonded to the first main surface, and a groove being formed in the second main surface at a position where the semiconductor chip is projected; It has The groove reaches a side surface connecting the first main surface and the second main surface of the heat diffusion member, and penetrates between a pair of the opposing side surfaces. Semiconductor device.

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