Semiconductor element mounting substrate and semiconductor device

Abstract

This substrate for mounting a semiconductor element comprises: a first substrate; a second substrate; a third substrate; a lateral conductor positioned on an inner surface of a groove and connected to a signal line; a first recess and a second recess that are positioned to extend from a third upper surface of the third substrate to a first lower surface of the first substrate, and that are positioned side by side across the groove; and a first lateral ground conductor and a second lateral ground conductor respectively positioned on inner surfaces of the first recess and the second recess. The substrate has a width-decreasing portion in which an upper interval between the first recess and the second recess is smaller than a lower interval therebetween.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor element mounting substrate and a semiconductor device. [Background technology]

[0002] International Publication No. 2018 / 021209 discloses a semiconductor element mounting substrate and a semiconductor device having a first substrate having an upper surface including a mounting region for mounting a semiconductor element and a peripheral region, a frame-shaped second substrate positioned on the peripheral region of the first substrate, and a frame-shaped third substrate positioned on the second substrate. Summary of the Invention [Means for solving the problem]

[0003] The semiconductor element mounting substrate according to the present disclosure is a first substrate having a first upper surface including a mounting area for mounting a semiconductor element and a peripheral area surrounding the mounting area; a frame-shaped second substrate located on the peripheral region of the first substrate and surrounding the mounting region; a frame-shaped third substrate located on the second substrate and surrounding the mounting area; Equipped with the first substrate, the second substrate, and the third substrate have a common first outer surface facing outward; a groove portion located on the first outer surface from the first upper surface to the first lower surface of the first substrate; a signal line located on a second upper surface of the second substrate; a through conductor located inside the second substrate and connected to the signal line; a side conductor located on an inner surface of the groove and electrically connected to the through conductor; a first cutout portion located on the first outer surface of the third substrate and overlapping with the groove portion in a plan view; a first recess and a second recess located on the first outer surface from a third upper surface of the third substrate to the first lower surface of the first substrate and arranged side by side with the groove therebetween; a first ground side conductor and a second ground side conductor located on inner surfaces of the first recess and the second recess, respectively; Further comprising: A reduced width portion is included between the first recess and the second recess, in which the distance between the first recess and the second recess is narrower at an upper portion than at a lower portion.

[0004] The semiconductor device according to the present disclosure includes: The above-mentioned semiconductor element mounting substrate, a semiconductor element mounted in the mounting area and electrically connected to the signal line; Equipped with. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a perspective view illustrating a semiconductor device according to an embodiment of the present disclosure. [Figure 2A] 1 is a perspective view of a semiconductor element mounting substrate according to a first embodiment of the present disclosure, as viewed from above. [Figure 2B] 1 is a perspective view of a semiconductor element mounting substrate according to a first embodiment of the present disclosure, as viewed from below. [Figure 2C] 1 is a perspective view of a semiconductor element mounting substrate according to a first embodiment of the present disclosure, viewed from below with a main portion of a first substrate removed. [Diagram 3] FIG. 2B is a cross-sectional view taken along line AA in FIG. 2A. [Figure 4] FIG. 2B is an enlarged view of a portion C1 of FIG. 2A. [Diagram 5] FIG. 2C is an enlarged view of a portion C2 of FIG. 2C. [Figure 6] FIG. 2C mainly shows signal conductors in portion C2 of FIG. 2C. [Figure 7] FIG. 2C mainly shows the internal ground conductor in portion C2 of FIG. 2C. [Figure 8] 4 is an enlarged perspective view showing the periphery of a first cutout portion. FIG. [Figure 9] 13 is a diagram showing a part of a semiconductor element mounting board according to Modification 1. FIG. [Figure 10A] 11 is a perspective view of a semiconductor element mounting substrate according to Modification 2, seen from above. FIG. [Figure 10B] 11 is a perspective view of a semiconductor element mounting board according to Modification 2, seen from below. FIG. [Figure 10C] FIG. 10B is a cross-sectional view taken along line AA in FIG. 10A. [Figure 11] FIG. 2 is an exploded perspective view of the semiconductor device of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings.

[0007] (Embodiment 1) FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present disclosure. FIGS. 2A to 2C show a semiconductor element mounting substrate according to embodiment 1 of the present disclosure. FIG. 2A is a perspective view of the semiconductor element mounting substrate 1 according to embodiment 1 as seen from above, FIG. 2B is a perspective view as seen from below, and FIG. 2C is a perspective view as seen from below with the main part of the first substrate removed. FIG. 3 is a cross-sectional view taken along line AA in FIG. 2A. Hereinafter, the direction of each part will be expressed with the direction from the first substrate 101 toward the third substrate 103 (Z direction) as the upward direction, and the direction parallel to the substrate surface of the first substrate 101 (XY plane direction) as the horizontal direction. The direction may not coincide with the direction of the semiconductor element mounting substrate 1 or the semiconductor device 20 when in use. In this specification, in order to avoid confusion, the upper surface of the first substrate 101 will be referred to as the first upper surface S101, and the lower surface of the first substrate 101 will be referred to as the first lower surface. Similarly, the upper surface of second substrate 102 is referred to as the second upper surface, the lower surface of second substrate 102 as the second lower surface, the upper surface of third substrate 103 as the third upper surface, and the lower surface of third substrate 103 as the third lower surface.

[0008] The semiconductor device 20 and the semiconductor element mounting substrate 1 include a first substrate 101, a second substrate 102, and a third substrate 103. The first substrate 101 may have a single-layer structure or a laminated structure in which a plurality of insulating layers are stacked. When the first substrate 101 has a laminated structure, a metal film may be located between the plurality of insulating layers. The same applies to the second substrate 102 and the third substrate 103. The laminated structure allows the design of signal wiring with a multi-layer structure.

[0009] The first substrate 101 has a first upper surface S101 including a mounting area a for mounting a semiconductor element 11 and a peripheral area b surrounding the mounting area a. The first substrate 101 is made of ceramics such as an alumina (Al2O3)-based sintered body (alumina ceramics).

[0010] The second substrate 102 is located on the peripheral region b of the first substrate 101. When viewed from above (when viewed from the Z direction), the outer edge of the second substrate 102 overlaps with the outer edge of the first substrate 101, except for a portion. The second substrate 102 is frame-shaped surrounding the mounting region a. Like the first substrate 101, the second substrate 102 is made of ceramics such as an alumina (Al2O3)-based sintered body (alumina ceramics).

[0011] The third substrate 103 has a frame shape surrounding the mounting area a. The third substrate 103 is located on the second substrate 102. In plan view, the outer edge of the third substrate 103 overlaps with the outer edge of the second substrate 102, except for a portion. In plan view, the inner edge of the third substrate 103 may be located outward from the inner edge of the second substrate 102. The third substrate 103 is made of, for example, the same material as the first substrate 101 and the second substrate 102.

[0012] 2A, 2B, and 3, the first substrate 101 has a main portion 101a including a mounting region a and a frame portion 101b including a peripheral region b, and a gap portion 30 may be located between the main portion 101a and the frame portion 101b. The first substrate 101 may be configured to be divided into the main portion 101a and the frame portion 101b, or may be configured such that a part of the main portion 101a and a part of the frame portion 101b are connected to each other.

[0013] In the manufacturing process of the semiconductor element mounting board 1 or the semiconductor device 20, or due to heat generation from the semiconductor element 11 when the semiconductor device 20 is operated, a temperature change or a temperature gradient occurs in the semiconductor element mounting board 1. Then, stress may occur due to thermal expansion or thermal contraction of the semiconductor element mounting board 1 or the semiconductor element 11. Even in such a case, the presence of the void portion 30 can relieve the stress generated in the semiconductor element mounting board 1, so that it is possible to reduce the occurrence of damage or cracks in the semiconductor element mounting board 1. In addition, since the deformation or warping of the mounting area a caused by the deformation or warping of the semiconductor element mounting board 1 can be reduced, the semiconductor element 11 can be stably mounted in the mounting area a. In addition, the damage to the semiconductor element 11 caused by the deformation or warping of the mounting area a can be reduced.

[0014] When the first substrate 101 is divided into a main portion 101a and a frame portion 101b, the main portion 101a may be made of a metal material. Examples of the metal material include iron, copper, nickel, chromium, cobalt, tungsten, molybdenum, and alloys of these metals. The mounting area a may be electrically connected to a first ground conductor layer 7 described later by a conductive bonding material such as solder or brazing material. This configuration improves the heat dissipation of the semiconductor element mounting substrate 1, and the first ground conductor layer 7, the second ground conductor layer 8, the first side ground conductor 31A, and the second side ground conductor 31B described later are connected to a ground layer 25 provided on an external mounting substrate described later via the mounting area a, stabilizing the ground potentials of each. In addition, the bonding area between the mounting area a to which the ground potential of the semiconductor element mounting substrate 1 is applied and the ground conductor provided on the external mounting substrate can be increased, so that the ground potential of the semiconductor element mounting substrate 1 including the mounting area a is further stabilized. Therefore, the frequency characteristics in the signal transmission portion of the semiconductor device mounting board 1 can be further improved.

[0015] The first substrate 101, the second substrate 102, and the third substrate 103 have a common first outer surface S1a facing outward, and a first inner surface S1b located on the opposite side to the first outer surface S1a. The first inner surface S1b faces inward of the semiconductor element mounting substrate 1. As shown in FIG. 3, the first inner surface S1b of the first substrate 101 faces the void portion 30. The first inner surface S1b of the second substrate 102 may protrude inward beyond the first inner surface S1b of the first substrate 101 and the first inner surface S1b of the third substrate 103.

[0016] <Signal transmission section> The semiconductor element mounting substrate 1 has, for example, a plurality of signal transmission parts 1a to 1f. Hereinafter, one signal transmission part 1b located between the first outer side surface S1a and the first inner side surface S1b will be described. The signal transmission part 1b has the same configuration as the other signal transmission parts 1a, 1c to 1f.

[0017] Fig. 4 is an enlarged view of a portion C1 in Fig. 2A. Fig. 5 is an enlarged view of a portion C2 in Fig. 2C. Fig. 6 is a view mainly showing the signal conductor in portion C2 in Fig. 2C. In Fig. 2C, portion C2 shows signal transmission portion 1f, but Figs. 5 to 7 will be described as views of signal transmission portion 1b as seen from the first inner side surface S1b. In Figs. 4 and 5, the conductor portion is indicated by shading.

[0018] The semiconductor element mounting board 1 includes a signal line 2, a groove portion 3, a through conductor 4, a side conductor 5, an electrode 6, a connection terminal 28, and a signal electrode 33 as components of the signal transmission portion 1b.

[0019] The signal line 2 is located on the second upper surface of the second substrate 102 from one end of the second substrate 102 on the inner edge side to above the peripheral region b. The signal line 2 is made of, for example, iron, copper, nickel, gold, chromium, cobalt, molybdenum, manganese, tungsten, etc., or an alloy of these materials. The signal line 2 is connected to the semiconductor element 11.

[0020] The groove portion 3 is located on the first outer side surface S1a of the first substrate 101 from the first upper surface S101 to the first lower surface of the first substrate 101.

[0021] The side conductor 5 extends over the inner surface of the groove 3 and is electrically connected to the signal line 2, the electrode 6 (described later), and the through conductor 4, thereby conducting high-frequency signals. The side conductor 5 is made of, for example, iron, copper, nickel, gold, chromium, cobalt, molybdenum, manganese, tungsten, etc., or an alloy of these materials.

[0022] The groove 3 is located inside the outer edge of the second substrate 102 when viewed from above. Therefore, the second substrate 102 protrudes at the location of the groove 3. This configuration reduces the risk of the side conductor 5 formed in the groove 3 being damaged or short-circuited due to external influences, and the electrical continuity of the side conductor 5 can be maintained in a good state. Note that, in a planar perspective, the outer edge of the second substrate 102 may be located outside the outer edge of the first substrate 101. This configuration causes the second substrate 102 on the upper surface of the groove 3 to protrude further outward, so that the risk of the side conductor 5 formed in the groove 3 being damaged or short-circuited due to external influences is further reduced, and the electrical continuity of the side conductor 5 can be maintained in a good state.

[0023] The side conductor 5 in the groove 3 is electrically connected to an external mounting board via a conductive bonding material such as solder. During this connection, a meniscus of the bonding material is formed at the lower end of the inner surface of the groove 3. This action ensures that the side conductor 5 is electrically and stably connected to the external mounting board. Therefore, the semiconductor element mounting board 1 can reduce fluctuations in characteristic impedance in the signal transmission portion and improve frequency characteristics.

[0024] The groove 3 has a curved portion in plan view. More specifically, the groove 3 may be, for example, semicircular (semicircle, semiellipse, semioval, etc.) in plan view. A temperature change or a temperature gradient occurs in the substrate 1 for mounting a semiconductor element due to heat generated by the semiconductor element 11 during the manufacturing process of the substrate 1 for mounting a semiconductor element or the semiconductor device 20 or during operation of the semiconductor device 20. Stress may occur due to thermal expansion or thermal contraction of the substrate 1 for mounting a semiconductor element. Even in such a case, the groove 3 has a curved portion, so that it is possible to reduce the concentration of stress locally in the groove 3, and to reduce the occurrence of damage or cracks in the first substrate 101, the side conductor 5, the electrode 6, the signal electrode 33 on the first lower surface, the first side ground conductor 31A, and the second side ground conductor 31B.

[0025] The through conductor 4 (FIG. 6) is electrically connected to the signal line 2, and is located from the second upper surface to the second lower surface of the second substrate 102. The through conductor 4 is further electrically connected to the side conductor 5 via an electrode 6 provided around the upper end of the groove portion 3 on the first upper surface of the first substrate 101. The through conductor 4 is located so as to overlap with the other end of the signal line 2, and is electrically connected thereto. In this case, the high-frequency electrical signal can be transmitted from the through conductor 4 to the signal line 2 more reliably, and the transmission loss and reflection loss of the transmitted high-frequency electrical signal can be reduced.

[0026] The electrode 6 (FIG. 6) is located on the first upper surface of the first substrate 101 or the second lower surface of the second substrate 102, between the first substrate 101 and the second substrate 102, and is electrically connected to the side conductor 5. The electrode 6 is a signal conductor layer located inside the semiconductor element mounting substrate 1. More specifically, the electrode 6 may be provided around the upper end (end on the second substrate 102 side) of the groove 3 in a direction (XY direction) perpendicular to the direction in which the side conductor 5 extends on the first upper surface of the first substrate 101 or the second lower surface of the second substrate 102, and may be electrically connected to the side conductor 5. Furthermore, when seen through a plan view, the outer edge of the electrode 6 may be located inside the semiconductor element mounting substrate 1 with respect to the outer edge of the side conductor 5. In other words, the electrode 6 may not be located in a portion of the second lower surface of the second substrate 102 that is exposed above the groove 3, that is, the electrode 6 may not be exposed on the second lower surface of the second substrate 102. This configuration can reduce the spreading of the bonding material to the electrodes 6 via the side conductors 5 when the semiconductor device 20 is electrically connected to a mounting board via a conductive bonding material such as solder. As a result, stress caused by the difference in thermal expansion coefficient between the second substrate 102 and the bonding material can be reduced. In addition, the possibility of the characteristic impedance fluctuating unstably due to the way the bonding material spreads can be reduced. As a result, the frequency characteristics of the side conductors 5 and electrodes 6, which are signal transmission parts, can be maintained more favorably.

[0027] The electrode 6 has a semicircular outline (outline on the mounting area a side) in a planar perspective view (semicircle, semiellipse, semioval, etc.). With this configuration, the electrode 6 can be easily formed in the manufacturing process of the semiconductor element mounting board 1, and the possibility of localized stress occurring in the above-mentioned outline of the electrode 6 can be reduced. Furthermore, the semiconductor element mounting board 1 can reduce bias in the spread of the electric field distribution in the vicinity of the above-mentioned outline of the electrode 6. Therefore, the semiconductor element mounting board 1 can reduce the risk that the electrode 6 will peel off or that cracks will occur in the first board 101 or the second board 102 due to stress occurring in the above-mentioned outline of the electrode 6, and can further improve the frequency characteristics of the signal transmission part.

[0028] The connection terminal 28 (FIG. 6) protrudes from the electrode 6 in the opposite direction to the groove 3, and is located on the first upper surface of the first substrate 101 or the second lower surface of the second substrate 102. The connection terminal 28 is an inner-layer connection terminal, and the through conductor 4 is connected to the surface of the connection terminal on the second substrate 102 side. This connection electrically connects the electrode 6 to the signal line 2 via the connection terminal 28 and the through conductor 4. The connection terminal 28 increases the electrostatic capacitance generated between the electrode 6 and the connection terminal 28 and the first ground conductor layer 7 (described later), and can alleviate the reduction in the characteristic impedance of the signal transmission part by the electrode 6 and the connection terminal 28. This makes it easy to set the characteristic impedance of the signal transmission part to a desired value, and can realize the miniaturization of the semiconductor element mounting substrate 1. In addition, the frequency characteristics of the signal transmission part can be further improved.

[0029] In a plan view, the connection terminal 28 may be positioned linearly from the center of the outer edge of the electrode 6 (the edge on the outer periphery of the second substrate 102) in the opposite direction to the groove 3. With this configuration, the semiconductor element mounting substrate 1 can shorten the length of the signal transmission portion formed by the electrode 6 and the connection terminal 28, and can further improve the frequency characteristics of the signal transmission portion.

[0030] The signal electrode 33 (FIG. 6) is a film-like conductor that spreads around the groove 3 so as to surround the groove 3 on the first lower surface of the first substrate 101. The signal electrode 33 is connected to the side conductor 5 in the groove 3. The signal electrode 33 has a semicircular outline (outline on the mounting area a side) in a plan view (semicircle, semiellipse, semioval, etc.). This configuration makes it possible to easily form the signal electrode 33 in the manufacturing process of the semiconductor element mounting substrate 1, and to reduce the possibility of local stress occurring at the outer edge portion of the signal electrode 33. Furthermore, when the semiconductor device 20 is mounted on an external mounting substrate via the signal electrode 33 with a conductive bonding material such as solder, it is possible to reduce the concentration of stress occurring around the signal electrode 33 and the bonding material in a portion. Therefore, the semiconductor element mounting substrate 1 can reduce the risk that the signal electrode 33 will peel off or that cracks will occur in the first substrate 101 due to stress occurring at the portion of the outline of the electrode 6. Furthermore, due to the above-mentioned configuration of the signal electrode 33, the semiconductor element mounting board 1 can reduce bias in the spread of the electric field distribution in the vicinity of the above-mentioned outline of the signal electrode 33. Furthermore, the signal electrode 33 can stabilize the electrical connection between the semiconductor element 11 and the external mounting board. Therefore, the frequency characteristics of the signal transmission part having the signal electrode 33 can be improved.

[0031] Fig. 7 is a diagram mainly showing the internal ground conductor in a portion C2 of Fig. 2C. In Fig. 7, the first ground conductor layer 7 is shown with the central portion cut away.

[0032] The semiconductor element mounting substrate 1 further includes, as components of the signal transmission section 1b, a first ground conductor layer 7, a second ground conductor layer 8, metal layers 34, 35, a first recess 10A, a second recess 10B, a first side ground conductor 31A and a second side ground conductor 31B.

[0033] The first ground conductor layer 7, the second ground conductor layer 8 and the metal layers 34, 35 may be integrally configured in the plurality of signal transmission portions 1a to 1f.

[0034] The first ground conductor layer 7 is located on the first upper surface of the first substrate 101 or the second lower surface of the second substrate 102, between the first substrate 101 and the second substrate 102, with a gap between the electrode 6. The first ground conductor layer 7 is a ground conductor layer located inside the semiconductor device mounting substrate 1. The first ground conductor layer 7 may be located so as to surround the electrode 6 inside the semiconductor device mounting substrate 1, and this configuration can reduce the characteristic impedance of the side conductor 5 and the electrode 6. Furthermore, the possibility that the electric field generated in the signal transmission portion from the side conductor 5 to the through conductor 4 via the electrode 6 spreads to an unintended range can be reduced, and the electric field can be coupled between the electrode 6 and the first ground conductor layer 7. Therefore, the spread of the electric field distribution in the signal transmission portion can be reduced. In addition, a high-frequency electric signal can be transmitted while being electric-field-coupled between the electrode 6 and the first ground conductor layer 7. In addition, the characteristic impedance in the signal transmission portion can be stabilized.

[0035] The second ground conductor layer 8 is positioned on the second upper surface of the second substrate 102 so as to sandwich the signal line 2. With this configuration, the second upper surface of the second substrate 102 can have a so-called coplanar line configuration in which the signal transmission portion is sandwiched between the ground potential portions. This can further improve the frequency characteristics of the signal transmission portion having the signal line 2. The first ground conductor layer 7 may be positioned at a location overlapping the signal line 2 and the second ground conductor layer 8 when viewed from the Z direction. With this configuration, the signal transmission portion having the signal line 2 has a so-called grounded coplanar line configuration, and the frequency characteristics of the signal transmission portion can further be improved. A part of the second ground conductor layer 8 may be positioned between the second substrate 102 and the third substrate 103.

[0036] The metal layer 34 is connected to the first side ground conductor 31A and the second side ground conductor 31B, and extends over the first lower surface of the first substrate 101. The metal layer 34 is located on the first lower surface of the first substrate 101 so as to sandwich the signal line 2 in a planar perspective view. The presence of the metal layer 34 on the first lower surface facilitates electrical connection with the mounting substrate. In addition, the heat dissipation of the semiconductor element mounting substrate 1 via the metal layer 34 is improved.

[0037] Metal layer 35 is connected to first side ground conductor 31A and second side ground conductor 31B, and extends to the third top surface of third substrate 103. Due to the presence of metal layer 35, an electric field generated when a high-frequency electric signal is transmitted to signal line 2 is coupled to metal layer 35 on the third top surface, thereby reducing the spread of unnecessary and unstable electric field distribution around signal line 2. As a result, semiconductor device mounting substrate 1 can further improve the frequency characteristics of the signal transmission portion.

[0038] The first recess 10A and the second recess 10B are located on the first outer side S1a from the third upper surface of the third substrate 103 to the first lower surface of the first substrate 101. When viewed from the Y direction (a direction perpendicular to the first outer side S1a), the first recess 10A and the second recess 10B are located side by side with the groove portion 3 in between. The first recess 10A and the second recess 10B are located on both sides of the groove portion 3 with a gap between them.

[0039] The first side ground conductor 31A is located on the inner surface of the first recess 10A. The second side ground conductor 31B is located on the inner surface of the second recess 10B. With this configuration, the first side ground conductor 31A and the second side ground conductor 31B are located to sandwich the side conductor 5 through which high-frequency signals are conducted, so that the signal transmission portion is sandwiched between the ground potential portion even on the first outer side surface S1a, and unnecessary and unstable spread of the electric field distribution generated in the signal transmission portion of the semiconductor element mounting substrate 1 and fluctuations in characteristic impedance can be reduced. This can further improve the frequency characteristics of the semiconductor element mounting substrate 1.

[0040] The first side ground conductor 31A may be continuous across the first substrate 101, the second substrate 102, and the third substrate 103. Furthermore, the first side ground conductor 31A may be located over the entire inner surface of the first recess 10A. The second side ground conductor 31B may be continuous across the first substrate 101, the second substrate 102, and the third substrate 103. Furthermore, the second side ground conductor 31B may be located over the entire inner surface of the second recess 10B. This configuration can increase the areas of the first side ground conductor 31A and the second side ground conductor 31B. Therefore, the ground potential of the semiconductor element mounting substrate 1 can be stabilized, and unnecessary and unstable expansion of the electric field distribution around the side conductor 5 and fluctuations in the characteristic impedance can be more stably reduced.

[0041] In the first side ground conductor 31A, a portion located on the first substrate 101, a portion located on the second substrate 102, and a portion located on the third substrate 103 may overlap with each other at least partially when viewed from above. With this configuration, the semiconductor element mounting substrate 1 can further reduce unnecessary and unstable spreading of the electric field distribution and fluctuations in the characteristic impedance that occur in the signal transmission portion of the semiconductor element mounting substrate 1. The same applies to the second side ground conductor 31B.

[0042] The semiconductor element mounting board 1 further includes a first cutout portion 9, a second cutout portion 41, and an inner surface groove 32 as components of the signal transmission portion 1b.

[0043] The first cutout 9 (FIG. 4) is located on the first outer surface S1a of the third substrate 103 and overlaps with the groove 3 in a plan view. The first cutout 9 may be concave and located from the third upper surface to the third lower surface of the third substrate 103. No ground conductor is located on the inner surface of the first cutout 9. When the semiconductor element mounting substrate 1 is made smaller, the distance between the signal line 2 and the surrounding ground conductor becomes narrow, which increases the electrostatic capacitance generated between the signal transmission portion and the ground potential portion, and this may result in a decrease in the characteristic impedance. However, the first cutout 9 can reduce the electrostatic capacitance and mitigate the decrease in the characteristic impedance.

[0044] The first cutout portion 9 may have an outer shape larger than the groove portion 3 in a plan view. With this configuration, the semiconductor element mounting substrate 1 can reduce stress concentration on the second substrate 102 located between the groove portion 3 and the first cutout portion 9. This can reduce the possibility of cracks or breakage occurring in the second substrate 102.

[0045] The width W21 (FIG. 4) of the first cutout portion 9 in the X direction (direction along the outer edge of the third upper surface of the third substrate 103) may be smaller than the width W25a (FIG. 4) of the first recess 10A located on the third substrate 103 in the X direction, or the width W25b (FIG. 4) of the second recess 10B located on the third substrate 103 in the X direction. The X direction may be defined as the horizontal direction (first direction) along the first outer side surface S1a. If the distance between the first recess 10A and the second recess 10B and the first cutout portion 9 becomes too close, the outward protruding portion of the third substrate 103 becomes small and becomes easily damaged. Therefore, by reducing the width W21 of the first cutout portion 9 and securing the protruding portion, processing that maintains the strength of the third substrate 103 becomes easier.

[0046] The second cutout 41 (FIG. 5) is located on the first inner surface S1b of the first substrate 101. The second cutout 41 may overlap the groove 3 when viewed from the Y direction (a direction perpendicular to the first outer surface S1a). The second cutout 41 may be concave and located from the first upper surface to the first lower surface of the first substrate 101. No ground conductor is located on the inner surface of the second cutout 41. The second cutout 41 reduces the thickness of the ceramic (dielectric) of the first substrate 101 located in the Y direction of the groove 3. Thus, the effective dielectric constant around the side conductor 5 of the groove 3 decreases. Therefore, by adjusting the thickness (thickness in the Y direction) of the second cutout 41, it becomes easy to set the characteristic impedance of the signal transmission part to a desired value, and the reflection characteristics in the low frequency band can be reduced, and the frequency characteristics of the signal transmission part can be further improved.

[0047] A width W22 (FIG. 5) in the X direction (a direction along the outer edge of the third upper surface of the third substrate 103) of the second cutout portion 41 may be larger than a width W23 (FIG. 5) in the X direction of the groove portion 3. According to this configuration, by making the width W22 of the second cutout portion 41 larger than the width (corresponding to the width W23) of the side conductor 5 through which a high-frequency signal is transmitted, a decrease in impedance can be more easily reduced.

[0048] Furthermore, the width W22 (FIG. 5) of the second cutout portion 41 in the X direction may be greater than the width W21 (FIG. 4) of the first cutout portion 9 in the X direction.

[0049] The inner surface groove 32 is located on the first inner side surface S1b of the third substrate 103, and sandwiches the signal line 2 therebetween from the X direction (the direction along the outer edge of the third upper surface of the third substrate 103) in a plan view. The inner surface groove 32 is located from the third upper surface to the third lower surface of the third substrate 103. An inner surface ground conductor that is at ground potential is located on the inner surface of the inner surface groove 32. The inner surface groove 32 in which the inner surface ground conductor is located can reduce unnecessary and unstable spread of the electric field distribution at the end of the signal line 2 on the mounting area a side, and can reduce fluctuations in the characteristic impedance of the signal transmission section 1b.

[0050] <Distance between first recess and second recess> On the first outer surface S1a, the groove portion 3 is located between the first recess 10A and the second recess 10B. Between the first recess 10A and the second recess 10B, there is included a narrowed width portion H1 (FIG. 4) in which the distance between the first recess 10A and the second recess 10B is narrower at the top (positive direction of the Z axis) than at the bottom (negative direction of the Z axis).

[0051] The narrowed width portion H1 may be located in a height range including the upper end of the groove portion 3, or in a height range above the groove portion 3. In the narrowed width portion H1, the interval between the first recess 10A and the second recess 10B may be narrowed in a stepwise manner or may be gradually narrowed. The narrowed width portion H1 narrows the interval between the first recess 10A and the second recess 10B at the upper portion of the narrowed width portion H1 compared to the case where the narrowed width portion H1 is not present. Therefore, the interval between the first side ground conductor 31A and the second side ground conductor 31B can be narrowed at the upper portion of the narrowed width portion H1. And, by narrowing the interval, the cutoff frequency of the high-frequency signal transmitted through the side conductor 5, the electrode 6, the through conductor 4, and the signal line 2 in the groove portion 3 becomes high, and the frequency characteristic of the signal transmission portion 1b becomes broadband. Furthermore, the presence of the contracted width portion H1 allows the distance between the groove portion 3 and the first recess 10A and the distance between the groove portion 3 and the second recess 10B to be made wider on the first lower surface of the first substrate 101. When the semiconductor element mounting substrate 1 is mounted on the mounting substrate, the signal electrode 33 and the metal layer 34 of the semiconductor element mounting substrate 1 are joined to the signal electrode and the ground electrode of the mounting substrate via a conductive bonding material such as solder. Therefore, the distance between the groove portion 3 and the first recess 10A and the distance between the groove portion 3 and the second recess 10B are made wider, which reduces the risk of the signal electrode 33 and the metal layer 34 being short-circuited by the conductive bonding material spread on the first lower surface of the first substrate 101 during the above bonding. This improves the mounting reliability of the semiconductor element mounting substrate 1.

[0052] The distance W1 between the first recess 10A and the second recess 10B in the first substrate 101, the distance W2 between the first recess 10A and the second recess 10B in the second substrate 102, and the distance W3 between the first recess 10A and the second recess 10B in the third substrate 103 may be configured to satisfy the following conditions (1) and (2). W1 ≥ W2, W2 ≥ W3 (1) At least one of the values ​​of W1, W2, and W3 is different (2)

[0053] With this configuration, the distance between the first recess 10A and the second recess 10B becomes narrower at the top between the first substrate 101 and the second substrate 102, or between the second substrate 102 and the third substrate 103. Since the distance between the first grounded side surface conductor 31A and the second grounded side surface conductor 31B becomes narrower at the top, the cutoff frequency of the high-frequency signal transmitted through the side conductor 5, the electrode 6, the through conductor 4, and the signal line 2 in the groove 3 becomes higher, and the frequency characteristic of the signal transmission section 1b becomes broadband. Furthermore, since the distance between the groove 3 and the first recess 10A and the distance between the groove 3 and the second recess 10B can be made wider while realizing the broadband, the mounting reliability of the semiconductor element mounting substrate 1 can be improved.

[0054] Furthermore, the intervals W1 to W3 may satisfy the following condition (3). W1>W2 (3) According to this configuration, at the height where the penetrating conductor 4 is located, the distance between the first recess 10A and the second recess 10B, i.e., the distance between the first side grounding conductor 31A and the second side grounding conductor 31B, can be narrowed, thereby making the frequency characteristics of the signal transmission section 1b wider bandwidth.

[0055] Furthermore, the intervals W1 to W3 may satisfy the following condition (4). W2 = W3 (4) According to this configuration, a configuration can be adopted in which the first recess 10A and the second recess 10B located on the second substrate 102 and the first recess 10A and the second recess 10B located on the third substrate 103 overlap in a large area in a plan view. In the overlapping area, the first and second grounding conductors 31A and 31B located on the second substrate 102 are continuous with the first and second grounding conductors 31A and 31B located on the third substrate 103. This makes it possible to stabilize the shapes of the first and second grounding conductors 31A and 31B, and to stabilize the ground potential of the signal transmission section 1b. This makes it possible to stabilize the frequency characteristics of the signal transmission section 1b.

[0056] If the gap W2 is too narrow, the characteristic impedance decreases, and the reflection characteristics in the low frequency band deteriorate in association with the broadening of the frequency characteristics. However, by using the second cutout portion 41 to increase the characteristic impedance around the side conductor 5, the deterioration of the reflection characteristics can be reduced.

[0057] The thickness (maximum dimension in the Y direction) of the first recess 10A may be uniform from the first substrate 101 to the third substrate 103. The thickness (maximum dimension in the Y direction) of the second recess 10B may be uniform from the first substrate 101 to the third substrate 103.

[0058] <Third top surface of third substrate> FIG. 8 is an enlarged perspective view showing the periphery of the first cutout portion.

[0059] The third upper surface of the third substrate 103 includes a conductor region R1 where the metal layer 35 is located, and a non-conductor region R2 where the metal layer 35 is not located. The non-conductor region R2 extends from a position P1 between the first recess 10A and the first notch 9 to a position P2 between the first notch 9 and the second recess 10B to an outer edge E103 (FIG. 8) of the third upper surface of the third substrate 103. The outer edge E103 of the third upper surface means an edge on the first outer side surface S1a side of the third upper surface of the third substrate 103. According to this configuration, when the first outer side surface S1a is formed by dicing or the like, the occurrence of burrs on the metal layer 35 can be reduced at the outer edge E103 of the third upper surface from the position P1 to the position P2. Therefore, the occurrence of conductors such as burrs on the first outer side surface S1a in the vicinity of the signal line 2 is reduced, and stable frequency characteristics can be obtained. Furthermore, by adjusting the area of ​​the non-conductive region R2, it becomes easier to adjust the characteristic impedance of the signal transmission portion 1b.

[0060] The non-conductor region R2 has a widened portion H11 ( FIG. 8 ) in which a width D1 in the Y direction (a direction perpendicular to the first outer surface S1a) becomes wider toward the first cutout portion 9. This configuration can reduce the tendency for the impedance of a high-frequency signal conducted from the signal line 2 to the side conductor 5 to decrease.

[0061] The conductor region R1 extends over the entire side E10A (FIG. 4) of the first recess 10A located on the third upper surface of the third substrate 103, and the entire side E10B (FIG. 4) of the second recess 10B located on the third upper surface of the third substrate 103. With this configuration, the ground potential of the metal layer 35 is stabilized.

[0062] (Variation 1) Fig. 9 is a diagram showing a part of a semiconductor element mounting board of Modification 1. A portion C1 shown in Fig. 9 corresponds to the portion C1 in Fig. 2A.

[0063] As shown in FIG. 9, the distance W1 between the first recess 10A and the second recess 10B in the first substrate 101, the distance W2 between the first recess 10A and the second recess 10B in the second substrate 102, and the distance W3 between the first recess 10A and the second recess 10B in the third substrate 103 may satisfy condition (5). W2>W3 (5) Furthermore, condition (6) may be satisfied. W1 = W2 (6)

[0064] By satisfying condition (5), the distance between the first and second side ground conductors 31A and 31B becomes narrower above the groove 3. This increases the cutoff frequency of the high-frequency signal transmitted through the side conductor 5, electrode 6, through conductor 4, and signal line 2 in the groove 3, and broadens the frequency characteristics of the signal transmission section 1b. Furthermore, while achieving a broadband characteristic, the distance between the groove 3 and the first recess 10A and the distance between the groove 3 and the second recess 10B can be made wider, thereby improving the mounting reliability of the semiconductor element mounting board 1.

[0065] By satisfying the condition (6), the first recess 10A and the second recess 10B located on the first substrate 101 and the first recess 10A and the second recess 10B located on the second substrate 102 can have a large overlapping portion in plan view. In the overlapping portion in plan view, the first side ground conductor 31A and the second side ground conductor 31B located on the first substrate 101 are continuous with the first side ground conductor 31A and the second side ground conductor 31B located on the second substrate 102. This makes it possible to stabilize the shapes of the first side ground conductor 31A and the second side ground conductor 31B, and to stabilize the ground potential of the signal transmission section 1b. This makes it possible to stabilize the frequency characteristics of the signal transmission section 1b.

[0066] (Variation 2) 10A to 10C show a semiconductor element mounting substrate according to Modification 2. FIG. 10A is a perspective view of a semiconductor element mounting substrate 1A according to Modification 2 seen from above, FIG. 10B is a perspective view of the semiconductor element mounting substrate 1A seen from below, and FIG. 10C is a cross-sectional view taken along line AA in FIG. 10A. As shown in FIGS. 10A to 10C, the first substrate 101 may be integrally configured including the mounting region a and the peripheral region b. The semiconductor element mounting substrate 1A having this configuration does not have the gap 30 of the first substrate 101 shown in FIG. 3, the first inner side surface S1b of the first substrate 101, and the second cutout portion 41 shown in FIG. 5. The other configurations are the same as those of the semiconductor element mounting substrate 1 of the above-described embodiment.

[0067] In the semiconductor device mounting board 1A of the second modification, the same components as those in the semiconductor device mounting board 1 shown in the first embodiment provide the same effects as those of the components.

[0068] (Variation 3) As shown in FIG. 2A or FIG. 10A, the first substrate 101, the second substrate 102, and the third substrate 103 have outer surfaces S2a and S3a adjacent to the first outer surface S1a, a corner T1 located between the first outer surface S1a and the outer surface S2a, and a corner T2 located between the first outer surface S1a and the outer surface S3a. As shown in the signal transmission section 1d of FIG. 2A or FIG. 10A, the second recess 10C may intersect with the outer surface S2a. Similarly, as shown in the signal transmission section 1a of FIG. 2A or FIG. 10A, the first recess 10D may intersect with the outer surface S3a. The outer surfaces S2a and S3a correspond to an example of the second outer surface according to the present disclosure.

[0069] According to this configuration, the shapes of first substrate 101, second substrate 102, and third substrate 103 in the vicinity of corners T1, T2 are simplified, reducing the risk of damage such as cracks occurring at corners T1, T2.

[0070] (Configuration of Semiconductor Device) Fig. 11 is an exploded perspective view of the semiconductor device of Fig. 1. When assembling the semiconductor device 20, the semiconductor element 11 is placed on the mounting area a of the first substrate 101 and is bonded and fixed to the first substrate 101 with an adhesive or the like, and the semiconductor element 11 and the signal line 2 are electrically connected with a bonding wire or the like. In this manner, the semiconductor element 11 is mounted on the semiconductor element mounting substrate 1, thereby completing the semiconductor device 20 as a product. Although not shown, the upper surface of the semiconductor element mounting substrate 1 may have a lid.

[0071] The semiconductor device 20 may further include a mounting board 21 bonded to the first lower surface of the first substrate 101. The mounting board 21 is composed of, for example, a plurality of insulating layers, and on the upper surface of the upper layer, a signal conductor 26 made of a metal material such as copper foil and a second connection terminal 27 are provided, to which the side conductor 5 and the signal electrode 33 on the first lower surface are electrically connected via a conductive bonding material such as solder and to which a high-frequency electrical signal is transmitted. Furthermore, the mounting board 21 has a ground layer 25, which is made of a metal material such as copper foil and is at a ground potential, formed at a predetermined interval so as to sandwich the signal conductor 26 between them and surround the second connection terminal 27 on the upper surface of the upper layer.

[0072] The ground layer 25 is joined to the metal layer 34, the first side ground conductor 31A, the second side ground conductor 31B, and the lower surface of the mounting area a made of a metal material, which are provided on the lower surface of the semiconductor element mounting substrate 1, via a joining material such as solder. The mounting substrate 21 has the second connection terminal 27, the signal conductor 26, and the ground layer 25 provided on the upper surface thereof, thereby forming a so-called coplanar line, which is one type of planar transmission line.

[0073] The mounting board 21 may have a ground conductor 22 formed in an inner layer. The ground conductor 22 has a formation region 23 where the ground conductor 22 is formed and a non-formation region 24 where the ground conductor 22 is not formed. The non-formation region 24 of the ground conductor layer is not provided at a position overlapping at least the signal electrode 33 (FIG. 6) and the second connection terminal 27 on the first lower surface in a plan view. This configuration can alleviate the difficulty in adjusting the characteristic impedance to a desired range when the semiconductor device 20 is mounted on the mounting board 21. This is because, when the non-formation region 24 overlaps with the signal electrode 33 (FIG. 6) and the second connection terminal 27, the electrostatic capacitance generated between the signal conductor 26 and the ground potential portion increases and the characteristic impedance decreases in the signal transmission portion between the signal conductor 26 and the side conductor 5 due to the conductive bonding material such as solder that electrically connects the signal electrode 33 on the first lower surface and the second connection terminal 27 and the meniscus formed on the side of the side conductor 5 by this bonding material.

[0074] Furthermore, the non-forming area 24 may be located inward (toward the side conductor 5) of the first ground side conductor 31A and the second ground side conductor 31B sandwiching the side conductor 5 in a direction perpendicular to the signal transmission direction of the signal line 2 (i.e., the direction from the signal line 2 to the semiconductor element 11) in a plan view. This configuration can reduce unnecessary and unstable expansion of the electric field distribution and fluctuations in characteristic impedance in the signal transmission portion between the signal conductor 26 and the side conductor 5. As a result, the semiconductor element mounting board 1 can further improve the frequency characteristics of the signal transmission portion.

[0075] The present disclosure described above is not limited to the above-mentioned embodiment, and various modifications and the like are possible within the scope of the gist of the present disclosure. In addition, the above-mentioned intervals W1, W2, W3, and widths W21, W22, W23, W25a, and W25b may not be constant from the upper end to the lower end of the relevant part. When the values ​​differ depending on the height to be measured, a representative value may be obtained from the measured values ​​at a plurality of heights that divide the relevant part equally from the upper end to the lower end, and the representative value may be used as the intervals W1, W2, W3, and widths W21, W22, W23, W25a, and W25b. As the representative value, the central 80% measured values ​​may be extracted from the measured values ​​at the above-mentioned plurality of heights, and the average value of the extracted measured values ​​may be used. [Industrial Applicability]

[0076] The present disclosure can be used for semiconductor element mounting substrates and semiconductor devices. [Explanation of symbols]

[0077] 1. Semiconductor device mounting substrate 1e~1f Signal transmission section 101 First board 102 Second board 103 Third Board a. Mounting area b. Surrounding area 2 Signal Line 3 Groove 4 Through conductor 5 Side conductor 6 electrodes 7 First Ground Conductor Layer 8 Second Ground Conductor Layer 9 First notch 10A, 10D First recess 10B, 10C Second recess 11 Semiconductor elements 20 Semiconductor Devices 21 Mounting board 22 Ground Conductor 23 Formation area 24 Non-formation area 25 Ground Layer 26 Signal Conductor 27 Second connection terminal 28 Connection terminal 30 Cavity 31A First Side Ground Conductor 31B Second side ground conductor 32 Inner groove 33 Signal electrode 34 Metal layer 35 Metal layer 41 Second notch S101 1st top surface S1a 1st outer surface S1b 1st inner surface S2a, S3a outer surface (second outer surface) T1, T2 corner H1 reduced width part H11 Widening section W1~W3 interval W21~W23, W25a, W25b, D1 width R1 Conductor area R2 Non-conductor area

Claims

1. a first substrate having a first upper surface including a mounting area for mounting a semiconductor element and a peripheral area surrounding the mounting area; a frame-shaped second substrate located on the peripheral region of the first substrate and surrounding the mounting region; a frame-shaped third substrate located on the second substrate and surrounding the mounting area; Equipped with the first substrate, the second substrate, and the third substrate have a common first outer surface facing outward; a groove portion located on the first outer surface from the first upper surface to the first lower surface of the first substrate; a signal line located on a second upper surface of the second substrate; a through conductor located inside the second substrate and connected to the signal line; a side conductor located on an inner surface of the groove and electrically connected to the through conductor; a first cutout portion located on the first outer surface of the third substrate and overlapping with the groove portion in a plan view; a first recess and a second recess located on the first outer surface from a third upper surface of the third substrate to the first lower surface of the first substrate and arranged side by side with the groove therebetween; a first ground side conductor and a second ground side conductor located on inner surfaces of the first recess and the second recess, respectively; Further comprising: A narrowed portion is included between the first recess and the second recess, and the gap between the first recess and the second recess is narrower at an upper portion than at a lower portion. A substrate for mounting semiconductor elements.

2. a distance W1 between the first recess and the second recess in the first substrate; a distance W2 between the first recess and the second recess in the second substrate; A distance W3 between the first recess and the second recess in the third substrate is W1 ≧ W2, W2 ≧ W3, and at least one of W1, W2, and W3 is different in value; 2. The semiconductor element mounting substrate according to claim 1.

3. W1>W2; The semiconductor element mounting substrate according to claim 2.

4. W2=W3. The semiconductor element mounting substrate according to claim 3.

5. the first substrate has a first inner side opposite the first outer side; Furthermore, a signal electrode extending onto the first lower surface of the first substrate and connected to the side conductor; A second cutout portion located on the first inner surface; Equipped with The semiconductor element mounting substrate according to claim 1 .

6. The semiconductor element mounting substrate according to claim 5 , wherein the second cutout portion is positioned so as to overlap with the groove portion when viewed from a direction perpendicular to the first outer surface.

7. a width of the first cutout portion in a first direction along an outer edge of the third upper surface of the third substrate is larger than a width of the groove portion in the first direction; The semiconductor element mounting substrate according to claim 5.

8. a width of the second cutout portion in a first direction along an outer edge of the third upper surface of the third substrate is larger than a width of the first cutout portion in the first direction; The semiconductor element mounting substrate according to claim 5.

9. a width of the first cutout portion in a first direction along an outer edge of the third upper surface of the third substrate is smaller than a width of the first recess portion located in the third substrate in the first direction or a width of the second recess portion located in the third substrate in the first direction; The semiconductor element mounting substrate according to claim 1 .

10. the third upper surface of the third substrate includes a conductive region where a metal layer is located and a non-conductive region where no metal layer is located; the non-conductive region extends from between the first recess and the first cutout portion to between the first cutout portion and the second recess to an outer edge of the third upper surface of the third substrate; The semiconductor element mounting substrate according to claim 1 .

11. The non-conductive region has a widened portion whose width in a direction perpendicular to the first outer surface increases toward the first cutout portion. The semiconductor element mounting substrate according to claim 10.

12. the conductor region extends over an entire side of the first recess located on the third upper surface of the third substrate and an entire side of the second recess located on the third upper surface of the third substrate; The semiconductor element mounting substrate according to claim 10.

13. the first substrate, the second substrate, and the third substrate each have a second outer surface adjacent to the first outer surface, The first recess or the second recess intersects with the second outer surface. The semiconductor element mounting substrate according to claim 1 .

14. A semiconductor element mounting substrate according to any one of claims 1 to 4, a semiconductor element mounted in the mounting area and electrically connected to the signal line; A semiconductor device comprising:

15. Further comprising a mounting substrate joined to the first lower surface of the first substrate. The semiconductor device according to claim 14.

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