Semiconductor Device

Abstract

To prevent loss of confidentiality and authenticity due to security attacks on the reverse side.SOLUTION: A semiconductor device mounted on a circuit board 1 having a first surface on which electronic circuits 15 are formed and a second surface that is the reverse side of the first surface, with the first surface facing a printed circuit board 2, comprises a wiring board 17 to be attached to the second side of the circuit board 1, and the circuit board 1 has a via conductor 14 connecting the first surface and the second surface, and the electronic circuits 15 are connected through the via conductor 14 to a wiring conductor 13c on the bonding surface of the circuit board 17.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device capable of preventing a decrease in confidentiality and authenticity due to a security attack on the rear surface of a circuit board. [Background technology]

[0002] 2. Description of the Related Art With the advancement of semiconductor manufacturing technology, various semiconductor devices including integrated electronic circuits have been used to process signals.

[0003] In some types of signal processing (e.g., encryption and decryption), confidentiality and / or authenticity of the processed signals may be required. In this case, it is required that signals containing confidential information are not transmitted over signal lines that are directly accessible from the outside. It is also required that circuits that process signals containing confidential information do not leak the contents of the signals in the form of unwanted radio waves or power supply noise.

[0004] For example, Patent Document 1 discloses a technology for a back-surface buried wiring structure that prevents security attacks such as noise observation and fault injection via the back silicon substrate of an IC chip, and detects physical attacks from the back side, i.e., exposure attacks. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-110293 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, the above-mentioned Patent Document 1 has a problem that the back surface of the circuit board is exposed when flip-chip mounting is performed in which the electronic circuit side of the IC chip is mounted on the printed board with the electronic circuit side facing down. This makes it possible for an attacker to take evasive measures, such as a bypass attack in which a bypass circuit is provided for the wiring on the back surface, and creates the possibility of being subjected to advanced attacks by attackers.

[0007] The present invention has been made to solve the problems (issues) associated with the conventional technology described above, and aims to provide a semiconductor device that can prevent a decrease in confidentiality and authenticity due to security attacks on the back surface of a circuit board. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems and achieve the object, the present invention provides a semiconductor device in which a circuit board having a first surface on which an electronic circuit is formed and a second surface behind the first surface is mounted with the first surface facing a printed board, the semiconductor device further comprising a wiring board attached to the second surface of the circuit board, the circuit board having via conductors connecting the first surface and the second surface, and the electronic circuit is connected to a wiring conductor provided on a bonding surface of the wiring board through the via conductor. The wiring board has a capacitance wiring conductor formed of a strip conductor formed on the joint surface, the wiring conductor is connected so as to pass a discharge current of the capacitance wiring conductor, and the electronic circuit is provided with a capacitance sensor circuit that detects the approach of an object from a change in capacitance of the capacitance wiring conductor and detects a disconnection from the cessation of the discharge current. It is characterized by:

[0009] In the present invention, the circuit board and the wiring board are bonded together by oxide film bonding.

[0010] In the present invention, in the above-mentioned invention, the circuit board is flip-chip mounted on the printed board.

[0011] In the present invention, in the above-mentioned invention, the wiring conductor is formed of a strip conductor.

[0012] In the present invention, the wiring conductor is formed in a meandering shape, a stripe shape, or a mesh shape.

[0013] Further, the present invention relates to the above-mentioned invention, Further provided with a reference capacitance charge / discharge circuit for improving the sensitivity of capacitance measurement. It is characterized by:

[0015] The present invention also provides a method for producing a semiconductor device comprising the steps of: A semiconductor device is provided in which a circuit board has a first surface on which an electronic circuit is formed and a second surface behind the first surface, the first surface being mounted on a printed circuit board, the semiconductor device further comprising a wiring board attached to the second surface of the circuit board, the circuit board having via conductors connecting the first surface and the second surface, the electronic circuit being connected to a wiring conductor provided on a bonding surface of the wiring board through the via conductor, The wiring board is formed in a meandering shape over the entire joining surface, and the electronic circuit is characterized by including a capacitance sensor circuit that detects the cut location and the approach of an object by a change in capacitance of the wiring conductor. Effect of the Invention

[0017] According to the present invention, it is possible to provide a semiconductor device that can prevent a decrease in confidentiality and authenticity due to a security attack on the rear surface of a circuit board. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a perspective view showing a configuration of a semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the semiconductor device taken along line AA in FIG. [Diagram 3] FIG. 3 is a diagram showing a bonding surface of the wiring board of FIG. [Figure 4] FIG. 4 is a circuit diagram showing a configuration of a capacitance sensor circuit of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a timing chart showing the operation of the capacitance sensor circuit of FIG. [Figure 6] FIG. 6 is a circuit diagram showing a configuration of a cut detection circuit of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a timing chart showing the operation of the cutoff detection circuit in FIG. 6, in particular, the normal operation and the operation when the semiconductor device is under attack. [Figure 8] FIG. 8 is a diagram showing a bonding surface of a wiring substrate of the semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a circuit diagram showing a configuration of a capacitance sensor circuit of a semiconductor device according to the second embodiment. [Figure 10]FIG. 10 is a timing chart showing the operation of the capacitance sensor circuit of FIG. [Figure 11] FIG. 11 is a diagram showing a bonding surface of a wiring substrate of a semiconductor device according to the third embodiment. [Figure 12] FIG. 12 is a circuit diagram showing a configuration of a capacitance sensor circuit of a semiconductor device according to the third embodiment. [Figure 13] FIG. 13 is a timing chart showing the operation of the capacitance sensor circuit of FIG. [Figure 14] FIG. 14 is a circuit diagram showing a configuration of a high-resolution capacitive sensor circuit of a semiconductor device according to the fourth embodiment. [Figure 15] FIG. 15 is a timing chart showing the operation of the high resolution capacitive sensor circuit of FIG. [Figure 16] FIG. 16 is a diagram showing the principle for realizing the high resolution of the high resolution capacitive sensor circuit of FIG. [Figure 17] FIG. 17 is a diagram showing the results of a computer simulation of increasing the resolution of the high-resolution capacitive sensor circuit of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device according to the present invention will be described in detail with reference to the drawings.

[0020] [Embodiment 1] First, an overview of the semiconductor device according to the present embodiment 1 will be described. In the present embodiment 1, a semiconductor device will be described in which a circuit board 1 forming an electronic circuit 15 and a wiring board 17 forming wiring conductors 13a, 13b, and 13c for detecting security attacks are bonded by oxide film bonding.

[0021] Fig. 1 is a perspective view showing the configuration of a semiconductor device according to embodiment 1. As shown in Fig. 1, the semiconductor device includes a circuit board 1, a printed board 2, a wiring conductor 3, an oxide film bonding surface 16, and a wiring board 17. The circuit board 1 has two surfaces parallel to the XY plane of Fig. 1. Here, the surface on which the electronic circuit 15 is provided is referred to as the "first surface," and the surface opposite to the first surface is referred to as the "second surface."

[0022] The circuit board 1 includes a semiconductor substrate 11 and a plurality of wiring layers 12a formed in the semiconductor substrate 11 parallel to the XY plane. For example, the semiconductor substrate 11 is made of silicon, and the wiring layers 12a are made of copper. Note that the materials of the semiconductor substrate 11 and the wiring layers 12a are not limited to these. An electronic circuit 15 is formed on the circuit board 1. Also, the circuit board 1 includes via conductors 14 that connect the wiring layers 12a formed on the first surface of the circuit board 1 to the second surface of the circuit board 1.

[0023] The electronic circuit 15 includes a detection circuit that detects cutting attacks, bypass attacks, etc. on the semiconductor device. A first surface of the circuit board 1 is provided with a plurality of pad conductors 12ac for supplying power to the electronic circuit 15 and inputting and outputting signals.

[0024] 1, and includes a plurality of embedded wiring conductors 13 formed on the bonding surface with the circuit board 1. For example, the wiring board 17 is made of silicon, and the embedded wiring conductors 13 are made of copper.

[0025] An oxide film bonding surface 16 is formed on the second surface of the circuit board 1 except for the via conductor portion described later, and the wiring board 17 is placed on this oxide film bonding surface 16 to bond the two boards (circuit board 1 and wiring board 17). Since the oxide film is an insulating film, the oxide film bonding surface 16 is not formed on the via conductor portion of the second surface. Here, the oxide film bonding is a technique for bonding the wafers by placing silicon wafers on top of each other and heating them to form an oxide film on the bonding surface of the silicon wafers. The advantages of oxide film bonding include a high bonding strength and the ability to insulate the substrate potential of the wiring board 17 from the substrate potential (usually the ground potential) of the circuit board 1, making it a floating node.

[0026] With this configuration, it is possible to prevent a bypass attack by an attacker, since embedded wiring conductor 13 of wiring board 17 is not exposed on the surface opposite to the bonding surface of wiring board 17. Also, since the substrate potential of wiring board 17 is insulated from the substrate potential (usually ground potential) of circuit board 1 and is set to a floating potential, a change in the electric field from the outside can be detected by providing a capacitance circuit in wiring board 17.

[0027] The semiconductor device in which the circuit board 1 and the wiring board 17 are bonded together by oxide film bonding is flip-chip mounted on the printed circuit board 2 by, for example, bump conductors on the first surface of the circuit board 1 on which the electronic circuit 15 is formed. Such flip-chip mounting is a mounting technique in which bare chips, which are chips cut out from a semiconductor, are flipped (inverted) and mounted.

[0028] The printed circuit board 2 is used for connecting multiple semiconductor devices and for supplying a power supply voltage V DD The wiring conductor 3 is a substrate for applying a power supply voltage V DD The buried wiring conductor 13 is a wiring for applying a voltage and transmitting a signal. The buried wiring conductor 13 will be described later.

[0029] Next, the configuration of the semiconductor device according to the first embodiment will be described. Fig. 2 is a cross-sectional view of the semiconductor device taken along line AA in Fig. 1. As shown in Fig. 2, circuit board 1 includes semiconductor substrate 11, multilayer wiring conductor 12, via conductor 14, and electronic circuit 15. Furthermore, wiring board 17 includes embedded wiring conductor 13. Circuit board 1 and wiring board 17 are oxide-film bonded by oxide-film bonding surface 16.

[0030] Circuit board 1 and wiring board 17 are bonded with a strong bonding strength by oxide film bonding. Furthermore, the substrate potential of wiring board 17 is insulated from the substrate potential (usually ground potential) of circuit board 1, and is at a floating potential. Therefore, by providing a capacitance circuit in wiring board 17, it is possible to detect changes in the electric field from the outside.

[0031] The semiconductor substrate 11 has a multilayer wiring conductor 12 including a plurality of wiring layers 12a on a first surface of the circuit board 1. In the example of FIG. 2, the multilayer wiring conductor 12 includes six wiring layers 12a. Each wiring layer 12a is patterned by any semiconductor process technology. In this way, an electronic circuit 15 is formed in the multilayer wiring conductor 12. The electronic circuit 15 includes a plurality of circuit elements 15a such as transistors, diodes, capacitors, resistors, and inductors.

[0032] The electronic circuit 15 can be formed by a CMOS process technology or other process technology. A part of the wiring layer 12a is formed as a pad conductor 12ac. The via conductors 14 are formed penetrating the semiconductor substrate 11 in the Z direction (thickness direction). At least one via conductor 14 is electrically connected to the multilayer wiring conductor 12, and at least one via conductor 14 is formed as an electrode on the second surface of the circuit board 1.

[0033] The wiring board 17 has embedded wiring conductors 13 on the bonding surface of the wiring board 17. The embedded wiring conductors 13 are formed by digging grooves in the wiring board 17 by etching and embedding metal therein to form wiring. The printed circuit board 2 has already been described, so a detailed description thereof will be omitted here.

[0034] Next, the pattern of the bonding surface of the wiring board 17 of the semiconductor device according to the first embodiment will be described. Fig. 3 is a diagram showing the bonding surface of the wiring board 17 of Fig. 1. As shown in Fig. 3, the wiring conductors 13a and 13b are strip conductors formed in parallel to each other to form a mutual capacitance circuit. The nodes N31 and N32 are connected to the capacitance sensor circuit 20 in the electronic circuit 15 through the via conductor 14 of Fig. 2.

[0035] With this structure, when an attacker attempts to attack by bringing a probe close, the capacitance value measured by the capacitance sensor circuit 20 changes, making it possible to detect the fact that an attack has been attempted by bringing a probe close.

[0036] Moreover, wiring conductor 13c includes a plurality of linear strip conductors connected to each other, and is formed in a meandering shape from node N33 to node N34 so as to cover substantially the entire joint surface of wiring board 17. Nodes N33 and N34 are connected to disconnection detection circuit 30 in electronic circuit 15 through via conductor 14 of circuit board 1 bonded by an oxide film in FIG.

[0037] With this structure, when an attacker launches a remote attack using a laser, the wiring conductor 13c is cut and the cut detection circuit 30 can detect the fact that a cutting attack has occurred.

[0038] Next, the configuration of the capacitance sensor circuit 20 will be described. Fig. 4 is a circuit diagram showing the configuration of the capacitance sensor circuit 20 of the semiconductor device according to the first embodiment. As shown in Fig. 4, the capacitance sensor circuit 20 includes switching elements 21 and 22, a constant current source 23, a pulse gate circuit 24, and a pulse counter 25. The capacitance sensor circuit 20 is provided inside the electronic circuit 15, and is connected to nodes N31 and N32 in Fig. 3 through the via conductor 14 in Fig. 2.

[0039] The capacitance sensor circuit 20 repeats charging and discharging by alternately turning on and off the switching element 21 and the switching element 22. The pulse gate circuit 24 detects the voltage of the node N31 and the reference voltage V CThe voltage of node N31 is compared with the reference voltage V C When the voltage Vcc becomes lower than the threshold voltage Vcc, the pulse counter 25 outputs a pulse signal. The pulse counter 25 counts the number of pulses output by the pulse gate circuit 24 and outputs a pulse number D OUT Output.

[0040] Next, the operation of the capacitance sensor circuit 20 will be described. Fig. 5 is a timing chart showing the operation of the capacitance sensor circuit 20 of Fig. 4. As shown in Fig. 4, the voltage of the node N31 is equal to the power supply voltage V DD Thereafter, when switching element 21 is turned off and switching element 22 is turned on, the charge in the capacitance is discharged at a constant current by constant current source 23, and the voltage at node N31 drops in a slope shape.

[0041] The pulse gate circuit 24 detects whether the voltage at the node N31 is a reference voltage V C When it becomes lower (t1), the pulse signal V PULSE When charging the capacitance, the voltage at node N31 is equal to the reference voltage V C When it becomes higher (t2), the pulse signal V PULSE Stops output of.

[0042] When the capacitance value connected to the node N31 is large, the capacitance sensor circuit 20 detects that the voltage of the node N31 is closer to the reference voltage V C This is because when a large capacitance is discharged by the constant current source 23, it takes time to discharge, that is, the slope of the discharge of the voltage at the node N31 becomes gentler. On the other hand, when a capacitance is charged, the charging speed does not have much effect on the size of the capacitance value, so the timing at which the voltage at the node N31 becomes lower than the reference voltage V C The timing at which it becomes higher (t4) is the same as when the capacitance is small.

[0043] Therefore, the pulse signal V PULSE The time for which the pass signal V is output is long when the capacitance connected to the capacitance sensor circuit 20 is small, and is short when the capacitance is large.PULSE The capacitance value can be measured by counting the number of pulses using the pulse counter 25. In other words, the approach of an attacker's hand or a probe can be detected by the change in the capacitance value.

[0044] Next, the configuration of the disconnection detection circuit 30 will be described. Fig. 6 is a circuit diagram showing the configuration of the disconnection detection circuit 30 of the semiconductor device according to the first embodiment. As shown in Fig. 6, the disconnection detection circuit 30 includes switching elements 26 to 28 and a latch circuit 29. The disconnection detection circuit 30 is provided inside the electronic circuit 15, and is connected to nodes N33 and N34 in Fig. 3 through the via conductor 14 in Fig. 2. The disconnection detection circuit 30 receives a reset signal and a constant voltage from another part of the electronic circuit 15, and generates a detection signal.

[0045] Next, the operation of the cut detection circuit 30 will be described. Fig. 7 is a timing chart showing the operation of the cut detection circuit 30 of Fig. 6, in the normal operation and the operation when the semiconductor device is attacked. Normally, the voltage of the node N33 is equal to the voltage of the node N34 (ground voltage), and the detection signal remains at a low level. In contrast, when the semiconductor device is remotely attacked by a laser and the wiring conductor 13c is cut, the voltage of the node N33 becomes a high voltage. As a result, the detection signal transitions from a low level to a high level.

[0046] When the detection signal transitions from a low level to a high level, the operation of the electronic circuit 15 is stopped, thereby making it possible to protect the signals processed inside the semiconductor device from an attacker.

[0047] As described above, in the first embodiment, the circuit board 1 and the wiring board 17 are bonded together by oxide film bonding, so that the circuit such as the wiring conductor is not exposed on the back surface of the semiconductor device, and bypass attacks from the back surface can be prevented. In addition, by providing the wiring conductors 13a, 13b, and 13c in the semiconductor device and the capacitance sensor circuit 20 and the cut detection circuit 30 in the electronic circuit 15, it is possible to detect the approach of an attacker's probe and the fact that a cutting attack has been made. The semiconductor device according to the first embodiment can prevent the deterioration of confidentiality and authenticity due to security attacks by stopping the operation of the electronic circuit 15 when it detects the approach of an attacker's probe and the fact that a cutting attack has been made.

[0048] [Embodiment 2] Incidentally, in the above-mentioned embodiment 1, separate circuits are used for detecting the approach of an attacker's probe and for detecting the fact that a cutting attack has been made, but this complicates the structure of the electronic circuit 15. Therefore, in the present embodiment 2, a semiconductor device will be described in which detection of the approach of an attacker's probe and detection of the fact that a cutting attack has been made are performed using a single circuit.

[0049] First, the bonding surface of the wiring board 17 of the semiconductor device according to the second embodiment will be described. FIG. 8 is a diagram showing the bonding surface of the wiring board 17 of the semiconductor device according to the second embodiment. As shown in FIG. 8, the wiring conductor 13d forms a flat self-capacitance circuit using a strip conductor. The wiring conductor 13e includes a plurality of linear strip conductors connected to each other, and is formed in a meandering shape from the node N36 to the node N37 so as to substantially cover the entire bonding surface of the wiring board 17. The nodes N35, N36, and N37 are connected to the capacitance sensor circuit 40 in the electronic circuit 15 through the via conductor 14 of the circuit board 1 bonded by the oxide film in FIG. 2.

[0050] The wiring conductor 13d is connected as a self-capacitance circuit to a capacitance sensor circuit 40 in the electronic circuit 15. The capacitance value of the wiring conductor 13d increases when a probe or the like approaches. Therefore, the capacitance sensor circuit 40 can detect the change in the capacitance value and detect the approach of the probe or the like.

[0051] Furthermore, the wiring conductor 13e is connected via nodes N36 and N37 to a charge discharge path of a self-capacitance circuit formed by the wiring conductor 13d of the capacitance sensor circuit 40. When an attacker performs a cutting attack or the like, the wiring conductor 13e is cut and the potential of the node N35 becomes high, so that the capacitance sensor circuit 40 can detect the fact that an attacker has performed a remote attack or the like using a laser.

[0052] Next, the configuration of the capacitance sensor circuit 40 will be described. Fig. 9 is a circuit diagram showing the configuration of the capacitance sensor circuit 40 of the semiconductor device according to the second embodiment. As shown in Fig. 9, the capacitance sensor circuit 40 includes switching elements 31 and 32, a constant current source 33, a pulse gate circuit 34, and a pulse counter 35. The capacitance sensor circuit 40 is provided inside the electronic circuit 15, and is connected to nodes N35, N36, and N37 in Fig. 8 through the via conductor 14 in Fig. 2.

[0053] The capacitance sensor circuit 40 repeatedly charges and discharges the self-capacitance circuit formed by the wiring conductor 13d by alternately turning on and off the switching element 31 and the switching element 32. Meanwhile, a meander circuit formed by the wiring conductor 13e is connected to the discharge path of the capacitance sensor circuit 40. The pulse gate circuit 34 detects the voltage of the node N35 and the reference voltage V C The voltage at node N35 is compared with the reference voltage V C When the voltage Vcc is lower than the threshold voltage Vcc, the pulse counter 35 outputs a pulse signal. The pulse counter 35 counts the number of pulses output by the pulse gate circuit 24 and outputs a pulse number D OUT Output.

[0054] Next, the operation of the capacitance sensor circuit 40 will be described. Fig. 10 is a timing chart showing the operation of the capacitance sensor circuit 40 of Fig. 9. As shown in Fig. 10, the voltage of the node N35 is equal to the power supply voltage V DDThereafter, when switching element 31 is turned off and switching element 32 is turned on, the charge in the capacitance is discharged via wiring conductor 13a at a constant current from constant current source 33, and the voltage at node N35 drops in a slope pattern.

[0055] The pulse gate circuit 34 detects whether the voltage at the node N35 is a reference voltage V C When it becomes lower (t5), the pulse signal V PULSE When charging the capacitance, the voltage at node N35 is equal to the reference voltage V c When it becomes higher (t6), the pulse signal V PULSE Stops output of.

[0056] When the capacitance value connected to node N35 is large, the capacitance sensor circuit 40 detects that the voltage at node N35 is closer to the reference voltage V C This is because when a large capacitance is discharged by the constant current source 33, it takes time to discharge. In other words, this is because the slope of the discharge of the voltage at the node N35 becomes gentler. On the other hand, when a capacitance is charged, the charging speed does not have much effect on the size of the capacitance value, so the timing at which the voltage at the node N35 becomes lower than the reference voltage V C The timing at which it becomes higher (t8) is the same as when the capacitance value is small.

[0057] Therefore, the pulse signal V PULSE The time for which the pass signal V is output is long when the capacitance connected to the capacitance sensor circuit 40 is small, and is short when the capacitance is large. PULSE The capacitance value can be measured by counting the number of pulses with the pulse counter 35. In other words, the approach of an attacker's hand or probe can be detected by the change in the capacitance value. Also, if the semiconductor device is subjected to a remote attack by an attacker using a laser, the wiring conductor 13e is cut off. Therefore, the charge is not discharged and the node N35 is fixed to the power supply potential. As a result, the pulse signal V PULSE This will stop the output of the laser, making it possible to detect the fact that a remote laser attack has been launched by an attacker.

[0058] As described above, the semiconductor device according to the second embodiment can detect the approach of an attacker's probe or the like and the fact that a remote attack using a laser has been received, by including the wiring conductor 13d, the wiring conductor 13e, and the capacitance sensor circuit 40 in the electronic circuit 15. The semiconductor device according to the second embodiment can prevent a decrease in confidentiality and authenticity due to a security attack by stopping the operation of the electronic circuit 15 when it detects the approach of an attacker's probe or the fact that a remote attack using a laser has been received.

[0059] [Embodiment 3] Incidentally, in the above-mentioned first and second embodiments, two circuits are required: a capacitance circuit for detecting the approach of a probe and a meandering circuit for detecting the disconnection of wiring due to a remote attack by a laser. Therefore, in the third embodiment, a semiconductor device that detects the approach of a probe and the disconnection of wiring due to a remote attack by a laser using only a meandering circuit will be described.

[0060] First, the bonding surface of the wiring board 17 of the semiconductor device according to the third embodiment will be described. Fig. 11 is a diagram showing the bonding surface of the wiring board 17 of the semiconductor device according to the third embodiment. As shown in Fig. 11, the wiring conductor 13f includes a plurality of linear strip conductors connected to each other, and is formed in a meandering shape from node N38 to node N39 so as to cover substantially the entire bonding surface of the wiring board 17. The nodes N38 and N39 are connected to the capacitance sensor circuit 50 in the electronic circuit 15 through the via conductor 14 of the circuit board 1 electrically connected by the oxide film bonding in Fig. 2.

[0061] The wiring conductor 13f is connected as a self-capacitance circuit to a capacitance sensor circuit 50 in the electronic circuit 15. The capacitance value of the wiring conductor 13f increases when a probe or the like approaches. Therefore, the capacitance sensor circuit 50 can detect the change in the capacitance value and detect the fact that a probe or the like is approaching.

[0062] Furthermore, when the wiring conductor 13f is cut by a remote attack using a laser, the capacitance value of the wiring conductor 13f decreases. Therefore, the capacitance sensor circuit 50 can detect this decrease in capacitance value and detect the fact that a remote attack using a laser has been received from an attacker.

[0063] Next, the configuration of the capacitance sensor circuit 50 will be described. Fig. 12 is a circuit diagram showing the configuration of the capacitance sensor circuit 50 of the semiconductor device according to the third embodiment. As shown in Fig. 12, the capacitance sensor circuit 50 includes switching elements 41 and 42, a constant current source 43, a pulse gate circuit 44, and a pulse counter 45. The capacitance sensor circuit 50 is provided in the electronic circuit 15, and is connected to the node 38 and the node N39 in Fig. 11 through the via conductor 14 in Fig. 2.

[0064] The capacitance sensor circuit 50 repeats charging and discharging by alternately turning on and off the switching element 41 and the switching element 42. The pulse gate circuit 44 controls the voltage of the node N38 and the reference voltage V C The voltage at node N38 is compared with the reference voltage V C When the voltage Vcc is lower than the threshold voltage Vcc, the pulse counter 45 outputs a pulse signal. The pulse counter 45 counts the number of pulses output by the pulse gate circuit 44 and outputs a pulse number D OUT Output.

[0065] Next, the operation of the capacitance sensor circuit 50 will be described. Fig. 13 is a timing chart showing the operation of the capacitance sensor circuit 50 of Fig. 12. As shown in Fig. 12, the voltage of the node N38 is equal to the power supply voltage V DD Thereafter, when switching element 41 is turned off and switching element 42 is turned on, the charge in the capacitance is discharged at a constant current by constant current source 43, and the voltage at node N38 drops in a slope shape.

[0066] The pulse gate circuit 44 detects whether the voltage at the node N38 is a reference voltage V C When it becomes lower (t9), the pulse signal V PULSEWhen charging the capacitance, the voltage at node N38 is equal to the reference voltage V C becomes higher (t 10 ) and pulse signal V PULSE Stops output of.

[0067] When the capacitance value connected to node N38 is large, the capacitance sensor circuit 50 detects that the voltage at node N38 is closer to the reference voltage V than when the capacitance value is low. C lower (t 11 ) timing becomes slower. This is because when a large capacitance is discharged by the constant current source 43, it takes time to discharge, that is, the slope of the discharge of the voltage at the node N38 becomes gentler. On the other hand, when a capacitance is charged, the charging speed does not have much effect on the size of the capacitance value, so the voltage at the node N38 becomes slower than the reference voltage V C becomes higher (t 12 ) timing is the same as when the capacity is small.

[0068] On the other hand, when the wiring conductor 13f is cut, the self-capacitance value of the wiring conductor 13f decreases in the capacitance sensor circuit 50. As a result, the voltage of the node N38 becomes equal to or lower than the reference voltage V C The timing when it becomes lower (t 13 ) is earlier than the timing before the wiring conductor 13f is cut, for example, than t9. With this configuration, it is possible to detect the approach of an attacker's probe and the fact that a remote attack using a laser has been received, using only the wiring conductor 13f. In addition, since the capacitance value changes depending on the wiring length from the cut location of the wiring conductor 13f to the node N38, the cut location can also be identified by measuring the capacitance value with the capacitance sensor circuit 50.

[0069] As described above, in the third embodiment, the semiconductor device is provided with the wiring conductor 13f and the capacitance sensor circuit 50 in the electronic circuit 15, thereby making it possible to detect the approach of a probe by an attacker and the fact that a remote attack using a laser has been received. The semiconductor of the third embodiment stops the operation of the electronic circuit 15 when it detects the approach of a probe or the fact that a remote attack using a laser has been received, thereby making it possible to prevent a decrease in confidentiality and authenticity due to a security attack from the back side of the circuit board 1.

[0070] [Embodiment 4] However, in the above-mentioned embodiments 1 to 3, there are cases where the resolution of the capacitance sensor circuit is insufficient. Therefore, in embodiment 4, a semiconductor device in which the resolution of the capacitance sensor circuit is improved will be described.

[0071] First, the configuration of the high-resolution capacitance sensor circuit 60 of the semiconductor device according to the fourth embodiment will be described. Fig. 14 is a circuit diagram showing the configuration of the high-resolution capacitance sensor circuit 60 of the semiconductor device according to the fourth embodiment. As shown in Fig. 14, the high-resolution capacitance sensor circuit 60 includes a charge / discharge circuit 60a including switching elements 51 and 52 and a constant current source 53, a charge / discharge circuit 60b including switching elements 54 and 55, a constant current source 56 and a reference capacitance 59, a pulse gate circuit 57 and a pulse counter 58. The high-resolution capacitance sensor circuit 60 is provided inside the electronic circuit 15 and is connected to the nodes N35, N36 and N37 in Fig. 3 through the via conductor 14 in Fig. 2.

[0072] The high resolution capacitive sensor circuit 60 is connected to a power supply voltage V DD The self-capacitance circuit formed by the wiring conductor 13d is repeatedly charged and discharged by alternately turning on and off the switching elements 51 and 52 of the charge / discharge circuit 60a connected to the high resolution capacitance sensor circuit 60. The meander circuit formed by the wiring conductor 13e is connected to the discharge path of the high resolution capacitance sensor circuit 60. The high resolution capacitance sensor circuit 60 is connected to a reference voltage V CBy alternately turning on and off switching elements 54 and 55 of a charge / discharge circuit 60 b connected to the node N 40 , reference capacitor 59 is repeatedly charged and discharged, and the voltage at node N 40 is used as the reference voltage for pulse gate circuit 57 .

[0073] When the voltage of node N35 becomes lower than the voltage of node N40, the pulse gate circuit 57 outputs a pulse signal V PULSE During the time when the pulse gate circuit 57 outputs a pulse, the voltage of the node N40 changes in a slope shape, so that the pulse signal V PULSE The time for which the output is longer. In other words, the number of pulses output for a certain capacitance value D OUT Since the capacitance per unit pulse is increased, the capacitance value per unit pulse is decreased, and the resolution is increased. The pulse counter 58 counts the number of pulses output by the pulse gate circuit 57, and the number of pulses D OUT Output.

[0074] Next, the operation of the high resolution capacitance sensor circuit 60 will be described. Fig. 15 is a timing chart showing the operation of the high resolution capacitance sensor circuit 60 of Fig. 14. As shown in Fig. 14, the voltage of the node N35 is equal to or higher than the power supply voltage V DD Thereafter, when switching element 51 is turned off and switching element 52 is turned on, the charge in the capacitance is discharged via wiring conductor 13e with a constant current from constant current source 53, and the voltage at node N35 drops in a slope pattern.

[0075] In addition, the voltage of the node N40, which is the reference voltage of the pulse gate circuit 57, is the reference voltage V C Thereafter, when switching element 54 is turned off and switching element 55 is turned on, the charge in reference capacitor 59 is discharged with a constant current from constant current source 56, and the voltage at node N40 also drops in a slope shape.

[0076] The pulse gate circuit 57 operates such that the voltage at the node N35 becomes lower than the voltage at the node N40 (t 15 ) and pulse signal V PULSE When charging the capacitance, the voltage of node N35 becomes higher than the voltage of node N40 (t 16 ) and pulse signal V PULSE Stops output of.

[0077] In the high resolution capacitance sensor circuit 60, when the capacitance value connected to the node N35 is large, the voltage of the node N35 becomes lower than the voltage of the node N40 (t 17 ) timing becomes slower. This is because when a large capacitance is discharged by constant current source 53, it takes time to discharge, that is, the slope of the discharge of the voltage at node N35 becomes gentler. On the other hand, when a capacitance is charged, the charging speed does not have much effect on the size of the capacitance value, so the voltage at node N35 becomes higher than the voltage at node N45 (t 18 ) The timing is the same as when the capacitance value is small.

[0078] Therefore, the pulse signal V PULSE The time when the capacitance connected to the high resolution capacitance sensor circuit 60 is small is long, and when it is large is short. OUT Since the voltage of the node N40 that controls the output of the capacitance sensor circuit 20 is changed in a slope shape, even if the capacitance value connected to the node N35 is the same as that of the conventional capacitance sensor circuit 20, the pulse signal V PULSE The time for which the pulse is output can be extended.

[0079] Next, the principle for realizing the high resolution of the high resolution capacitive sensor circuit 60 will be described. Fig. 16 is a diagram showing the principle for realizing the high resolution of the high resolution capacitive sensor circuit 60 of Fig. 14. As shown in Fig. 16, the slope of the voltage change of the node N35 in the normal state (hereinafter referred to as "slope 5") is expressed as follows: SENSE If the current value of the constant current source 53 is I1, then it can be expressed by the following equation. dV / dt=I1 / C SENSE

[0080] When an attacker brings a probe or the like close, the capacitance value of node N35 of high-resolution capacitance sensor circuit 60 increases. If the increased capacitance value is ΔC, the slope of the voltage change at node N35 (hereinafter referred to as “slope 6”) is expressed by the following equation. dV / dt=I1 / C SENSE +ΔC

[0081] Here, the reference voltage of the pulse gate circuit 24 of the conventional capacitance sensor circuit 20 is V C ', the pulse signal V of the pulse gate circuit 24 in the normal state PULSE The voltage at node N35 with a slope of 5 is the reference voltage V C 'The timing when it became lower (t 19 ) is output from the pulse gate circuit 24. Also, when an attacker brings a probe or the like close, the pulse signal V PULSE The voltage at node N35 with a slope of 6 is the reference voltage V C 'The timing when it became lower (t 20 ) is output.

[0082] The pulse signal V of the pulse gate circuit 24 PULSE The voltage at node N35 is equal to the reference voltage V C ', the charge stops when the capacitance becomes higher than 0.01, but in the case of charging, the charge is almost constant regardless of the capacitance value. Therefore, the number of pulses counted by the pulse counter 25 in normal operation and when an attacker approaches a probe, etc., is D OUT Difference dD OUT is the number of pulses per unit time, P t Then, it is expressed by the following equation. dD OUT =(t 20 -t 19 )×P t

[0083] On the other hand, the slope of the node N40 of the pulse gate circuit 57 of the high resolution capacitance sensor circuit 60 (hereinafter referred to as "slope 7") is a slope of the capacitance value of the reference capacitor 59, C REFIf the current value of the constant current source 56 of the charge / discharge circuit 60b is I2, then it can be expressed by the following equation. dV / dt=I2 / C REF

[0084] The pulse output V of the pulse gate circuit 57 in the normal state of the high-resolution capacitance sensor circuit 60 PULSE is the timing (t 19 ) is output from the pulse gate circuit 57. Also, when an attacker brings a probe or the like close, the pulse signal V PULSE is the timing (t 21 ) is output.

[0085] The pulse signal V of the pulse gate circuit 57 PULSE The operation stops when the voltage at node N35 becomes higher than the voltage at node N40 with a gradient of 7, but in the case of charging, it is almost constant regardless of the capacitance value. Therefore, the number of pulses D counted by the pulse counter 58 in normal operation and when an attacker approaches a probe or the like is OUT Difference dD OUT2 is the number of pulses per unit time, P t Then, it is expressed by the following equation. dD OUT2 =(t 21 -t 19 )×P t

[0086] Here, t 21 t 20 Since it is larger than dD OUT2 ddD OUT In this way, when the same capacitance difference ΔC is expressed as the number of pulses, the number of pulses D OUT The larger the value of , the smaller the capacitance change per unit pulse, and therefore the higher the resolution. In other words, a high-resolution sensor can be realized.

[0087] Next, the characteristics of the high resolution capacitive sensor circuit 60 will be described with reference to simulation results. Fig. 17 is a diagram showing the results of a computer simulation of increasing the resolution of the high resolution capacitive sensor circuit 60 of Fig. 14. As shown in Fig. 17, the computer simulation calculated the output of the pulse counter 25 of the conventional capacitive sensor circuit 20 and the output of the pulse counter 58 of the high resolution capacitive sensor circuit 60 when the capacitance difference ΔC was changed from 1 fF to 1 pF.

[0088] Pulse count D of pulse counters 25 and 58 OUT When comparing the outputs, the output of the pulse counter 58 of the high resolution capacitance sensor circuit 60 changes more significantly for the same change in capacitance, and the high resolution capacitance sensor circuit 60 can achieve high resolution for changes in capacitance value.

[0089] As described above, in the fourth embodiment, a high-resolution capacitance sensor circuit 60 having high resolution for capacitance changes can be realized by using a slope-shaped voltage change by using the reference capacitor 59 and the charge / discharge circuit 60b for the reference signal of the pulse gate circuit 57. The high-resolution capacitance sensor circuit 60 can detect the approach of a probe due to an attack on the back surface of the circuit board 1 or the fact that a remote attack using a laser has been received from a smaller capacitance change, and can prevent a decrease in confidentiality or authenticity due to a security attack.

[0090] The configurations illustrated in the above embodiments are merely functional schematics, and are not necessarily physically configured as illustrated. In other words, the form of distribution and integration of each device is not limited to that illustrated, and all or part of the devices can be functionally or physically distributed and integrated in any unit according to various loads, usage conditions, etc. [Industrial Applicability]

[0091] The semiconductor device according to each embodiment of the present invention is suitable for preventing a decrease in confidentiality and authenticity due to a security attack on the back surface. [Explanation of symbols]

[0092] 1 Circuit Board 2 Printed circuit board 3. Wiring conductor 11 Semiconductor substrate 12 Multilayer wiring conductor 12a wiring layer 12ac Pad Conductor 13 Buried wiring conductor 13a 13b, 13c, 13d, 13e 13f Wiring conductor 14 Via conductor 15 Electronic circuits 16 Oxide film bonding surface 17 Wiring board 20, 40, 50 Capacitive sensor circuit 21, 22, 26, 27, 28, 31, 32, 41, 42, 51, 52, 54, 55 Switching elements 23, 33, 43, 53, 56 constant current source 24, 34, 44, 57 Pulse gate circuit 25, 35, 45, 58 Pulse Counter 29 Latch Circuit 30 Disconnection detection circuit 59 Reference capacity 60 High Resolution Capacitive Sensor Circuit 60a, 60b charge / discharge circuit Nodes N31 to N40

Claims

1. A semiconductor device comprising: a circuit board having a first surface on which an electronic circuit is formed and a second surface behind the first surface; and a semiconductor device mounted on the circuit board with the first surface facing a printed circuit board, a wiring board attached to the second surface of the circuit board, the circuit board includes a via conductor connecting the first surface and the second surface; the electronic circuit is connected to a wiring conductor provided on a bonding surface of the wiring board through the via conductor; The wiring board has a capacitance wiring conductor formed of a strip conductor on the bonding surface, the wiring conductor is connected so as to pass a discharge current of the capacitance wiring conductor; The electronic circuit includes: A capacitance sensor circuit is provided for detecting the approach of an object from a change in capacitance of the capacitance wiring conductor and detecting disconnection from the cessation of discharge current. A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the circuit board and the wiring board are bonded together by oxide film bonding.

3. 2. The semiconductor device according to claim 1, wherein the circuit board is flip-chip mounted on the printed circuit board.

4. 2. The semiconductor device according to claim 1, wherein the wiring conductor is formed of a strip conductor.

5. 5. The semiconductor device according to claim 4, wherein the wiring conductor is formed in a meandering, stripe or mesh shape.

6. A semiconductor device according to claim 1, further comprising a reference capacitance charge / discharge circuit for improving the sensitivity of capacitance measurement.

7. A semiconductor device comprising a circuit board having a first surface on which an electronic circuit is formed and a second surface behind the first surface, the first surface of the circuit board being mounted toward a printed circuit board, a wiring board attached to the second surface of the circuit board, the circuit board includes a via conductor connecting the first surface and the second surface; the electronic circuit is connected to a wiring conductor provided on a bonding surface of the wiring board through the via conductor; The wiring board is formed in a meandering shape on the entire bonding surface, The electronic circuit includes: a capacitance sensor circuit for detecting a cut location and an approach of an object based on a change in capacitance of the wiring conductor.

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