Serial Data Receiving Circuit

Abstract

To provide an improved serial data reception circuit.SOLUTION: A serial data reception circuit according to one example of the present invention includes input that receives an analog input signal, and includes a first sampler that samples the analog input signal with respect to a first reference voltage, a second sampler that samples the analog input signal with respect to a second reference voltage with an opposite sign of the first reference voltage, and a reference voltage control circuit that adjusts the first reference voltage or the second reference voltage on the basis of a first sample of the analog input signal. The first sample is the sample acquired in sampling time corresponding to one bit that is one bit before and one bit after in the serial data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a serial data receiving circuit.

[0002] This application claims priority to U.S. Patent Application No. 62 / 975,540, filed in the United States Patent and Trademark Office on February 12, 2020, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Baud-rate receivers for serial data are useful in that they can use a single clock phase and do not require a phase interpolator. However, such receivers can use parameters such as a reference voltage that are controlled by other circuits. In a similar way, it is useful to control the parameters of a continuous time linear equalizer. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT EMBODIMENT The problem that the present invention seeks to solve is to provide an improved serial data receiving circuit. [Means for solving the problem]

[0005] A serial data receiving circuit according to one embodiment of the present invention is a serial data receiving circuit having an input for receiving an analog input signal, comprising a first sampler for sampling the analog input signal against a first reference voltage, a second sampler for sampling the analog input signal against a second reference voltage having an opposite sign to the first reference voltage, and a reference voltage control circuit for adjusting the first reference voltage or the second reference voltage based on a first sample of the analog input signal, the first sample being taken at a sampling time corresponding to one bit that is one bit ahead and one bit behind in the serial data.

[0006] According to an embodiment of the present invention, the magnitude of the second reference voltage may be equal to the magnitude of the first reference voltage.

[0007] According to one embodiment of the present invention, the reference voltage control circuit may adjust a third reference voltage based on the first sample, and the first reference voltage may be equal to a function of the third reference voltage.

[0008] According to an embodiment of the present invention, the second reference voltage may be equal to a function of the third reference voltage.

[0009] According to one embodiment of the present invention, the first reference voltage may be equal to a first fraction of the third reference voltage, the first fraction being within 20% of 1 / 3, and the second reference voltage may be equal to a second fraction of the third reference voltage, the second fraction being within 20% of -1 / 3.

[0010] According to one embodiment of the present invention, the adjustment of the third reference voltage may include increasing the third reference voltage when the first sample is greater than the third reference voltage, and decreasing the third reference voltage when the first sample is less than the third reference voltage.

[0011] According to one embodiment of the present invention, the reference voltage control circuit may include a third sampler that samples the analog input signal against the third reference voltage, a first pattern filter that selects a bit pattern including three consecutive 1 bits, and a first accumulator that accumulates an output value of the third sampler in a register for a sample corresponding to a second bit of each pattern matched by the first pattern filter.

[0012] According to one embodiment of the present invention, the output of the first pattern filter may be used for adjusting DFE coefficients of an order greater than one.

[0013] According to an embodiment of the present invention, the reference voltage control circuit may further include a first digital-to-analog converter that generates the third reference voltage from a register of the first accumulator.

[0014] The serial data receiving circuit according to an embodiment of the present invention may further include a continuous-time linear equalizer coupled to the input.

[0015] The serial data receiving circuit according to an embodiment of the present invention may further include an equalizer control circuit coupled to the continuous-time linear equalizer for controlling one or more control parameters of the continuous-time linear equalizer.

[0016] According to one embodiment of the present invention, the equalizer control circuit may include a fourth sampler that samples the analog input signal against a fourth reference voltage, a second pattern filter that selects a bit pattern including one bit that is 0 bits ahead and 0 bits behind, a second accumulator that accumulates in a register the output value of the fourth sampler for a sample corresponding to the second bit of each pattern matched by the second pattern filter, and a second digital-to-analog converter that generates the fourth reference voltage from the register of the second accumulator.

[0017] According to one embodiment of the present invention, the equalizer control circuit may further include a fifth sampler that samples the analog input signal against a fifth reference voltage, a third pattern filter that selects a bit pattern including one bit that is 0 bits ahead and 0 bits behind, a third accumulator that accumulates in a register a weighted output value of the fifth sampler for a sample corresponding to the second bit of each pattern matched by the third pattern filter, and a third digital-to-analog converter that generates the fifth reference voltage from the register of the third accumulator.

[0018] According to one embodiment of the present invention, the weighting value for weighting positive sampler output values ​​may be within 20% of 0.16, and the weighting value for weighting negative sampler output values ​​may be within 20% of 0.84.

[0019] The serial data receiving circuit according to one embodiment of the present invention may further include a processing circuit that calculates a bit error rate indicator based on a register of the first accumulator, a register of the second accumulator, and a register of the third accumulator.

[0020] According to one embodiment of the present invention, the processing circuitry may calculate the bit error rate indicator for each of a plurality of settings of one or more control parameters of the continuous-time linear equalizer, and set the control parameter to the setting that maximizes the bit error rate indicator.

[0021] A serial data receiving circuit according to one embodiment of the present invention is a serial data receiving circuit having an input for receiving an analog input signal, comprising a baud-rate clock and data recovery circuit, and a reference voltage control circuit for controlling a first reference voltage or a second reference voltage of the baud-rate clock and data recovery circuit, the reference voltage control circuit comprising a first sampler for sampling the analog input signal against a third reference voltage, a first pattern filter for selecting a bit pattern including three consecutive 1 bits, and a first accumulator for accumulating an output value of the first sampler in a register for a sample corresponding to a second bit of each pattern matched by the first pattern filter.

[0022] According to an embodiment of the present invention, the reference voltage control circuit may further include a digital-to-analog converter that generates the third reference voltage from a register of the first accumulator.

[0023] According to one embodiment of the present invention, the first reference voltage may be equal to a first fraction of the third reference voltage, the first fraction being within 20% of 1 / 3, and the second reference voltage may be equal to a second fraction of the third reference voltage, the second fraction being within 20% of -1 / 3.

[0024] A serial data receiving circuit according to one embodiment of the present invention is a serial data receiving circuit having an input for receiving an analog input signal, comprising a baud-rate clock and data recovery means, and a reference voltage control circuit for controlling a first reference voltage or a second reference voltage of the baud-rate clock and data recovery means, the reference voltage control circuit comprising a first sampler for sampling the analog input signal against a third reference voltage, a first pattern filter for selecting a bit pattern including three consecutive 1 bits, and a first accumulator for accumulating an output value of the first sampler in a register for a sample corresponding to a second bit of each pattern matched by the first pattern filter. Effect of the Invention

[0025] According to one embodiment of the present invention, a serial data receiving circuit can be improved. [Brief description of the drawings]

[0026] [Figure 1] 1 is a block diagram of a data transmission system according to an embodiment of the present invention. [Figure 2A] FIG. 4 is a waveform diagram according to one embodiment of the present invention. [Figure 2B] FIG. 2 is a circuit diagram of a baud rate CDR and reference voltage control circuit according to one embodiment of the present invention. [Figure 2C] 1 is a graph showing an estimation error according to one embodiment of the present invention. [Figure 3A] FIG. 2 is a schematic diagram of a CTLE according to one embodiment of the present invention. [Figure 3B] 1 is a graph showing a CTLE frequency response according to one embodiment of the present invention. [Figure 3C] 1 is an equation illustrating the behavior of the CTLE according to one embodiment of the present invention. [Figure 4A] 2 is a circuit diagram of a portion of an equalizer control circuit according to one embodiment of the present invention. [Figure 4B] 2 is a circuit diagram of a portion of an equalizer control circuit according to one embodiment of the present invention. [Figure 4C]1 is a normal distribution graph according to one embodiment of the present invention. [Figure 5A] 11 is a graph of a simulation result according to one embodiment of the present invention. [Figure 5B] 11 is a graph of a simulation result according to one embodiment of the present invention. [Figure 5C] 11 is a graph of a simulation result according to one embodiment of the present invention. [Figure 5D] 11 is a graph of a simulation result according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The detailed description below relates to an embodiment of a system and method for controlling CDR and CTLE parameters, and does not represent all aspects realized or utilized by the embodiment of the present invention. However, the same or equivalent functions and structures realized in different embodiments are included within the scope of the present invention. The same reference numerals are used throughout the specification to refer to the same or similar components.

[0028] FIG. 1 illustrates a system for transmitting digital data from a serial transmitter 105 to a serial receiver 110. The system illustrated in FIG. 1 may be used for or within a display device, for example, to transmit video data (from a host) to a display device, or within a display device to transmit data from a timing controller to respective driver integrated circuits over a serial data link. In accordance with one embodiment of the present invention, the serial transmitter 105 is coupled to the serial receiver 110 via a channel 115 that causes the waveform received by the receiver 110 to be different from the waveform transmitted by the transmitter 105. For example, the channel 115 exhibits attenuation with frequency. For example, the channel 115 has more attenuation at higher frequencies than at lower frequencies.

[0029] The serial receiver 110 may include a continuous time linear equalizer (CTLE) 120. The CTLE 120 may exhibit a frequency dependent attenuation (or gain) designed to partially compensate for the attenuation due to the frequency of the channel 115. The serial receiver 110 may further include a clock and data recovery circuit (CDR) 125. The CDR 125 is used to infer the phase and frequency of a clock contained in the received signal to detect data in the received signal. The continuous time linear equalizer 120 may be an analog circuit that receives an analog signal from the channel 115 and generates an analog output signal that is sent to the clock and data recovery circuit 125. The clock and data recovery circuit 125 may receive the analog output signal from the continuous time linear equalizer 120 and generate a digital data stream as an output.

[0030] As will be described in more detail below, the clock and data recovery circuit 125 may use one or more reference voltages generated by a reference voltage control circuit (RVC) 130 during operation. As will be described in more detail below, the frequency response of the continuous-time linear equalizer 120 may be controlled by one or more control signals, which may be generated by an equalizer control circuit (EC) 135. A decision feedback equalizer (DFE) 137 may be used to remove the effect of previous data on the current data. Control of the DFE 137 may also be adjusted using the reference voltage control circuit 130.

[0031] 2A is a graph showing a portion of two waveforms at the output of the continuous-time linear equalizer 120. A first waveform 205 corresponding to the bit sequence 011 and a second waveform 210 corresponding to the bit sequence 100 are shown. At the transition sampling point 215, the data can be inferred by comparing the preceding bit with an upper threshold (e.g., a first threshold voltage) α if the preceding bit is 1, and with a lower threshold (e.g., a second threshold voltage) -α if the preceding bit is 0. The clock phase error can be measured by determining whether the two bit patterns touch an applicable threshold (e.g., a second threshold voltage for a sequence of 100) before the clock edge (meaning the clock is late) or after the clock edge (meaning the clock is early). Thus, the sampling method of the bit sequences 011 and 100 can be used for clock recovery. For example, in one embodiment of the present invention, using a single clock edge to perform clock and data recovery (instead of using two clocks separated by a half bit period to trigger the data sampler and crossing sampler, respectively) is referred to as "baud-rate clock and data recovery."

[0032] FIG. 2B shows a circuit including a baud-rate clock and data recovery circuit 125. The baud-rate clock and data recovery circuit 125 includes a first sampler 225, a second sampler 230, a first multiplexer 235, a second multiplexer 240, a CDR pattern filter 245, and a flip-flop 250. The first sampler 225 samples the analog input signal Vin against a first reference voltage, and the second sampler 230 samples the analog input signal Vin against a second reference voltage that is the same (approximately, but not necessarily exactly) as the inverse voltage of the first reference voltage, i.e., the same or nearly the same, as shown in FIG. 2B. The first multiplexer 235 operates as a crossing multiplexer, and the second multiplexer 240 operates as a data multiplexer. The CDR pattern filter 245 filters for the bit patterns 011 and 100, and the flip-flop 250 is coupled to the output of the second multiplexer 240. In operation, the flip-flop 250 stores the most recently received bit and selects whether (i) the first multiplexer 235 selects the output of the first sampler 225 and the second multiplexer 240 selects the output of the second sampler 230, or (ii) the first multiplexer 235 selects the output of the second sampler 230 and the second multiplexer 240 selects the output of the first sampler 225. Thus, the baud rate clock and data recovery circuit 125 (together with the circuitry that controls the phase or frequency of the clock) performs clock and data recovery as described with reference to FIG. 2A.

[0033] The first and second reference voltages are provided to the baud rate clock and data recovery circuit 125 by the reference voltage control circuit 130. The reference voltage control circuit 130 can include a third sampler 255, a pattern filter 260, a first accumulator 265, a first digital-to-analog converter 270, and a second digital-to-analog converter 275. The third sampler 255 samples the analog input signal relative to a third reference voltage (e.g., 3*α). In one embodiment of the present invention, for example, the pattern filter 260 is referred to as a "first pattern filter." The first digital-to-analog converter 270 is coupled to provide the third reference voltage to the third sampler 255, and the second digital-to-analog converter 275 generates an output of the reference voltage control circuit 130 (used as the first reference voltage and inverted to be used as the second reference voltage). In operation, the first accumulator 265 accumulates (in a register of the first accumulator 265) a sample from the third sampler 255 each time the pattern filter matches the pattern 111, and each time this happens, the first accumulator 265 accumulates +1 or -1 depending on the value of the sample taken at a sampling time corresponding to a middle bit of the pattern 111. For example, if the analog input signal exceeds the third reference voltage at a sampling time corresponding to a middle bit of the pattern 111 (i.e., a sampling time corresponding to one bit with one leading and one following), the first accumulator 265 accumulates by +1 (i.e., adds 1 to the register of the first accumulator 265 or "increments" the register by 1), and if the analog input signal is less than the third reference voltage at the sampling time, the first accumulator 265 "decrements" the register by 1, i.e., accumulates by -1 (represented as a binary 0).

[0034] The first pattern filter 260 may include two shift registers, a first and a second register. The first shift register (which is three bits long) stores the three most recent data bits detected. The second shift register (which is two bits long and has an output that can be coupled to the input of the first accumulator 265) stores the two most recent samples determined by the third sampler 255. The first pattern filter 260 also checks whether the three most recent data bits detected are all 1. If so, the first pattern filter 260 may further include logic to activate an enable input of the first accumulator 265 to allow the output of the second shift register to accumulate in the next clock cycle. That is, if the output of the second shift register is 1, the logic increments the register of the first accumulator 265 by 1, and if the output of the second shift register is 0, the logic decrements the register of the first accumulator 265 by 1. 2B, the third reference voltage is three times the first reference voltage (e.g., 3α), or equivalently, the first reference voltage is 1 / 3 of the third reference voltage. According to one embodiment of the invention, the ratios of the first and second reference voltages to the third reference voltage are not exactly 1 / 3 and -1 / 3, but are, for example, within a 20% range of 1 / 3 and -1 / 3.

[0035] In operation, the third reference voltage can reach an equilibrium value when, on average, the first accumulator 265 decrements and increments its register equally often. At a sampling time corresponding to the second bit of the bit pattern 111, the analog input signal TIFF0007617746000001.tif13133, where hi is the channel pulse response at a delay of i bit periods. Thus, at equilibrium, The CDR update equation for the clock and data recovery circuit 125 is: It could also be TIFF0007617746000003.tif14143. By solving these two equations, TIFF0007617746000004.tif23146. In this manner, the reference voltage control circuit 130 can generate a first reference voltage that, when the clock phase is normal, generates a crossing that is aligned with the sampling time, thereby generating a useful clock phase error signal that can be used to correct the clock phase.

[0036] According to one embodiment of the invention, the solution for α is accurate and can work with very high loss channels (e.g., channels having losses exceeding DC losses by up to 32 dB at the Nyquist frequency). Neither the baud rate clock and data recovery circuit 125 nor the reference voltage control circuit 130 require multiple clock phases, thereby eliminating the need for a phase interpolator. The reference voltage control circuit 130 can be used with higher order DFE taps (h_2 and above), but that information can be obtained from the output 280 of the first pattern filter 260. According to one embodiment of the invention, α adaptation is separated from the CDR operation, and the reference voltage control circuit 130 does not require a training sequence upon start-up. FIG. 2C is a graph showing the estimation error of α as a function of sampling error, where the output of the reference voltage control circuit 130 is not affected by the sampling error (e.g., clock jitter). This indicates tolerance to sampling errors caused by random jitter or sampling errors before CDR locking at startup.

[0037] According to one embodiment of the present invention, the continuous-time linear equalizer 120 can be controlled by the equalizer control circuit 135, as described above. FIG. 3A shows an example of a circuit for the continuous-time linear equalizer 120. In the circuit shown in FIG. 3A, an adjustable resistor Rs and an adjustable capacitor Cs can be controlled by appropriate control signals. For example, the adjustable capacitor Cs can be made up of a series of capacitors connected together by transistor switches, and the variable capacitor Cs can be controlled by applying a control signal to the transistor switches to include more or fewer capacitors. The variable resistor Rs can similarly be realized as a series of resistors connected together by transistor switches, or as a field effect transistor whose channel acts as a variable resistor and whose resistance can be adjusted by adjusting the gate voltage. FIG. 3B shows an approximate frequency response of the circuit of FIG. 3A, and FIG. 3C shows a characteristic equation for the continuous-time linear equalizer 120 of FIG. 3A.

[0038] 4A shows a circuit for generating a fourth reference voltage, and FIGURE 4B shows a circuit for generating a fifth reference voltage, which are used to estimate the bit error rate of serial receiver 110, as described in more detail below. The bit error rate estimate can be applied to set one or more control parameters of continuous-time linear equalizer 120, as described in more detail below.

[0039] After setting the N DFE coefficients, The file is TIFF0007617746000005.tif20170.

[0040] In the above equation, the fourth term We assume that TIFF0007617746000006.tif29146 has a Gaussian or "normal" distribution (denoted by N(0,σ)). In this case, the bit error rate is The Q-function is given by: Given by TIFF0007617746000008.tif27165. When TIFF0007617746000009.tif32169 is at its maximum, it can be predicted that the bit error rate will be at its maximum. In this way, the amount TIFF0007617746000010.tif33169 (and the amounts explained below) TIFF0007617746000011.tif36160) can be said to be a "bit error rate indicator."

[0041] As will be described in more detail below, the circuits of Figures 4A and 4B operate to estimate (i) a median β, which is equal to the mean in a symmetric distribution, and (ii) a left one-sigma point γ for the distribution of the analog input signal Vin for the middle bit of the bit pattern 010. As shown in Figure 4C, the mean and one-sigma point have the property that for a normal distribution, 16% of the probability density function lies to the left of the left one-sigma point, and the remaining 84% of the distribution lies to the right of it. Because TIFF0007617746000012.tif15140 and Since it is TIFF0007617746000013.tif20167, The file is TIFF0007617746000014.tif26141.

[0042] In this way (as mentioned above, The bit error rate (which is a function of α, β, and γ) can be calculated from α, β, and γ. The equalizer control circuit 135 adjusts the control parameters of the continuous-time linear equalizer 120 to: TIFF0007617746000016.tif35160 to minimize the estimated bit error rate. For example, the equalizer control circuit 135 can perform an exhaustive search of all possible settings of the control parameters of the continuous-time linear equalizer 120 if the number of settings of the control parameters of the continuous-time linear equalizer 120 is small enough that this approach is practical. If not, the equalizer control circuit 135 can perform, for example, a gradient descent search to find We can find settings that maximize TIFF0007617746000017.tif32160 and thus minimize the bit error rate.

[0043] 4A measures the median for the distribution of the analog input signal Vin for the middle bit of the bit pattern 010. The circuit includes a fourth sampler 405, a second pattern filter 410, a second accumulator 415, and a digital-to-analog converter 420. The fourth sampler 405, the second pattern filter 410, and the second accumulator 415 are configured such that if the sample of the analog input signal Vin exceeds a fourth reference voltage at a sampling time corresponding to the second bit of the pattern matched by the second pattern filter 410, the second accumulator 415 increases its register, and if the sample of the analog input signal Vin does not reach the fourth reference voltage, the second accumulator 415 decreases its register. The second pattern filter 410 and the second accumulator 415 are configured in the same manner as described for the first pattern filter 260 and the first accumulator 265, i.e., the second pattern filter 410 may include two shift registers and logic that causes the second accumulator 415 to increment or decrement its register when a pattern match is detected.

[0044] The circuit further includes a digital-to-analog converter 420 that generates a fourth reference voltage (i.e., β) from (i.e., based on) the contents of the register of the second accumulator 415. At an equilibrium point, the increment and decrement frequencies of the register of the second accumulator 415 are equal on average. This occurs when the fourth reference voltage is equal to the mean of the distribution of samples of the analog input signal Vin that correspond to the middle bits of the bit pattern 010 (i.e., samples taken at sampling times that correspond to the middle bits of the bit pattern 010).

[0045] As explained above, Fig. 4B measures the left one-sigma point of the distribution of the analog input signal Vin for the middle bit of the bit pattern 010. The circuit includes a fifth sampler 425, a third pattern filter 430, a third accumulator 435, and a digital-to-analog converter 455. The third accumulator 435 is a weighted accumulator that adds the weighted output value of the fifth sampler 425 to its register. The third accumulator 435 has a weighting value of 0.16 for an "up" sample, i.e., if the analog input signal Vin exceeds the fifth reference voltage at the sampling time corresponding to the middle bit of the bit pattern 010, and a weighting value of 0.84 for a "down" sample, i.e., if the analog input signal Vin does not reach the fifth reference voltage at the sampling time corresponding to the middle bit of the bit pattern 010. Third pattern filter 430 and third accumulator 435 are configured in the same manner as described for first pattern filter 260 and first accumulator 265, except that third pattern filter 430 includes two shift registers and logic that causes third accumulator 435 to increment or decrement its register by 0.16 or 0.84 (depending on whether the output of the second shift register is 1 or 0, respectively) when a pattern match is detected.

[0046] At the equilibrium point, the increasing frequency of the register of the third accumulator 435 is equal to 0.84 / 0.16 times the decreasing frequency on average. That is, 0.84 / 0.16 of the samples exceed the fifth reference voltage, which means that the fifth reference voltage is one sigma to the left of the mean of the distribution. The weighting values ​​used may be 0.16 and 0.84, or the same ratio, or other weighting values ​​having a ratio within, for example, 20% of the ratio 0.84 / 0.16. The register of the third accumulator 435 may store a floating-point number or may store a fixed point number (or equivalently an integer).

[0047] According to one embodiment of the present invention, the weighting values ​​can be swapped so that the fifth reference voltage is a measurement of the right one-sigma point instead of the left one-sigma point, and the equation Use TIFF0007617746000018.tif25141.

[0048] 5A to 5D show simulation results according to an embodiment of the present invention. 5B shows the eye opening as a function of Rs value (ohms), with the Rs setting predicting the lowest bit error rate in simulations being 1400 ohms. FIG. 5B shows the eye opening as a function of Rs value (ohms), and it can be seen that the Rs value that minimizes the bit error rate maximizes the eye opening. Similarly, the graph in FIG. 5C shows that the eye width is maximized at the Rs value that minimizes the bit error rate. FIG. 5D shows the vertical eye opening for various Rs values ​​for a 50 MHz sinusoidal jitter. The graph includes curves labeled 510, 520, 530, 540, 550, 560, and 570, which are for Rs=800ohms, 1000ohms, 1200ohms, 1400ohms, 1600ohms, 1800ohms, and 2000ohms, respectively.

[0049] According to an embodiment of the present invention, the processing circuitry may perform some or all of the calculations described herein, such as calculating a bit error rate metric and setting control parameters for the continuous-time linear equalizer 120. The "processing circuitry" may be implemented using hardware, firmware, software, or a combination thereof. The processing circuitry may include, for example, an application-customized integrated circuit (ASIC), a general-purpose or dedicated central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), an FPGA, or other programmable logic device. Each function in the processing circuitry may be performed by hardwired hardware that performs that function, or by general-purpose hardware such as a CPU that executes instructions stored in a non-transitory storage medium. The processing circuitry may be fabricated on one printed circuit board (PCB) or may be distributed across interconnected PCBs. The processing circuitry may include other processing circuits, such as an FPGA and a CPU that are interconnected on a PCB.

[0050] A bit may be represented by a number selected from the set {0, 1}, or a number selected from the set {-1, 1}, where 0 and -1 are used interchangeably except when the context requires one or the other (e.g., using {-1, 1} for the input of an accumulator). Wherein, if the second number is "within Y%" of the first number, then the second number is at least (1-Y / 100) times the first number, and the second number is at most (1+Y / 100) times the first number. Here, the term "or" must be interpreted as "and / or", e.g., "A or B" means either "A" or "B", or one of "A and B". Here, when a method (e.g., an adjustment) or a first quantity (e.g., a first term or a first factor) is "based on" a second quantity (e.g., a second term or a second factor), it means that the second quantity is an input to the method or affects the first quantity, for example, that the second quantity is an input (e.g., one of a single input or multiple inputs) of a function that calculates the first quantity, that the first quantity is equal to the second quantity, or that the first quantity is the same as the second quantity (e.g., stored in the same location in memory).

[0051] The terms "first", "second", "third", etc. are used to refer to elements, components, regions, layers, portions, etc., but the terms "first", "second", "third", etc. are not intended to limit the elements, components, regions, layers, portions, etc. The terms "elements", "components", "regions", "layers", "portions", etc. are used to distinguish one element, component, region, layer, portion from another element, component, region, layer, portion, etc., without departing from the spirit and scope of the present invention.

[0052] For ease of description, spatial terms such as "below," "below," and "above" may be used to indicate the relationship of one illustrated part or feature to another. Such spatial terms are intended to indicate different positions and / or orientations of the illustrated devices in use or operation. For example, a part shown in the drawings as being "below" or "below" a device would be "above" it if the device were flipped upside down. Thus, for example, "below" and "below" can refer to both above and below. The device may be rotated, for example, 90 degrees or otherwise oriented, in which case the spatial terms must be interpreted accordingly. Also, when a layer is described as being "between" two other layers, that layer may be the only layer between the two layers, but there may also be one or more additional layers.

[0053] The terms used herein are used only for the purpose of describing specific embodiments and are not intended to limit the present invention. In this specification, the terms "substantially," "about," "generally," and similar terms are merely used to express approximations and do not express "degrees," but to express the inherent error of measurements or calculations that are known to those skilled in the art.

[0054] Herein, unless a number is specifically stated, all cases of singular or plural are included. The expression "comprising" a feature, step, operation, part, component, etc. means that other features, steps, operations, parts, components, etc. may be included in addition to the part in question. The term "and / or" includes all combinations of one or more of the listed items. The expressions "at least one" and the like preceding a list of items modify the whole, not each of them. In addition, the expression "may" used in describing an embodiment of the present invention means that it is applicable to "one or more embodiments of the present invention." The term "exemplary" refers to an example or drawing. The terms "use," "utilization," and the like are used in a similar manner along with other similar expressions.

[0055] When a part, layer, region, component, etc. is described as being "on" or "connected" to another part, layer, region, component, it includes not only the case where it is "directly" on or "directly" connected, but also the case where there is another part, layer, region, component, etc. in between. However, when it is described as being "directly on" or "directly connected", it means that there is no other part in between.

[0056] Numerical ranges recited herein include all sub-ranges of the same precision contained within said ranges. For example, a range "1.0 to 10.0" or "between 1.0 and 10.0" includes a minimum value of 1.0 and a maximum value of 10.0, and all sub-ranges therebetween, i.e., sub-ranges having a minimum value of 1.0 or greater and a maximum value of 10.0 or less, e.g., 2.4 to 7.6. Maximum values ​​recited herein are inclusive, including all lower numerical limits, and minimum values ​​recited herein are inclusive, including all higher numerical limits.

[0057] Although exemplary embodiments of the system and method for controlling CDR and CTLE parameters have been described and illustrated above, those skilled in the art may change and modify such embodiments. Accordingly, other systems and methods for controlling CDR and CTLE parameters constructed according to the principles presented herein are also encompassed by the present invention. The present invention is defined by the following claims and their equivalents. [Explanation of symbols]

[0058] 105:Serial transmitter 110: Serial receiver 115: Channel 120: Continuous-Time Linear Equalizer (CTLE) 125: Clock and Data Recovery Circuit (CDR) 130: Reference voltage control circuit 135: Equalizer control circuit 137: Decision Feedback Equalizer 225, 230, 255, 405, 425: Sampler 235, 240: Multiplexer 245, 260, 410, 430: Pattern Filter 250: Flip-flop 265, 415, 435: Accumulator 270, 275, 420, 455: Digital to Analog Converters

Claims

1. 1. A serial data receiving circuit having an input for receiving an analog input signal, comprising: a first sampler for sampling the analog input signal relative to a first reference voltage; a second sampler for sampling the analog input signal with respect to a second reference voltage having an opposite sign to the first reference voltage; a reference voltage control circuit that adjusts the first reference voltage or the second reference voltage based on a first sample of the analog input signal in response to occurrence of a bit pattern 111; Including, the first sample is a sample taken at a sampling time corresponding to a middle bit of the bit pattern 111; The reference voltage control circuit includes: a third sampler and a first pattern filter, for adjusting a ratio of the first reference voltage to the third reference voltage within a first range and for adjusting a ratio of the second reference voltage to the third reference voltage within a second range different from the first range; The third sampler is adjusting a third reference voltage for adjusting the first reference voltage and the second reference voltage based on the first sample, and sampling the analog input signal with respect to the third reference voltage; The first pattern filter is A signal input to the third sampler is connected to the third sampler, and the signal input to the third sampler is used to select the bit pattern 111 according to an output value of the third sampler. the first reference voltage and the second reference voltage are adjusted at an output of the first pattern filter; Serial data receiving circuit.

2. 2. The serial data receiving circuit of claim 1, wherein the magnitude of the second reference voltage is equal to the magnitude of the first reference voltage.

3. the first reference voltage is equal to a function of the third reference voltage; 2. The serial data receiving circuit according to claim 1.

4. 4. The serial data receiving circuit of claim 3, wherein the second reference voltage is equal to a function of the third reference voltage.

5. the first range is equal to a first fraction of the third reference voltage, the first fraction being greater than or equal to 4 / 15 and less than or equal to 6 / 15 of the third reference voltage; the second range is equal to a second portion of the third reference voltage, the second portion being greater than or equal to −6 / 15 and less than or equal to −4 / 15 of the third reference voltage; 5. The serial data receiving circuit according to claim 4.

6. The adjustment of the third reference voltage includes: When the first sample is greater than the third reference voltage, increasing the third reference voltage; when the first sample is less than the third reference voltage, decreasing the third reference voltage; 4. The serial data receiving circuit according to claim 3.

7. The reference voltage control circuit includes: a first accumulator for accumulating in a register an output value of the third sampler for a sample corresponding to a second bit of each pattern matched by the first pattern filter; Including, 4. The serial data receiving circuit according to claim 3.

8. 8. The serial data receiving circuit of claim 7, wherein the reference voltage control circuit further comprises a digital-to-analog converter that generates the third reference voltage from a register of the first accumulator.

9. 9. The serial data receiving circuit of claim 8, further comprising a continuous-time linear equalizer coupled to said input.

10. 10. The serial data receiving circuit of claim 9, further comprising an equalizer control circuit coupled to the continuous-time linear equalizer for controlling one or more control parameters of the continuous-time linear equalizer.

11. The equalizer control circuit includes: a fourth sampler for sampling the analog input signal relative to a fourth reference voltage; a second pattern filter that selects the bit pattern 010; a second accumulator for accumulating in a register an output value of the fourth sampler for a sample corresponding to a second bit of each pattern matched by the second pattern filter; a digital-to-analog converter for generating the fourth reference voltage from the register of the second accumulator; Including, 11. The serial data receiving circuit according to claim 10.

12. The equalizer control circuit includes: a fifth sampler for sampling the analog input signal relative to a fifth reference voltage; a third pattern filter that selects the bit pattern 010; a third accumulator for accumulating in a register the weighted output value of the fifth sampler for a sample corresponding to a second bit of each pattern matched by the third pattern filter; a digital-to-analog converter for generating the fifth reference voltage from the register of the third accumulator; Further comprising:

12. The serial data receiving circuit according to claim 11.

13. 13. The serial data receiving circuit of claim 12, wherein, if the analog input signal exceeds the fifth reference voltage at a sampling time corresponding to an intermediate bit of the bit pattern 010, a weighting value for weighting the weighted output value is greater than or equal to 4 / 5 and less than or equal to 6 / 5 of 0.16, and if the analog input signal does not reach the fifth reference voltage, a weighting value for weighting the weighted output value is greater than or equal to 4 / 5 and less than or equal to 6 / 5 of 0.

84.

14. a register of the first accumulator; a register of the second accumulator; the third accumulator register; and a processing circuit for calculating a bit error rate indicator based on the 14. The serial data receiving circuit according to claim 13.

15. The processing circuitry includes: calculating the bit error rate indicator for each of a plurality of settings of one or more control parameters of the continuous-time linear equalizer; setting said control parameters to the settings where said bit error rate indicator is greatest; 15. The serial data receiving circuit according to claim 14.

16. 1. A serial data receiving circuit having an input for receiving an analog input signal, comprising: a baud-rate clock and data recovery circuit; a reference voltage control circuit for controlling the first reference voltage or the second reference voltage of the baud rate clock and the data recovery circuit; Including, The baud rate clock and data recovery circuit comprises: a first sampler for sampling the analog input signal relative to the first reference voltage; a second sampler for sampling the analog input signal with respect to the second reference voltage, the second reference voltage being opposite in sign to the first reference voltage; a first multiplexer and a second multiplexer connected to the first sampler and the second sampler; a flip-flop connected to the first multiplexer and the second multiplexer; Including, The reference voltage control circuit includes: a third sampler for sampling the analog input signal with respect to a third reference voltage for adjusting the first and second reference voltages; a first pattern filter that selects the bit pattern 111; a first accumulator for accumulating in a register an output value of the third sampler for a sample corresponding to a second bit of each pattern matched by the first pattern filter; Including, Serial data receiving circuit.

17. 17. The serial data receiving circuit of claim 16, wherein the reference voltage control circuit further comprises a digital-to-analog converter that generates the third reference voltage from a register of the first accumulator.

18. the first reference voltage is equal to a first fraction of the third reference voltage, the first fraction being greater than or equal to 4 / 15 and less than or equal to 6 / 15 of the third reference voltage; the second reference voltage is equal to a second portion of the third reference voltage, the second portion being greater than or equal to −6 / 15 and less than or equal to −4 / 15 of the third reference voltage; 18. The serial data receiving circuit according to claim 17.

19. 1. A serial data receiving circuit having an input for receiving an analog input signal, comprising: a baud-rate clock and data recovery means; a reference voltage control circuit for controlling the baud rate clock and the first reference voltage or the second reference voltage of the data recovery means; Including, The baud rate clock and data recovery means a first sampler for sampling the analog input signal relative to the first reference voltage; a second sampler for sampling the analog input signal with respect to the second reference voltage, the second reference voltage being opposite in sign to the first reference voltage; a first multiplexer and a second multiplexer connected to the first sampler and the second sampler; a flip-flop connected to the first multiplexer and the second multiplexer; Including, The reference voltage control circuit includes: a third sampler for sampling the analog input signal with respect to a third reference voltage for adjusting the first and second reference voltages; a first pattern filter that selects the bit pattern 111; a first accumulator for accumulating in a register an output value of the third sampler for a sample corresponding to a second bit of each pattern matched by the first pattern filter; a serial data receiving circuit including:

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