Interconnects including side connections to the board

Abstract

An interconnect structure is disclosed that includes a base substrate, a set of conductive pads disposed on the base substrate, and an interconnect layer disposed on the base substrate. The interconnect layer has an edge adjacent to the set of conductive pads and includes a set of side connection pads disposed on the edge of the interconnect layer. Each side connection pad is positioned relative to a corresponding one of the conductive pads disposed on the base substrate.

Description

[Technical field]

[0001] The present invention relates generally to interconnect technology, and more particularly to interconnect structures, interconnect layer carrying structures, and methods for fabricating the same. [Background technology]

[0002] In response to the increasing demand for high-bandwidth signal transmission between chips (or dies), several technologies have been proposed for high-density interconnection between chips.

[0003] To establish interconnections between chips mounted on organic substrates, interconnect structures have been developed using interconnect members attached or embedded in the substrate. Examples of such interconnect members disposed on organic substrates include silicon bridges and organic layered interconnects. The use of such interconnect members often restricts the routing of wiring for connecting and driving the chips. It also restricts the layout of the chip terminals. For example, even if it is preferable to place the ground and power terminals of the chip above the interconnect members, it is often difficult to route wiring from the power and ground terminals of the chip to the external power and ground lines of the organic substrate. Summary of the Invention

[0004] According to one embodiment of the present invention, an interconnect structure is provided, the interconnect structure comprising: a base substrate, a set of conductive pads disposed on the base substrate, and an interconnect layer disposed on the base substrate, the interconnect layer having an edge adjacent the set of conductive pads and including a set of exposed side connection pads disposed on the edge of the interconnect layer, each side connection pad positioned relative to a corresponding one of the conductive pads disposed on the base substrate.

[0005] According to the interconnect structure of the present invention, a novel side connection can be introduced between the conductive pads of the base substrate and the side connection pads of the interconnect layer. The introduction of the novel side connection improves the flexibility of the wiring layout of the interconnect layer. This improves the flexibility of the routing, which allows the wiring to be optimized, thereby improving the performance of electronic devices using the interconnect structure. In addition, the constraints on the terminal layout of the chip using the interconnect layer are relaxed.

[0006] In a preferred embodiment, each side connection pad has a top surface exposed at the top surface of the interconnect layer and an edge surface exposed at an edge of the interconnect layer, the edge surface facing a corresponding one of the conductive pads, such that both the edge surface and the top surface are involved in the side connection, increasing the contact area, thereby improving the reliability of the side connection and the manufacturing yield.

[0007] In another preferred embodiment, the edge and / or top surface of each side connection pad has a barrier metal, which can improve the reliability of the side connection.

[0008] In another preferred embodiment, the interconnect layer further includes an insulating material providing a top surface of the interconnect layer, and a set of first bonding pads are exposed from the insulating material at the top surface of the interconnect layer. The set of first bonding pads is used for mounting a chip. Each of the first bonding pads is connected to a corresponding one of the side connection pads via a wiring embedded in the insulating material. Thus, an electrical connection can be introduced between a chip mounted on the base substrate and another component of the base substrate via the first bonding pads and the side connection.

[0009] In one particular embodiment, the interconnect layer further includes a second bonding pad carrying a chip and a third bonding pad carrying another chip, the second bonding pad being connected to the third bonding pad through a trace embedded in the insulating material, thus providing inexpensive, reliable, high density interconnects between the mounted chips, including novel side connections.

[0010] In a preferred embodiment, an edge of the interconnect layer has one or more curved or angled shapes extending its length, and the set of side connection pads and the set of conductive pads are contoured to the one or more curved or angled shapes, thereby increasing the density of side connections and / or the contact area for the side connections.

[0011] In a preferred embodiment, each pair of one side connection pad of the interconnection layer and one corresponding conductive pad disposed on the base substrate is used independently for power or ground, which can suppress voltage drop compared to when wiring is routed on the base substrate while avoiding the area of ​​the interconnection layer. The use of the interconnection layer to provide a power or ground line that functions as a signal return current path is favorable for high-speed signal transmission.

[0012] In one particular embodiment, the base substrate has a top surface. Each conductive pad has a pad surface. The top surface of the base substrate and the pad surface of each conductive pad have portions that are treated with a surface treatment that increases surface roughness. This can prevent bridging between adjacent side connections and improve the reliability of the side connections, even when the pitch between the side connections is finer.

[0013] In one particular embodiment, the interconnect structure further comprises a pair of solder joints each connecting one side connection pad of the interconnect layer with one corresponding conductive pad disposed on the base substrate.

[0014] In another specific embodiment, the interconnect structure further comprises one or more chips mounted on the base substrate, at least one of the chips having a terminal electrically connected through one of the side connection pads to one of the conductive pads disposed on the base substrate.

[0015] According to another embodiment of the present invention, there is provided an interconnect layer carrying structure, the interconnect layer carrying structure including a support substrate, a release layer formed on the support substrate, and an interconnect layer portion disposed on the release layer and having an edge, the interconnect layer portion including an insulating material and a set of side connection pads embedded in the insulating material, the set of side connection pads being located and exposed at the edge of the interconnect layer portion and formed at predetermined intervals along the edge of the interconnect layer portion.

[0016] Another embodiment of the present invention relates to an interconnect layer carrying structure that can be used to manufacture the aforementioned interconnect structure by transferring a precisely formed interconnect layer onto a substrate. The provision of the interconnect layer allows for increased flexibility in routing the interconnect layer and can alleviate the constraints on the terminal layout of the chip that uses the interconnect layer. The provision of the interconnect layer carrying structure reduces the production cost of the interconnect structure and increases the production yield.

[0017] According to another embodiment of the present invention, there is provided a method for manufacturing an interconnect structure, the method including providing a base substrate having a set of conductive pads disposed thereon, and disposing an interconnect layer on the base substrate, the interconnect layer including a set of exposed side connection pads located at edges thereof, the interconnect layer being disposed such that edges of the interconnect layer are adjacent the set of conductive pads and each side connection pad is positioned relative to a corresponding one of the conductive pads disposed on the base substrate.

[0018] The interconnect structure manufactured by the method according to the embodiment of the present invention allows the introduction of a novel side connection between the conductive pad of the base substrate and the side connection pad of the interconnect layer. The introduction of the novel side connection improves the flexibility of the wiring layout by the interconnect layer. This improves the flexibility of the routing, and thus the wiring can be optimized, thereby improving the performance of electronic devices using the interconnect structure. In addition, the constraints on the terminal layout of the chip using the interconnect layer are relaxed.

[0019] In a preferred embodiment, the base substrate has a top surface and each conductive pad has a pad surface. The method further includes roughening at least a portion of the top surface and the pad surface of each conductive pad by applying a surface treatment that increases the surface roughness to both at least a portion of the top surface of the base substrate near the conductive pads and the pad surface of each conductive pad. This can prevent bridging between adjacent side connections and improve the reliability of the side connections even when the pitch between the side connections is fine.

[0020] In one particular embodiment, disposing the interconnect layer includes placing an interconnect layer carrying structure upside down on the base substrate, the interconnect layer carrying structure including a support substrate, a release layer on the support substrate, and an interconnect layer portion on the release layer, and disposing the interconnect layer includes removing the release layer to release the interconnect layer portion from the support substrate, thereby providing an interconnect layer disposed on the base substrate.

[0021] According to another embodiment of the present invention, there is provided a method of manufacturing an interconnect layer carrying structure. The method includes providing a support substrate. The method also includes applying a release layer to the support substrate. The method further includes constructing an interconnect layer portion on the release layer. The interconnect layer portion has an edge and includes an insulating material and a set of side connection pads embedded in the insulating material. The set of side connection pads are located and exposed at edges of the interconnect layer portion and are formed at predetermined intervals along the edges of the interconnect layer portion.

[0022] The interconnect layer-carrying structure produced by the method according to the embodiment of the present invention can be used to produce the aforementioned interconnect structure by transferring a precisely formed interconnect layer onto a substrate. The provision of the interconnect layer allows for increased flexibility in routing the interconnect layer and can alleviate the constraints on the terminal layout of the chip using the interconnect layer. The provision of the interconnect layer-carrying structure reduces the production cost of the interconnect structure and increases the production yield.

[0023] In one particular embodiment, constructing the interconnect layer includes providing a set of side connection pads on the release layer by patterning a conductive material, and constructing the interconnect layer further includes constructing an insulating portion on the release layer to embed the set of side connection pads.

[0024] Additional features and advantages are realized through the teachings of the present invention.Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.

[0025] The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the claims which follow. These and other features and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that the sizes and relative positions of the various elements and layers in the figures are not necessarily drawn to scale. Some of these elements or layers have been arbitrarily enlarged and positioned to facilitate clarity of the drawings. [Brief description of the drawings]

[0026] [Figure 1A] 1 is a schematic diagram of an interconnect substrate according to one embodiment of the present invention; [Figure 1B] 1 is a schematic diagram of an interconnect substrate according to one embodiment of the present invention; [Diagram 2] FIG. 2 is a schematic diagram of an interconnect layer carrying structure used to transfer an interconnect layer onto a target substrate, according to one embodiment of the present invention. [Figure 3A] 1A-1C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect substrate using an interconnect layer carrying structure according to one embodiment of the present invention. [Figure 3B] 1A-1C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect substrate using an interconnect layer carrying structure according to one embodiment of the present invention. [Figure 3C] 1A-1C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect substrate using an interconnect layer carrying structure according to one embodiment of the present invention. [Figure 4A] 1A-1C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect substrate using an interconnect layer carrying structure according to one embodiment of the present invention. [Figure 4B] 1A-1C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect substrate using an interconnect layer carrying structure according to one embodiment of the present invention. [Figure 4C] 1A-1C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect substrate using an interconnect layer carrying structure according to one embodiment of the present invention. [Diagram 5] FIG. 2 is a schematic diagram of an interconnect layer carrying structure used to transfer an interconnect layer onto a target substrate according to another embodiment of the present invention. [Figure 6A] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an organic-based substrate according to an embodiment of the present invention. [Figure 6B] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an organic-based substrate according to an embodiment of the present invention. [Figure 6C] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an organic-based substrate according to an embodiment of the present invention. [Figure 6D] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an organic-based substrate according to an embodiment of the present invention. [Figure 7A] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an organic-based substrate according to an embodiment of the present invention. [Figure 7B] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an organic-based substrate according to an embodiment of the present invention. [Figure 7C] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an organic-based substrate according to an embodiment of the present invention. [Figure 7D] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an organic-based substrate according to an embodiment of the present invention. [Figure 8] 2 is a cross-sectional view of an electronic device around an interconnect layer in accordance with one embodiment of the present invention. [Figure 9A] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an electronic device according to an embodiment of the present invention; [Figure 9B] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an electronic device according to an embodiment of the present invention; [Figure 9C] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an electronic device according to an embodiment of the present invention; [Figure 10A] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 10B] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 10C] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 10D] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 10E] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 10F] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 11A] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 11B] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 11C]1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 11D] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 11E] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 12A] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 12B] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 12C] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 12D] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 13A] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 13B] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 13C] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 13D] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 13E] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 14A] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 14B] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 14C] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 14D] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 15A] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 15B] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 15C] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 15D] 1A-1D are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to one embodiment of the present invention. [Figure 16A] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 16B] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 16C] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 16D] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 17A] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 17B] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 17C] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 18A]5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 18B] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 18C] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 18D] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 19A] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 19B] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 19C] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 19D] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 20A] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 20B] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 20C] 5A-5C are cross-sectional views of a structure obtained in a manufacturing process of an interconnect layer-carrying structure according to another embodiment of the present invention. [Figure 21A] FIG. 2 is a top view of an interconnect substrate without solder joints, according to one embodiment of the present invention. [Figure 21B] FIG. 2 illustrates a top view of an interconnect substrate with solder joints according to one embodiment of the present invention. [Figure 22A] FIG. 2 is a top view of an interconnect substrate without solder joints according to another embodiment of the present invention. [Figure 22B] FIG. 2 is a top view of an interconnect substrate without solder joints according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to specific embodiments, however, those skilled in the art will recognize that the embodiments described below are merely examples and are not intended to limit the scope of the present invention.

[0028] One or more embodiments are directed to an interconnect structure, an interconnect layer carrying structure for use in fabricating the interconnect structure, and a method for fabricating the interconnect structure and the interconnect layer carrying structure that provides high density interconnections between chips mounted thereon as well as novel lateral connections between a base substrate and an interconnect layer disposed thereon. In describing the embodiments with reference to Figures 1A-22B, multiple identical elements are identified by a generic reference numeral, while each of the multiple individual elements may be identified by an individual subscript reference numeral that is added to the generic reference numeral. For example, the multiple bond pads shown in Figure 1A are generally referenced by numeral 112, and the individual bond pads are referenced by numerals 112-1 and 112-2.

[0029] An overview of the interconnect structure before chip mounting will now be described with reference to FIGS. 1A and 1B.

[0030] 1A and 1B are schematic diagrams of an interconnection substrate 100 for interconnecting mounted chips. The interconnection substrate 100 is an interconnection structure prior to mounting chips. 1A and 1B are cross-sectional and top views of the interconnection substrate 100, respectively. Note that the cross-sectional view shown in FIG. 1A corresponds to the cross section indicated by "X" in the top view of FIG. 1B.

[0031] As shown in FIG. 1A , the interconnect substrate 100 includes an organic-based substrate 110, a plurality of bonding pads 112 for chip bonding formed on the organic-based substrate 110, a set of conductive pads 114 for side connection formed on the organic-based substrate 110, and an interconnect layer 130 disposed on the organic-based substrate 110.

[0032] The organic base substrate 110 can be a laminate substrate having a suitable number of wiring layers with a core, such as a glass-epoxy core, and an interlayer dielectric, and can be manufactured by any lamination process. The bonding pads 112 and the conductive pads 114 can be the outermost layers of the laminate substrate. Each bonding pad 112 is connected to a signal line via a wiring in the organic base substrate 110. Each conductive pad 114 is connected to a power supply or ground line via a wiring in the organic base substrate 110, which can function as a signal return current path, which is a path for current to return to the power supply. The bonding pads 112, the conductive pads 114, and the wiring are made of one of a metal material (e.g., Cu, Al, etc.) and other conductive materials. In a particular embodiment, metallic copper can be used. For convenience of illustration, the internal structure of the inside of the organic base substrate 110 is omitted in the drawing. The organic base substrate 110 is also adopted as a base substrate in the described embodiment. However, an inorganic substrate such as a glass substrate can also be adopted as the base substrate.

[0033] In one particular embodiment, the interconnect substrate 100 includes a solder resist layer 116 formed on the organic base substrate 110. Each of the bonding pads 112 can be covered by the solder resist layer 116 and can be exposed from the solder resist layer 116 through an opening formed therein. Each of the bonding pads 112 can have pre-solder 118 formed in the opening of the solder resist layer 116. Each of the conductive pads 114 can be partially covered by the solder resist layer 116 and can be exposed from the solder resist layer 116 at one edge near the interconnect layer 130 disposed on the organic base substrate 110. The thickness of the pads 112, 114 can typically be in the range of 1 to 20 micrometers. The thickness of the solder resist layer 116 can be within a suitable range, typically in the range of 2 to 50 micrometers. The solder resist layer, which is typically an organic material, is used as an insulating layer disposed on the organic base substrate. However, as an alternative to the use of solder resist layer 116, a dielectric layer of insulating material other than solder mask material, such as an inorganic insulating material, is also contemplated.

[0034] The plurality of bonding pads 112 can be divided into a plurality of groups. A group of bonding pads (hereinafter referred to as a first group) 112-1 is positioned in a flip chip area (hereinafter referred to as a first flip chip area) 110b-1 on the interconnect substrate 100. Another group of bonding pads (hereinafter referred to as a second group) 112-2 is positioned in a different flip chip area (hereinafter referred to as a second flip chip area) 110b-2 on the interconnect substrate 100. The second group of bonding pads 112-2 can be located at a distance from the first group of bonding pads 112-1. Note that pre-solder 118-1, 118-2 formed on the bonding pads 112-1, 112-2 is shown in the top view of FIG. 1B. The first and second flip chip areas 110b-1, 110b-2 are areas where a chip (hereinafter referred to as a first chip) and another chip (hereinafter referred to as a second chip) will be mounted, respectively, after a subsequent chip mounting process.

[0035] The interconnect layer 130 is disposed on the top surface of the organic base substrate 110 and is located in the defined area 110a between the first and second groups of bonding pads 112-1, 112-2. The defined area 110a where the interconnect layer 130 is disposed is free of solder resist. The interconnect layer 130 can be accurately positioned in the defined area 110a using appropriate alignment marks and can be attached to the organic base substrate 110. The defined area 110a of the interconnect layer 130 partially overlaps both the first and second flip chip areas 110b-1, 110b-2. The defined area 110a where the interconnect layer 130 is disposed can be recessed to adjust the height of the top surface of the interconnect layer 130 and the top surface of the solder resist layer 116.

[0036] The interconnect layer 130 is bonded to the top surface of the organic base substrate 110 by an adhesive 132. The adhesive 132 can be a paste or liquid type or a film type adhesive material.

[0037] Further referring to FIG. 1A, this figure shows the structure of the interconnect layer 130 in more detail. The interconnect layer 130 includes an organic insulating material 134, a conductive pattern 136 embedded in the organic insulating material 134, and a number of pads 140-142 exposed on a top surface 130a of the interconnect layer 130 that can be provided by the organic insulating material 134. The pads 140-142 of the interconnect layer 130 are divided into two types. The first type is the side connection pads 140 used for side connection, and the second type is the bonding pads 141, 142 used for chip bonding.

[0038] It should be noted that organic insulating material 134 is employed as the insulating material of interconnect layer 130 in the described embodiment. When an organic-based substrate 110 is employed, organic materials are preferred to mitigate the mismatch in coefficient of thermal expansion (CTE) between interconnect layer 130 and organic-based substrate 110 (which is typically used as a packaging substrate). However, the insulating material is not limited to organic materials. In another embodiment, inorganic insulating materials can also be employed as the insulating material.

[0039] In the embodiment described, as a representative description of the first flip chip area 110b-1, the interconnect layer 130 has an edge E1 located next to the set of conductive pads 114-1 disposed on the organic base substrate 110 and an edge E2 located next to the set of conductive pads 114-2. A set of side connection pads 140-1 is located at the edge E1 and exposed. Each side connection pad 140-1 is disposed relative to a corresponding one of the conductive pads 144-1 disposed on the organic base substrate 110. When the set of conductive pads 114-1 is disposed in a row with a predetermined interval (e.g., pitch width) along one edge close to the interconnect layer 130, the set of side connection pads 140-1 is also disposed in a row with a predetermined interval (e.g., pitch width) that matches the interval of the conductive pads 114-1 along the edge E1 of the interconnect layer 130. Although not limited to a particular one, in one particular embodiment, the side connection pad 140-1 and the conductive pad 114-1 have a one-to-one relationship.

[0040] Each side connection pad 140 has a top surface TS exposed at the top surface 130a of the interconnect layer 130 and an edge surface ES exposed at one edge (e.g., E1) of the interconnect layer 130. The top surface TS is parallel to the top surface of the organic base substrate 110, while the edge surface ES is perpendicular to the top surface of the organic base substrate 110 and faces a corresponding one of the conductive pads 114. In a preferred embodiment, the edge surface ES and / or the top surface TS of each side connection pad 140 has a barrier metal layer. Examples of barrier metal layers include Au / Pd / Ni stacks and Au / Ni stacks (wherein the first element (e.g., Au in each case) is at the top of the stack), an Au layer, and a Pd layer. Note that the symbols Au, Pd, Ni, etc. represent the major elements in each layer of the stack, but each layer may contain small or trace amounts of other elements to form alloys and / or may contain small or trace additives from the manufacturing process. Also, the bonding pads 112 and conductive pads 114 disposed on the organic-based substrate 110 may or may not each have a similar barrier metal layer.

[0041] 1A and 1B, the interconnect substrate 100 may include a set of solder joints 119 each connecting one side connection pad 140 of the interconnect layer 130 with one corresponding conductive pad 114 disposed on the organic base substrate 110. Each solder joint 119 contacts the side connection pad 140 (top surface TS and edge surface ES) and the exposed surface of the conductive pad 114. Note that the solder joints 119-1, 119-2 formed on the conductive pads 114-1, 114-2 and the side connection pads 140-1, 140-2 are also shown in the top view of FIG. 1B. The symbol "G" denotes ground, while the symbol "P" denotes power.

[0042] In the described embodiment, pads 112, 114 and substrate each have a surface (pad surface PS of conductive pad 114 and bonding pad 112 and substrate surface SS around conductive pad 114 and bonding pad 112) that has a surface treatment applied to it to increase the surface roughness. In one or more embodiments, the surface treatment includes sandblasting and / or plasma treatment. Thus, conductive pad 114 has a pad surface PS exposed from substrate surface SS that is rougher than the exposed surface of the untreated pad. Also, bonding pad 112 has a pad surface PS exposed from substrate surface SS that is rougher than the exposed surface of the untreated pad. Also, the substrate has a portion of substrate surface SS proximate conductive pad 114 and bonding pad 112 that is rougher than other portions of the substrate surface.

[0043] The substrate surface SS is defined as the surface of the portion including the organic base substrate 110 as the substrate body and the solder resist layer 116 formed on the substrate body. The substrate surface SS may include the top surface of the solder resist layer 116, the top surface of the organic base substrate 110 without the solder resist, the interconnect layer, and the adhesive, or at least a portion of the surface of the adhesive 132, or a combination thereof.

[0044] The substrate surface SS, which may be provided by the organic material of the solder resist layer 116, the organic base substrate 110, or the adhesive 132, or a combination thereof, has low wettability to molten solder. The pad surface PS of each of the conductive pads 114 and the bonding pads 112 has high wettability to molten solder. In the context of the present invention, the term "low wettability" means that the surface has a contact angle greater than 90° (90°<θ≦180°). On the other hand, the term "high wettability" means that the surface has a contact angle less than 90° (0°<θ<90°). The contact angle (θ) is the angle at which the liquid (molten solder)-air interface meets the solid (the conductive material of the pads 112, 114 or the organic material of the substrate)-liquid interface, providing an inverse measure of wettability.

[0045] In a particular embodiment, the roughness parameter (Ra) of the portion of the substrate surface SS to which the surface treatment has been applied is greater than 0.4 μm and less than 2 μm, more preferably greater than 0.5 μm and less than 1 μm, as long as the thickness of the solder resist layer after the surface treatment remains sufficiently constant, where Ra represents the average roughness. With regard to another roughness parameter (Rq), the roughness parameter (Rq) of said portion of the substrate surface SS can be greater than 700 nm and less than 4 μm, more preferably greater than 0.8 μm and less than 2 μm, where Rq represents the root-mean-square roughness. The same applies to the pad surface PS.

[0046] Additionally, each of pads 140, 141, 142 of interconnect layer 130 may have a pad surface that is rougher than the exposed surfaces of other untreated pads that are exposed from top surface 130a of interconnect layer 130 and that do not have a surface treatment applied thereto that increases the surface roughness. Also, top surface 130a of interconnect layer 130 may have portions proximate pads 140, 141, 142 that are rougher than other portions of interconnect layer 130 that do not have a surface treatment applied thereto that increases the surface roughness.

[0047] In the described embodiment, as representatively illustrated for the first flip chip area 110b-1, the side connection pads 140-1, the conductive pads 114-1, and thus the solder joints 119-1 are located within the flip chip area 110b-1. The same is true for the other flip chip area 110b-2. However, the location of the side connections (side connection pads 140, conductive pads 114, and solder joints 119) is not limited. In another embodiment, the side connections are located away from the flip chip area 110b, since they are not directly involved in chip bonding.

[0048] Now, looking again at the structure of the interconnect layer 130, the bonding pads 141, 142 are exposed from the organic insulating material 134 on the upper surface 130a of the interconnect layer 130. The bonding pads 141, 142 of the interconnect layer 130, together with the bonding pads 112 disposed on the organic base substrate 110, are used to mount the chip disposed thereon. In the embodiment described, the bonding pads 141, 142 of the interconnect layer 130 are functionally divided into two types. The first type is the first bonding pad 141 for power or ground, and the second type is the second bonding pad 142 for signal transmission between chips.

[0049] Each of the first bonding pads 141 for power or ground is connected to a corresponding side connection pad 140 via a trace (which is part of the conductive pattern 136) embedded in the organic insulating material 134, which is further connected to a power or ground line of the organic base substrate 110 through a solder joint 119.

[0050] The bonding pads 141, 142 of the interconnect layer 130 are divided into a number of groups according to their connection partners. A group of bonding pads (hereinafter referred to as a first set) 141-1, 142-1 are positioned in a first flip chip area 110b-1, and another group of bonding pads (hereinafter referred to as a second set) 141-2, 142-2 are positioned in a second flip chip area 110b-2. Although not shown in FIG. 1A, one bonding pad 142-1 of the first set is electrically connected to a corresponding bonding pad 142-2 of the second set by a wire or trace (which is also part of the conductive pattern 136) embedded in the organic insulating material 134. It is noted that the conductive pattern 136 includes a number of conductive layers, including one or more intermediate layers of organic insulating material, and some of the adjacent conductive layers may be connected by conductive vias formed through the intermediate layers. Additionally, the conductive pattern 136 includes a number of electrical paths separated by organic insulating material.

[0051] 1A, bond pad 141-1 is connected to side bond pad 140-1 located in the same flip chip area 110b-1, but not to another side bond pad 140-2 located in a different flip chip area 110b-2, although power and ground can be shared between multiple chips, such that a power or ground line for a first chip can be connected to a power or ground line for a second chip.

[0052] 1B shows four bonding pads 141, 142, two solder joints (two side connection pads 140 and two conductive pads 114) for each chip, and two bonding pads 112 on the organic base substrate 110. However, the number of bonding pads, the number of solder joints (and thus the number of side connection pads and the number of conductive pads) for each chip, and the number of bonding pads on the organic base substrate 110 are not limited and may be determined by the specifications of the chip. Also, the number of flip chip areas is not limited to two.

[0053] As described below, a first set of bonding pads 141-1, 142-1 of the interconnect layer 130 and a first group of bonding pads 112-1 of the organic-based substrate 110 are formed as a two-dimensional array and configured to receive terminal bumps of a first chip, and the same is true for the other chips.

[0054] In the described embodiment, the interconnect layer 130 shown in Figure 1 can be attached onto the organic-based substrate 110 using a novel interconnect layer support structure. Referring now to Figure 2, an interconnect layer support structure 120 used to transfer the interconnect layer onto a target substrate according to an exemplary embodiment of the present invention will be described.

[0055] 2 is a schematic diagram of an interconnect layer-carrying structure that can be used to fabricate the interconnect substrate 100 shown in FIGURES 1A and 1B by transfer of an interconnect layer 130 onto an organic-based substrate 110. FIGURE 2 is a cross-sectional view of an interconnect layer-carrying structure 120.

[0056] 2, the interconnect layer carrying structure 120 includes a support substrate 122, a release layer 124 formed on the support substrate 122, and an interconnect layer portion 131 formed on the release layer 124. The interconnect layer portion 131 shown in FIG 2 corresponds to the interconnect layer 130 shown in FIG 1, and is shown upside down with respect to FIG 1A with its top and bottom surfaces inverted.

[0057] The support substrate 122 is a rigid and stable substrate used in the fabrication of the interconnect layer 131. The support substrate 122 can be any suitable substrate that provides adequate rigidity and stability. In one or more embodiments, the support substrate 122 can be an inorganic substrate, including glass, semiconductors such as silicon, ceramics, and the like. In a preferred embodiment, the support substrate 122 is a glass substrate, because glass substrates have a transparency and a coefficient of thermal expansion (CTE) (3-12 ppm / ° C.) that is closer to the organic materials used in the construction of the interconnect layer 131, as compared to, for example, silicon substrates. Examples of such glass substrates include soda-lime glass, borosilicate glass, fused silica, and synthetic quartz glass, to name just a few.

[0058] The release layer 124 is a release coating configured to release the interconnect layer portion 131 from the support substrate 122 by an appropriate process. If the support substrate 122 is transparent, the release layer 124 can be irradiated with UV (ultraviolet) / IR (infrared) / visible light from the rear surface of the support substrate 122 to release the interconnect layer portion 131 from the support substrate 122.

[0059] In one or more embodiments, the release layer 124 can be any photosensitive release layer known in the field of wafer bonding / debonding technology that allows debonding from the support substrate interface by laser irradiation. In one particular embodiment, the release layer 124 can be a light-to-heat converting release coating that converts absorbed light energy into heat. In these particular embodiments, the release layer 124 can be burned, separated, or decomposed by ablation by laser irradiation after the interconnect layer portion 131 is secured to the organic-based substrate 110. In other embodiments, the release layer 124 can be a thermal or UV-releasable adhesive layer that loses or loses adhesion by heat or UV irradiation. After debonding, any remaining release layer 124 can be cleaned as needed. In other embodiments, any of the known debonding methods can be used, such as mechanical debonding, thermal desorption, and solvent debonding.

[0060] As described with reference to Figures 1A and 1B, the interconnect layer portion 131 includes an organic insulating material 134, a plurality of pads 140-142 facing the supporting substrate 122 and embedded in the organic insulating material 134, and a plurality of traces (or wiring) 136a-136d embedded in the organic insulating material 134.

[0061] Although not shown in FIG. 2, in one particular embodiment in which a film-type adhesive material is used for adhesive 132 in FIG. 1, interconnect layer portion 131 may further include an adhesive layer formed on organic insulating material 134 and may completely cover the top surface of organic insulating material 134.

[0062] The plurality of pads 140-142 includes a side connection pad 140, a first bonding pad 141 for power or ground, and a second bonding pad 142 for signal transmission. As shown in FIG. 1, each side connection pad 140 is configured to be connected to a corresponding conductive pad 114 (to which the interconnect layer portion 131 is transferred) disposed on the organic base substrate 110 by a solder joint 119. The plurality of pads 140-142 are divided into a plurality of groups, such as a first set of pads 140-1, 141-1, 142-1 and a second set of pads 140-2, 141-2, 142-2. Each pair of a side connection pad 140-1 and a corresponding bonding pad 142-1 is electrically coupled by a trace 136a. Each pair of bond pad 142-1 and corresponding bond pad 142-2 is electrically coupled by a trace (the traces connecting bond pads 142-1, 142-2 are not shown in FIG. 2).

[0063] The organic insulating material 134 can be disposed on the release layer 124. In the described embodiment, the top surface of the organic insulating material 134 can be a flat exposed surface. In another embodiment, the top surface of the organic insulating material 134 can be covered with an adhesive layer. The pads 140-142 can be exposed from the bottom surface of the organic insulating material 134 and contact the release layer 124. In the described embodiment, each pad 140-142 includes a barrier metal layer 138 formed on the release layer 124. Each pad 140-142 can further include a seed metal layer that can be used to deposit a conductive material (e.g., the barrier metal layer 138 and the pad body) on the bottom surface (corresponding to the top surface TS) on the release layer 124 by electrolytic plating. In a preferred embodiment, each side connection pad 140 further includes a barrier metal layer 139 formed on its edge surface ES.

[0064] The organic insulating material 134 can be any one of photosensitive insulating resins such as PI (polyimide), BCB (benzocyclobutene), PBO (polybenzoxazole), or other photosensitive polymers. The use of organic insulating materials mitigates the CTE mismatch between the interconnect layer 130 and the organic base substrate 110. The conductive pattern 136 can be made of any one of metal materials (e.g., Cu, Al, etc.) and other conductive materials. In a particular embodiment, metallic copper can be used for the conductive pattern 136. The barrier metal layers 138, 139 can include, but are not limited to, Au / Pd / Ni stacks or Au / Ni stacks (where the first element (e.g., Au in either case) is the bottom layer of the stack in FIG. 2), Au layers, or Pd layers.

[0065] In the embodiment described, edges E1, E2 of interconnect layer portion 131 are aligned with edges GE1, GE2 of support substrate 122. As shown in Figure 2, interconnect layer portion 131 is provided as being made of an organic material and fabricated on support substrate 122 in the form of a tape held by support substrate 122 as a rigid backing. The process of fabricating interconnect layer carrying structure 120 is described below.

[0066] A process for manufacturing an interconnect substrate 100 by use of an interconnect layer carrying structure 120 will now be described with reference to Figures 3A-3C and 4A-4C. Figures 3A-3C and 4A-4C are cross-sectional views of structures obtained in the manufacturing process of an interconnect substrate 100.

[0067] 3A, the manufacturing process of the interconnect substrate 100 may include providing an organic-based substrate 110 and an interconnect layer support structure 120. The organic-based substrate 110 may include a plurality of bonding pads 112, a set of conductive pads 114, and a solder resist layer 116 disposed thereon. Note that there is a defined area 110a on the organic-based substrate 110 that is free of the solder resist layer.

[0068] As shown in FIG. 3A, the manufacturing process may further include applying an adhesive 132 to the organic base substrate 110 in the defined area 110a. In the described embodiment, the adhesive 132 is a paste or liquid type adhesive material that can be conventionally used as an underfill when bonding a chip to a substrate. The use of a paste or liquid type adhesive can prevent the occurrence of voids in the adhesive 132. However, in a particular embodiment in which an adhesive of a film type adhesive material is formed on the interconnect layer portion 131, the step of applying the adhesive can be omitted.

[0069] As shown in Fig. 3B, the manufacturing process may include placing the interconnect layer support structure 120 on the organic base substrate 110 such that the edges E1, E2 of the interconnect layer 131 are located next to each set of conductive pads 114 and each side connection pad 140 is positioned relative to a corresponding one of the conductive pads 114 disposed on the organic base substrate 110. The interconnect layer support structure 120 can be placed upside down on the organic base substrate 110 using a bonder such that the pads 140-142 face up and the exposed surface of the organic insulating material 134 faces down. The bottom of the organic insulating material 134 is attached to the top surface of the organic base substrate 110 within the defined area 110a.

[0070] Because the bonding pads 141, 142 of the interconnect layer portion 131 and the bonding pads 112 on the organic base substrate 110 are configured to receive bumps of a mounted chip, the interconnect layer carrying structure 120 is accurately positioned in the defined area 110a using suitable alignment marks that may be pre-formed on the organic base substrate 110. After the step of disposing the interconnect layer carrying structure 120 on the organic base substrate 110, the manufacturing process may further include a step of curing the adhesive 132 to securely bond the interconnect layer portion 131 to the organic base substrate 110.

[0071] In other embodiments, the step of applying adhesive 132 can be performed by a capillary method or an injection flow method after placement of the interconnect layer support structure 120 .

[0072] 3C, the manufacturing process may include peeling the interconnect layer portion 131 from the support substrate 122 by removing the release layer 124. In one particular embodiment, the support substrate 122 is transparent, and the peeling from the support substrate 122 may be performed by ablation of the release layer 124 by laser irradiation through the support substrate 122 while scanning a laser beam.

[0073] By performing the above steps, the interconnect layer portion 131 is transferred from the interconnect layer carrying structure 120 to the organic-based substrate 110 in the defined area 110a, resulting in the interconnect layer 130 attached to the organic-based substrate 110. A peeling step shown in FIG. 3C positions the interconnect layer 130 on the organic-based substrate 110 such that the set of pads 140-142 face in opposite directions from the organic-based substrate 110.

[0074] 4A, the manufacturing process may include, after removing the release layer 124, performing a cleaning of the residues on the interconnect layer 130, which may include the residues of the release layer 124. The cleaning of the residues may be performed by virtually any means, such as O2 plasma exposure. In a particular embodiment, the manufacturing process may also include, after removing the release layer 124, performing an etching of the surfaces of the pads 140-142, which may include a seed metal layer formed thereon, to expose the exposed surfaces of the metal stack 138.

[0075] 4B, the manufacturing process may include applying a surface treatment that increases surface roughness to exposed pad surfaces PS of conductive pads 114 and bonding pads 112 and portions of exposed substrate surface SS around conductive pads 114 and bonding pads 112. Examples of such surface treatments that increase surface roughness include sandblasting (abrasive blasting) and plasma treatment.

[0076] In a preferred embodiment, sandblasting is employed as the surface treatment. Sandblasting can be performed using an appropriate abrasive medium with a particle size under appropriate conditions such as the impact speed of the abrasive medium. There are many types, such as dry blasting and wet blasting. Wet blasting, in which an abrasive medium and a liquid such as water are sprayed against the workpiece, is preferred because it can use finer abrasive media than dry blasting. Sandblasting is preferred because it mechanically and physically modifies the exposed surface without significantly affecting the chemical surface condition. In addition, the roughness of the exposed surface can be more accurately controlled over a wider control range by using appropriate abrasive particles.

[0077] In a particular embodiment, plasma treatment is employed as the surface treatment. The plasma treatment can be argon (Ar) plasma, oxygen (O2) plasma, or a mixture thereof. Preferably, plasma treatment using Ar plasma can be employed since Ar plasma can prevent oxidation. However, O2 plasma treatment can also be considered when the pads 112, 114 are protected by a noble metal layer, such as an Au layer, formed on the top surface. The plasma treatment can be performed under appropriate conditions, which can include RF (radio frequency) power, acceleration voltage, gas flow rate, application time, etc., to sufficiently increase the surface roughness.

[0078] Although plasma treatment is often applied to a target surface to remove organic residues and thereby chemically modify surface properties by cleaning and / or functionalizing the surface, the plasma treatment according to the exemplary embodiment differs from such plasma treatments for cleaning and / or functionalizing the surface in terms of its purpose and conditions. In general, the plasma treatment is applied for a relatively long time to sufficiently roughen the target surface. Furthermore, plasma treatments that increase surface roughness physically roughen the surface, so that the roughening effect lasts for a relatively long time. In contrast, the effectiveness of plasma treatments in terms of cleaning and / or functionalizing the surface is short. This is because the cleaning surface tends to become contaminated over time, and the cleaning / functionalizing effect decreases over time due to the change in the surface condition over time. Furthermore, plasma treatments (especially O2 plasma treatments) can make the resin surface more hydrophilic due to the interaction between the active species and the surface molecules, so it is preferable to leave the exposed surface of the solder resist layer 116 for a while after the plasma treatment until the hydrophilicity is sufficiently reduced.

[0079] Increasing surface roughness improves solder wetting of highly wettable surfaces, while improving dewetting of less wettable surfaces. The wettability of molten solder is determined by the surface roughness of the solid components when the three phase materials are identical. The wettability is expressed by the contact angle in the Wenzel equation as follows: cosθ w =rcosθ Here, θ w is the apparent contact angle, θ is the Young's contact angle, and r is the roughness ratio (r = 1 for a smooth surface and r > 1 for a rough surface).

[0080] When the surface irregularities are minute, air remains at the interface, and the surface is chemically heterogeneous, the Cassie equation holds as follows: cosθ c '=fcosθ a +(1-f)cosθ b where f is the ratio of the areas in contact with the liquid and solid phases, θ ais the contact angle of component A with respect to a certain surface area f, θ b represents the contact angle of component B with respect to the remaining surface area (1-f). When the liquid comes into contact with air (e.g., θ b = 180°), the Cassie formula is as follows: cosθ c '=fcosθ a +1-f

[0081] Therefore, the contact angle θ c ' becomes large even when the interface between the solid and the liquid contains air. When the surface becomes homogeneous again at f=1, the Wenzel equation holds true.

[0082] The application of surface treatments changes the different wettability of the exposed surfaces in different strengthening directions. The substrate surface SS with low wettability (90°<θ<180°) becomes more anti-wettable (θ w At the same time, the pad surface PS with high wettability (0<θ<90°) further progresses in wettability (θ w <θ). The increased surface roughness improves the solder wettability of the exposed pad surface PS of the highly wettable pad 114, while improving the dewetting of the less wettable substrate surface SS. This prevents bridging of adjacent side connections during soldering, even when the pitch between side connections and bonding is small, and improves the reliability of side connections and chip bonding.

[0083] The surface treatment to increase the surface roughness is performed after the step of peeling the interconnect layer portion 131 from the support substrate 122. In this embodiment, the surfaces of the pads 140, 141, 142 (including the top surfaces TS (and possibly the edge surfaces ES) of the side connection pads 140) and at least a portion of the top surface 130a of the interconnect layer 130 close to the pads 140, 141, 142 may also be subjected to the surface treatment.

[0084] As shown in FIG. 4C, the manufacturing process may include forming a set of solder joints 119 to connect the side connection pads 140 of the interconnect layer 130 with the corresponding conductive pads 114 disposed on the organic base substrate 110, respectively. This step may also form a set of pre-solder 118. Each solder joint 119 may be formed by applying a solder paste to the side connection pads 140 and the corresponding conductive pads 114 and heating the solder paste to melt the solder paste to form a mechanical and electrical bond. The paste may be applied by jet printing, stencil printing, or syringe. In an alternative embodiment, injection melt soldering (IMS) may be employed to form the solder joints 119. The IMS technique is advantageous when the use of a large amount of solder is preferred.

[0085] In the described embodiment, the step of heating the solder paste 117 to form the set of solder joints 119 is performed prior to chip mounting. This is preferable if there is a delay before a subsequent chip mounting process is performed. The formation of the solder joints 119 is also preferably performed prior to chip mounting if the subsequent chip mounting process does not use a reflow process. However, if the subsequent chip mounting process does use a reflow process, it is possible to omit the heating step of the solder paste 117 at this stage and delay completion of the solder joints 119 until the reflow process of the subsequent chip mounting process.

[0086] The interconnect substrate 100 (including the organic-based substrate 110, the interconnect layer 130, and a set of solder joints 119 formed on the side connection pads 140 of the interconnect layer 130 and the corresponding conductive pads 114 of the organic-based substrate 110) obtained by the manufacturing process shown in the series of Figures 3A to 3C and 4A to 4C can be passed on to a subsequent process, such as a chip mounting process.

[0087] FIG. 5 is a schematic diagram of an interconnect layer carrying structure used for transferring an interconnect layer onto a target substrate according to another embodiment of the present invention. In the embodiment described with reference to FIG. 2, the edges E1, E2 of the interconnect layer portion 131 are aligned with the edges GE1, GE2 of the support substrate 122. In contrast, in the particular embodiment shown in FIG. 5, the interconnect layer portion 131 is formed in a predetermined area on the support substrate 122 such that the support substrate 122 has a base portion 122a on which the interconnect layer portion 131 is fabricated and an extension portion 122b (or flange) 122b of both edges extending outside the base portion 122a. The extension portion 122b is a portion of the support substrate 122 that abuts the edges E1, E2 of the interconnect layer portion 131 when inverted. In the embodiment shown in FIG. 5, the edges E1, E2 of the interconnect layer portion 131 are not aligned with the edges GE1, GE2 of the support substrate 122. The extension 122 b of the support substrate 122 has a plane configured to be approximately parallel to the plane of the organic-based substrate 110 by abutment of the extension 122 b during transfer of the interconnect layer 130 from the support substrate 122 onto the organic-based substrate 110 .

[0088] In one particular embodiment, the organic-based substrate 110 has a solder resist layer 116 having a flat surface for abutment. The flat surface of the extension 122b of the support substrate 122 is configured to abut directly or indirectly against the flat surface of the solder resist layer 116 of the organic-based substrate 110 upon transfer of the interconnect layer 130.

[0089] In a particular embodiment, the plane of the extension 122b is provided as the top surface 124a of the release layer 124. However, the release layer 124 need not extend to the area of ​​the extension 122b of the support substrate 122. In another embodiment, the extension 122b of the support substrate 122 directly provides a plane configured to be substantially parallel to the plane of the solder resist layer 116 when the support substrate 122 is in contact with the solder resist layer 116.

[0090] Also, in certain embodiments, the solder resist layer 116 has a flat surface for abutment, although in other embodiments, the height of the top surface of the interconnect layer 130 and the height of the top surface of the solder resist layer 116 can be adjusted by using a suitable spacer inserted between the extension 122a of the support substrate 122 and the solder resist layer 116 to obtain a suitable height difference.

[0091] In a particular embodiment having the interconnect layer support structure 120 shown in FIG. 5, the step of placing the interconnect layer support structure 120 on the organic base substrate 110 shown in FIG. 3B includes a substep of leveling the plane of the extension portion 122b by abutment so that the plane of the extension portion 122b is approximately parallel to the upper surface of the solder resist layer 116 of the organic base substrate 110.

[0092] 6A to 6D, a process for manufacturing the organic-based substrate 110 will be described below. FIG. 6A to 6D are cross-sectional views of a structure obtained in the manufacturing process of the organic-based substrate 110.

[0093] As shown in Figure 6A, the manufacturing process may include providing an organic base substrate 110 having a plurality of bonding pads 112 and a set of conductive pads 114. The bonding pads 112 and the conductive pads 114 may be made of copper metal and may be formed by any layering process, such as semi-additive, additive, or subtractive processes. Although the process shown in Figures 6A-6D only illustrates the manufacturing process of the conductive pads 112, 114, the organic base substrate may be composed of a core of a composite material, such as glass epoxy, a general wiring layer, and an insulating layer.

[0094] 6B, the manufacturing process may include applying a photosensitive solder resist 115 to the organic base substrate 110, including areas for the bonding pads 112 and conductive pads 114. Such a photosensitive resist may be applied by any process, such as spray coating, dip coating, curtain coating, lamination, etc.

[0095] As shown in FIG. 6C, the manufacturing process may include exposing and developing a photosensitive solder resist 115 using a mask 117 to obtain the structure shown in FIG. 6D (having a patterned solder resist 116). The patterned solder resist 116 shown in FIG. 6D has openings 116b over the bonding pads 112 and cavities 116a exposing the surface of the defined area 110a and the edges of the conductive pads 114 near the defined area 110a. In the embodiment shown in FIG. 6C, the mask 117 is a dark-field mask and the solder resist is positive tone. However, in other embodiments, a bright-field mask and a negative tone photosensitive resist material may be employed.

[0096] In the following, an alternative process for manufacturing an organic-based substrate 110 will be described with reference to Figures 7A to 7D. Figures 7A to 7D are cross-sectional views of structures obtained in an alternative manufacturing process for an organic-based substrate.

[0097] As shown in FIG. 7A, the manufacturing process of the organic base substrate may include a step of preparing an organic base substrate 110 having a plurality of bonding pads 112 and a set of conductive pads 114. As shown in FIG. 7B, the manufacturing process may include a step of applying a solder resist 115 to the organic base substrate 110. As shown in FIG. 7C, the manufacturing process may include a step of treating the solder resist 115 with laser irradiation to obtain the structure shown in FIG. 7D (having a patterned solder resist 116). The patterned solder resist 116 has an opening 116b on the bonding pad 112 and a cavity 116a exposing the defined area 110a and the edge of the conductive pad 114 close to the defined area 110a.

[0098] The interconnection structure after the chips are mounted will now be outlined with reference to FIG.

[0099] FIG. 8 is a schematic diagram of an electronic device 190 including an interconnect substrate 100 as an interposer and an interconnect structure after chip mounting. FIG. 8 is an enlarged cross-sectional view of the electronic device 190 around the interconnect layer 130. As shown in FIG. 8, the interconnect substrate 100 is mounted with two chips 150-1 and 150-2. Examples of chips include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a SoC (System on Chip), a memory device such as a HBM (High Bandwidth Memory), and the like. The first chip 150-1 and the adjacent second chip 150-2 can be configured to perform mutual signal transmission through the interconnect layer 130 located between the first and second chips 150-1, 150-2. In the described embodiment, the chip 150 is connected to a power or ground line of the organic base substrate 110 through a wiring in the interconnect layer 130, which serves as a signal return current path.

[0100] 8, electronic device 190 includes interconnect substrate 100 as described above, and first and second chips 150-1, 150-2 mounted on interconnect substrate 100 with their active surfaces facing down. Each chip 150 can be positioned on interconnect substrate 100 in a location corresponding to flip chip area 110b. Gaps between interconnect substrate 100 and chips 150 can be filled with underfill 168, which can be comprised of epoxy or urethane.

[0101] The first group of bonding pads 112-1 and the first set of bonding pads 141-1, 142-1 are positioned in a first flip chip area 110b-1 on which a first chip 150-1 is mounted. The first chip 150-1 has a set of terminal bumps 151-1, 152-1 electrically connected to the first set of pads 141-1, 142-1 of the interconnect layer 130 through solders 156-1, 157-1. The first chip 150-1 also has a set of other terminals 154-1 electrically connected to the first group of bonding pads 112-1 on the organic base substrate 110 through solders 158-1. The terminal bumps 151-1, 152-1, 154-1 can be, but are not limited to, Cu pillar-type bumps. The terminal bump 151-1 can be a power or ground terminal configured to connect to a power or ground line that can function as a signal return current path. More specifically, the terminal bump 151 is connected to a bonding pad 141 that is connected to a corresponding side connection pad 140 via a trace embedded in the organic insulating material 134, which is further connected to a power or ground line of the organic base substrate 110 through a solder joint 119. The same is true for the second flip chip area 110b-2 and the second chip 150-2.

[0102] 8, the interconnect substrate 100 with multiple chips 150 mounted thereon constitutes an electronic package, which may have bumps formed on the bottom of the interconnect substrate 100 and is further mounted to a motherboard through package interconnects between the bumps of the interconnect substrate 100 and pads formed on the motherboard. Also, the final assembly product including the interconnect substrate 100, the chips 150, and the motherboard may be one of electronic devices, which is also the interconnect structure after the chips are mounted.

[0103] The chips 150 can communicate with each other through the interconnect layer 130, while being connected to the motherboard through the internal structure of the organic base substrate 110. Furthermore, according to the described embodiment, the power and ground lines to the chips 150 can be routed through the interconnect layer 130 with side connections realized by the solder joints 119. This can reduce voltage drops compared to when the wiring is routed on the organic base substrate while avoiding the area of ​​the interconnect layer. The use of the interconnect layer allows the power or ground line to function as a signal return current path, which is favorable for high-speed signal transmission.

[0104] This interconnect structure allows the introduction of a novel side connection between the conductive pads 114 of the organic base substrate 110 and the side connection pads 140 of the interconnect layer 130. The introduction of the novel side connection improves the flexibility of wiring by the interconnect layer 130. It also relaxes the constraints on the terminal layout of the chip 150 using the interconnect layer 130. Such an interconnect structure is suitable for heterogeneous integration.

[0105] Although FIG. 8 only shows two chips and one interconnect layer 130 through which the two chips communicate, the number of chips in an electronic device, the number of chips per interconnect layer, and the number of interconnect layers are not limited.

[0106] 9A to 9C, the manufacturing process of the electronic device, which is carried out subsequently after the manufacturing process of the interconnects, will be described. FIG. 9A to FIG. 9C are cross-sectional views of a structure obtained in the manufacturing process of the electronic device 190.

[0107] 9A, the electronic device manufacturing process may include mounting multiple chips 150 with their active surfaces facing down on the interconnect substrate 100. A first chip 150-1 may be positioned at the location of the first group of bonding pads 112-1 and the first set of bonding pads 141-1, 141-2 of the interconnect layer 130. The same is true for the second chip 150-2.

[0108] The chip 150 prepared in this step may include terminal bumps 151, 152, 154, which may each comprise a pillar 161, 162, or 164 with a solder cap 166, 167, or 168 formed thereon. In the described embodiment, the terminal bumps 151, 152, 154 are Cu pillar bumps. However, in other embodiments, the terminal bumps 151, 152, 154 may be, for example, flip chip bumps, fine pitch micro bumps, Cu pillar bumps, Cu post bumps with Sn caps (SLID), or the like. In the described embodiment, there is no solder present on the bonding pads 141, 142 of the interconnect substrate 100 prepared in this step because each bonding pad 141, 142 does not have a barrier metal layer 138 on top to enhance wettability. However, there is no problem if solder is applied to the bonding pads 141 and 142 before the chip is mounted.

[0109] As shown in FIG. 9B, the manufacturing process may include forming solder interconnects 156, 157, 158 between bonding pads 112 and 141, 142 and pillars 161, 162, 164 by a solder reflow process.

[0110] By performing the steps shown in Figures 9A and 9B, chip 150 is mounted to interconnect substrate 100 such that terminal bumps 151 of chip 150 are bonded to bonding pads 141 and electrically connected by solder joints 119 through side connection pads 140 to conductive pads 114 disposed on organic base substrate 110.

[0111] As shown in FIG. 9C, the manufacturing process may include injecting underfill 168 to fill gaps between interconnect substrate 100 and chips 150 via a capillary flow underfill process, followed by curing to fix first chip 150-1 and second chip 150-2 to interconnect substrate 100.

[0112] In the described embodiment, the underfill 168 is described to be applied onto the organic-based substrate 110 after the reflow process. However, in another embodiment, a no-flow underfill can be first injected onto the interconnect substrate 100. The chip 150 is then placed onto the underfill-injected interconnect substrate 100. Finally, the reflow process simultaneously forms the solder interconnects 156, 157, 158 and cures the underfill. In the described embodiment, a solder reflow process is used as the bonding process. However, in another embodiment, a thermocompression (TC) bonding process can be used instead of the solder reflow process.

[0113] A process for fabricating an interconnect layer-carrying structure that can be used for transferring an interconnect layer onto an organic-based substrate is described below with reference to the sequence of Figures 10A-10F, 11A-11E, 12A-12D, 13A-13E, 14A-14D, and 15A-15D. Figures 10A-10F, 11A-11E, 12A-12D, 13A-13E, 14A-14D, and 15A-15D show cross-sectional views of structures obtained in the fabrication process of an interconnect layer-carrying structure 120.

[0114] As shown in Fig. 10A, the manufacturing process of the interconnect layer carrying structure 120 may include a step of preparing a support substrate 200. In the described embodiment, the support substrate 200 prepared in this step is a glass wafer or panel, and the following process is described assuming a laser debonding process. However, in the case of a mechanical or thermal debonding process, other substrates such as silicon wafers can be used as the support substrate 200. The thickness of the support substrate 200 can range, for example, from several hundred micrometers to several millimeters.

[0115] 10B, the manufacturing process may include applying a release layer 202 to the support substrate 200. The release layer 202 may be formed by virtually any means, such as, for example, spin coating. In one embodiment, the release layer 202 may have a thickness of, for example, about 1 micrometer or less. After the release layer 202 is formed, the interconnect layer is built on the release layer 202 by the steps described below.

[0116] As shown in FIG. 10C, the manufacturing process may include forming a first seed metal layer 204 on the release layer 202. The first seed metal layer 204 can be formed by virtually any means, such as by sputtering. In one particular embodiment, a stack of titanium and copper layers (Ti / Cu, where Ti is at the bottom of the stack) is formed by sputtering on the release layer 202 to form the first seed metal layer 204. In one embodiment, the titanium layer can be tens of nanometers thick, and the copper layer can be hundreds of nanometers thick. The same applies to the other seed layers described below.

[0117] As shown in FIG. 10D, the manufacturing process may include depositing a plating resist 206 on the first seed metal layer 204. In one particular embodiment, the plating resist 206 may be composed of any one of photosensitive resins. The thickness of the plating resist 206 may range from 10 micrometers to 50 micrometers. The plating resist 206 may be formed by virtually any means, for example, spin coating. In addition to liquid type resists, film type resists may also be used. In the case of film type resists, the plating resist 206 is formed by a lamination process. The same applies to other plating resists described below.

[0118] As shown in FIG. 10E, the manufacturing process may include creating a plurality of openings 206a in the plating resist 206. The openings 206a correspond to the pads 140, 141, 142 shown in FIG. 2. The openings 206a may be created by virtually any means, such as photolithography. In a particular embodiment, the openings 206a are created in the plating resist 206 by exposing a photosensitive resin deposited by spin coating through a photomask 208 and developing it. It should be noted that the manufacturing process is described with a particular type of resist or photosensitive resin for patterning. For example, FIG. 10E illustrates the use of a positive resist. However, the type of resist or photosensitive resin is not limited to the particular type shown in the drawings. Positive and negative resists or photosensitive resins may be employed as well. The same applies to other resists and photosensitive resins described below.

[0119] As shown in FIG. 10F, the manufacturing process may further include forming a barrier metal layer 210 on the first seed metal layer 204 at the openings 206a of the plating resist 206. In a particular embodiment, the barrier metal layer 210 is a Au / Pd / Ni metal stack, which may include a gold layer on the first seed metal layer 204, a palladium layer on the gold layer, and a nickel layer on the palladium layer. When the interconnect layer 130 obtained in the manufacturing process of the interconnect substrate 110 is transferred onto the organic-based substrate 110, the gold layer will be the top. The barrier metal layer 210 can be formed on the first seed metal layer 204 by virtually any metallization process, such as electrolytic plating.

[0120] 11A, the manufacturing process may include depositing a first conductive layer 212 on a barrier metal layer 210. The first conductive layer 212 may be formed by virtually any means, such as, for example, electroplating. In one particular embodiment, the first conductive layer 212 is formed by deposition of metallic copper by electroplating. The same applies to the other conductive layers described below.

[0121] As shown in Figure 11B, the manufacturing process can include removing the plating resist 206 from the first seed metal layer 204. As shown in Figure 11C, the manufacturing process can include removing portions of the first seed metal layer 204 that are exposed from the metal stack 210, 212.

[0122] By performing the steps shown in FIGS. 10C-10F and 11A-11C, a set of side connection pads 140 and bonding pads 141, 142 are formed on the release layer 202 by patterning the conductive material.

[0123] As shown in FIG. 11D, the manufacturing process may include forming a first organic insulating portion 214 on the release layer 202 to embed a set of pads 140, 141, 142 (including the first seed metal layer 204, the barrier metal layer 210, and the first conductive layer 212). In a particular embodiment, the first organic insulating portion 214 is made of any one of photosensitive insulating resins. The thickness of the first organic insulating portion 214 can range from a few micrometers to tens of micrometers. The first organic insulating portion 214 can be formed by virtually any means, such as spin coating. In addition to liquid type resin, film type resin can also be used. In the case of film type resin, the first organic insulating portion 214 is formed by a lamination process. The same applies to other organic insulating portions described below.

[0124] As shown in Fig. 11E, the manufacturing process may include exposing and developing a first organic insulating portion 214 to have a plurality of via openings 214a at the locations of the pads 140, 141, 142. The via openings 214a can be manufactured by virtually any means, for example photolithography. In one particular embodiment, the via openings 214a are configured by exposing a photosensitive insulating resin deposited by spin coating through a photomask 216 and developing it. Fig. 11E illustrates the use of a negative resist.

[0125] As shown in FIG. 12A, the manufacturing process may include forming a second seed metal layer 218 on the top surface of the first organic insulator 214 and on the exposed surface of the first conductive layer 212 in the via opening 214a.

[0126] As shown in FIG. 12B, the manufacturing process may include depositing a plating resist 220 on the second seed metal layer 218. As shown in FIG. 12C, the manufacturing process may include patterning an opening pattern 220a in the plating resist 220 using a photomask 222. The opening pattern 220a includes a wiring or trace pattern for the bonding pad 142. The opening pattern 214a can be manufactured by virtually any means, such as photolithography. FIG. 12C illustrates the use of a positive resist.

[0127] As shown in Figure 12D, the manufacturing process may include depositing a second conductive layer 224 on areas of the second seed metal layer 218 that are free of the plating resist. As shown in Figure 13A, the manufacturing process may include removing the plating resist 220 from the second seed metal layer 218. As shown in Figure 13B, the manufacturing process may include removing portions of the second seed metal layer 218 that are exposed from the second conductive layer 224.

[0128] By performing the steps illustrated in Figures 11E, 12A-12D, 13A, and 13B, the conductive material is patterned to form bonding pads 142 and traces connecting corresponding bonding pads.

[0129] As shown in Figure 13C, the manufacturing process may include depositing a second organic insulating layer 226 on the first organic insulating portion 214 to embed the second conductive layer 224. As shown in Figure 13D, the manufacturing process may include exposing and developing the second organic insulating layer 226 to have a plurality of via openings 226a at the locations of the pads 140, 141. No openings are formed at the locations of the pads 142 because the bonding pads 142 are isolated from the pads 140, 141. Figure 13D illustrates the use of a negative resist.

[0130] As shown in FIG. 13E, the manufacturing process may include forming a third seed metal layer 230 on the top surface of the second organic insulating layer 226 and on the exposed surface of the second conductive layer 224 in the via opening 226a.

[0131] As shown in Figure 14A, the manufacturing process may include a step of patterning a plating resist 232 on the third seed metal layer 230 using a photomask 234. The plating resist 232 has an opening pattern 232a that includes a wiring or trace pattern for the pads 140, 141. Figure 14A illustrates the use of a positive resist.

[0132] As shown in Figure 14B, the manufacturing process may include depositing a third conductive layer 236 on areas of the third seed metal layer 230 that are free of plating resist. As shown in Figure 14C, the manufacturing process may include removing the plating resist 232 from the third seed metal layer 230. As shown in Figure 14D, the manufacturing process may include removing portions of the third seed metal layer 230 that are exposed from the third conductive layer 236.

[0133] By performing the steps shown in FIGS. 13C-13E and 14A-14D, the conductive material is patterned to form wiring connecting the side connection pads 140 and the corresponding bonding pads 141.

[0134] As shown in Figure 15A, the manufacturing process may include depositing a third organic insulating layer 238 on the second organic insulating layer 226 to embed a third conductive layer 236. As shown in Figure 15B, the manufacturing process may include exposing and developing the third organic insulating layer 238 with a photomask 240.

[0135] As shown in Fig. 15C, the manufacturing process may further include a step of cutting the support substrate 200 together with its upper structure (including the release layer 202) using a dicing blade to obtain individual structures shown in Fig. 15D (almost identical to the interconnect layer-carrying structure 120 shown in Fig. 2). The cutting line (dashed line in Fig. 15C) corresponds to one edge E of the interconnect layer-carrying structure 120 and passes through the position where the metal stack corresponding to the side connection pads 140 is divided. The cutting of the support substrate 200 completes the manufacture of a set of side connection pads 140.

[0136] Since the outline of the interconnect layer portion 131 is defined by the cutting process, the edges of the interconnect layer portion 131 have a straight line shape and a set of side connection pads 140 are formed in a row, and therefore a corresponding set of conductive pads 114 are also formed in a row.

[0137] It should be noted that the manufacturing process may further include forming a barrier metal layer on the edge surface ES of the side connection pad 140 by virtually any metallization process, such as electroless plating. In a particular embodiment where electroless plating is employed, the barrier metal layer is formed on the edge surface ES of the side connection pad 140 by selective plating of the exposed edge surface ES of the side connection pad 140. The formation of the barrier metal layer may be preferably performed prior to attachment of the interconnect layer portion 131 to the organic base substrate 110 to avoid voids due to pad size differences between the interconnect layer portion 131 and the organic base substrate 110. Although the composition and additives of the barrier metal layer are different between the top surface TS and the edge surface ES, the barrier metal layer on the edge surface ES is preferably the same as that of the top surface TS in terms of the combination of metal materials that uniforms the diffusion rate of the solder elements, thereby mitigating local alloy formation and stress concentrations. For example, if the barrier metal on the top surface TS is a Ni / Au stack, it is preferable to employ a Ni / Au stack on the edge surface ES as well.

[0138] The interconnect layer carrying structure 120 obtained by this process can be passed to a subsequent process such as the fabrication of a series of interconnect structures as shown in Figures 3A-3C and 4A-4C. In one embodiment, the interconnect layer carrying structure 120 separated from the glass wafer or panel by dicing as shown in Figure 15D can be provided to the next step in the production chain. The interconnect layer portion 131 is made of an organic material and is provided in the form of a tape held by a support substrate 122 as a rigid backing.

[0139] The interconnect layer-carrying structure 120 obtained by this process may have two conductive layers (other than the pad body) including an intermediate layer of organic insulating material, although the number of conductive layers is not limited. By repeatedly performing a series of steps of (i) depositing an organic insulating layer, (ii) exposing and developing the organic insulating layer, (iii) forming a seed layer, (iv) depositing a plating resist, (v) exposing and developing the plating resist, (vi) depositing a conductive layer, (vii) removing the plating resist, and (viii) removing the seed layer, each conductive layer is stacked one-to-one with an intermediate layer of organic insulating material.

[0140] The above-described manufacturing process for the interconnect layer carrying structure 120 is cost-effective and allows for a scalable number of interconnect layer carrying structures to be cut from a single wafer or panel.

[0141] An alternative process for manufacturing an interconnect layer carrying structure will now be described with further reference to Figures 16A-16D, 17A-17C, 18A-18D, 19A-19D, and 20A-20C in conjunction with Figures 10A-10F and 11A-11D. Figures 10A-10F, 11A-11D, 16A-16D, 17A-17C, 18A-18D, 19A-19D, and 20A-20C are cross-sectional views of structures obtained in an alternative manufacturing process for an interconnect layer carrying structure 120.

[0142] 10A-10F and 11A-11D are the same as the above-mentioned exemplary embodiment, so the following description will start from the step of FIG. 16A. By performing the steps of FIG. 10A-10F and 11A-11D, a structure including a support substrate 200, a release layer 202 formed on the support substrate 200, a set of pads 140, 141, 142 (including a first seed metal layer 204, a barrier metal layer 210, and a first conductive layer 212) formed on the release layer 202, and a first organic insulating portion 214 formed on the release layer 202 but not yet exposed and developed is obtained.

[0143] As shown in Figure 16A, the manufacturing process may include exposing and developing a first organic insulating portion 214 to have multiple via openings 214a at the locations of pads 140, 141, 142, and to expose one edge of side connection pad 140, shown in Figure 16A by open space 214b. Figure 16A illustrates a scenario where a negative resist is used.

[0144] As shown in FIG. 16B, the manufacturing process may include forming a second seed metal layer 218 on the top surface of the first organic insulator 214, the exposed surface of the first conductive layer 212 in the via opening 214a and the open space 214b, and the exposed surface of the release layer 202 in the open space 214b.

[0145] As shown in FIG. 16C, the manufacturing process may include depositing a plating resist 220 on the second seed metal layer 218. As shown in FIG. 16D, the manufacturing process may include patterning an opening pattern 220a in the plating resist 220. As shown in FIG. 17A, the manufacturing process may include depositing a second conductive layer 224 on areas of the second seed metal layer 218 that are free of the plating resist. As shown in FIG. 17B, the manufacturing process may include removing the plating resist 220 from the second seed metal layer 218. As shown in FIG. 17C, the manufacturing process may include removing portions of the second seed metal layer 218 exposed from the second conductive layer 224.

[0146] As shown in Figure 18A, the manufacturing process may include depositing a second organic insulating layer 226 on the first organic insulating portion 214 to embed the second conductive layer 224. As shown in Figure 18B, the manufacturing process may include exposing and developing the second organic insulating layer 226 using a photomask 228 to have multiple via openings 226a at the locations of the pads 140 and to expose one edge of the side connection pads 140, shown in Figure 18B by the open spaces 226b. Figure 18B illustrates the use of a negative resist.

[0147] As shown in FIG. 18C, the manufacturing process may include forming a third seed metal layer 230 on the top surface of the second organic insulating layer 226, the exposed surface of the second conductive layer 224 in the via opening 226a and the open space 226b, and the exposed surface of the release layer 202 in the open space 226b.

[0148] As shown in Fig. 18D, the manufacturing process may include a step of patterning a plating resist 232 on the third seed metal layer 230 using a photomask 234. The plating resist 232 has an opening pattern 232a including a wiring pattern for the pads 140, 141. Fig. 18D illustrates the use of a positive resist.

[0149] As shown in Figure 19A, the manufacturing process may include depositing a third conductive layer 236 on areas of the third seed metal layer 230 that are free of plating resist. As shown in Figure 19B, the manufacturing process may include removing the plating resist 232 from the third seed metal layer 230. As shown in Figure 19C, the manufacturing process may include removing portions of the third seed metal layer 230 that are exposed from the third conductive layer 236.

[0150] As shown in Figure 19D, the manufacturing process may include depositing a third organic insulating layer 238 on the second organic insulating layer 226 to embed the third conductive layer 236. As shown in Figure 20A, the manufacturing process may include exposing and developing the third organic insulating layer 238 with a photomask 240 to expose edges of the side connection pads 140.

[0151] The first organic insulating portion 214, the second organic insulating layer 226, and the third organic insulating layer 238 are patterned to form the outer shape of the interconnect layer portion 131 while exposing at least the edge surface ES of each side connection pad 140 from the organic insulating layers 214, 226, 238.

[0152] It should be noted that the manufacturing process may further include forming a barrier metal layer on the edge surface ES of the side connection pad 140 by virtually any metallization process, such as electroless plating. The formation of the barrier metal layer on the edge surface ES may be performed at any stage of forming the side connection pad 140 and exposing the edge surface ES of the side connection pad 140. Thus, the formation of the barrier metal layer may be performed after the subsequent step of cutting the support substrate 200.

[0153] As shown in Fig. 20B, the manufacturing process may further include cutting the support substrate 200 together with the release layer 202 to obtain individual structures shown in Fig. 20C (substantially identical to the interconnect layer-carrying structure 120 shown in Fig. 5). The cutting line is located away from one edge E of the interconnect layer portion 131 and the set of side connection pads 140.

[0154] Since the outer shape of the interconnect layer portion 131 is defined by photolithography, the edges of the interconnect layer portion 131 may have any suitable shape. Also, this alternative manufacturing process allows for easy fabrication of the edge extensions (or flanges) 122b that extend outward from the base portion 122a, which makes it convenient to control the height of the top surface 130a of the interconnect layer 130. This increases the density of the interconnects between the terminal bumps 151, 152, 154 and the bonding pads 141, 142, 112, improving the yield and reliability of the interconnects even when the pitch between the pads is reduced.

[0155] In one particular embodiment, the organic insulating layers 214, 226, 238 are patterned such that the edge E of the interconnect layer portion 131 has a linear shape and a set of side connection pads 140 are formed in a row, thereby forming a corresponding set of conductive pads 114 in a row.

[0156] In a preferred embodiment, the organic insulating layers 214, 226, 238 are patterned such that an edge E of the interconnect layer portion 131 has one or more curved or angled shapes extending its length, and a set of side connection pads 140 are formed to follow the contours of the one or more curved or angled shapes, thereby resulting in a set of conductive pads 114 also being formed to follow the contours of the one or more curved or angled shapes.

[0157] An overview of the interconnection substrate 100A will be described with reference to FIGS. 21A and 21B. FIG. 21A is a top view of the interconnection substrate 100A without solder joints. FIG. 21B is a top view of the interconnection substrate 100A with solder joints. As shown in FIGS. 21A and 21B, the edge E of the interconnection layer 130 has one or more angled shapes like a square wave. A set of side connection pads 140 are arranged along the contour of this square wave-like shape. As a result, the edge of the solder resist layer 116 adjacent to the interconnection layer 130 also has one or more angled shapes like a square wave-like shape. In addition, a set of conductive pads 112 are arranged along the contour of this square wave-like shape. Since the edge E is longer by the amount of bending compared to the case of a straight shape, the density of side connection can be increased.

[0158] An overview of the interconnection substrate 100B will be described with reference to FIG. 22A. FIG. 22A is a top view of the interconnection substrate 100B without solder joints. As shown in FIG. 22A, the edge E of the interconnection layer 130 has one or more angled shapes, such as a square wave shape, and is elongated similarly to the embodiment shown in FIG. 21A and FIG. 21B. The side connection pad 140 is formed along the contour of this square wave shape. Thus, the conductive pad 112 is also formed along the contour of this square wave shape.

[0159] An overview of the interconnection substrate 100C will be described with reference to FIG. 22B. FIG. 22B is a top view of the interconnection substrate 100C without solder joints. As shown in FIG. 22B, the edge E of the interconnection layer 130 has one or more curved shapes. The side connection pads 140 are formed along the contours of these curved shapes. The conductive pads 112 are also formed along the contours of these curved shapes.

[0160] In the interconnection boards 100B and 100C, the edge E is longer by the amount of bending, so that the contact area of ​​each side connection can be increased instead of increasing the density of the side connections.

[0161] The interconnect structure according to one or more embodiments of the present invention allows for the introduction of a novel side connection between the conductive pads 114 of the organic base substrate 110 and the side connection pads 140 of the interconnect layer 130. The introduction of the novel side connection increases the flexibility of the wiring layout of the interconnect layer 130. This allows for the wiring to be optimized due to the increased flexibility of the routing, thereby improving the performance of electronic devices using the interconnect structure. In addition, the constraints on the terminal layout of the chip using the interconnect layer 130 are relaxed.

[0162] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention in any way. In this specification, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It is further understood that the term "comprises" and / or "comprising" as used herein specifies the presence of a stated feature, step, layer, element, or component, or combination thereof, but does not exclude the presence or addition of one or more other features, steps, layers, elements, components, or groups thereof, or combinations thereof.

[0163] In the following claims, it is intended to include corresponding structure, materials, acts, and equivalents, where present, of all means-plus-function or step-plus-function elements, any structure, material, or act that performs a function in combination with other claimed elements as specifically claimed. The description of one or more aspects of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the form disclosed.

[0164] Numerous improvements and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used in this specification is chosen to best explain the principles of the embodiments, practical applications, or technical improvements of the technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed in this specification.

[0165] In a preferred embodiment of the invention described herein, there is provided an interconnect layer carrying structure comprising a support substrate, a release layer formed on the support substrate, and an interconnect layer portion disposed on the release layer and having an edge, the interconnect layer portion including an insulating material and a set of side connection pads embedded in the insulating material and exposed at an edge of the interconnect layer portion and formed at a predetermined interval along the edge of the interconnect layer portion. Each side connection pad preferably has a lower surface exposed at the lower surface of the interconnect layer portion and an edge surface exposed at the edge of the interconnect layer portion. The insulating material preferably constitutes the lower surface of the interconnect layer portion, and the interconnect layer portion further includes a set of first bonding pads exposed from the insulating material at the lower surface of the interconnect layer portion and used for mounting a chip. Each of the set of first bonding pads is connected to a corresponding one of the side connection pads via a wiring embedded in the insulating material. Each side connection pad may be configured to be connected by a solder joint to a corresponding conductive pad (that receives the transferred interconnect layer portion) disposed on the base substrate.

[0166] In a preferred embodiment of the invention described herein, a method for manufacturing an interconnect layer carrying structure is provided, the method comprising: providing a support substrate; applying a release layer to the support substrate; and constructing an interconnect layer on the release layer, the interconnect layer having an edge and including an insulating material and a set of side connection pads embedded in the insulating material, the set of side connection pads being located and exposed at the edge of the interconnect layer and formed at a predetermined interval along the edge of the interconnect layer. Constructing the interconnect layer preferably comprises providing the set of side connection pads on the release layer by patterning a conductive material, and forming an insulating portion on the release layer to embed the set of side connection pads. Constructing the interconnect layer may comprise forming a set of first bonding pads on the release layer, patterning traces configured to connect each side connection pad of the set of side connection pads with a corresponding bonding pad of the set of first bonding pads, and forming a second insulating portion to embed the traces. Constructing the interconnect layer may further include forming a second bonding pad and a third bonding pad on the release layer, patterning a trace connecting the second bonding pad and the third bonding pad, and forming a third insulating portion to embed the trace. The method may further include completing the interconnect layer and the set of side connection pads by cutting the support substrate with the structures thereon through the patterned conductive material. The insulating portion may be patterned to expose at least an edge surface of each side connection pad from the insulating portion, and the method further includes cutting the support substrate away from the set of side connection pads.

Claims

1. An organic-based substrate; a set of conductive pads disposed on the organic base substrate; an interconnect layer disposed on the organic base substrate, the interconnect layer having edges adjacent the set of conductive pads and including a set of exposed side connection pads located at the edges, each side connection pad of the set of side connection pads being solder-bonded to a corresponding one of the set of conductive pads disposed on the organic base substrate; Equipped with At least a portion of the organic base substrate proximate the conductive pad and a pad surface of the conductive pad have an increased surface roughness due to a surface treatment, and due to the increased surface roughness, the pad surface has an improved solder wettability, while the at least a portion of the organic base substrate has an improved desolder wettability. Interconnect structure.

2. the interconnect layer further comprises an organic insulating material constituting a top surface of the interconnect layer; 2. The interconnect structure of claim 1, wherein each of the side connection pads has a top surface exposed at the top surface of the interconnect layer and an edge surface exposed at the edge of the interconnect layer, the edge surface facing the corresponding one of the conductive pads.

3. 3. The interconnect structure of claim 2, wherein the top and edge surfaces of the set of side connection pads and at least a portion of the top and edge of the interconnect layer near the side connection pads have an increased surface roughness due to a surface treatment, and due to the increased surface roughness, the top and edge surfaces of the set of side connection pads have improved solder wettability, while the top and at least a portion of the edge of the interconnect layer have improved desolder wettability.

4. 4. The interconnect structure of claim 2 or 3, wherein a set of first bonding pads are exposed from the insulating material on the top surface of the interconnect layer, the set of first bonding pads are used for mounting a chip, and each of the first bonding pads of the set of bonding pads is connected to a corresponding conductive pad of the side connection pad via a wiring embedded in the insulating material.

5. 5. The interconnect structure of claim 4, wherein the interconnect layer further includes a second bonding pad for mounting the chip and a third bonding pad for mounting another chip, the second bonding pad being connected to the third bonding pad via a trace embedded in the insulating material.

6. 4. The interconnect structure of claim 1, wherein the edge of the interconnect layer has one or more curved or angled shapes extending its length, and the set of side connection pads and the set of conductive pads are formed along the contours of the one or more curved or angled shapes.

7. 7. The interconnect structure of claim 1, wherein each pair of a side connection pad of the interconnect layer and a corresponding conductive pad disposed on the organic base substrate is independently used for power or ground.

8. 8. An interconnect structure as described in any one of claims 1 to 7, further comprising one or more chips mounted on the organic base substrate, at least one of the chips having a terminal electrically connected through one of the side connection pads to a corresponding one of the conductive pads disposed on the organic base substrate.

9. 1. A method for manufacturing an interconnect structure, comprising: Providing an organic base substrate having a set of conductive pads disposed thereon; disposing an interconnect layer on the organic base substrate including a set of side connection pads located at edges and exposed, the interconnect layer being disposed on the organic base substrate such that the edges of the interconnect layer are adjacent the set of conductive pads and each side connection pad of the set of side connection pads is positioned relative to a corresponding conductive pad of the set of conductive pads disposed on the organic base substrate; applying a surface treatment to at least a portion of the organic base substrate proximate the conductive pad and to a pad surface of the conductive pad, the surface treatment increasing the surface roughness, the increased surface roughness improving the solder wettability of the pad surface while improving the desolder wettability of the at least a portion of the organic base substrate; forming a set of solder joints respectively connecting the set of side connection pads of the interconnect layer to the set of conductive pads disposed on the organic base substrate; A method comprising:

10. providing the interconnect layer; placing an interconnect layer-carrying structure including a support substrate, a release layer on the support substrate, and the interconnect layer on the release layer upside down on the organic-based substrate; removing the release layer to release the interconnect-carrying structure from the support substrate; Including, The method of claim 9 , wherein a top surface of the interconnect layer disposed on the organic-based substrate comprises an organic insulating material.

11. 11. The method of claim 10, wherein applying the surface treatment further comprises applying a surface treatment that increases surface roughness to pad surfaces of the set of side connection pads and at least a portion of an exposed surface of the organic insulating material proximate the side connection pads, the increased surface roughness improving solder wettability of the pad surfaces of the side connection pads while improving desolder wettability of the at least a portion of the exposed surface of the organic insulating material.

12. 12. The method of claim 9, further comprising mounting one or more chips on the organic base substrate such that at least one of the chips has a terminal electrically connected to one of the conductive pads disposed on the organic base substrate through one of the side connection pads.

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