Regulator

Abstract

[Problem] To provide a regulator that is capable of suppressing output voltage fluctuation while reducing electric power consumption. [Solution] A regulator comprising: a plurality of analog-to-digital converters that compare an output voltage with a threshold voltage so as to successively output, at respective different times, digital signals that are in accordance with the output voltage; an output control circuit that controls the output voltage on the basis of the digital signals; and a timing control circuit that controls, on the basis of at least one of a gate leakage current and a channel leakage current of a transistor in the plurality of analog-to-digital converters, times at which the respective plurality of analog-to-digital converters carry out an analog-to-digital conversion operation to convert the output voltage into the digital signals and times at which the respective plurality of analog-to-digital converters adjust the threshold voltage.

Description

[Technical field]

[0001] The present disclosure relates to regulators. [Background technology]

[0002] As the number of battery-powered electronic devices increases, there is a growing demand for power supply circuits with low power consumption. One such power supply circuit is the LDO (Low Drop Out) regulator (see Patent Documents 1 and 2). With an LDO regulator, the input / output potential difference between the input and output voltages can be reduced, and power consumption in the regulator can be suppressed, thereby extending the battery life. For this reason, LDO regulators have become an essential component in battery-powered electronic devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2016-519356 [Patent Document 2] Special Publication No. 2016-511485 Summary of the Invention [Problem to be solved by the invention]

[0004] The LDO regulator can include an AD converter that outputs a digital signal corresponding to the difference voltage between the output voltage and a threshold voltage, and an impedance variable circuit that controls the output voltage based on the digital signal.

[0005] The threshold voltage of an AD converter varies over time, so a periodic reset operation (also called an auto-zero operation) is necessary. The period during which the auto-zero operation is performed is the dead band time during which the AD converter cannot perform AD conversion operations. During the dead band time, the output voltage cannot be controlled, so there is a risk that the output voltage will fluctuate.

[0006] It is possible to implement circuit-related measures to shorten the dead band time, but if such measures result in increased power consumption, this is undesirable as it defeats the purpose of the LDO regulator.

[0007] Therefore, the present disclosure provides a regulator that can suppress fluctuations in output voltage while reducing power consumption. [Means for solving the problem]

[0008] In order to solve the above problems, according to the present disclosure, there is provided a method for switching between analog and digital converters, the method comprising: comparing an output voltage with a threshold voltage to output a digital signal corresponding to the output voltage in sequence at different timings; an output control circuit that controls the output voltage based on the digital signal; A regulator is provided, comprising: a timing control circuit that controls a timing at which each of the plurality of analog-to-digital converters performs an analog-to-digital conversion operation to convert the output voltage into the digital signal and a timing at which the threshold voltage is adjusted, based on at least one of a gate leakage current and a channel leakage current of a transistor in the plurality of analog-to-digital converters.

[0009] The timing control circuit may adjust the threshold voltages of the analog-to-digital converters other than the one of the plurality of analog-to-digital converters during a period in which the one of the plurality of analog-to-digital converters is performing the analog-to-digital conversion operation.

[0010] The timing control circuit may have transistors with the same characteristics as transistors in the multiple analog-to-digital converters, and may control the timing at which each of the multiple analog-to-digital converters performs the analog-to-digital conversion operation and the timing at which the threshold voltage is adjusted based on at least one of a gate leakage current and a channel leakage current of the transistors with the same characteristics.

[0011] The transistors with the same characteristics in the timing control circuit may have a gate oxide film with the same thickness as a gate oxide film of the transistors in the plurality of analog-to-digital converters.

[0012] The transistors of the same characteristics in the timing control circuit may have an impurity concentration profile that is the same as a profile of impurity concentrations of transistors in the plurality of analog-to-digital converters.

[0013] The timing control circuit may adjust the threshold voltage more frequently as at least one of a gate leakage current and a channel leakage current of the transistor having the same characteristics increases.

[0014] The timing control circuit includes: a capacitor that stores a charge according to a gate current in a state where the drain, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage corresponding to the charge stored in the capacitor with a reference voltage; The digital signal processing device may further include a clock generator that generates a clock signal that controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted based on a comparison result of the comparator.

[0015] The timing control circuit includes: a capacitor that stores a charge according to a drain current in a state where the gate, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage corresponding to the charge stored in the capacitor with a reference voltage; The digital signal processing device may further include a clock generator that generates a clock signal that controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted based on a comparison result of the comparator.

[0016] The timing control circuit includes: the first transistor and the second transistor having the same characteristics; a capacitor for storing a charge according to a gate current in a state in which the drain, source, and backgate of the first transistor are short-circuited and connected to a reference voltage node, and a drain current in a state in which the gate, source, and backgate of the second transistor are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage corresponding to the charge stored in the capacitor with a reference voltage; The digital signal processing device may further include a clock generator that generates a clock signal that controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted based on a comparison result of the comparator.

[0017] the plurality of analog-to-digital converters includes a first analog-to-digital converter and a second analog-to-digital converter; The timing control circuit includes: adjusting the threshold voltage of the second analog-to-digital converter while the first analog-to-digital converter is performing the analog-to-digital conversion operation; The threshold voltage may be adjusted in the first analog-to-digital converter while the second analog-to-digital converter is performing the analog-to-digital conversion operation.

[0018] the timing control circuit generates a clock signal having a period corresponding to at least one of a gate leakage current and a channel leakage current of a transistor in the first analog-to-digital converter and the second analog-to-digital converter; When the clock signal is at a first logic level, the first analog-to-digital converter performs the analog-to-digital conversion operation and the second analog-to-digital converter adjusts the threshold voltage; When the clock signal is at a second logic level, the second analog-to-digital converter may perform the analog-to-digital conversion operation and the first analog-to-digital converter may adjust the threshold voltage.

[0019] The timing control circuit may shorten the period of the clock signal as at least one of a gate leakage current and a channel leakage current of a transistor in the first analog-to-digital converter and the second analog-to-digital converter increases.

[0020] The timing control circuit may have transistors with the same characteristics as transistors in the first analog-digital converter and the second analog-digital converter, and may control the timing at which the transistors in the first analog-digital converter and the second analog-digital converter perform the analog-digital conversion operation and the timing at which the threshold voltage is adjusted based on at least one of a gate leakage current and a channel leakage current of the transistors with the same characteristics.

[0021] The timing control circuit includes: a capacitor that stores a charge according to a gate current in a state where the drain, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage according to the charge stored in the capacitor with a reference voltage; The period of the clock signal may be set in accordance with a comparison result of the comparator.

[0022] The timing control circuit includes: the first transistor and the second transistor having the same characteristics; a first current circuit in which the drain, source, and back gate of the first transistor are short-circuited and connected to a first voltage node; a second current circuit in which the drain, source, and backgate of the second transistor are short-circuited and connected to a second voltage node; a first switch that switches whether or not a charge corresponding to a gate current of the first transistor in the first current circuit is to be stored in the capacitor; a second switch that switches whether or not a current corresponding to the charge stored in the capacitor is passed to the gate of the second transistor in the second current circuit; The comparator may switch between the first switch and the second switch to pass a current corresponding to the stored charge in the capacitor to the gate of the second transistor in the second current circuit when a voltage corresponding to the stored charge in the capacitor is higher than a first reference voltage, and may store charge corresponding to the gate current of the first transistor in the first current circuit in the capacitor by switching between the first switch and the second switch when the voltage corresponding to the stored charge in the capacitor is equal to or lower than a second reference voltage that is a voltage level lower than the first reference voltage.

[0023] a capacitor that stores a charge according to a drain current in a state where the gate, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage according to the charge stored in the capacitor with a reference voltage; The period of the clock signal may be set in accordance with a comparison result of the comparator.

[0024] The timing control circuit includes: the first transistor and the second transistor having the same characteristics; a first current circuit in which the gate, the source and the back gate of the first transistor are shorted and connected to a first voltage node; a second current circuit in which the gate, the source, and the back gate of the second transistor are shorted and connected to a second voltage node; a first switch that switches whether or not a charge corresponding to a drain current of the first transistor in the first current circuit is to be stored in the capacitor; a second switch that switches whether or not a discharge current corresponding to the accumulated charge of the capacitor is to be passed to the second voltage node via the drain of the second transistor in the second current circuit; The comparator may flow a discharge current corresponding to the accumulated charge of the capacitor to the drain of the second transistor in the second current circuit by switching the first switch and the second switch when a voltage corresponding to the accumulated charge of the capacitor is higher than a first reference voltage, and may store charge corresponding to the drain current of the first transistor in the first current circuit in the capacitor by switching the first switch and the second switch when the voltage corresponding to the accumulated charge of the capacitor is equal to or lower than a second reference voltage having a voltage level lower than the first reference voltage.

[0025] The timing control circuit includes: a capacitor for storing a charge according to a gate current in a state in which the drain, source, and back gate of the transistor having the same characteristics are shorted and connected to a reference voltage node, and a drain current in a state in which the gate, source, and back gate of the transistor having the same characteristics are shorted and connected to a reference voltage node; a comparator for comparing a voltage according to the charge stored in the capacitor with a reference voltage; The period of the clock signal may be set in accordance with a comparison result of the comparator.

[0026] The timing control circuit includes: the first transistor and the second transistor having the same characteristics; a first current circuit in which the drain, source, and back gate of the first transistor are short-circuited and connected to a first voltage node; a second current circuit in which the drain, source, and backgate of the second transistor are short-circuited and connected to a second voltage node; the third transistor and the fourth transistor having the same characteristics; a third current circuit in which the gate, the source and the back gate of the third transistor are short-circuited and connected to the first voltage node; a fourth current circuit in which the gate, the source, and the back gate of the fourth transistor are short-circuited and connected to the second voltage node; a first switch that switches whether or not to store a charge in the capacitor according to a gate current of the first transistor in the first current circuit and a drain current of the third transistor in the third current circuit; a second switch that switches whether or not a current corresponding to the charge stored in the capacitor is passed to a gate of the second transistor in the second current circuit and a drain of the fourth transistor in the fourth current circuit; The comparator may, when a voltage corresponding to the accumulated charge of the capacitor is higher than a first reference voltage, flow a current corresponding to the accumulated charge of the capacitor to the gate of the second transistor in the second current circuit and the drain of the fourth transistor in the fourth current circuit by switching the first switch and the second switch, and, when a voltage corresponding to the accumulated charge of the capacitor is equal to or lower than a second reference voltage having a voltage level lower than the first reference voltage, store a charge in the capacitor corresponding to the gate current of the first transistor in the first current circuit and the drain current of the third transistor in the third current circuit by switching the first switch and the second switch. [Brief description of the drawings]

[0027] [Figure 1] 1 is a block diagram showing a schematic configuration of a regulator according to a first embodiment. [Diagram 2] FIG. 1 is a block diagram showing a schematic configuration of a regulator according to a comparative example. [Diagram 3] FIG. 4 is a diagram showing the operation timing of a first ADC and a second ADC. [Figure 4] 3 is a circuit diagram showing an example of the internal configuration of a comparator in the first ADC and the second ADC in FIG. 1 and FIG. 2. [Diagram 5] 6 is a waveform diagram showing how the threshold voltage of a transistor in a comparator varies. [Figure 6] FIG. 2 is a block diagram showing the internal configuration of the timing control circuit in FIG. [Figure 7] FIG. 7 is a signal waveform diagram of each part in the timing control circuit of FIG. 6. [Figure 8]FIG. 11 is a circuit diagram showing the internal configuration of a timing control circuit according to a second embodiment. [Figure 9] FIG. 11 is a circuit diagram showing the internal configuration of a timing control circuit according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, an embodiment of a regulator will be described with reference to the drawings. The following description will focus on the main components of the regulator, but the regulator may have components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0029] (First embodiment) Fig. 1 is a block diagram showing a schematic configuration of a regulator 1 according to a first embodiment, and Fig. 2 is a block diagram showing a schematic configuration of a regulator 101 according to a comparative example. Regulators 1 and 101 in Fig. 1 and 2 are LDO regulators with a small input / output voltage difference between the input voltage and the output voltage, but will be simply referred to as regulators hereinafter. Before describing regulator 1 in Fig. 1, regulator 101 according to a comparative example in Fig. 2 will be described.

[0030] The regulator 101 in FIG. 2 includes a first analog-to-digital converter (hereinafter referred to as the first ADC) 2, a second analog-to-digital converter (hereinafter referred to as the second ADC) 3, an impedance variable circuit (output control circuit) 4, and an oscillator (OSC) 5.

[0031] The first ADC2 and the second ADC3 each have a plurality of comparators 6, and a reference voltage VREF[0:6] with a different voltage level is input to each comparator 6. The number of comparators 6 and reference voltages is arbitrary. The internal configuration of the comparator 6 will be described later, but the comparator 6 compares the output voltage with a threshold voltage and outputs a binary signal indicating the comparison result. Since the threshold voltage varies over time, the comparator 6 must periodically perform a reset operation (also called an auto-zero operation), and the period during which the auto-zero operation is performed is called the auto-zero period. The factors that cause the threshold voltage of the comparator 6 to vary will be described later.

[0032] The oscillator 5 generates a clock signal CLK synchronized with the auto-zero period. For example, the period when the clock signal CLK is at a high level is the auto-zero period of the first ADC2, and the period when the clock signal CLK is at a low level is the auto-zero period of the second ADC3. In other words, the period when the clock signal CLK is at a high level is the period when the second ADC3 performs AD conversion (hereinafter also referred to as the AD conversion period), and the period when the clock signal CLK is at a low level is the AD conversion period of the first ADC2.

[0033] FIG. 3 is a diagram showing the operation timing of the first ADC2 and the second ADC3. In FIG. 3, the operation of the first ADC2 is phase A, and the operation of the second ADC is phase B. In FIG. 3, ON indicates a period during which the AD conversion operation is performed, and AZ indicates a period during which the auto-zero operation is performed. As shown in the figure, the first ADC2 and the second ADC3 alternately perform AD conversion operations, and the second ADC3 performs auto-zero operation during a period during which the first ADC2 performs AD conversion, and the first ADC2 performs auto-zero operation during a period during which the second ADC3 performs AD conversion. The first ADC2 switches between AD conversion operation and auto-zero operation based on the output signal CLK of the oscillator 5, while the second ADC3 switches between AD conversion operation and auto-zero operation based on a signal obtained by inverting the output signal CLK of the oscillator 5 by an inverter IV1.

[0034] The variable impedance circuit 4 in Fig. 1 and Fig. 2 has a control circuit 4a and an impedance adjustment circuit 4b. The control circuit 4a outputs a gate control signal consisting of multiple bits according to the digital signals output from the first ADC2 and the second ADC3. The impedance adjustment circuit 4b has a plurality of transistor circuits connected between an input voltage node n1 and an output voltage node n2, and a corresponding gate control signal is input to each transistor circuit, and the impedance according to the gate control signal is set. That is, the impedance adjustment circuit 4b adjusts the impedance between the input voltage node n1 and the output voltage node n2 according to the digital signals output from the first ADC2 and the second ADC3.

[0035] In this manner, the regulator 1 in FIG. 1 controls the output voltage by individually setting the impedances of the multiple transistor circuits using the digital signals output from the first ADC 2 and the second ADC 3.

[0036] A load circuit 7 and a bypass capacitor (pass capacitor) C1 are connected to the impedance adjustment circuit 4b. Although the magnitude of the load of the load circuit 7 varies with time, the output voltage output from the impedance adjustment circuit 4b is fed back to the first ADC2 and the second ADC3 and controlled so that the output voltage is constant.

[0037] Fig. 4 is a circuit diagram showing an example of the internal configuration of the comparator 6 in the first ADC 2 and the second ADC 3 in Fig. 1 and Fig. 2. The comparator 6 in Fig. 4 has switches SW1 to SW3, a capacitor C2, a PMOS transistor Q1, an NMOS transistor Q2, and an inverter IV2.

[0038] The switch SW1 switches whether to connect the input node of the reference voltage VREF to one end of the capacitor C2. The switch SW2 switches whether to connect the node of the output voltage VOUT to one end of the capacitor C2. The switch SW3 switches whether to connect the other end of the capacitor C2 to the input node of the inverter IV2. The output signal of the inverter IV2 is the output signal COMPOUT of the comparator 6 and is input to the variable impedance circuit 4.

[0039] The source of the PMOS transistor Q1 is connected to the power supply voltage node, the drain is connected to the input node of the inverter IV2, and the gate is connected to the other end of the capacitor C2. The drain of the NMOS transistor Q2 is connected to the input node of the inverter IV2, the source is connected to the ground node, and the gate is connected to the other end of the capacitor C2.

[0040] Switches SW1 and SW3 are on when the clock signal CLK is at high level, and switch SW2 is on when the clock signal CLK is at low level. When switch SW3 is on, the gate and drain of PMOS transistor Q1 are shorted, and the gate and drain of NMOS transistor Q2 are shorted. Therefore, when switch SW3 is on, the gate voltage of PMOS transistor Q1 becomes almost the threshold voltage, and the gate voltage of NMOS transistor Q2 also becomes almost the threshold voltage. At this time, since switch SW1 is also on, a potential difference of the reference voltage minus the threshold voltage is applied across capacitor C2, and a charge according to that potential difference is stored in capacitor C2. This is the auto-zero operation.

[0041] When the clock signal CLK goes to low level, the switches SW1 and SW3 are both turned off and the switch SW2 is turned on. This causes the output voltage to be supplied to one end of the capacitor C2. If the output voltage is higher than the reference voltage, the voltage on the other end of the capacitor C2 becomes higher than the threshold voltage, the NMOS transistor Q2 is turned on, and the output of the comparator 6 becomes high level. On the other hand, if the output voltage is lower than the reference voltage, the voltage on the other end of the capacitor C2 becomes lower than the threshold voltage, the PMOS transistor Q1 is turned on, and the output of the comparator 6 becomes low level.

[0042] 5 is a waveform diagram showing the fluctuation of the threshold voltage of the transistors Q1 and Q2 in the comparator 6. The threshold voltage gradually decreases while the comparator 6 is performing an AD conversion operation. If the fluctuation of the threshold voltage exceeds a predetermined allowable error range, the comparator 6 will no longer be able to perform a normal comparison operation.

[0043] The regulator 1 in Fig. 1 takes measures against the fluctuation of the threshold voltage of the transistors Q1 and Q2 in the comparator 6. The regulator 1 in Fig. 1 includes a timing control circuit 10 instead of the oscillator 5 in Fig. 2. The configuration within the comparator 6 in Fig. 1 other than the timing control circuit 10, specifically, the internal configurations of the first ADC 2, the second ADC 3, and the variable impedance circuit 4 are the same as those in Fig. 2 and are therefore denoted by the same reference numerals.

[0044] One of the factors that cause the fluctuation of the threshold voltage of the transistors Q1 and Q2 in the comparator 6 is the gate leakage of the transistors Q1 and Q2. Therefore, the timing control circuit 10 in FIG. 1 determines the oscillation period of the signal CLK based on the result of monitoring the gate leakage current of the transistors Q1 and Q2. That is, the timing control circuit 10 in FIG. 1 generates the signal CLK for controlling the timing at which the first ADC2 and the second ADC3 perform the AD conversion operation and the timing at which the auto-zero operation is performed based on the gate leakage current of the transistors Q1 and Q2. In this specification, the period of the signal CLK is called the interleave period. The regulator 1 according to this embodiment can optimize the interleave period of the first ADC2 and the second ADC based on the gate leakage current of the transistors Q1 and Q2 in the comparator 6.

[0045] Fig. 6 is a block diagram showing the internal configuration of the timing control circuit 10 of Fig. 1. The timing control circuit 10 of Fig. 6 includes a first gate leakage detection circuit 11, a second gate leakage detection circuit 12, switches SW4 and SW5, a capacitor C3, a first comparator 13, a second comparator 14, an SR flip-flop (hereinafter, SR-F / F) 15, a D flip-flop (DF / F) 16, and an inverter IV3.

[0046] The first gate leakage detection circuit 11 has a PMOS transistor Q3. The drain, source, and backgate of this transistor Q3 are short-circuited and connected to the power supply voltage node. The leakage current passing through the gate of the transistor Q3 is a current from the drain, source, or backgate. By shorting the drain, source, and backgate of the transistor Q3 and connecting it to the power supply voltage node, the current flowing from the power supply voltage node through the drain, source, and backgate of the transistor Q3 to the gate becomes the gate leakage current.

[0047] The second gate leakage detection circuit 12 has an NMOS transistor Q4. The drain, source, and backgate of this transistor Q4 are short-circuited and connected to the ground node. A leakage current from the gate of the transistor Q4 passes through the drain, source, or backgate. By shorting the drain, source, and backgate of the transistor Q4 and connecting it to the ground node, a current flowing from the gate of the transistor Q4 through the drain, source, and backgate to the ground node becomes a gate leakage current.

[0048] The transistor Q3 in the first gate leakage detection circuit 11 and the transistor Q4 in the second gate leakage detection circuit 12 have the same characteristics as the transistors Q1, Q2 in the first ADC2 and the second ADC3. Here, the same characteristics means, for example, at least one of the cases where the thickness of the gate oxide film of each transistor is equal and the impurity concentration profile of each transistor is equal. When the gate oxide films of the two transistors are equal and / or the impurity concentration profiles of the two transistors are equal, the threshold voltages of the two transistors are approximately equal and the gate leakage currents of the two transistors are also approximately equal. Therefore, by making the transistors Q3, Q4 in the first gate leakage detection circuit 11 and the second gate leakage detection circuit 12 have the same characteristics as the transistors Q1, Q2 in the first ADC2 and the second ADC3, a gate leakage current equivalent to the gate leakage current of the transistors Q1, Q2 in the first ADC2 and the second ADC3 can be made to flow in the first gate leakage detection circuit 11 and the second gate leakage detection circuit 12.

[0049] The switch SW4 is connected between the gate of the transistor Q3 and one end of the capacitor C3. When the output signal QSR of the SR-F / F15 is at a low level, the switch SW4 is turned on to connect the gate of the transistor Q3 to one end of the capacitor C3. The switch SW5 is connected between the gate of the transistor Q4 and one end of the capacitor C3. When the output signal QSR of the SR-F / F15 is at a high level, the switch SW5 is turned on to connect the gate of the transistor Q4 to one end of the capacitor C3.

[0050] One end of the capacitor C3 is connected to one end of the switches SW4 and SW5, the positive input node of the first comparator 13, and the negative input node of the second comparator 14. The other end of the capacitor C3 is connected to the ground node. When the switch SW4 is on, the capacitor C3 accumulates a charge corresponding to the gate leakage current detected by the first gate leakage detection circuit 11. When the switch SW5 is on, the capacitor C3 passes a gate leakage current corresponding to the accumulated charge from the gate of the second gate leakage detection circuit 12 to the ground node.

[0051] The positive input node of the first comparator 13 is connected to one end of the capacitor C3, and the negative input node is set to a first reference voltage REF1. The output of the first comparator 13 becomes high level when a voltage according to the charge stored in the capacitor C3 (the voltage between the two electrodes of the capacitor C3) is equal to or higher than the first reference voltage REF1.

[0052] The positive input node of the second comparator 14 is set to the second reference voltage REF2, and the negative input node is connected to one end of the capacitor C3. The output of the second comparator 14 becomes high level when the voltage according to the charge stored in the capacitor C3 is equal to or lower than the second reference voltage REF2.

[0053] The SR-F / F 15 is in a set state when the output of the first comparator 13 is at a high level, and its output signal QSR is at a high level. Also, the SR-F / F 15 is in a reset state when the output of the second comparator 14 is at a high level, and its output signal QSR is at a low level.

[0054] The DF / F16 inverts the output signal CLK when the output signal QSR of the SR-F / F15 transitions from low to high. The output signal CLK of the DF / F16 is input to the D input node of the DF / F16 via the inverter IV3. This causes the DF / F16 to generate a signal CLK that is the output signal QSR of the SR-F / F15 divided by two. The output signal CLK of the DF / F16 is used to switch the operation of the first ADC2 and the second ADC3. In this way, the DF / F16 and the inverter IV3 form a clock generator.

[0055] 7 is a signal waveform diagram of each part in the timing control circuit 10 of FIG. 6. Hereinafter, the operation of the timing control circuit 10 of FIG. 6 will be described with reference to FIG. 7. Before time t1, the signal QSR is at a low level, the switch SW4 is on, and the switch SW5 is off. As a result, the gate leakage current flowing from the power supply voltage node through the drain, source, or backgate of the transistor Q3 to the gate flows to the capacitor C3 via the switch SW4. Therefore, charge is stored in the capacitor C3, and the voltage between both electrodes of the capacitor C3 increases linearly.

[0056] At time t1, the voltage between both electrodes of capacitor C3 becomes equal to or higher than the first reference voltage REF1, the output of first comparator 13 becomes high level, SR-F / F15 is set, and its output signal QSR transitions from low level to high level. As a result, switch SW4 turns off and switch SW5 turns on, and the charge stored in capacitor C3 is discharged through switch SW5. This discharge current is a gate leakage current that flows from the gate of transistor Q4 through the drain, source, or backgate to the ground node.

[0057] Between times t1 and t2, the charge stored in the capacitor C3 is discharged by the gate leakage current of the transistor Q4, and the voltage between the electrodes of the capacitor C3 decreases linearly. At time t2, the voltage between the electrodes of the capacitor C3 becomes equal to or lower than the second reference voltage REF2, and the output of the second comparator 14 becomes high level. This causes the SR-F / F 15 to enter a reset state, and its output signal QSR transitions to low level. When the signal QSR becomes low level, the switch SW4 is turned on, and the switch SW5 is turned on. Therefore, the gate leakage current from the first gate leakage detection circuit 11 flows to the capacitor C3, and the capacitor C3 accumulates charge again.

[0058] After that, at time t3, the voltage between both electrodes of the capacitor C3 becomes equal to or higher than the first reference voltage REF1 again, and the operation from time t1 onwards is repeated. As shown in Fig. 7, the voltage between both electrodes of the capacitor C3 becomes sawtooth wave (SAW) shaped.

[0059] The output signal QSR of the SR-F / F15 is at a high level between times t1 and t2, and at a low level between times t2 and t3. That is, the period of the signal QSR is from time t1 to t3. The DF / F16 and the inverter IV3 generate a signal CLK by dividing the signal QSR by two. The signal CLK is at a low level before time t1, at a high level between times t1 and t3, and at a low level between times t3 and t5. As shown in FIG. 3, while the signal CLK is at a low level, for example, the first ADC2 performs an AD conversion operation and the second ADC3 performs an auto-zero operation, and while the signal CLK is at a high level, for example, the first ADC2 performs an auto-zero operation and the second ADC3 performs an AD conversion operation.

[0060] In this way, in the first embodiment, the gate leakage currents of the transistors Q1, Q2 in the first ADC2 and the second ADC3 are detected by the first gate leakage detection circuit 11 and the second gate leakage detection circuit 12, and the period of the signal CLK that switches the operation of the first ADC2 and the second ADC3 is determined according to the gate leakage current. As a result, when the gate leakage current is large, the period (interleave period) of the signal CLK is shortened to increase the frequency of the auto-zero operation, while when the gate leakage current is small, the interleave period is lengthened, so that the frequency of switching between the AD conversion operation and the auto-zero operation can be reduced and the power consumption of the first ADC2 and the second ADC3 can be reduced.

[0061] Second Embodiment Fluctuations in the threshold of the comparator 6 in the first ADC 2 and the second ADC 3 are not necessarily caused by gate leakage currents of the transistors Q1 and Q2 that constitute the comparator 6. Channel leakage currents of the transistors Q1 and Q2 that constitute the comparator 6 can also be a factor that causes the threshold of the comparator 6 to fluctuate.

[0062] Therefore, in the second embodiment, the period of the signal CLK that switches between the operations of the first ADC 2 and the second ADC 3 is controlled in accordance with the channel leakage current of the transistors Q1 and Q2 that configure the comparator 6.

[0063] The regulator 1 according to the second embodiment has a block configuration similar to that of Fig. 1. The internal configuration of a timing control circuit 10a in the regulator 1 is different from that of Fig. 6.

[0064] Fig. 8 is a circuit diagram showing the internal configuration of a timing control circuit 10a according to the second embodiment. In Fig. 8, components common to Fig. 6 are given the same reference numerals, and the following description will focus on the differences.

[0065] The timing control circuit 10a in FIG. 8 includes a first channel leakage detection circuit 17, a second channel leakage detection circuit 18, switches SW4 and SW5, a capacitor C3, a first comparator 13, a second comparator 14, an SR-F / F 15, a DF / F 16, and an inverter IV3.

[0066] The internal configurations of the first channel leak detection circuit 17 and the second channel leak detection circuit 18 are different from those of the first gate leak detection circuit 11 and the second gate leak detection circuit 12 in FIG.

[0067] The first channel leakage detection circuit 17 in Fig. 8 has a PMOS transistor Q5. The gate, source, and backgate of this transistor Q5 are short-circuited and connected to the power supply voltage node. The leakage current passing through the drain of the transistor Q5 is a current from the gate, source, and backgate. By shorting the gate, source, and backgate of the transistor Q5 and connecting it to the power supply voltage node, the current flowing from the power supply voltage node through the gate, source, and backgate of the transistor Q5 to the drain becomes a channel leakage current.

[0068] The second channel leakage detection circuit 18 has an NMOS transistor Q6. The gate, source, and backgate of this transistor Q6 are short-circuited and connected to the ground node. By shorting the gate, source, and backgate of the transistor Q6 and connecting it to the ground node, the current flowing from the drain of the transistor Q6 through the gate, source, and backgate to the ground node becomes a channel leakage current.

[0069] The transistor Q5 in the first channel leakage detection circuit 17 and the transistor Q6 in the second channel leakage detection circuit 18 have the same characteristics as the transistors Q1, Q2 in the first ADC2 and the second ADC3, and the channel leakage currents detected by the first channel leakage detection circuit 17 and the second channel leakage detection circuit 18 are approximately the same as the channel leakage currents of the transistors Q1, Q2 in the first ADC2 and the second ADC3.

[0070] Each part in the timing control circuit 10a in Fig. 8 is represented by a signal waveform similar to that in Fig. 7. When the output signal QSR of the SR-F / F 15 is at a low level, the switch SW4 is turned on, and the channel leakage current from the first channel leakage detection circuit 17 passes through the switch SW4 to accumulate charge in the capacitor C3. When the voltage between the electrodes of the capacitor C3 becomes equal to or higher than the first reference voltage REF1, the output of the first comparator 13 becomes high level, and the output signal QSR of the SR-F / F 15 transitions to a high level. This turns off the switch SW4 and turns on the switch SW5, and the accumulated charge in the capacitor C3 is discharged according to the channel leakage current flowing through the second channel leakage detection circuit 18.

[0071] The capacitor C3 is charged and discharged according to the channel leakage current flowing through the first channel leakage detection circuit 17 and the second channel leakage detection circuit 18, and the SR-F / F 15 switches the logic of the output signal QSR according to the charging and discharging speed of the capacitor C3. The DF / F 16 generates a signal CLK that is half the frequency of the signal QSR. Depending on whether the signal CLK is at high level or low level, the operation of the first ADC2 and the second ADC3 is alternately switched.

[0072] In this way, the timing control circuit 10a according to the second embodiment controls the period of the signal CLK in accordance with the channel leakage currents of the transistors Q1, Q2 in the first ADC2 and the second ADC3, and therefore can optimize the interleaving period of the first ADC2 and the second ADC3.

[0073] (Third embodiment) A gate leakage current and a channel leakage current may flow in the transistors Q1 and Q2 in the first ADC 2 and the second ADC 3, and which one is dominant may vary depending on the manufacturing process and manufacturing variations. Therefore, it is also possible to control the period of the signal CLK by taking into account both the gate leakage current and the channel leakage current.

[0074] The regulator 1 according to the third embodiment has a block configuration similar to that of Fig. 1. The internal configuration of a timing control circuit 10b in the regulator 1 is different from that of Fig. 6.

[0075] Fig. 9 is a circuit diagram showing the internal configuration of a timing control circuit 10b according to the third embodiment. In Fig. 9, components common to Fig. 6 and Fig. 8 are given the same reference numerals, and the following description will focus on the differences.

[0076] The timing control circuit 10b in FIG. 9 includes the first gate leakage detection circuit 11 and the second gate leakage detection circuit 12 shown in FIG. 6, the first channel leakage detection circuit 17 and the second channel leakage detection circuit 18 shown in FIG. 8, switches SW4 and SW5, a capacitor C3, a first comparator 13, a second comparator 14, an SR-F / F 15, a DF / F 16, and an inverter IV3.

[0077] The gate in the first gate leakage detection circuit 11 and the drain in the first channel leakage detection circuit 17 are both connected to one end of a switch SW4. The gate in the second gate leakage detection circuit 12 and the drain in the second channel leakage detection circuit 18 are both connected to the other end of a switch SW5.

[0078] When the output signal QSR of the SR-F / F 15 is at a low level, the switch SW4 is turned on, and both the gate leakage current flowing in the first gate leakage detection circuit 11 and the channel leakage current in the first channel leakage detection circuit 17 flow through the switch SW4 to the capacitor C3, and charge is accumulated in the capacitor C3. When the voltage between the electrodes of the capacitor C3 becomes equal to or higher than the first reference voltage REF1, the output signal QSR of the SR-F / F 15 transitions to a high level. This turns off the switch SW4 and turns on the switch SW5. Thus, the charge accumulated in the capacitor C3 is discharged according to the gate leakage current flowing in the second gate leakage detection circuit 12 and the channel leakage current flowing in the second channel leakage detection circuit 18. When the voltage between the electrodes of the capacitor C3 becomes equal to or lower than the second reference voltage REF2, the output signal QSR of the SR-F / F 15 transitions to a low level.

[0079] As described above, in the third embodiment, the gate leakage currents and channel leakage currents of the transistors Q1, Q2 in the first ADC2 and the second ADC3 are detected by the first gate leakage detection circuit 11, the second gate leakage detection circuit 12, the first channel leakage detection circuit 17, and the second channel leakage detection circuit 18, and the period of the signal CLK is controlled according to the detected gate leakage currents and channel leakage currents. This makes it possible to optimize the interleaving period of the first ADC2 and the second ADC3.

[0080] The regulator 1 according to the first to third embodiments described above has been described as an example in which two ADCs (the first ADC2 and the second ADC) are alternately switched to perform AD conversion operations in sequence, and while one ADC is performing an AD conversion operation, the other performs an auto-zero operation. However, it is also possible to use three or more ADCs to perform AD conversion operations in sequence and to perform auto-zero operations in sequence.

[0081] The present technology can be configured as follows. (1) a plurality of analog-to-digital converters which output digital signals corresponding to the output voltages at different times in sequence by comparing the output voltages with threshold voltages; an output control circuit that controls the output voltage based on the digital signal; a timing control circuit that controls a timing at which each of the plurality of analog-to-digital converters performs an analog-to-digital conversion operation to convert the output voltage into the digital signal and a timing at which the threshold voltage is adjusted, based on at least one of a gate leakage current and a channel leakage current of a transistor in the plurality of analog-to-digital converters. (2) The regulator of (1), wherein the timing control circuit adjusts the threshold voltages of the analog-to-digital converters other than the one of the plurality of analog-to-digital converters during a period in which the one of the plurality of analog-to-digital converters is performing the analog-to-digital conversion operation. (3) The regulator described in (1) or (2), wherein the timing control circuit has transistors with the same characteristics as transistors in the plurality of analog-to-digital converters, and controls the timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and the timing at which the threshold voltage is adjusted based on at least one of a gate leakage current and a channel leakage current of the transistors with the same characteristics. (4) The regulator according to (3), wherein the transistors having the same characteristics in the timing control circuit have a gate oxide film having the same thickness as a gate oxide film of the transistors in the plurality of analog-to-digital converters. (5) The regulator according to (3) or (4), wherein the transistors of the same characteristics in the timing control circuit have an impurity concentration profile that is the same as a profile of an impurity concentration of transistors in the plurality of analog-to-digital converters. (6) The regulator according to any one of (3) to (5), wherein the timing control circuit adjusts the threshold voltage more frequently as at least one of a gate leakage current and a channel leakage current of the transistor having the same characteristics increases. (7) The timing control circuit comprises: a capacitor that stores a charge according to a gate current in a state where the drain, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage corresponding to the charge stored in the capacitor with a reference voltage; and a clock generator that generates a clock signal that controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted based on a comparison result of the comparator. (8) The timing control circuit comprises: a capacitor that stores a charge according to a drain current in a state where the gate, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage corresponding to the charge stored in the capacitor with a reference voltage; and a clock generator that generates a clock signal that controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted based on a comparison result of the comparator. (9) The timing control circuit comprises: the first transistor and the second transistor having the same characteristics; a capacitor for storing a charge according to a gate current in a state in which the drain, source, and backgate of the first transistor are short-circuited and connected to a reference voltage node, and a drain current in a state in which the gate, source, and backgate of the second transistor are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage corresponding to the charge stored in the capacitor with a reference voltage; and a clock generator that generates a clock signal that controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted based on a comparison result of the comparator. (10) The plurality of analog-to-digital converters includes a first analog-to-digital converter and a second analog-to-digital converter; The timing control circuit includes: adjusting the threshold voltage of the second analog-to-digital converter while the first analog-to-digital converter is performing the analog-to-digital conversion operation; The regulator of any one of (1) to (6), further comprising: a first analog-to-digital converter that adjusts the threshold voltage while the second analog-to-digital converter is performing the analog-to-digital conversion operation. (11) The timing control circuit generates a clock signal having a period corresponding to at least one of a gate leakage current and a channel leakage current of a transistor in the first analog-to-digital converter and the second analog-to-digital converter; When the clock signal is at a first logic level, the first analog-to-digital converter performs the analog-to-digital conversion operation and the second analog-to-digital converter adjusts the threshold voltage; The regulator of claim 10, wherein when the clock signal is at a second logic level, the second analog-to-digital converter performs the analog-to-digital conversion operation and the first analog-to-digital converter adjusts the threshold voltage. (12) The regulator described in (11), wherein the timing control circuit shortens the period of the clock signal as at least one of a gate leakage current and a channel leakage current of a transistor in the first analog-to-digital converter and the second analog-to-digital converter increases. (13) The regulator described in (11) or (12), wherein the timing control circuit has transistors with the same characteristics as transistors in the first analog-digital converter and the second analog-digital converter, and controls the timing at which the transistors in the first analog-digital converter and the second analog-digital converter perform the analog-digital conversion operation and the timing at which the threshold voltage is adjusted based on at least one of a gate leakage current and a channel leakage current of the transistors with the same characteristics. (14) The timing control circuit comprises: a capacitor that stores a charge according to a gate current in a state where the drain, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage according to the charge stored in the capacitor with a reference voltage; The regulator according to (13), further comprising: a setting for a period of the clock signal in response to a comparison result of the comparator. (15) The timing control circuit comprises: the first transistor and the second transistor having the same characteristics; a first current circuit in which the drain, source, and back gate of the first transistor are short-circuited and connected to a first voltage node; a second current circuit in which the drain, source, and backgate of the second transistor are short-circuited and connected to a second voltage node; a first switch that switches whether or not a charge corresponding to a gate current of the first transistor in the first current circuit is to be stored in the capacitor; a second switch that switches whether or not a current corresponding to the charge stored in the capacitor is passed to the gate of the second transistor in the second current circuit; The regulator according to claim 14, wherein the comparator flows a current corresponding to the stored charge of the capacitor to the gate of the second transistor in the second current circuit by switching the first switch and the second switch when a voltage corresponding to the stored charge of the capacitor is higher than a first reference voltage, and stores a charge corresponding to the gate current of the first transistor in the first current circuit in the capacitor by switching the first switch and the second switch when the voltage corresponding to the stored charge of the capacitor is equal to or lower than a second reference voltage having a voltage level lower than the first reference voltage. (16) A capacitor that stores a charge according to a drain current in a state where the gate, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage according to the charge stored in the capacitor with a reference voltage; The regulator according to (13), further comprising: a setting for a period of the clock signal in response to a comparison result of the comparator. (17) The timing control circuit comprises: the first transistor and the second transistor having the same characteristics; a first current circuit in which the gate, the source and the back gate of the first transistor are shorted and connected to a first voltage node; a second current circuit in which the gate, the source, and the back gate of the second transistor are shorted and connected to a second voltage node; a first switch that switches whether or not a charge corresponding to a drain current of the first transistor in the first current circuit is to be stored in the capacitor; a second switch that switches whether or not a discharge current corresponding to the accumulated charge of the capacitor is to be passed to the second voltage node via the drain of the second transistor in the second current circuit; The regulator according to (16), wherein the comparator flows a discharge current corresponding to the stored charge in the capacitor to the drain of the second transistor in the second current circuit by switching the first switch and the second switch when a voltage corresponding to the stored charge in the capacitor is higher than a first reference voltage, and stores charge corresponding to the drain current of the first transistor in the first current circuit in the capacitor by switching the first switch and the second switch when the voltage corresponding to the stored charge in the capacitor is equal to or lower than a second reference voltage having a voltage level lower than the first reference voltage. (18) The timing control circuit comprises: a capacitor for storing a charge according to a gate current in a state in which the drain, source, and back gate of the transistor having the same characteristics are shorted and connected to a reference voltage node, and a drain current in a state in which the gate, source, and back gate of the transistor having the same characteristics are shorted and connected to a reference voltage node; a comparator for comparing a voltage according to the charge stored in the capacitor with a reference voltage; The regulator according to (13), further comprising: a setting for a period of the clock signal in response to a comparison result of the comparator. (19) The timing control circuit comprises: the first transistor and the second transistor having the same characteristics; a first current circuit in which the drain, source, and back gate of the first transistor are short-circuited and connected to a first voltage node; a second current circuit in which the drain, source, and backgate of the second transistor are short-circuited and connected to a second voltage node; the third transistor and the fourth transistor having the same characteristics; a third current circuit in which the gate, the source and the back gate of the third transistor are short-circuited and connected to the first voltage node; a fourth current circuit in which the gate, the source, and the back gate of the fourth transistor are short-circuited and connected to the second voltage node; a first switch that switches whether or not to store a charge in the capacitor according to a gate current of the first transistor in the first current circuit and a drain current of the third transistor in the third current circuit; a second switch that switches whether or not a current corresponding to the charge stored in the capacitor is passed to a gate of the second transistor in the second current circuit and a drain of the fourth transistor in the fourth current circuit; The regulator according to (18), wherein when a voltage corresponding to the accumulated charge of the capacitor is higher than a first reference voltage, the comparator switches the first switch and the second switch to pass a current corresponding to the accumulated charge of the capacitor to the gate of the second transistor in the second current circuit and the drain of the fourth transistor in the fourth current circuit, and when a voltage corresponding to the accumulated charge of the capacitor is equal to or lower than a second reference voltage having a voltage level lower than the first reference voltage, the comparator switches the first switch and the second switch to store charge corresponding to the gate current of the first transistor in the first current circuit and the drain current of the third transistor in the third current circuit in the capacitor.

[0082] The aspects of the present disclosure are not limited to the above-mentioned individual embodiments, but include various modifications that may be conceived by a person skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0083] 1, 101 regulator, 2 first ADC, 3 second ADC, 4 impedance variable circuit, 4a control circuit, 4b impedance adjustment circuit, 5 oscillator, 6 comparator, 7 load circuit, 11 first gate leakage detection circuit, 12 second gate leakage detection circuit, 13 first comparator, 14 second comparator, 15 SR-F / F, 16 DF / F, 17 first channel leakage detection circuit, 18 second channel leakage detection circuit

Claims

1. a plurality of analog-to-digital converters which output digital signals corresponding to the output voltages at different timings in sequence by comparing the output voltages with threshold voltages; an output control circuit that controls the output voltage based on the digital signal; a timing control circuit that controls a timing at which each of the plurality of analog-to-digital converters performs an analog-to-digital conversion operation to convert the output voltage into the digital signal, and a timing at which the threshold voltage is adjusted, based on at least one of a gate leakage current and a channel leakage current of a transistor in the plurality of analog-to-digital converters.

2. 2. The regulator of claim 1, wherein the timing control circuit adjusts the threshold voltages of the analog-to-digital converters other than the one of the plurality of analog-to-digital converters during a period in which the one of the plurality of analog-to-digital converters is performing the analog-to-digital conversion operation.

3. 2. The regulator according to claim 1, wherein the timing control circuit has transistors with the same characteristics as transistors in the plurality of analog-to-digital converters, and controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted based on at least one of a gate leakage current and a channel leakage current of the transistors with the same characteristics.

4. 4. The regulator according to claim 3, wherein the transistors of the same characteristics in the timing control circuit have a gate oxide film of the same thickness as a gate oxide film of the transistors in the plurality of analog-to-digital converters.

5. 4. The regulator of claim 3, wherein the transistors of the same characteristics in the timing control circuit have an impurity concentration profile that is the same as a profile of the impurity concentration of transistors in the plurality of analog-to-digital converters.

6. 4. The regulator according to claim 3, wherein the timing control circuit adjusts the threshold voltage more frequently as at least one of a gate leakage current and a channel leakage current of the transistor having the same characteristics increases.

7. The timing control circuit includes: a capacitor that stores a charge according to a gate current in a state where the drain, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage corresponding to the charge stored in the capacitor with a reference voltage; 4. The regulator according to claim 3, further comprising: a clock generator that generates a clock signal that controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted, based on a comparison result of the comparator.

8. The timing control circuit includes: a capacitor that stores a charge according to a drain current in a state where the gate, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage corresponding to the charge stored in the capacitor with a reference voltage; 4. The regulator according to claim 3, further comprising: a clock generator that generates a clock signal that controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted based on a comparison result of the comparator.

9. The timing control circuit includes: the first transistor and the second transistor having the same characteristics; a capacitor for storing a charge according to a gate current in a state in which the drain, source, and backgate of the first transistor are short-circuited and connected to a reference voltage node, and a drain current in a state in which the gate, source, and backgate of the second transistor are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage corresponding to the charge stored in the capacitor with a reference voltage; 4. The regulator according to claim 3, further comprising: a clock generator that generates a clock signal that controls a timing at which each of the plurality of analog-to-digital converters performs the analog-to-digital conversion operation and a timing at which the threshold voltage is adjusted based on a comparison result of the comparator.

10. the plurality of analog-to-digital converters includes a first analog-to-digital converter and a second analog-to-digital converter; The timing control circuit includes: adjusting the threshold voltage in the second analog-to-digital converter while the first analog-to-digital converter is performing the analog-to-digital conversion operation; 2. The regulator of claim 1, wherein the first analog-to-digital converter adjusts the threshold voltage while the second analog-to-digital converter is performing the analog-to-digital conversion operation.

11. the timing control circuit generates a clock signal having a period corresponding to at least one of a gate leakage current and a channel leakage current of a transistor in the first analog-to-digital converter and the second analog-to-digital converter; when the clock signal is at a first logic level, the first analog-to-digital converter performs the analog-to-digital conversion operation and the second analog-to-digital converter adjusts the threshold voltage; 11. The regulator of claim 10, wherein the second analog-to-digital converter performs the analog-to-digital conversion operation and the first analog-to-digital converter adjusts the threshold voltage when the clock signal is at a second logic level.

12. 12. The regulator of claim 11, wherein the timing control circuit shortens the period of the clock signal as at least one of a gate leakage current and a channel leakage current of a transistor in the first analog-to-digital converter and the second analog-to-digital converter increases.

13. 12. The regulator of claim 11, wherein the timing control circuit has transistors with the same characteristics as transistors in the first analog-to-digital converter and the second analog-to-digital converter, and controls timings at which transistors in the first analog-to-digital converter and the second analog-to-digital converter perform the analog-to-digital conversion operation and timings at which the threshold voltages are adjusted, based on at least one of a gate leakage current and a channel leakage current of the transistors with the same characteristics.

14. The timing control circuit includes: a capacitor that stores a charge according to a gate current in a state where the drain, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage according to the charge stored in the capacitor with a reference voltage; The regulator according to claim 13 , further comprising: a period of the clock signal set in response to a comparison result of the comparator.

15. The timing control circuit includes: the first transistor and the second transistor having the same characteristics; a first current circuit in which the drain, the source and the back gate of the first transistor are short-circuited and connected to a first voltage node; a second current circuit in which the drain, the source and the back gate of the second transistor are short-circuited and connected to a second voltage node; a first switch that switches whether or not a charge corresponding to a gate current of the first transistor in the first current circuit is to be stored in the capacitor; a second switch that switches whether or not a current corresponding to the charge stored in the capacitor is passed to a gate of the second transistor in the second current circuit, 15. The regulator according to claim 14, wherein the comparator causes a current corresponding to the stored charge of the capacitor to flow to the gate of the second transistor in the second current circuit by switching between the first switch and the second switch when a voltage corresponding to the stored charge of the capacitor is higher than a first reference voltage, and stores a charge corresponding to the gate current of the first transistor in the first current circuit in the capacitor by switching between the first switch and the second switch when the voltage corresponding to the stored charge of the capacitor is equal to or lower than a second reference voltage having a voltage level lower than the first reference voltage.

16. a capacitor that stores a charge according to a drain current in a state where the gate, source, and back gate of the transistor having the same characteristics are short-circuited and connected to a reference voltage node; a comparator for comparing a voltage according to the charge stored in the capacitor with a reference voltage; The regulator according to claim 13 , further comprising: a period of the clock signal set in response to a comparison result of the comparator.

17. The timing control circuit includes: the first transistor and the second transistor having the same characteristics; a first current circuit in which the gate, the source and the back gate of the first transistor are short-circuited and connected to a first voltage node; a second current circuit in which the gate, the source and the back gate of the second transistor are short-circuited and connected to a second voltage node; a first switch that switches whether or not a charge corresponding to a drain current of the first transistor in the first current circuit is to be stored in the capacitor; a second switch that switches whether or not a discharge current corresponding to the accumulated charge of the capacitor is to be passed to the second voltage node via the drain of the second transistor in the second current circuit; 17. The regulator according to claim 16, wherein the comparator switches between the first switch and the second switch to cause a discharge current corresponding to the stored charge in the capacitor to flow to the drain of the second transistor in the second current circuit when a voltage corresponding to the stored charge in the capacitor is higher than a first reference voltage, and switches between the first switch and the second switch to cause a charge corresponding to the drain current of the first transistor in the first current circuit to be stored in the capacitor when the voltage corresponding to the stored charge in the capacitor is equal to or lower than a second reference voltage having a voltage level lower than the first reference voltage.

18. The timing control circuit includes: a capacitor for storing a charge according to a gate current in a state in which the drain, source, and back gate of the transistor having the same characteristics are shorted and connected to a reference voltage node, and a drain current in a state in which the gate, source, and back gate of the transistor having the same characteristics are shorted and connected to a reference voltage node; a comparator for comparing a voltage according to the charge stored in the capacitor with a reference voltage; The regulator according to claim 13 , further comprising: a period of the clock signal set in response to a comparison result of the comparator.

19. The timing control circuit includes: the first transistor and the second transistor having the same characteristics; a first current circuit in which the drain, the source and the back gate of the first transistor are short-circuited and connected to a first voltage node; a second current circuit in which the drain, the source and the back gate of the second transistor are short-circuited and connected to a second voltage node; a third transistor and a fourth transistor having the same characteristics; a third current circuit in which the gate, the source and the back gate of the third transistor are short-circuited and connected to the first voltage node; a fourth current circuit in which the gate, the source, and the back gate of the fourth transistor are short-circuited and connected to the second voltage node; a first switch that switches whether or not to store a charge in the capacitor according to a gate current of the first transistor in the first current circuit and a drain current of the third transistor in the third current circuit; a second switch that switches whether or not a current corresponding to the charge stored in the capacitor is passed to a gate of the second transistor in the second current circuit and a drain of the fourth transistor in the fourth current circuit, 20. The regulator according to claim 18, wherein the comparator causes a current corresponding to the stored charge of the capacitor to flow to the gate of the second transistor in the second current circuit and the drain of the fourth transistor in the fourth current circuit by switching between the first switch and the second switch when a voltage corresponding to the stored charge of the capacitor is higher than a first reference voltage, and stores a charge corresponding to a gate current of the first transistor in the first current circuit and a drain current of the third transistor in the third current circuit in the capacitor by switching between the first switch and the second switch when a voltage corresponding to the stored charge of the capacitor is equal to or lower than a second reference voltage having a voltage level lower than the first reference voltage.

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