Manufacturing method of semiconductor package structure

Abstract

To provide a semiconductor package structure, in which the sealing property of a package structure can be improved and the product quality can be improved.SOLUTION: A semiconductor package structure and a manufacturing method for the same are provided. The semiconductor package structure includes a mount layer 1, a first element layer 2, a first insulating layer 3, a conductive copper column 4, and a second element layer 5. The mount layer 1 covers the first element layer 2. The first element layer 2, the first insulating layer 3, and the second element layer 5 are stacked in order. The conductive copper column 4 penetrates the first insulating layer 3. The first element layer 2 and the second element layer 5 are electrically connected to each other through the conductive copper column 4. The first element layer 2 includes a first circuit layer 201, a groove 202, and an embedded element 203. The embedded element 203 is connected to the first circuit layer 201. The groove 202 is provided below the embedded element 203. The projections of the groove 202 and the embedded element 203 in a direction where the embedded element 203 is pasted overlap with each other partially or entirely.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor package structure and a manufacturing method thereof. [Background technology]

[0002] With the development of electronic technology, the performance requirements of electronic products are becoming higher and higher, and as a result, the circuits of electronic elements and circuit boards are becoming more and more complex, and there is a demand for electronic products to be smaller and thinner. Therefore, the integration, miniaturization, and multi-function of the circuits of electronic elements and circuit boards is an inevitable trend. By reducing the line width and pitch, the wiring density of the entire board can be greatly increased, but this leads to a series of problems such as a decrease in the bonding strength between the circuit and the substrate, and a sharp increase in short circuits between circuits due to the reduction in pitch. Embedded circuit boards have emerged as a solution to these problems.

[0003] In the prior art, when mounting an element on a substrate, the distance between the element pin and the substrate is very small, and the mounting material cannot be properly filled all the way to the bottom of the element, resulting in poor sealing between the element pins and poor electrical insulation performance, which affects the service life of the element. Therefore, a new semiconductor package structure is in high demand. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure aims to solve at least to some extent one of the technical problems existing in the prior art. [Means for solving the problem]

[0005] Therefore, an object of an embodiment of the present disclosure is to provide a semiconductor package structure that can improve the hermeticity of an element.

[0006] In order to achieve the above technical object, the technical means adopted in the embodiment of the present disclosure includes a semiconductor package structure for connecting to an external functional circuit, the semiconductor package structure comprising a mounting layer, a first element layer, a first insulating layer, a conductive copper pillar, and a second element layer, the mounting layer covers the first element layer, the first element layer, the first insulating layer, and the second element layer are stacked in order, the conductive copper pillar penetrates the first insulating layer, the first element layer and the second element layer are electrically connected via the conductive copper pillar, the first element layer comprises a first circuit layer, a groove, and an embedded element, the embedded element is connected to the first circuit layer, the groove is provided below the embedded element, a projection of the embedded element partially or completely overlaps with the groove along the attachment direction of the embedded element, the second element layer comprises a second circuit layer, a first solder resist layer, and a solder ball, the first solder resist layer partially covers the second circuit layer, and the solder ball is for realizing an electrical connection between the second circuit layer and the external functional circuit.

[0007] In addition, according to the manufacturing method of the grooved semiconductor package structure of the above embodiment of the present disclosure, it can further have the following additional technical features.

[0008] Furthermore, in an embodiment of the present disclosure, the first element layer further includes a second solder resist layer partially covering the first circuit layer.

[0009] Furthermore, in an embodiment of the present disclosure, the first insulating layer comprises a PP material or an ABF material.

[0010] Furthermore, in the embodiments of the present disclosure, the number of the embedded elements includes one or more, and the number of the grooves includes one or more.

[0011] Further, in embodiments of the present disclosure, the embedded element includes an active element or a passive element.

[0012] Furthermore, in an embodiment of the present disclosure, the depth of the groove is equal to or greater than the thickness of the first circuit layer.

[0013] In another aspect, the present disclosure further provides a method for manufacturing a conductor package structure for manufacturing the semiconductor package structure according to any one of the above embodiments, the method including the steps of: preparing a temporary mounting plate including a first metal layer and a mounting plate that are stacked together; fabricating a first circuit layer using the first metal layer as a base material; pressing a first insulating layer onto the first circuit layer so as to cover the first circuit layer; fabricating a conductive copper column and a second circuit layer on the first insulating layer; removing the mounting plate and fabricating a groove on the first circuit layer; attaching an embedded element such that the projection of the embedded element and the groove along the attachment direction of the embedded element partially or completely overlap each other; soldering a solder ball to the second circuit layer and fabricating a first solder resist layer to partially cover the second circuit layer; and covering the first circuit layer, the embedded element, and the groove with a mounting material.

[0014] Furthermore, in an embodiment of the present disclosure, the step of manufacturing a first circuit layer using the first metal layer as a base material specifically includes the steps of applying a first photoresist layer to the first metal layer, subjecting the first photoresist layer to an exposure and development process to obtain a first circuit pattern, and subjecting the first circuit pattern to an etching process to obtain a first circuit layer.

[0015] Furthermore, in an embodiment of the present disclosure, the step of producing a conductive copper pillar and a second circuit layer in the first insulating layer specifically includes the steps of drilling a hole in the first insulating layer to form a copper-free hole that penetrates the first insulating layer and exposes the first circuit layer to the outside, performing hole-fill plating on the copper-free hole to form a conductive copper pillar and a second metal seed layer, applying a second photoresist layer to the second metal seed layer, subjecting the second photoresist layer to an exposure and development process to obtain a second circuit pattern, and subjecting the second circuit pattern to an etching process to obtain a second circuit layer.

[0016] Furthermore, in an embodiment of the present disclosure, the step of creating a groove in the first circuit layer specifically includes the steps of: applying a third photoresist layer to the underside of the first circuit layer, which is the surface of the first circuit layer facing the bonding surface of the first insulating layer; subjecting the third photoresist layer to an exposure and development process to obtain a third circuit pattern; and subjecting the third circuit pattern to an etching process to obtain the groove.

[0017] Further, in an embodiment of the present disclosure, the step of applying a first photoresist layer to the first metal layer specifically includes a step of applying the first photoresist layer to the first metal layer by film attachment or coating.

[0018] The present disclosure further provides an integrated circuit system including at least one semiconductor package structure according to any one of the above embodiments. Effect of the Invention

[0019] Advantages and beneficial effects of the present disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure.

[0020] In the package structure of the present disclosure, a groove is provided below the embedded element, so that during the mounting process of the embedded element, the mounting material can completely seep into the space below the pins of the embedded element, filling the space between the pins of the embedded element with the mounting material, and achieving a complete seal between the pins, thereby improving the hermeticity, achieving electrical insulation between the pins, and improving the service life of the entire package structure. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a schematic diagram of a semiconductor package structure in a specific embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic diagram of steps of a method for manufacturing a semiconductor package structure in a specific embodiment of the present disclosure. [Diagram 3] FIG. 3 is a schematic diagram of a structural change in a manufacturing procedure of a semiconductor package structure in a specific embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic diagram of a semiconductor package structure in a conventional process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings, and the principles and procedures of the semiconductor package structure in the embodiments of the present disclosure will be explained as follows.

[0023] First, the drawbacks of the conventional mounting process will be described with reference to the drawings.

[0024] Referring to FIG. 4, in the conventional process, when mounting an embedded element, the gap between the pin of the embedded element and the element body is very small, and the mounting material cannot enter under the embedded element normally, and the material cannot completely encase the embedded element. Therefore, the conventional process is likely to cause a gap to exist under the embedded element, resulting in poor sealing. Furthermore, there is a high possibility that water vapor, oxygen and other gases that can corrode the element will exist in the gap. If these gases exist in the gap for a long time, it will accelerate the deterioration of the element, shorten the service life of the element, and affect the product quality.

[0025] Based on the above shortcomings, referring to Fig. 1, the present disclosure provides a novel semiconductor package structure that can be connected to an external function circuit, where the external function circuit can be other semiconductor structures, other integrated circuits, active or passive elements, or circuits on a PCB. The semiconductor package structure may include a mounting layer 1, a first device layer 2, a first insulating layer 3, a conductive copper column 4, and a second device layer 5, where the mounting layer 1 may cover the first device layer 2, where the first device layer 2, the first insulating layer 3, and the second device layer 5 may be stacked in order, where the conductive copper column 4 may penetrate the first insulating layer 3, where the first device layer 2 and the second device layer 5 may be electrically connected through the conductive copper column 4, where the first device layer 2 may include a first circuit layer 201, a groove 202, and an embedded device 203, where the first circuit layer 201 may be a circuit layer connected to the embedded device 203, where the embedded device 203 may be connected to the first circuit layer 201 through a pin or a solder pad, and the groove 202 is a buried device. the groove 202 along the application direction of the embedded element 203 and the projection of the embedded element 203 may overlap partially or completely; the second element layer 5 may include a second circuit layer 501, a first solder resist layer 502 and solder balls 503; the second circuit layer 501 may be a circuit layer connected to the solder balls 503 and connected to the first circuit layer 201 via the conductive copper pillars 4; the first solder resist layer 502 may partially cover the second circuit layer 501 so that some positions of the second circuit layer 501 can be connected to the solder balls 503; and the solder balls 503 can realize electrical connection between the second circuit layer 501 and an external functional circuit.

[0026] Furthermore, in some embodiments of the present disclosure, the first element layer may further include a second solder resist layer, and the second solder resist layer may partially cover the first circuit layer. Partially covering may mean covering all other areas of the first circuit layer except for the area required for connection to the embedded element, or may mean covering a specific area in the first circuit layer, and the specific area may be an area required for corrosion prevention. The second solder resist layer can prevent a part of the area of ​​the first circuit layer from being oxidized or corroded when the embedded element is attached or structurally mounted.

[0027] Furthermore, in some embodiments of the present disclosure, the first insulating layer may include a PP material or an ABF material. Both the PP material and the ABF material have good insulating performance, good corrosion resistance, and are non-toxic, and can be applied to the insulating layer of a semiconductor. The first insulating layer may be an insulating layer formed of other conventional insulating materials or other insulating materials that will appear in the future, or an insulating layer formed by mixing PP, ABF, and other insulating layers. Specifically, the mixing may be a mixing of materials, or a physical compression of layers formed of different materials. For example, one sub-insulating layer may be formed of a PP material, another sub-insulating layer may be formed of an ABF material, and the two sub-insulating layers may be compressed to form a corresponding first insulating layer.

[0028] Furthermore, in some embodiments of the present disclosure, the embedded element may include one or more, the number of the grooves may include one or more, and the number of the embedded elements may correspond one-to-one to the number of the grooves. In one semiconductor structure, the number of embedded elements is usually not only one, but also the number of grooves may be provided in one-to-one correspondence therewith. The one-to-one corresponding grooves can fill the space under the pins of each embedded element with the mounting material, improve the hermeticity of the entire structure, reduce the damage caused to the embedded elements by static electricity and other impurities in the air, and improve the service life of the embedded elements.

[0029] Furthermore, in some embodiments of the present disclosure, the embedded elements may include active elements or passive elements, where active elements may be triodes, MOS transistors and other transistors, or may be chips or other small integrated circuits, and passive elements may be resistors, capacitors or other passive elements.

[0030] Furthermore, in some embodiments of the present disclosure, the depth of the groove may be equal to or greater than the thickness of the first circuit layer. The groove not only allows the packaging material to penetrate and cover and encapsulate the entire embedded device with the packaging material, but also allows electrical isolation of some areas of the first circuit layer. Thus, the depth of the groove may be equal to or greater than the thickness of the first circuit layer, allowing some areas of the first circuit layer to be electrically isolated.

[0031] Furthermore, in some embodiments of the present disclosure, the material of the solder ball may include at least one of gold, copper, or tin. The solder ball may be made of copper, tin, or gold, or may be made by mixing two or three of the above three materials. The above three materials have good conductive properties and are easily available, which can improve the practicality of the device. Gold has better corrosion resistance, but tin and copper are cheaper than gold, so the use of copper or tin can reduce the cost of materials.

[0032] Also, referring to FIG. 2 and corresponding to the structure of FIG. 1, an embodiment of the present disclosure further provides a manufacturing method for a semiconductor packaging structure for manufacturing a semiconductor packaging structure described in any one of the above embodiments, and the method may include the following steps S1, S2, S3, S4, S5, S6, S7, and S8.

[0033] In step S1, a temporary plate including a first metal layer and a mounting plate is prepared.

[0034] In some embodiments of the present disclosure, the temporary mounting plate may include a first metal layer and a mounting plate. The thickness of the first metal layer may be a thickness that matches the circuit layer fabrication, and the mounting plate may be a normal insulating mounting plate or a mounting plate formed by pressing different thin layers made of different materials. The first metal layer may be laminated with the mounting plate, and physical or chemical separation may be possible in a subsequent process. The physical separation may be mechanically torn or mechanically polished to separate. The chemical separation may be chemically etching the material of the mounting plate. If the mounting plate is formed by pressing multiple thin layers of different materials, various chemicals may be used to etch the corresponding materials to remove the mounting plate.

[0035] In step S2, a first circuit layer is fabricated using the first metal layer as a substrate.

[0036] In some embodiments of the present disclosure, the first metal layer can be a substrate for fabricating the first circuit layer, and the first metal layer can be made into a circuit layer capable of realizing functions and electrical signal transmission through processes such as exposure, development, and etching. The first circuit layer can be used to later attach embedded elements. Since different circuit layers may have different thicknesses, the first metal layer can be further processed to be thinner or thicker during the fabrication of the first circuit layer to meet the thickness requirements of the fabrication of the circuit layer.

[0037] In step S3, a first insulating layer is pressed onto the first circuit layer so as to cover the first circuit layer.

[0038] In some embodiments of the present disclosure, it is necessary to completely cover the first circuit layer with the first insulating layer when the first insulating layer is pressed onto the first circuit layer, so as to avoid any gaps occurring in the first circuit layer that would affect the hermeticity of the first circuit layer and further affect the functional realization and service life of the circuit layer.

[0039] In step S4, conductive copper pillars and a second circuit layer are fabricated on the first insulating layer.

[0040] In some embodiments of the present disclosure, it is necessary to fabricate a conductive copper pillar and a second circuit layer on the first insulating layer. The conductive copper pillar can realize the electrical connection or signal connection between the first circuit layer and the second circuit layer. The second circuit layer can be the circuit layer that is connected to the first circuit layer and the external functional circuit in the subsequent process, and the second circuit layer can be a functional circuit layer or a conductive circuit layer.

[0041] In step S5, the support plate is removed, and a groove is formed in the first circuit layer.

[0042] In some embodiments of the present disclosure, the support plate may be removed first, which may be removed by chemically corroding or physically tearing, and after the support plate is removed, a groove may be fabricated from the surface of the first circuit layer opposite to the surface covered with the first insulating layer, and a photoresist layer may be applied from the bottom surface of the first circuit layer, where the bottom surface may be the surface of the first circuit layer opposite to the pressing surface of the first insulating layer, and the groove is finally obtained by an exposure, development, and etching process, and the groove may be provided between different regions of the first circuit layer, and the groove may not only allow the packaging material to fill the space below the embedded device, but also realize electrical isolation of some regions of the first circuit layer.

[0043] In step S6, the embedded element is attached.

[0044] In some embodiments of the present disclosure, the embedded element may be applied such that the projection of the groove along the application direction of the embedded element partially or completely overlaps with the embedded element, and when the pin of the embedded element faces downward, the groove may be directly below the embedded element or diagonally below, partially overlapping with the vertical projection of the embedded element.

[0045] In step S7, solder balls are soldered to the second circuit layer, and a first solder resist layer is fabricated to partially cover the second circuit layer.

[0046] In some embodiments of the present disclosure, the solder balls may be soldered to the second circuit layer, and a solder resist layer may be fabricated, and two or more solder balls may be soldered. The location of the first solder resist layer may be another area of ​​the second circuit layer where the solder balls are not soldered. The first solder resist layer partially covers the second circuit layer and can improve the corrosion resistance of some areas of the second circuit layer without interfering with the connection between the solder balls and the external functional circuit.

[0047] In step S8, the first circuit layer, the embedded elements and the grooves are covered with a packaging material.

[0048] In some embodiments of the present disclosure, the first circuit layer, the embedded element, and the groove may be covered with a packaging material. The packaging material should completely cover and encase the first circuit layer and the embedded element. The groove is filled and covered with the packaging material. Since the groove and the embedded element overlap partially or completely in a direction perpendicular to the horizontal plane, when the packaging material is applied, the packaging material can seep through the groove to the embedded element and fill the gap between the pins below the embedded element and the circuit layer, thereby completely sealing the pins below the embedded element and preventing static electricity, moisture, etc. in the air from damaging the circuit layer or pins and affecting the service life of the element and the circuit layer.

[0049] Furthermore, the step of fabricating a first circuit layer using the first metal layer as a substrate specifically includes: Step S11 of applying a first photoresist layer to the first metal layer; Step S12: subjecting the first photoresist layer to an exposure and development process to obtain a first circuit pattern; The method may include the steps of: performing an etching process on the first circuit pattern to obtain a first circuit layer; and S13.

[0050] In some embodiments of the present disclosure, in the fabrication of the first circuit layer, the first metal layer may be first covered with a first photoresist layer, and the first photoresist layer may be exposed and developed to obtain a first circuit pattern. The first circuit pattern can protect the parts of the first metal layer that do not need to be etched and expose the parts that need to be etched, and then the parts that need to be etched are etched and removed by chemical etching, and then the etching solution and the remaining unexposed photoresist layer are removed by an alkaline solution, and finally the first circuit layer is obtained. In the chemical etching, the metal can be removed by using an acidic etching reagent, for example, an iron chloride reagent having acidity, and may be removed by using a sodium hydroxide solution as an alkaline solution.

[0051] Furthermore, the step of fabricating the conductive copper pillars and the second circuit layer on the first insulating layer specifically includes: Step S21: drilling holes in the first insulating layer to form copper-free holes penetrating the first insulating layer and exposing the first circuit layer to the outside; Step S22: performing hole filling plating on the non-copper hole to form a conductive copper pillar and a second metal seed layer; applying a second photoresist layer to the second metal seed layer (S23); Step S24: subjecting the second photoresist layer to an exposure and development process to obtain a second circuit pattern; and step S25 of subjecting the second circuit pattern to an etching process to obtain a second circuit layer.

[0052] In some embodiments of the present disclosure, the first insulating layer may be drilled by laser or other methods to form copper-free holes, and the number of copper-free holes may be one or more, and the specific number may be determined according to circuit requirements. The copper-free holes may penetrate the first insulating layer and be opened to the first circuit layer to be exposed to the outside. Then, the copper-free holes are filled with plating, and in the filling plating process, copper foil may be first deposited on the sidewall of the copper-free holes to gradually fill the entire copper-free holes, and then electroplating is continued, thereby forming a second metal seed layer on the first insulating layer that can be used for fabricating a circuit layer. Then, a second photoresist material is applied to the second metal seed layer, which can completely cover the second metal seed layer. Then, the second photoresist material is exposed and developed to obtain a second circuit pattern, and the second circuit pattern can block a part of the metal seed layer that does not need to be etched, avoiding corrosion by the etching solution, and can expose a part of the metal seed layer that needs to be etched, which facilitates the subsequent etching process. Finally, the second circuit pattern was etched with an acidic etchant to remove some of the metal seed layer, followed by removing the etchant and unexposed photoresist material using an alkaline solution, and finally removing the alkaline solution by water rinsing to obtain the final second circuit layer.

[0053] Furthermore, the step of forming a groove in the first circuit layer specifically includes: Step S31: applying a third photoresist layer to a lower surface of the first circuit layer, the lower surface being a surface of the first circuit layer facing a bonding surface of the first insulating layer; Step S32: subjecting the third photoresist layer to an exposure and development process to obtain a third circuit pattern; and Step S33 of subjecting the third circuit pattern to an etching process to obtain the grooves.

[0054] In some embodiments of the present disclosure, a third photoresist material can be applied to the lower surface of the first circuit layer, since it has been removed by a physical or chemical method before the groove is fabricated. The lower surface can be the surface of the side facing the compression surface of the first insulating layer in the first circuit layer, that is, the other side surface facing the surface of the first insulating layer compressed in the first circuit layer. Then, the third photoresist material is subjected to an exposure and development process to obtain a third circuit pattern. The third circuit pattern can protect a part of the circuit of the first circuit layer and expose the area of ​​the groove. Finally, the third circuit layer is etched to remove the etching solution and the alkaline solution to obtain the groove. The groove can not only facilitate the packaging material to penetrate to the bottom of the embedded device, but also realize the electrical isolation of a part of the area of ​​the first circuit layer.

[0055] Furthermore, the step of applying a first photoresist layer to the first metal layer may specifically include applying the first photoresist layer to the first metal layer by film application or coating. The photoresist layer may be applied to the first metal layer by coating and film application, and the specific application method is not limited. The photoresist layer in all the embodiments of the present disclosure may be applied by film application or coating.

[0056] Hereinafter, a manufacturing procedure for the semiconductor package structure of the present disclosure will be described with reference to FIG.

[0057] First, referring to FIG. 3a, a temporary placement plate 100 including a first metal layer 101 and a placement plate 102 is prepared.

[0058] 3b, the first circuit layer 103 is fabricated using the first metal layer 101 as a substrate. Through a normal manufacturing process, a photolithography mask is attached to the first metal layer 101, and the first circuit layer 103 is obtained through exposure, development, and etching processes.

[0059] Next, referring to FIG. 3c, the first insulating layer 104 is mechanically pressed onto the first circuit layer 103 so as to completely cover the first circuit layer 103.

[0060] Next, referring to FIG. 3d, the first insulating layer 104 is fabricated with conductive copper pillars 105 and a second circuit layer 106 through a drilling and electroplating process, and the drilling can be performed by a laser drilling process.

[0061] 3e, the support plate 102 is removed, and the groove 107 is formed in the first circuit layer 103. During the fabrication, a photoresist is applied to the bottom surface of the first circuit layer 103, and the groove 107 can be obtained by an exposure, development and etching process.

[0062] Also, referring to FIG. 3f, embedded element 108 is attached to first circuit layer 103 so that the projections of embedded element 108 and groove 107 along the attachment direction of embedded element 108 completely overlap each other.

[0063] Next, referring to FIG. 3g, solder balls 109 are soldered to the second circuit layer 106, and a first solder resist layer 110 is fabricated so as to partially cover the second circuit layer 106.

[0064] Finally, referring to FIG. 3h, the first circuit layer 103, the embedded elements 108 and the grooves 107 are covered with the mounting material 111 such that the mounting material 111 completely encases and covers the first circuit layer 103, the embedded elements 108 and the grooves 107.

[0065] In addition, corresponding to the semiconductor package structure of Figure 1, an embodiment of the present disclosure further provides an integrated circuit system, which may include at least one of the semiconductor package structures described in any one of the above embodiments. The semiconductor package structure of the present disclosure includes solder balls, which can be connected to other elements or integrated circuits, and can further form an integrated circuit system, which has good hermeticity and corrosion resistance.

[0066] In some alternative embodiments, the functions / operations depicted in the schematic diagrams may not occur in the order depicted in the flowcharts. For example, depending on such functions / operations, two blocks shown as successive may actually be performed more or less simultaneously, or the blocks may be performed in the opposite order. In addition, the embodiments shown and described in the flowcharts of the present disclosure are provided as examples, and are intended to facilitate a more complete understanding of the technology. The disclosed methods are not limited to the operations and logical flow depicted herein. Alternative embodiments are predictable, and the order of various operations therein may be changed, and sub-operations described as part of a larger operation therein may be performed independently.

[0067] In the above description of this specification, a description referring to terms such as "one embodiment / example," "another embodiment / example," or "some embodiments / examples" means that the specific features, structures, materials, or characteristics described with respect to the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, exemplary descriptions of the above terms are not necessarily all for the same embodiment or example. And, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in any one or more of the embodiments or examples.

[0068] Although embodiments of the present disclosure have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present disclosure, and that the scope of the present disclosure is limited by the claims and their equivalents.

[0069] Although the preferred embodiments of the present disclosure have been specifically described above, the present disclosure is not limited to the above-described embodiments, and those skilled in the art may make various equivalent modifications and substitutions without violating the spirit of the present disclosure, and all of these equivalent modifications and substitutions are included in the scope defined by the claims of the present disclosure.

Claims

1. A method for manufacturing a semiconductor package structure, comprising: The semiconductor package structure includes:

1. A semiconductor package structure for connecting to an external functional circuit, comprising: The semiconductor device includes a mounting layer, a first element layer, a first insulating layer, a conductive copper pillar, and a second element layer, the mounting layer covers the first element layer, the first element layer, the first insulating layer, and the second element layer are stacked in order, the conductive copper pillar penetrates the first insulating layer, and the first element layer and the second element layer are electrically connected via the conductive copper pillar, the first element layer comprises a first circuit layer, a groove, and an embedded element, the embedded element is connected to the first circuit layer, the groove is provided below the embedded element, and a projection of the embedded element partially or completely overlaps with the groove along a bonding direction of the embedded element; the second element layer includes a second circuit layer, a first solder resist layer, and solder balls, the first solder resist layer partially covers the second circuit layer, and the solder balls are for realizing an electrical connection between the second circuit layer and the external function circuit; The method for manufacturing the semiconductor package structure includes: preparing a temporary support plate including a first metal layer and a support plate that are stacked together; fabricating a first circuit layer using the first metal layer as a substrate; pressing a first insulating layer onto the first circuit layer so as to cover the first circuit layer; fabricating conductive copper posts and a second circuit layer on the first insulating layer; removing the support plate and forming a groove in the first circuit layer; applying the embedded element such that the projections of the embedded element and the groove along a direction of application of the embedded element partially or completely overlap; soldering solder balls to the second circuit layer and fabricating a first solder resist layer to partially cover the second circuit layer; and covering the first circuit layer, the embedded element, and the groove with a packaging material.

2. The step of fabricating a first circuit layer using the first metal layer as a substrate specifically includes: applying a first layer of photoresist to the first metal layer; subjecting the first photoresist layer to an exposure and development process to obtain a first circuit pattern; 2. The method for manufacturing a semiconductor package structure as claimed in claim 1, further comprising: subjecting the first circuit pattern to an etching process to obtain a first circuit layer.

3. The step of fabricating the conductive copper pillars and the second circuit layer on the first insulating layer specifically includes: drilling the first insulating layer to form a copper-free hole penetrating the first insulating layer and exposing the first circuit layer to the outside; performing hole filling plating on the copper-free hole to form a conductive copper pillar and a second metal seed layer; applying a second photoresist layer to the second metal seed layer; subjecting the second photoresist layer to an exposure and development process to obtain a second circuit pattern; 2. The method for manufacturing a semiconductor package structure as claimed in claim 1, further comprising: subjecting the second circuit pattern to an etching process to obtain a second circuit layer.

4. The step of fabricating a groove in the first circuit layer specifically includes: applying a third photoresist layer to a lower surface of the first circuit layer, the lower surface being a surface of the first circuit layer facing the compression surface of the first insulating layer; subjecting the third photoresist layer to an exposure and development process to obtain a third circuit pattern; 3. The method for manufacturing a semiconductor package structure as claimed in claim 2, further comprising: subjecting the third circuit pattern to an etching process to obtain the groove.

5. The step of applying a first photoresist layer to the first metal layer specifically includes:

3. The method for manufacturing a semiconductor package structure as claimed in claim 2, further comprising the step of attaching the first photoresist layer to the first metal layer by film attachment or coating.

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