Driving device and driving method for semiconductor device

Abstract

In the present invention, according to a gate signal (Sg) for performing on and off control of a semiconductor element (5), a drive circuit (100) outputs to a control electrode (G) of the semiconductor element (5) one of a first voltage for turning on the semiconductor element and a second voltage for turning off the semiconductor element. A protection circuit (400) is configured in a mode for executing a protective operation that turns off the semiconductor element (5) when an abnormality occurs during the on period of the semiconductor element (5). A selection circuit (300) outputs selection signals (S1, S2) for switching the protective operation mode by the protection circuit (400) according to the drive state of the semiconductor element (5) that corresponds to the gate signal (Sg) using a delay gate signal (Sgd) delayed by a delay circuit (200).

Description

[Technical field]

[0001] The present disclosure relates to a driving device and a driving method for a semiconductor device. [Background technology]

[0002] When an arm short circuit occurs in a power converter equipped with power semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor) and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a large current flows through the power semiconductor elements when the DC link voltage of the power converter is applied. This causes a very large loss (heat) in the semiconductor elements, which may cause thermal destruction. Therefore, in order to ensure the reliability of the power converter, it is necessary to detect the short circuit state and protect the semiconductor elements before the heat generation of the semiconductor elements reaches their short circuit withstand capacity.

[0003] On the other hand, there is a trade-off between the short circuit resistance and power loss of a semiconductor element: increasing the short circuit resistance increases the power loss during normal operation. Therefore, to reduce loss in semiconductor elements, it is necessary to expand the range that can be protected by ingenuity on the drive circuit side.

[0004] For example, International Publication No. 2017 / 026367 (Patent Document 1) describes a configuration in which a short-circuit protection function using an RTC (Real-Time Current Control) circuit is combined with a power switching device of a semiconductor element. When the drain current (main circuit current) of the semiconductor element becomes an overcurrent, the RTC circuit operates to throttle the drain current by lowering the gate-source voltage of the semiconductor element.

[0005] The protection circuit described in Patent Document 1 can operate to prevent damage to elements due to surge voltage by reducing the gate-source voltage when the current during a short circuit is large. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2017 / 026367 Summary of the Invention [Problem to be solved by the invention]

[0007] On the other hand, the current flowing through the semiconductor element when the short circuit protection circuit is operating varies depending on the occurrence circumstances such as the timing of the short circuit. In contrast, in the protection circuit described in Patent Document 1, the content of the protection operation against the occurrence of a short circuit current is fixed, so there is a concern that more power loss than necessary will occur depending on the occurrence circumstances of the short circuit.

[0008] The present disclosure has been made to solve the problems described above, and aims to achieve a protective function when an abnormality occurs in a semiconductor element, while simultaneously ensuring protective performance and suppressing unnecessary power loss. [Means for solving the problem]

[0009] According to an aspect of the present disclosure, there is provided a drive device for a semiconductor element. The drive device for a semiconductor element, in which a current flowing from a first main electrode to a second main electrode is controlled in response to a voltage of a control electrode, includes a drive circuit, a protection circuit, and a selection circuit. The drive circuit outputs to the control electrode one of a first voltage for turning on the semiconductor element and a second voltage for turning off the semiconductor element in response to a gate signal that controls on / off of the semiconductor element. The protection circuit executes a protection operation to turn off the semiconductor element when an abnormality occurs during an on-period of the semiconductor element. The selection circuit switches the mode of the protection operation by the protection circuit in response to a drive state of the semiconductor element in response to a turn-on command.

[0010] According to another aspect of the present disclosure, there is provided a method for driving a semiconductor element, in which a current flowing from a first main electrode to a second main electrode is controlled in response to a voltage of a control electrode, the method comprising the steps of: outputting a first voltage to the control electrode for turning on the semiconductor element in response to a turn-on command for the semiconductor element; executing a protection operation for turning off the semiconductor element when an abnormality occurs during an on-period of the semiconductor element; and switching a mode of the protection operation in response to a drive state of the semiconductor element in response to the turn-on command. Effect of the Invention

[0011] According to the present disclosure, by switching the mode of protection operation depending on the driving state of the semiconductor element in response to the turn-on command, it is possible to ensure both protection performance and suppress unnecessary power loss in the protection function when an abnormality occurs in the semiconductor element. [Brief description of the drawings]

[0012] [Figure 1] 1 is a block diagram illustrating a configuration of a driving device for a semiconductor element according to an embodiment of the present invention. [Diagram 2] 1 is a circuit diagram illustrating a configuration example of a drive device according to a first embodiment. [Diagram 3] 4 is an operational waveform diagram when a semiconductor element is turned on by the driving device according to the first embodiment. FIG. [Figure 4] 4 is a flowchart illustrating a control process of a driving method of a semiconductor element according to the first embodiment. [Diagram 5] FIG. 11 is a circuit diagram illustrating a configuration example of a drive device according to a second embodiment. [Figure 6] 13 is an operational waveform diagram when a semiconductor element is turned on by the driving device according to the second embodiment. FIG. [Figure 7] 10 is a flowchart illustrating a control process of a method for driving a semiconductor element according to a second embodiment. [Figure 8] FIG. 11 is a circuit diagram illustrating a configuration example of a drive device according to a third embodiment. [Figure 9]13 is an operational waveform diagram when a semiconductor element is turned on by a driving device according to embodiment 3. FIG. [Figure 10] FIG. 13 is a circuit diagram illustrating a configuration example of a drive device according to a fourth embodiment. [Figure 11] FIG. 13 is a circuit diagram illustrating a configuration example of a drive device according to a fifth embodiment. [Figure 12] 13 is an operational waveform diagram when a semiconductor element is turned on by a driving device according to embodiment 5. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference characters, and their description will not be repeated in principle.

[0014] Embodiment 1 FIG. 1 is a block diagram illustrating the configuration of a driving device for a semiconductor device according to the present embodiment.

[0015] As shown in Fig. 1, a driving device 10 according to this embodiment controls the on / off of a semiconductor element 5 in response to a gate signal Sg. In the example of Fig. 1, the semiconductor element 5 is configured as a MOSFET and has a gate (G) which is a control electrode, a drain (D) which is a first main electrode (high voltage side), and a source (S) which is a second main electrode (low voltage side). In the semiconductor element 5, a current flowing from the first main electrode to the second main electrode is controlled in response to the voltage of the control electrode. The MOSFET can be fabricated using a semiconductor substrate such as SiC (silicon carbide), Si, or GaN (gallium nitride).

[0016] A current Id (hereinafter also referred to as the "drain current Id") flowing from the first main electrode (D) to the second main electrode (S) of the semiconductor element 5 changes depending on a gate-source voltage Vgs (hereinafter also referred to simply as the "gate voltage"), which is the voltage of the control electrode with respect to the second main electrode (low voltage side).

[0017] The semiconductor element 5 is not limited to a MOSFET, and may be an IGBT, a thyristor, or the like, as long as it is a switching element in which the current between the main electrodes is controlled according to the voltage of the control electrode. For example, when the semiconductor element 5 is an IGBT, the control electrode is the gate, while the first main electrode is the "collector" and the second main electrode is the "emitter."

[0018] The driving device 10 includes a driving circuit 100, a delay circuit 200, a selection circuit 300, and a protection circuit 400. The driving device 10 outputs a driving voltage Vdv to a semiconductor element 5. The driving voltage Vdv controls the gate voltage of the semiconductor element 5 via a gate resistor 6, thereby realizing on / off control of the semiconductor element 5 and a protection operation when a short circuit current is detected.

[0019] The drive circuit 100 receives a gate signal Sg as an input and outputs one of a first voltage (on drive voltage) V1 for turning on the semiconductor element 5 and a second voltage (off drive voltage) V2 for turning off the semiconductor element 5 to an output node Nout electrically connected to the semiconductor element 5 via a gate resistor 6. The gate signal Sg is set to a logical high level (hereinafter simply referred to as "H level") during a period in which the semiconductor element 5 is turned on, and is set to a logical low level (hereinafter simply referred to as "L level") during a period in which the semiconductor element 5 is turned off. Furthermore, the operation of the drive circuit 100 is also controlled by control signals Sa and Sbd from a protection circuit 400, which will be described later.

[0020] The delay circuit 200 receives the gate signal Sg and outputs a delayed gate signal Sgd to which a predetermined delay time has been added. The selection circuit 300 outputs selection signals S1 and S2 for switching the mode of the protection operation by the protection circuit 400 based on the delayed gate signal Sgd from the delay circuit 200.

[0021] The protection circuit 400 has a function of detecting an abnormality of the semiconductor element 5 based on the voltage or current of the first main electrode (drain) of the semiconductor element 5, and when an abnormality is detected, performs a protection operation to prevent the semiconductor element 5 from being damaged by an overcurrent by outputting control signals Sa, Sbd to the drive circuit 100 or outputting a third voltage V3 to the output node Nout. As described below, the protection circuit 400 is configured to switch the protection operation according to the drive state of the semiconductor element 5 by operating based on the selection signals S1, S2 from the selection circuit 300. As described below, for example, the drive state of the semiconductor element 5 related to the protection control can be classified based on the elapsed time from the turn-on start timing when the gate signal Sg changes from the L level to the H level.

[0022] FIG. 2 is a circuit diagram illustrating a specific configuration of driving device 10A according to the first embodiment. 2, the driving device 10A includes a driving circuit 100A, a delay circuit 200A, a selection circuit 300A, and a protection circuit 400A. The driving circuit 100A, the delay circuit 200A, the selection circuit 300A, and the protection circuit 400A correspond to examples of the driving circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.

[0023] The drive circuit 100A includes a switching control circuit 103, resistance elements 104 and 106, and switching elements 105 and 107 that are turned on and off in a complementary manner.

[0024] The power supply 101 is connected between a power supply node Np and a GND node to generate an on-drive voltage (first voltage V1). The power supply node Np supplies the first voltage V1. The power supply 102 is connected between the GND node and a negative power supply node Nn to generate a negatively biased off-drive voltage (second voltage V2). That is, the second voltage V2 is a negative voltage (V2<0). The negative power supply node Nn supplies the second voltage V2. The GND node of the driving device 10A has the same potential as the source (second main electrode) of the semiconductor element 5.

[0025] A switching element 105 made of an N-type transistor and a resistive element 104 constituting an on-gate resistor are connected in series between a power supply node Np and an output node Nout. A switching element 107 made of a P-type transistor and a resistive element 106 constituting an off-gate resistor are connected in series between a negative power supply node Nn and an output node Nout.

[0026] The switching control circuit 103 generates a control signal Scn in accordance with the gate signal Sg. The control signal Scn is set to H level during an H level period of the gate signal Sg, and is set to L level during an L level period of the gate signal Sg.

[0027] The control signal Scn is input to the gates of the N-type transistor and the P-type transistor constituting the switching elements 105 and 107, respectively. As a result, the switching elements 105 and 107 are turned on and off complementarily. Specifically, during the H level period of the gate signal Sg, in response to Scn=H, the switching element 105 is turned on, while the switching element 107 is turned off. Therefore, the output node Nout is connected to the power supply node Np via the resistive element 104 (on-gate resistor), and the driving voltage Vdv output from the driving device 10A to the output node Nout becomes the first voltage V1.

[0028] Conversely, during the L level period of the gate signal Sg, in response to Scn=L, the switching element 107 is turned on while the switching element 105 is turned off. Therefore, the output node Nout is connected to the negative power supply node Nn via the resistance element 106 (off-gate resistance), and the driving voltage Vdv output from the driving device 10A to the output node Nout becomes the second voltage V2.

[0029] The delay circuit 200A includes a resistive element 201, a capacitor 202, and a trigger circuit 203. The gate signal Sg is input to an RC circuit formed by the resistive element 201 and the capacitor 202. The trigger circuit 203 generates a delayed gate signal Sgd in response to the output voltage of the RC circuit. The delayed gate signal Sgd is a signal obtained by adding a delay time TX according to an RC time constant to the gate signal Sg. That is, the delayed gate signal Sgd changes from an L level to an H level at a timing when the delay time TX has elapsed from the timing when the gate signal Sg changes from an L level to an H level. The delay time TX can be adjusted by the resistance value of the resistive element 201 and the capacitance value of the capacitor 202.

[0030] The selection circuit 300A includes an inverting buffer 301 and a non-inverting buffer 302. A The non-inverting buffer 302 outputs a selection signal S1 obtained by inverting the delay gate signal Sgd from the delay circuit 200. A The select signal S1 outputs a select signal S2 having the same logic level as the delay gate signal Sgd from the delay gate input terminal S1. That is, the select signals S1 and S2 have complementary logic levels.

[0031] The protection circuit 400A includes a logic gate 401 that generates a control signal Sa, a logic gate 402 that generates a control signal Sb, a delay circuit 403 for providing a delay time T1, a soft shutdown circuit 500, and a short circuit detection circuit 600A.

[0032] The short circuit detection circuit 600A includes resistance elements 601, 603, and 604, a diode 602, a capacitor 605, and a comparator 609. The resistance element 601 is connected between the drain of the semiconductor element 5 and a node N1. The resistance element 603 is connected between the nodes N1 and N2. The resistance element 604 is connected between the node N2 and a negative power supply node Nn.

[0033] The diode 602 is connected between the node N1 and the output node Nout, and has an anode connected to the node N1 and a cathode connected to the output node Nout. The capacitor 605 is connected in parallel with the resistive element 604 between the node N2 and the negative power supply node Nn.

[0034] The comparator 609 generates a short - circuit detection signal Soc based on the comparison result between the voltage Vsig at the node N2 and the determination voltage Vt by the power supply 608. Specifically, when Vsig > Vt, a short - circuit state in which an over - current occurs in the semiconductor element 5 is detected, and the short - circuit detection signal Soc is set to the H level.

[0035] During the off - period of the semiconductor element 5, a second voltage V2, which is a negative voltage, is supplied to the output node Nout. On the other hand, the drain - source voltage Vds (hereinafter, also simply referred to as the "drain voltage") rises. For this reason, in the short - circuit detection circuit 600A, the diode 602 conducts, and the voltage Vsig at the node N2 is clamped to a voltage equivalent to the second voltage V2. Therefore, the state of Vsig < Vt is maintained, and the short - circuit detection signal Soc is fixed at the L level.

[0036] Immediately after the semiconductor element 5 is turned on, a first voltage V1, which is a positive voltage, is supplied to the output node Nout. For this reason, in the short - circuit detection circuit 600A, the node N1 becomes a voltage obtained by dividing the drain voltage of the semiconductor element 5 by the resistive elements 601, 603, 604, but is clamped to the first voltage V1 by the diode 602. The resistive elements 603, 604, and the capacitor 605 constitute a "filter circuit" with the potential of the node N1 as the input voltage. At this time, the voltage Vsig at the node N2 corresponds to the output voltage of the filter circuit. That is, when the output node Nout is connected to the first voltage V1 and the drain voltage Vds is high, the voltage Vsig rises. Specifically, the voltage Vsig rises at a slope according to the time constant (RC time constant) determined by the resistance values of the resistive elements 603, 604 and the capacitance value of the capacitor 605.

[0037] In a normal turn-on state, the drain voltage (Vds) of the semiconductor element 5 is nearly zero (the steady-state on-voltage of the element), and the voltage at the node N1 also drops to near zero. As a result, in the above filter circuit, charging of the capacitor 605 stops, and then discharging of the capacitor 605 starts. As a result, the voltage Vsig at the node N2 transitions so as to decrease from the value at which the charging of the capacitor 605 ends (normal value Vnml) as a maximum value.

[0038] On the other hand, when the drain voltage Vds continues to be high due to the occurrence of a short circuit, the above filter circuit uses the capacitor 605 Since the charging state continues without stopping, the voltage Vsig at the node N2 continues to rise without reaching the maximum value. Therefore, the determination voltage Vt by the power supply 608 is determined based on the first voltage V1 and the time constant of the filter circuit formed by the resistor elements 603 and 604 and the capacitor 605 so that Vsig>Vt in the short-circuit state. In addition, to prevent erroneous determination of normal switching, it is set to Vt>Vnml. As a result, the short-circuit detection signal Soc is maintained at L level during the off period and normal on period of the semiconductor element 5, but changes to H level when a short-circuit state occurs during the on period.

[0039] The logic gate 401 outputs the logical product (AND) operation result of the selection signal S1 (inversion of the delayed gate signal Sgd) from the inverting buffer 301 and the short circuit detection signal Soc as a control signal Sa. The logic gate 402 outputs the logical product (AND) operation result of the selection signal S2 (delayed gate signal Sgd) from the non-inverting buffer 302 and the short circuit detection signal Soc as a control signal Sb. The delay circuit 403 outputs a control signal Sbd by adding a predetermined delay time T1 to the control signal Sb output by the logic gate 402.

[0040] The control signals Sa and Sbd are input to a switching control circuit 103. When the control signal Sa or Sbd changes from an L level to an H level during an H level period of the gate signal Sg, the switching control circuit 103 changes the control signal Scn from an H level to an L level. The control signal Sb is input to a soft shutoff circuit 500.

[0041] The soft shutoff circuit 500 has a resistor element 501, a diode 502, and a switching element 503 made up of an N-type transistor, which are connected in series between the output node Nout and the negative power supply node Nn. A control signal Sb is input to the gate of the N-type transistor that constitutes the switching element 503. The diode 502 is connected with the direction from the output node Nout to the negative power supply node Nn as the forward direction.

[0042] When the short circuit detection signal Soc is at L level, the control signals Sa, Sb, and Sbd are all fixed at L level. In contrast, when the short circuit detection signal Soc changes from L level to H level, one of the control signals Sa and Sb changes to H level depending on the timing of the change, while the other of the control signals Sa and Sb is maintained at L level.

[0043] Specifically, during the period from the turn-on start timing at which the gate signal Sg changes from an L level to an H level until the delay time TX set by the delay circuit 200A has elapsed (hereinafter referred to as the "turn-on period"), the selection signal S1 is at an H level while the selection signal S2 is at an L level, so that when the short circuit detection signal Soc changes to an H level, the control signal Sa changes to an H level. In response to this, the switching control circuit 103 changes the control signal Scn from an H level to an L level. At this time, the control signal Sb is maintained at an L level, so the switching element 503 of the soft shutoff circuit 500 is maintained off.

[0044] In contrast, during the period after the delay time TX has elapsed from the turn-on start timing (hereinafter referred to as the "steady on period"), the selection signal S2 is at H level while the selection signal S1 is at L level, so that when the short circuit detection signal Soc changes to H level, the control signal Sb changes to H level. In response to this, in the soft shutdown circuit 500, the switching element 503 is turned on to form a discharge path from the output node Nout to the negative power supply node Nn. As a result, a voltage drop occurs in the resistance element 501, and the drive voltage Vdv of the output node Nout drops from the first voltage V1 to the third voltage V3 (V1>V3>V2).

[0045] The switching control circuit 103 changes the control signal Scn from H level to L level in response to the control signal Sbd being set to H level at a timing when the delay time T1 by the delay circuit 403 has elapsed since the control signal Sb changed to H level. As a result, the switching element 107 is turned on, and the drive voltage Vdv of the output node Nout changes to the second voltage V2 (V2<0). In this way, the soft shutoff circuit 500 can temporarily reduce the drive voltage Vdv to the third voltage V3 by operating in response to the control signal Sb during the H level period of the control signal Scn.

[0046] Fig. 3 shows an operational waveform diagram when the semiconductor element is turned on by the driving device according to embodiment 1. In Fig. 3, regarding the change in voltage and current during the turn-on operation in response to the gate signal Sg, the solid line shows the waveform during normal operation, and the dotted line shows the waveform when a short circuit occurs.

[0047] 3, at time t1, the gate signal Sg changes from an L level to an H level, thereby starting a turn-on operation. During a period in which the semiconductor element 5 is off until time t1, the driving device 10A outputs the second voltage V2 as the driving voltage Vdv to the gate of the semiconductor element 5.

[0048] At time t1, as the gate signal Sg changes from the L level to the H level, the drive voltage Vdv output from the drive device 10A to the gate of the semiconductor element 5 changes to the first voltage V1. In response to this, the gate voltage Vgs rises from the second voltage V2, and after a mirror period during which the voltage rise temporarily stops, it further rises and reaches the first voltage V1.

[0049] First, the drain current Id, drain voltage Vds, and voltage Vsig in the short circuit detection circuit 600A during normal turn-on will be described with reference to the solid line waveform diagram.

[0050] The drain current Id starts to flow when the gate voltage Vgs rises and exceeds the threshold voltage Vth of the semiconductor element 5, and reaches a steady value around the end of the mirror period. The drain voltage Vds starts to decrease when the drain current Id starts to flow, and decreases in proportion to the rate of change of the drain current Id (dId / dt) due to parasitic inductance in the circuit. After that, it further decreases around the end of the mirror period, and reaches a steady state with Vds ≒ 0.

[0051] After time t1, because the drive voltage Vdv=V1 and the voltage Vsig is in a high Vds state, the voltage Vsig rises in response to the charging of the capacitor 605. Then, after the end of the mirror period, the voltage Vsig decreases toward 0 in conjunction with the decrease in the drain voltage Vds.

[0052] At time t2, the delay time TX caused by the delay circuit 200 has elapsed since time t1. That is, the period from time t1 to t2 corresponds to a turn-on period, and the period from time t2 until the gate signal Sg changes to the L level corresponds to a steady-on period.

[0053] First, the operation when a short circuit occurs in the semiconductor element 5 during the turn-on period will be described with reference to the waveform diagram of the dotted line between times t1 and t2. When a short circuit occurs, the drain current Id continues to increase even after the mirror period ends. Also, since the drain voltage Vds does not drop as it does in the normal state, the voltage Vsig continues to rise even after the mirror period ends. As a result, at time ts, the short circuit detection circuit 600A detects Vsig>Vt and sets the short circuit detection signal Soc (FIG. 2) to the H level. As described above, during the turn-on period, when the short circuit detection signal Soc changes to the H level, the control signal Sa input to the switching control circuit 103 changes to the H level.

[0054] In response to this, at time ts, in the drive circuit 100A, the switching element 107 is turned on, and the drive voltage Vdv output from the drive device 10A to the gate of the semiconductor element 5 changes to the second voltage V2, which is a negative voltage, as shown by the dotted line. As a result, the gate voltage Vgs decreases toward the second voltage V2, and the drain current Id also decreases. The drain voltage Vds rises due to a surge voltage that occurs at the timing when the drain current Id starts to decrease, and then reaches the voltage at the time of off. In this way, during the turn-on period, the semiconductor element 5 is immediately turned off in response to the detection of a short-circuit state.

[0055] Next, the operation when a short circuit occurs in semiconductor element 5 during the steady on-period will be described with reference to the waveform diagram indicated by the dotted line between times t3 and t6.

[0056] With drive voltage Vdv=V1 being continuously output to the gate of semiconductor element 5, a short circuit state occurs from time t3, causing drain current Id to rise, after which drain voltage Vds also begins to rise. In response to this, from time t4, voltage Vsig rises in conjunction with Vds, and at time t5, which is ΔT0 after time t4, short circuit detection circuit 600A detects Vsig>Vt and sets short circuit detection signal Soc (FIG. 2) to the H level. As described above, during the steady-on period, when short circuit detection signal Soc changes to the H level, control signal Sb input to soft shutoff circuit 500 changes to the H level.

[0057] In response to this, at time t5, in the soft shutoff circuit 500, the switching element 503 is turned on, and the drive voltage Vdv output from the drive device 10A to the gate of the semiconductor element 5 drops from the first voltage V1 to the third voltage V3. In response to this, the gate voltage Vgs drops, and the drain current Id also drops. Furthermore, at time t6, which is the delay time T1 caused by the delay circuit 403 after time t5, the control signal Sbd input to the switching control circuit 103 changes to the H level.

[0058] In response to this, at time t6, in the drive circuit 100A, the switching element 107 is turned on, and the drive voltage Vdv output from the drive device 10A to the gate of the semiconductor element 5 changes to the second voltage V2, which is a negative voltage. As a result, the semiconductor element 5 is turned off, and the gate voltage Vgs decreases toward the second voltage V2, and the drain current Id also decreases toward 0.

[0059] At this time, a surge voltage occurs in the drain voltage Vds at times t5 and t6 when the drain current Id starts to decrease. However, after time t5 when the short-circuit state is detected, the gate voltage is temporarily decreased to the third voltage V3 and then the semiconductor element 5 is turned off. Therefore, the surge voltage can be significantly suppressed compared to the case where the semiconductor element 5 is immediately turned off at time t5 when the short-circuit state is detected.

[0060] Specifically, the amount of decrease in the gate voltage at time t5 is suppressed, and the drain current Id when the semiconductor element 5 is turned off at time t6 is suppressed, thereby suppressing the surge voltage.

[0061] When a short circuit state is detected by monitoring the drain voltage of the semiconductor element 5 during the steady-on period, it is assumed that the drain current Id (short circuit current) has reached a level greater than that at the time of short circuit occurrence during the turn-on period, as shown in Fig. 3. For this reason, if the semiconductor element 5 is immediately turned off at the timing (time t5) at which the short circuit state is detected, the surge voltage will increase and the drain voltage Vds will exceed the withstand voltage, which may damage the semiconductor element 5.

[0062] In the driving device 10A of embodiment 1, when a short-circuit state is detected during the steady-on period, the surge voltage can be suppressed by applying the soft shutoff circuit 500. This makes it possible to prevent the semiconductor element 5 from being destroyed by the surge voltage generated by the protective operation for thermal protection in a short-circuit state, thereby ensuring the protection function.

[0063] On the other hand, when a short circuit state is detected during the turn-on period, the protection operation is performed by turning off the semiconductor element 5 from a state in which the drain current Id is not as large as in the steady-on period. Therefore, by immediately turning off the semiconductor element 5 in response to detection of a short circuit state, it is possible to suppress the power loss (heat generation) caused by the protection operation without destroying the semiconductor element 5 due to a surge voltage generated by the protection operation.

[0064] In this manner, in this embodiment, the turn-on period corresponds to an example of the "first period", and the control of the drive voltage Vdv after time ts corresponds to an example of the "first protection operation". Similarly, the steady-on period corresponds to an example of the "second period", and the control of the drive voltage Vdv after time t5 corresponds to an example of the "second protection operation". In addition, the delay time TX by the delay circuit 200A corresponds to an example of the "first time".

[0065] FIG. 4 shows a flowchart illustrating the control process of the method of driving semiconductor element 5 by driving device 10A.

[0066] During the off-period of the semiconductor element 5 in which the gate signal Sg is set to the L level, the driving device 10A performs step (hereinafter, simply referred to as "S") 100 to control the turn-on voltage Vcc of the gate signal Sg. on The semiconductor device 5 is turned on by detecting a turn-on command and waiting for a command. When the gate signal Sg changes from an L level to an H level, a turn-on command is detected and a YES determination is made in S100. This starts the processing from S110 onwards for turning on the semiconductor device 5. On the other hand, while the gate signal Sg is at an L level, a turn-on command is not detected (a NO determination is made in S100), and the processing from S110 onwards is not started.

[0067] When drive device 10A is instructed to turn on (YES in S100), in S110, it turns on switching element 105 of drive circuit 100A (FIG. 2) while turning off switching element 107, thereby setting drive voltage Vdv to first voltage V1. As a result, drive device 10A outputs first voltage V1 to the gate of semiconductor element 5.

[0068] Thereafter, in S120, driving device 10A determines whether or not a short circuit state is detected during a turn-on period from the turn-on command until the delay time TX by delay circuit 200A has elapsed. If short circuit detection signal Soc is set to an H level by short circuit detection circuit 600A between times t1 and t2 in FIG. 3, a YES determination is made in S120, and the process proceeds to S170.

[0069] In S170, driving device 10A turns off switching element 105 of driving circuit 100A (FIG. 2) while turning on switching element 107, thereby setting driving voltage Vdv to second voltage V2. As a result, driving device 10A outputs second voltage V2 to the gate of semiconductor element 5, thereby turning off semiconductor element 5. In this way, by the operation shown by the dotted line between times t1 and t2 in FIG. 3, semiconductor element 5 is immediately turned off in response to the detection of a short-circuit state.

[0070] In S120, when the short - circuit state is not detected even after the delay time TX by the delay circuit 200A has elapsed from the turn - on command (when the NO determination in S120 is made), the drive device 10A determines whether the short - circuit state is detected until a turn - off command is generated by S130 and S160.

[0071] When the short - circuit state is not detected until the time t2 in FIG. 3, that is, when the short - circuit detection signal Soc by the short - circuit detection circuit 600A is maintained at the L level, S120 is determined as NO. In this way, the turn - on period and the steady - on period during which the protection operation is switched according to the elapsed time from the start of turn - on are divided by the delay time TX by the delay circuit 200A. The delay time TX needs to be set longer than the time Ton required for the drain voltage Vds to drop to zero during normal operation. This required time Ton changes depending on the temperature and the drain current (at steady state), and becomes larger at low temperature and high drain current. Therefore, by performing the switching test of the semiconductor element 5, it can be set so that TX>Ton is guaranteed.

[0072] Also, as one of the specifications of the semiconductor element 5, the short - circuit tolerance Tsc [μs] is described in a data sheet or the like. Since the short - circuit tolerance Tsc indicates the time margin until element breakdown when a short - circuit current flows, it is necessary to set the delay time TX<Tsc. Therefore, the delay time TX is set to Ton<TX<Tsc according to the specifications of the semiconductor element 5 and the switching test.

[0073] When the gate signal Sg changes from the H level to the L level, the drive device 10A detects the turn - off command and determines S160 as YES. When the short - circuit state is not detected until the turn - off command is detected (the NO determination in S130 is maintained), S160 is determined as YES and the process proceeds to S170. In this case, the drive device 10A immediately turns off the semiconductor element 5 by outputting the second voltage V2 to the gate of the semiconductor element 5 in response to the turn - off command.

[0074] In contrast, if a short circuit state is detected during the steady-on period before the turn-off command is detected, a YES determination is made in S130, and the process proceeds to S140. In S140, drive device 10A turns on switching element 503 of soft shutdown circuit 500 in response to control signal Sb that is set to an H level in response to short circuit detection signal Soc. This realizes the operation at time t5 in FIG. 3, and drive device 10A can reduce drain current Id of semiconductor element 5 by outputting third voltage V3 to the gate of semiconductor element 5.

[0075] Drive device 10A maintains drive voltage Vdv at the third voltage in the period corresponding to times t5 to t6 in Fig. 3 until delay time T1 set by delay circuit 403 has elapsed (determination of NO in S150). Then, when delay time T1 set by delay circuit 403 has elapsed (determination of YES in S150), drive device 10A advances the process to S170 and outputs second voltage V2 to the gate of semiconductor element 5, thereby turning off semiconductor element 5.

[0076] In this way, when a short circuit condition is detected during the steady-on period, a soft shutdown is applied in which the voltage output to the gate of the semiconductor element 5 is reduced to the third voltage V3 to provide a period for reducing the drain current Id, and then the semiconductor element 5 is turned off by the second voltage V2.

[0077] At this time, a time lag occurs between when the driving device 10A reduces the driving voltage Vdv to the third voltage V3 and when the gate voltage Vgs of the semiconductor element 5 reduces to the third voltage V3 in order to discharge the gate capacitance. For this reason, the delay time T1 by the delay circuit 403 can be set in consideration of this time lag.

[0078] In this way, according to the driving device 10A of the first embodiment, the driving state of the semiconductor element 5 can be divided according to the elapsed time from the start of the turn-on operation, and the above-mentioned two types of protection operation can be switched. Specifically, in the short-circuit protection operation at turn-on, which cuts off a relatively small current, the semiconductor element 5 is immediately turned off to reduce power loss, and in the short-circuit protection operation during steady-on, which cuts off a large current, the semiconductor element 5 can be protected from damage due to a surge by applying soft cutoff. This makes it possible to ensure the protection performance of the semiconductor element against the occurrence of a short-circuit current while suppressing unnecessary power loss.

[0079] Embodiment 2 FIG. 5 is a circuit diagram illustrating a specific configuration of a driving device 10B according to the second embodiment.

[0080] 5, the driving device 10B includes a driving circuit 100A, a delay circuit 200A, a selection circuit 300A, and a protection circuit 400B. The driving circuit 100A, the delay circuit 200A, the selection circuit 300A, and the protection circuit 400B correspond to examples of the driving circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.

[0081] That is, the driving device 10B differs from the driving device 10A shown in Fig. 2 in that it includes a protection circuit 400B instead of the protection circuit 400A. The protection circuit 400B differs from the protection circuit 400A in Fig. 2 in that it includes a short circuit detection circuit 600B instead of the short circuit detection circuit 600A. Therefore, in the driving device 10B according to the second embodiment, the configuration for generating the short circuit detection signal Soc differs from that of the first embodiment (driving device 10A), while the protection operation according to the short circuit detection signal Soc is the same as that of the first embodiment.

[0082] The short circuit detection circuit 600B further includes a capacitor 606 and a switching element 607 constituted by an N-type transistor in addition to the resistive elements 601, 603, and 604, a diode 602, a capacitor 605, a power supply 608, and a comparator 609 similar to the short circuit detection circuit 600A (FIG. 2).

[0083] The capacitor 606 and the switching element 607 are connected in series between the node N2 and the negative power supply node Nn. The selection signal S1 from the selection circuit 300A is input to the gate of the N-type transistor constituting the switching element 607. As described above, the selection signal S1 is an inverted signal of the delayed gate signal Sgd, and therefore is set to H level during the turn-on period (times t1 to t2 in FIG. 3) and is set to L level during the steady-on period (after time t2 in FIG. 3). Therefore, the switching element 607 is on during the turn-on period (S1=H level) and off during the steady-on period (S1=L level).

[0084] In the short circuit detection circuit 600B, the capacitance of the node N2 is switched depending on the on / off of the switching element 607. Specifically, during a turn-on-on period in which the switching element 607 is on, the sum of the capacitances of the capacitors 605 and 606 is applied to the node N2. The sum of the capacitances of the capacitors 605 and 606 in the second embodiment is designed to be equal to the capacitance of the capacitor 606 in the first embodiment.

[0085] On the other hand, during the steady-state on-period in which the switching element 607 is turned off, the capacitor 605 Only the capacitance of the node N1 is added to the node N2. Therefore, the capacitance of the node N2 is smaller during the steady-on period than during the turn-on period. In this manner, in the short-circuit detection circuit 600B, the resistance elements 603 and 604 and the capacitor 605 alone or both the capacitors 605 and 606 form a "filter circuit" that uses the voltage of the node N1 as an input voltage.

[0086] In the short circuit detection circuit 600B, the time constant of the filter circuit that generates the voltage Vsig of the node N2 from the drain voltage Vds is switched between the turn-on period and the steady on period so that it is smaller in the steady on period than in the turn-on period. As a result, when a short circuit occurs, the slope of the voltage Vsig input to the comparator 609 increasing in conjunction with the drain voltage Vds is also larger in the steady on period than in the turn-on period.

[0087] Fig. 6 shows an operational waveform diagram when a semiconductor element is turned on by a driving device according to embodiment 2. In Fig. 6, as in Fig. 3, regarding the change in voltage and current during the turn-on operation in response to gate signal Sg, the solid line shows the waveform during normal operation, and the dotted line shows the waveform during the occurrence of a short circuit.

[0088] 6, the operational waveforms from time t1 when the turn-on operation starts to time t2 when the turn-on period ends are the same as those in FIG.

[0089] On the other hand, after time t2 when the turn-on period ends, the switching element 607 in the short circuit detection circuit 600B is turned off, so that the rate of increase of the voltage Vsig relative to the increase of the drain voltage Vds increases.

[0090] 3, when a short circuit occurs at time t3 and the drain current Id (dotted line) rises, and then the drain voltage Vds (dotted line) also starts to rise, the voltage Vsig rises together with Vds from time t4. At time t5, which is ΔT1 after time t4, the short circuit detection circuit 600B detects that Vsig>Vt.

[0091] As a result, the short circuit detection signal Soc (FIG. 5) is set to H level, and from time t5 onwards, similarly to after time t5 in FIG. 3, the semiconductor element 5 is turned off by applying soft shutdown.

[0092] As can be understood from a comparison of Figure 6 and Figure 3, due to the difference in the rate of increase of the voltage Vsig, ΔT1 in Figure 6 is shorter than ΔT0 in Figure 3. That is, in the second embodiment, it is possible to detect the occurrence of a short-circuit state earlier and initiate soft shutdown, compared to the first embodiment.

[0093] FIG. 7 is a flowchart illustrating a control process of a driving method for semiconductor element 5 by driving device 10B according to the second embodiment.

[0094] 7 and 4, drive device 10B differs in that it further executes the process of S210 in addition to the control process by drive device 10A shown in Fig. 3. When the determination of S120 is NO, that is, when a short-circuit state is not detected even after the delay time TX by delay circuit 200A has elapsed since the start of the turn-on operation, drive device 10B executes S210 and then executes the processes of S130 to S170 similar to those of Fig. 3.

[0095] In S210, drive device 10B changes the detection condition for the short-circuit state by turning off switching element 607 of short-circuit detection circuit 600B at the transition timing from the turn-on period to the steady-on period (time t2 in FIG. 6). As a result, in the detection of the short-circuit state by S130 during the steady-on period, the rise speed of voltage Vsig in short-circuit detection circuit 600B is increased, so that the short-circuit state can be detected earlier compared to the first embodiment.

[0096] As described above, in the method of detecting a short circuit state based on the drain voltage of the semiconductor element 5, the drain voltage Vds rises with a delay from the increase in the drain current Id, so there is a concern that the drain current Id will be large at the timing of detecting the short circuit state, and the energy to be cut off will increase. For this reason, during the steady-state on-state, when a large current is to be cut off, it is desirable to detect a short circuit state as early as possible and suppress the energy to be cut off.

[0097] According to the drive device of the second embodiment, in the steady-on period divided according to the elapsed time from the start of the turn-on operation, the speed of detecting a short-circuit state with respect to an increase in the drain voltage Vds can be increased by reducing the time constant of the filter circuit that generates the input (voltage Vsig) to the comparator 609 of the short-circuit detection circuit 600B. This shortens the time until the short-circuit state is detected, thereby suppressing the cut-off energy due to the protective operation during the steady-on period and improving the effectiveness of the protective operation for preventing the semiconductor element 5 from being destroyed.

[0098] In the example of FIG. 6, a configuration has been described in which the time constant of the filter circuit, i.e., the rate of increase of the voltage Vsig, is switched by switching the capacitance value added to node N2. However, a similar effect can also be achieved by switching the values ​​of other passive elements such as resistor elements.

[0099] Embodiment 3 FIG. 8 is a circuit diagram illustrating a specific configuration of a driving device 10C according to the third embodiment.

[0100] 8, the driving device 10C includes a driving circuit 100A, a delay circuit 200A, a selection circuit 300A, and a protection circuit 400C. The driving circuit 100A, the delay circuit 200A, the selection circuit 300A, and the protection circuit 400C correspond to examples of the driving circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.

[0101] That is, the driving device 10C differs from the driving device 10A shown in Fig. 2 in that it includes a protection circuit 400C instead of the protection circuit 400A. The protection circuit 400C differs from the protection circuit 400A in Fig. 2 in that it includes a short circuit detection circuit 600C instead of the short circuit detection circuit 600A. Therefore, while the configuration for generating the short circuit detection signal Soc of the driving device 10C according to the third embodiment is different from that of the first embodiment (driving device 10A), the protection operation in response to the short circuit detection signal Soc is similar to that of the first embodiment.

[0102] The short circuit detection circuit 600C further includes resistance elements 610-612 and a switching element 613 configured with an N-type transistor in addition to resistance elements 601, 603, and 604, a diode 602, a capacitor 605, and a comparator 609 similar to those of the short circuit detection circuit 600A (FIG. 2). On the other hand, the power supply 608 in FIG. 2 is not provided in the short circuit detection circuit 600C.

[0103] The resistance element 610 is connected between the power supply node Np and a node N3 where a judgment voltage Vt is generated. The resistance element 611 is connected between the node N3 and a negative power supply node Nn. The resistance element 612 and the switching element 613 are connected in series between the node N3 and the negative power supply node Nn. A selection signal S2 from the selection circuit 300B is input to the gate of the N-type transistor constituting the switching element 613. As described above, since the selection signal S2 is in phase with the delayed gate signal Sgd, it is set to an L level during the turn-on period (times t1 to t2 in FIG. 3) and is set to an H level during the steady-on period (after time t2 in FIG. 3). Therefore, the switching element 613 is turned on during the steady-on period (S2=H level) and turned off during the turn-on period (S2=L level).

[0104] The short circuit detection circuit 600C differs from the short circuit detection circuit 600A in FIG. 2 in that the determination voltage Vt is not a constant voltage from the power supply 608, but is switched during the turn-on period and the steady-on period.

[0105] In the short circuit detection circuit 600C, the determination voltage Vt is switched by switching the voltage division ratio in response to the on / off state of the switching element 613. Specifically, since the switching element 613 is turned off during the turn-on period, the determination voltage Vt is generated by dividing (V1-V2) by the resistance elements 610 and 611.

[0106] In contrast, during the steady on-period, the switching element 613 is turned on, and thus the determination voltage Vt is generated by dividing (V1-V2) by the resistive element 610 and the combined resistance of the resistive elements 611 and 612 connected in parallel. Here, since the combined resistance of the resistive elements 611 and 612 is lower than the resistance value of the resistive element 611, it can be understood that during the steady on-period, the determination voltage Vt is set lower than during the turn-on period.

[0107] On the other hand, in the short circuit detection circuit 600C, the voltage Vsig input to the comparator 609 (+ terminal) is generated by a configuration similar to that of the short circuit detection circuit 600A in FIG.

[0108] FIG. 9 shows an embodiment of the present invention. 3 9 shows an operational waveform diagram when the semiconductor element is turned on by the driving device according to the present invention. In Fig. 9, as in Figs. 3 and 6, the waveforms in normal state are shown by solid lines and the waveforms when a short circuit occurs are shown by dotted lines with respect to the changes in voltage and current during the turn-on operation in response to the gate signal Sg.

[0109] 9, the operational waveforms from time t1 when the turn-on operation starts to time t2 when the turn-on period ends are the same as those in FIG. 3 and FIG.

[0110] On the other hand, after time t2 when the turn-on period ends, the switching element 613 in the short circuit detection circuit 600C is turned on, thereby decreasing the determination voltage Vt.

[0111] Therefore, as in Fig. 3, when a short circuit occurs from time t3 and the drain current Id (dotted line) rises, and then the drain voltage Vds (dotted line) also starts to rise, from time t4, the voltage Vsig rises in conjunction with Vds at the same rate as in Fig. 3. Then, under the reduced determination voltage Vt, at time t5 when ΔT1 has elapsed since time t4, the short circuit detection circuit 600C detects that Vsig>Vt.

[0112] As a result, the short circuit detection signal Soc (FIG. 5) is set to the H level, and from time t5 onwards, similarly to after time t5 in FIG. 3, soft shutdown is applied and the semiconductor element 5 is turned off.

[0113] As can be understood from a comparison of Figure 8 and Figure 3, by lowering the determination voltage Vt, ΔT1 in Figure 8 becomes shorter than ΔT0 in Figure 3, similar to ΔT1 in Figure 6. That is, also in the third embodiment, it becomes possible to detect the occurrence of a short circuit state earlier and initiate soft shutdown, compared to the first embodiment.

[0114] The method of driving the semiconductor element 5 by the driving device 10C of embodiment 3 can be realized by using the flowchart of FIG. 7 similar to that of embodiment 2, and turning on the switching element 613 of the short circuit detection circuit 600C in S210 at the transition timing from the turn-on period to the steady-on period (time t2 in FIG. 6).

[0115] As a result, by changing the conditions for detecting a short circuit state in S210 so that the determination voltage Vt is lower than that during the turn-on period, the detection of a short circuit state by S130 during the steady-on period can detect the short circuit state earlier than in embodiment 1.

[0116] In this way, according to the third embodiment, in the steady on-period divided by the elapsed time from the start of the turn-on operation, the detection speed of the short-circuit state with respect to the rise in the drain voltage Vds can be increased by lowering the determination voltage Vt input to the comparator 609 of the short circuit detection circuit 600C. This shortens the time until the short circuit state is detected, so that, as in the second embodiment, the blocking energy due to the protective operation during the steady on-period can be suppressed, and the effectiveness of the protective operation for preventing the semiconductor element 5 from being destroyed can be improved.

[0117] In the example of Figure 8, a configuration has been described in which the judgment voltage is switched based on the voltage division ratio of resistive elements. However, as long as the judgment voltage can be switched in a similar manner, any configuration can be applied to achieve the same effect.

[0118] Embodiment 4 In the fourth embodiment, a configuration for detecting a short-circuit state based on a drain current Id will be described as another example of a method for detecting a short-circuit state of a semiconductor element 5.

[0119] FIG. 10 is a circuit diagram illustrating the configuration of a driving device 10D according to the fourth embodiment. 10, a driving device 10D includes a driving circuit 100A, a delay circuit 200A, a selection circuit 300A, and a protection circuit 400D. The driving circuit 100A, the delay circuit 200A, the selection circuit 300A, and the protection circuit 400D correspond to examples of the driving circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.

[0120] That is, driving device 10D differs from driving device 10A shown in Fig. 2 in that it includes a protection circuit 400D instead of protection circuit 400A. Protection circuit 400D differs from protection circuit 400A in Fig. 2 in that it includes a short circuit detection circuit 700 instead of short circuit detection circuit 600A.

[0121] That is, in driving device 10D according to embodiment 4, the configuration for generating short circuit detection signal Soc is different from that of embodiment 1 (driving device 10A). Short circuit detection circuit 700 includes a resistive element 702, an amplifier 703, a power supply 704 that outputs a determination voltage Vt, and a comparator 705.

[0122] Furthermore, in the fourth embodiment, a sense cell 701 for detecting a drain current is connected in parallel to the semiconductor element 5. The gate of the sense cell 701 is connected to the gate of the semiconductor element 5, and a sense current Idsn proportional to the drain current Id of the semiconductor element 5 flows through the sense cell 701 (Idsn <Id)。

[0123] The resistor element 702 is connected in series with the sense cell 701 so that the sense current Idsn passes through it. As a result, a voltage Vdsn proportional to the sense current Idsn, i.e., the drain current Id, is generated across the resistor element 702. The amplifier 703 amplifies the voltage Vdsn across the resistor element 702 and outputs a voltage Vsig. As a result, the voltage Vsig is also proportional to the drain current Id. In this way, the resistor element 702 and the amplifier 703 can form one embodiment of a "voltage conversion unit."

[0124] Similar to comparator 609 (FIG. 2), comparator 705 generates short circuit detection signal Soc based on the comparison result between voltage Vsig and determination voltage Vt. As a result, when Vsig>Vt, a short circuit state in which an overcurrent occurs in semiconductor element 5 is detected, and short circuit detection signal Soc is set to H level. The protection operation in response to short circuit detection signal Soc is similar to that in embodiment 1, and detailed description thereof will not be repeated.

[0125] In FIG. 10, the first embodiment is combined with the fourth embodiment, which detects a short-circuit state based on the drain current. However, the third embodiment can also be combined with the fourth embodiment.

[0126] That is, in the short circuit detection circuit 700 of FIG. 10, by generating the determination voltage Vt in the same manner as in the third embodiment, it is possible to combine the third and fourth embodiments.

[0127] Embodiment 5. Furthermore, in the first to fourth embodiments, an example has been described in which the driving state of the semiconductor element 5 is classified based on the time elapsed from the start timing of turn-on. However, it is also possible to classify the driving state of the semiconductor element 5 related to the protection control, i.e., to distinguish between the above-mentioned turn-on period and the steady-on period, based on other parameter values, for example, the gate voltage (Vgs) or the gate current.

[0128] FIG. 11 is a circuit diagram illustrating a configuration example of a driving device 10E according to the fifth embodiment. 11, the driving device 10E includes a driving circuit 100A, a delay circuit 200B, a selection circuit 300A, and a protection circuit 400A. A 1. Each of these corresponds to an example of the drive circuit 100, the delay circuit 200, the selection circuit 300, and the protection circuit 400 in FIG.

[0129] That is, the driving device 10E differs from the driving device 10A shown in Fig. 2 in that it includes a delay circuit 200B instead of the delay circuit 200A. The delay circuit 200B generates a delayed gate signal Sgd equivalent to that in Fig. 2 by a method different from that of the delay circuit 200A. 5 In the driving device 10E according to the present embodiment, the configuration for generating the delayed gate signal Sgd for distinguishing the turn-on period from the steady-on period differs from that of the first embodiment (driving device 10A), while the other configurations and the contents of the protection operations during the turn-on period and the steady-on period are the same as those of the first embodiment.

[0130] The delay circuit 200B includes a comparator 215. The comparator 215 outputs a delay gate signal Sgd based on a comparison result between the gate voltage Vgs of the semiconductor element 5 and a reference value Vst equivalent to the output voltage of the power supply 212. The delay gate signal Sgd is input to the inverting buffer 301 and the non-inverting buffer 302 of the selection circuit 300A, similar to the first embodiment.

[0131] The comparator 215 sets the delay gate signal Sgd to an L level when Vgs≦Vst, and sets it to an H level when Vgs>Vst.

[0132] Fig. 12 shows an operational waveform diagram when the semiconductor element is turned on by the driving device 10E shown in Fig. 11. The solid and dotted waveforms of the driving voltage Vdv, gate voltage Vgs, drain current Id, drain voltage Vds, and voltage Vsig shown in Fig. 12 are the same as those in Fig. 3. Fig. 12 differs from Fig. 3 in that it shows the transition of the delayed gate signal Sgd according to the gate voltage Vgs.

[0133] 12, the gate voltage Vgs starts to change from the second voltage V2 to the first voltage V1 at the start timing (time t1) of turn-on, passes through a mirror period, and then rises to the first voltage V1.

[0134] By setting reference value Vst input to comparator 215 to a value slightly lower than voltage 8 (i.e., first voltage V1) in the steady on state of gate voltage Vgs, it becomes possible to distinguish between the turn-on period and the steady on period, as in embodiments 1 to 4. As described above, in driving device 10E according to embodiment 5, the circuit operation during each of the turn-on period and the steady on period is the same as that of embodiment 1 (driving device 10A) both in normal operation and when a short-circuit state occurs, and therefore detailed description will not be repeated.

[0135] Since the gate voltage Vgs changes due to charging and discharging of the gate capacitance of the semiconductor element 5 by the gate current Ig shown in Fig. 10, it is also possible to divide the turn-on period and steady-on section according to the driving state of the semiconductor element 5 from the change in the gate current Ig corresponding to the transition of the gate voltage Vgs shown in Fig. 11. In this case, an input voltage proportional to the gate current Ig is input to the comparator 215, and the reference value Vst is set according to the characteristics of the gate current Ig at the time of turn-on.

[0136] The delay circuit 200B shown in FIG. 10 can be arranged in place of the delay circuit 200A in the second to fourth embodiments as well, and the fifth embodiment can be combined with the second to fourth embodiments.

[0137] In this manner, with regard to the multiple embodiments described above, we would like to confirm that it is intended from the beginning of the application that the configurations described in each embodiment may be appropriately combined, including combinations not mentioned in the specification, to the extent that no inconsistencies or contradictions arise.

[0138] 1, as exemplified in the first to fifth embodiments, at least a part of the functions of each circuit can be configured by an integrated circuit (IC) such as a field programmable gate array (FPGA) having a program capable of performing the same operation. That is, each circuit element described in the present embodiment can be arbitrarily configured by at least one of hardware processing and software processing, as long as it has the same function.

[0139] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0140] 5 Semiconductor element, 10, 10A to 10E Drive device, 100, 100A, 100D Drive circuit, 101, 102, 608, 704 Power supply, 103, 103D Switching control circuit, 105, 107, 503, 607, 613 Switching element, 200, 200A, 403 Delay circuit, 203 Trigger circuit, 300, 300A, 300B Selection circuit, 301 Inverting buffer, 302 Non-inverting buffer, 400, 400A to 400D Protection circuit, 401, 402 Logic gate, 500 Soft cutoff circuit, 502, 602 Diode, 600A to 600C, 700 Short circuit detection circuit, 609, 705 Comparator, 701 Sense cell, 703 Amplifier, Id Drain current, Idsn Sense current, N1 to N3 nodes, Ng gate node, Nn negative power supply node, Np power supply node, S1, S2 selection signals, Sa, Sb, Sbd, Sc, Scn control signal, Sg gate signal, Sgd delayed gate signal, Soc short circuit detection signal, T1, TX delay time, V1 first voltage, V2 second voltage, V3 third voltage, Vds drain voltage, Vdv drive voltage, Vgs gate voltage, Vt judgment voltage.

Claims

1. A drive device for a semiconductor element in which a current flowing from a first main electrode to a second main electrode is controlled in response to a voltage of a control electrode, a drive circuit for outputting to the control electrode one of a first voltage for turning on the semiconductor element and a second voltage for turning off the semiconductor element in response to a gate signal for controlling on / off of the semiconductor element; a protection circuit for performing a protection operation of turning off the semiconductor element when an abnormality occurs during an ON period of the semiconductor element; a selection circuit that switches a mode of the protection operation by the protection circuit in response to a drive state of the semiconductor element in response to a turn-on command; the selection circuit outputs a selection signal to the protection circuit so as to execute a first protection operation when an elapsed time from a timing at which the semiconductor element starts to be turned on in response to the gate signal is equal to or shorter than a predetermined first time during the on-period, and execute a second protection operation when the elapsed time exceeds the first time; the protection circuit controls the drive circuit to output the second voltage to the control electrode in response to detection of an abnormality in the semiconductor element during a first period in which the first protection operation is instructed by the selection signal, while controlling the drive circuit to output the second voltage to the control electrode in response to detection of an abnormality in the semiconductor element during a second period in which the selection signal instructs the second protection operation, after a period in which a third voltage is output to the control electrode; The third voltage is a voltage between the first voltage and the second voltage.

2. A drive device for a semiconductor element in which a current flowing from a first main electrode to a second main electrode is controlled in accordance with a voltage of a control electrode, a drive circuit for outputting to the control electrode one of a first voltage for turning on the semiconductor element and a second voltage for turning off the semiconductor element in response to a gate signal for controlling on / off of the semiconductor element; a protection circuit for performing a protection operation of turning off the semiconductor element when an abnormality occurs during an ON period of the semiconductor element; a selection circuit that switches a mode of the protection operation by the protection circuit in response to a drive state of the semiconductor element in response to a turn-on command; the selection circuit outputs a selection signal to the protection circuit so as to execute a first protection operation during the on-period until the voltage or current of the control electrode reaches a predetermined reference value, and execute a second protection operation after the voltage or current of the control electrode reaches the reference value; the protection circuit controls the drive circuit to output the second voltage to the control electrode in response to detection of an abnormality in the semiconductor element during a first period in which the first protection operation is instructed by the selection signal, while controlling the drive circuit to output the second voltage to the control electrode in response to detection of an abnormality in the semiconductor element during a second period in which the selection signal instructs the second protection operation, after a period in which a third voltage is output to the control electrode; The third voltage is a voltage between the first voltage and the second voltage.

3. The protection circuit includes: a soft interruption circuit for forming a discharge path from the control electrode via a resistive element; 3. The drive device according to claim 1, wherein in the second protection operation, the protection circuit activates the soft shutdown circuit in response to detection of an abnormality in the semiconductor element to form the discharge path, thereby providing a period during which the third voltage is output to the control electrode.

4. The protection circuit includes: a short circuit detection circuit that detects a short circuit state of the semiconductor element based on a current or a voltage of the first main electrode; The driving device according to any one of claims 1 to 3, wherein when the short circuit state is detected by the short circuit detection circuit, the protection circuit detects an abnormality in the semiconductor element and performs the first protection operation or the second protection operation in response to the selection signal from the selection circuit.

5. The short circuit detection circuit includes: a filter circuit having an input voltage being a voltage at a node at which a divided voltage of the voltage of the first main electrode is generated; a comparator for comparing an output voltage of the filter circuit with a determination voltage; 5. The drive device according to claim 4, wherein the short circuit detection circuit detects the short circuit state when the output voltage is higher than the determination voltage.

6. 6. The drive device according to claim 5, wherein a time constant of said filter circuit is switched in response to said selection signal from said selection circuit so that the time constant of said filter circuit is smaller in said second period than in said first period.

7. The short circuit detection circuit includes: a current-voltage converter that outputs a voltage according to a current of the first main electrode; a comparator that compares the output voltage of the current-voltage converter with a determination voltage; 5. The drive device according to claim 4, wherein the short circuit detection circuit detects the short circuit state when the output voltage is higher than the determination voltage.

8. 8. The drive device according to claim 5, wherein the determination voltage is switched in response to the selection signal from the selection circuit so that the determination voltage is lower in the second period than in the first period.

9. 5. The drive device according to claim 4, wherein the short circuit detection circuit is configured such that a detection speed of the short circuit state in response to an increase in current or voltage of the first main electrode during the second period is higher than the detection speed during the first period.

10. A method for driving a semiconductor element in which a current flowing from a first main electrode to a second main electrode is controlled in response to a voltage of a control electrode, comprising the steps of: outputting a first voltage to the control electrode in response to a turn-on command of the semiconductor device for turning on the semiconductor device; executing a protection operation of turning off the semiconductor element when an abnormality occurs during an on-period of the semiconductor element; and switching the mode of the protection operation in response to a drive state of the semiconductor element in response to the turn-on command, The step of performing the protective operation includes: a step of executing a first protection operation of outputting a second voltage to the control electrode for turning off the semiconductor element in response to detection of an abnormality in the semiconductor element during a first period during which an elapsed time from a timing when the turn-on of the semiconductor element is started in response to a gate signal that controls the on / off of the semiconductor element is equal to or shorter than a predetermined first time during the on-period; and executing a second protection operation of outputting the second voltage to the control electrode in response to detection of an abnormality in the semiconductor element, after providing a period during which a third voltage is output to the control electrode in a second period during which the elapsed time exceeds the first time, of the on-period; The driving method, wherein the third voltage is a voltage between the first voltage and the second voltage.

11. A method for driving a semiconductor element in which a current flowing from a first main electrode to a second main electrode is controlled in response to a voltage of a control electrode, comprising: outputting a first voltage to the control electrode in response to a turn-on command of the semiconductor device for turning on the semiconductor device; executing a protection operation of turning off the semiconductor element when an abnormality occurs during an on-period of the semiconductor element; and switching the mode of the protection operation in response to a drive state of the semiconductor element in response to the turn-on command, The step of performing the protective operation includes: executing a first protection operation of outputting a second voltage to the control electrode for turning off the semiconductor element in response to detection of an abnormality in the semiconductor element during a first period during the on-period until a voltage or a current of the control electrode reaches a predetermined reference value; and executing a second protection operation of outputting the second voltage to the control electrode in response to detection of an abnormality in the semiconductor element after a period during which a third voltage is output to the control electrode during the on-period after the voltage or current of the control electrode has reached the reference value, The driving method, wherein the third voltage is a voltage between the first voltage and the second voltage.

12. The step of performing the protective operation includes: detecting a short circuit state of the semiconductor element based on a current or a voltage of the first main electrode; 12. The driving method according to claim 10, wherein when the short-circuit state is detected, an abnormality in the semiconductor element is detected, and the first protective operation or the second protective operation is executed.

13. The step of performing the protective operation includes: The driving method according to claim 12 , further comprising the step of increasing a speed of detection of the short circuit condition with respect to an increase in current or voltage of the first main electrode at the end of the first period.

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