Semiconductor integrated circuit, semiconductor memory device, and memory system

Abstract

To provide a semiconductor integrated circuit, a semiconductor storage device, and a memory system capable of improving measurement resolution of a pulse signal while suppressing an area and power consumption.SOLUTION: Included are: a delay line group 530 having a plurality of delay lines 53β which have a plurality of flip flops 531_β with a delay amount Tw serially connected; a delay element group 540 which generates a plurality of output clock signals having a smaller delay difference in a second delay amount than in the delay amount Tw; and a delay part 55 which is capable of setting a smaller third delay amount than the second delay amount. The delay element group 540 and the delay part 55 are serially connected together between an output terminal of an input signal CLK_DET and an input terminal of the delay line group 530.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor integrated circuit, a semiconductor memory device, and a memory system. [Background technology]

[0002] 2. Description of the Related Art Semiconductor integrated circuits that measure the period of pulse signals such as clocks, and semiconductor memory devices and memory systems that include such integrated circuits are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-169826 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present embodiment is to provide a semiconductor integrated circuit, a semiconductor memory device, and a memory system that can increase the measurement resolution of a pulse signal while suppressing the area and current consumption. [Means for solving the problem]

[0005] The semiconductor integrated circuit of this embodiment includes a first delay circuit having a plurality of delay element groups, each of which has a first delay amount connected in series, a second delay circuit that generates a plurality of output clock signals having a delay difference of a second delay amount smaller than the first delay amount from an input clock signal, and a variable delay circuit that can set a third delay amount smaller than the second delay amount. The second delay circuit and the variable delay circuit are connected in series between an output terminal of a reference clock and an input terminal of the first delay circuit. [Brief description of the drawings]

[0006] [Figure 1]FIG. 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment of the present invention. [Diagram 2] 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention; [Diagram 3] FIG. 2 is a block diagram showing a configuration example of a DCC circuit. [Figure 4] FIG. 2 is a block diagram showing a configuration example of a DCD circuit. [Diagram 5] FIG. 4 is a circuit diagram showing an example of a delay element array circuit. [Figure 6] FIG. 2 is a circuit diagram showing an example of an edge detection circuit according to the first embodiment. [Figure 7] FIG. 2 is a block diagram showing a configuration example of a DCA circuit. [Figure 8] FIG. 4 is a circuit diagram showing a configuration example of a delay block circuit. [Figure 9] FIG. 4 is a circuit diagram showing a configuration example of a FINE delay circuit. [Figure 10] FIG. 4 is a circuit diagram showing a configuration example of a waveform generating circuit. [Figure 11] 4 is a timing chart illustrating an example of an operation of the DCC circuit. [Figure 12] 4 is a timing chart illustrating an example of the operation of a DCD circuit. [Figure 13A] 4 is a timing chart illustrating an example of the operation of a DCD circuit. [Figure 13B] 4 is a timing chart illustrating an example of the operation of a DCD circuit. [Figure 14] 4 is a flowchart illustrating the operation of an arithmetic circuit. [Figure 15] FIG. 4 is a waveform diagram showing an example of an input clock and an output clock of a DCC circuit. [Figure 16] Example values ​​of the code signal DN_F. [Figure 17] Example values ​​for the code signal DN_C. [Figure 18] Example values ​​for the code signal DN_FD. [Figure 19] Example values ​​of the code signal DN_CD. [Figure 20] 4 is a timing chart illustrating an operation of a FINE delay circuit. [Figure 21]13 is a diagram showing the relationship between the code signals DN_FD and DN_FDB and the delay times of the clocks FOUTB_EVN and FOUTB_ODD. [Figure 22] FIG. 2 illustrates an example of one state during operation of the COURSE delay circuit. [Figure 23] 23 is a timing chart illustrating the operation of the COURSE delay circuit in the state of FIG. 22; [Figure 24] FIG. 2 illustrates an example of one state during operation of the COURSE delay circuit. [Diagram 25] 25 is a timing chart illustrating the operation of the COURSE delay circuit in the state of FIG. 24; [Figure 26] 5 is a timing chart illustrating an example of an operation of the waveform generating circuit. [Figure 27] FIG. 4 is a circuit diagram showing an example of an edge detection circuit of a comparative example. [Figure 28] FIG. 11 is a circuit diagram showing an example of an edge detection circuit according to a second embodiment. [Figure 29] FIG. 1 is a circuit diagram showing an example of a PI circuit. [Figure 30A] FIG. 1 is a circuit diagram illustrating an example of the operation of a PI circuit. [Figure 30B] FIG. 1 is a circuit diagram illustrating an example of the operation of a PI circuit. [Diagram 31] 4 is a timing chart illustrating an example of the operation of a PI circuit. [Diagram 32] FIG. 13 is a block diagram showing an example of the configuration of a DLL circuit according to a third embodiment. [Diagram 33] 13 is a timing chart illustrating an example of the operation of the DCD circuit in the third embodiment. [Diagram 34] 4 is a timing chart illustrating phase adjustment of a clock signal in DDR communication. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. (First embodiment) (1. Composition) (1-1. Memory system configuration) 1 is a block diagram showing a configuration example of a memory system according to an embodiment of the present invention. The memory system of this embodiment includes a memory controller 1 and a semiconductor memory device 2. The memory system can be connected to a host. The host is, for example, an electronic device such as a personal computer or a mobile terminal.

[0008] The semiconductor storage device 2 includes a memory that stores data in a nonvolatile manner (hereinafter, referred to as nonvolatile memory). The nonvolatile memory is, for example, a NAND memory (NAND flash memory) having memory cells capable of storing 3 bits per memory cell, that is, a 3-bit / cell (TLC: Triple Level Cell) NAND memory. The nonvolatile memory 2 may be a 1-bit / cell, 2-bit / cell, or 4-bit / cell NAND memory.

[0009] The memory controller 1 controls writing of data to the semiconductor memory device 2 in accordance with a write request from the host. The memory controller 1 also controls reading of data from the semiconductor memory device 2 in accordance with a read request from the host. Signals transmitted and received between the memory controller 1 and the semiconductor memory device 2 include a chip enable signal / CE, a ready / busy signal / RB, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals RE, / RE, a write protect signal / WP, a signal DQ<7:0> which is data, and data strobe signals DQS, / DQS. In this specification, the symbol " / " before the name of a signal indicates the inverted logic of the signal without the symbol " / ".

[0010] For example, the semiconductor memory device 2 and the memory controller 1 are each formed as a semiconductor chip (hereinafter, simply referred to as a "chip").

[0011] The chip enable signal / CE is a signal for enabling the semiconductor memory device 2. The ready-busy signal / RB is a signal for indicating whether the semiconductor memory device 2 is in a ready state (a state in which an external command can be accepted) or a busy state (a state in which an external command cannot be accepted). The command latch enable signal CLE is a signal for indicating that the signal DQ<7:0> is a command. The address latch enable signal ALE is a signal for indicating that the signal DQ<7:0> is an address. The write enable signal / WE is a signal for loading a received signal into the semiconductor memory device 2, and is asserted by the memory controller 1 each time a command, address, and data are received. The write enable signal / WE instructs the semiconductor memory device 2 to load the signal DQ<7:0> while it is at the "L (Low)" level.

[0012] The read enable signals RE and / RE are signals for the memory controller 1 to read data from the semiconductor memory device 2. For example, they are used to control the operation timing of the semiconductor memory device 2 when outputting the signal DQ<7:0>. The write protect signal / WP is a signal for instructing the semiconductor memory device 2 to prohibit data writing and erasing. The signal DQ<7:0> is the substance of data transmitted and received between the semiconductor memory device 2 and the memory controller 1, and includes a command, an address, and data. The data strobe signals DQS and / DQS are signals for controlling the timing of input and output of the signal DQ<7:0>.

[0013] The memory controller 1 includes a RAM (Random Access Memory) 11, a processor 12, a host interface circuit 13, an ECC (Error Check and Correct) circuit 14, and a memory interface circuit 15. The RAM 11, the processor 12, the host interface circuit 13, the ECC circuit 14, and the memory interface circuit 15 are connected to each other via an internal bus 16.

[0014] The host interface circuit 13 outputs requests, user data (write data), etc. received from the host to the internal bus 16. In addition, the host interface circuit 13 transmits user data read from the semiconductor memory device 2, responses from the processor 12, etc. to the host.

[0015] The memory interface circuit 15 controls the process of writing user data and the like to the semiconductor memory device 2 and the process of reading user data and the like from the semiconductor memory device 2 based on instructions from the processor 12 .

[0016] The processor 12 performs overall control of the memory controller 1. The processor 12 is, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the processor 12 receives a request from the host via the host interface circuit 13, the processor 12 instructs the memory interface circuit 15 to write user data and parity to the semiconductor memory device 2 in accordance with the request. The processor 12 also instructs the memory interface circuit 15 to read the user data and parity from the semiconductor memory device 2 in accordance with the request from the host.

[0017] The processor 12 performs the following operations on the user data stored in the RAM 11: The memory controller 1 determines a storage area (memory area) on the semiconductor memory device 2. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for data (page data) in units of pages, which are writing units. In this specification, the user data stored in one page of the semiconductor memory device 2 is defined as unit data. The unit data is generally encoded by the ECC circuit 14 and stored in the semiconductor memory device 2 as a code word. In this embodiment, encoding is not essential. The memory controller 1 may store the unit data in the semiconductor memory device 2 without encoding, but FIG. 1 shows a configuration in which encoding is performed as an example. When the memory controller 1 does not encode, the page data matches the unit data. In addition, one code word may be generated based on one unit data, or one code word may be generated based on divided data obtained by dividing the unit data. In addition, one code word may be generated using multiple unit data.

[0018] The processor 12 determines a memory area of ​​the semiconductor memory device 2 to which the unit data is to be written for each unit data. A physical address is assigned to the memory area of ​​the semiconductor memory device 2. The processor 12 manages the memory area to which the unit data is to be written using the physical address. The processor 12 instructs the memory interface circuit 15 to specify the determined memory area (physical address) and write the user data to the semiconductor memory device 2. The processor 12 manages the correspondence between the logical address of the user data (logical address managed by the host) and the physical address. When the processor 12 receives a read request including a logical address from the host, it identifies the physical address corresponding to the logical address and instructs the memory interface circuit 15 to read the user data by specifying the physical address.

[0019] The ECC circuit 14 generates a codeword by encoding the user data stored in the RAM 11. The ECC circuit 14 also decodes the codeword read from the semiconductor memory device 2.

[0020] The RAM 11 temporarily stores user data received from the host before storing the data in the semiconductor memory device 2, and temporarily stores data read from the semiconductor memory device 2 before transmitting the data to the host. The RAM 11 is a general-purpose memory such as, for example, an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0021] 1 shows an example of a configuration in which the memory controller 1 includes the ECC circuit 14 and the memory interface circuit 15, but the ECC circuit 14 may be built into the memory interface circuit 15. Also, the ECC circuit 14 may be built into the semiconductor memory device 2.

[0022] When a write request is received from the host, the memory system operates as follows. The processor 12 temporarily stores data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface circuit 15. The memory interface circuit 15 writes the input codeword to the semiconductor memory device 2.

[0023] When a read request is received from the host, the memory system operates as follows. The memory interface circuit 15 inputs the codeword read from the semiconductor memory device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface circuit 13. (1-2. Configuration of Semiconductor Memory Device) 2 is a block diagram showing an example of the configuration of a semiconductor memory device according to this embodiment. The semiconductor memory device 2 according to this embodiment includes an interface chip 2A and a non-volatile memory 2B.

[0024] The interface chip 2A has a function of interfacing each of the signals, such as the chip enable signal / CE, the ready / busy signal / RB, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal / WE, the read enable signals RE, / RE, the write protect signal / WP, the signal DQ<7:0> which is data, and the data strobe signals DQS, / DQS, between the memory controller 1 and the nonvolatile memory 2B. The interface chip 2A transfers, for example, the command CMD and the address ADD in the signal DQ<7:0> together with the data strobe signals DQS, / DQS to the nonvolatile memory 2B. Also, for example, the interface chip 2A transmits and receives the write data and read data in the signal DQ<7:0> together with the data strobe signals DQS, / DQS to and from the nonvolatile memory 2B.

[0025] Moreover, the interface chip 2A has a frequency boost function for improving the I / O speed of the nonvolatile memory 2B. For example, the interface chip 2A has a function for transferring a signal input from the memory controller 1 to the nonvolatile memory 2B in a DDR (Double Date Rate) method. When using such a high-speed transfer method, it is necessary to adjust with high precision the duty cycle of a signal (specifically, the read enable signals RE, / RE and the data strobe signals DQS, / DQS) that indicates the timing of transmitting and receiving the signal DQ<7:0> between the memory controller 1 and the nonvolatile memory 2B. The interface chip 2A includes a DCC (Duty Cycle Correction) circuit 20 for adjusting the duty cycle of the read enable signals RE, / RE and the data strobe signals DQS, / DQS.

[0026] More specifically, the interface chip 2A includes a DCC circuit 20a that adjusts the duty cycle of the read enable signals RE, / RE output from the memory controller 1 and input to the nonvolatile memory 2B, and a DCC circuit 20b that adjusts the duty cycle of the data strobe signals DQS, / DQS output from the memory controller 1 and input to the nonvolatile memory 2. The DCC circuit 20b can also adjust the duty cycle of the data strobe signals DQS, / DQS output from the nonvolatile memory 2 and input to the memory controller 1. A detailed configuration of the DCC circuit 20 will be described later.

[0027] The non-volatile memory 2B includes a memory cell array 21, an input / output circuit 22, a logic control circuit 24, a register 26, a sequencer 27, a voltage generation circuit 28, a row decoder 30, a sense amplifier unit 31, a group of input / output pads 32, a group of logic control pads 34, and a group of power input terminals 35.

[0028] The memory cell array 21 includes a plurality of non-volatile memory cell transistors (not shown) associated with word lines and bit lines.

[0029] The input / output circuit 22 transmits and receives the signal DQ<7:0> and the data strobe signals DQS and / DQS to and from the memory controller 1 via the interface chip 2A. The input / output circuit 22 transfers the command and address in the signal DQ<7:0> to the register 26. The input / output circuit 22 also transmits and receives write data and read data to and from the sense amplifier unit 31.

[0030] The logic control circuit 24 receives a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals RE, / RE, and a write protect signal / WP from the memory controller 1 via the interface chip 2A. The logic control circuit 24 also transfers a ready / busy signal / RB to the memory controller 1 via the interface chip 2A to notify the outside of the state of the nonvolatile memory 2B.

[0031] Based on instructions from the sequencer 27, the voltage generation circuit 28 generates voltages necessary for operations such as writing, reading, and erasing data.

[0032] The row decoder 30 receives the block address and row address in the address register 26, selects a corresponding block based on the block address, and selects a corresponding word line based on the row address.

[0033] When reading data, the sense amplifier unit 31 senses read data read from the memory cell transistor to the bit line and transfers the sensed read data to the input / output circuit 22. When writing data, the sense amplifier unit 31 transfers write data to be written via the bit line to the memory cell transistor. The sense amplifier unit 31 has a plurality of sense amplifiers SA.

[0034] The input / output pad group 32 includes a plurality of terminals (pads) corresponding to the signals DQ<7:0> and data strobe signals DQS and / DQS in order to transmit and receive various signals including data to and from the interface chip 2A.

[0035] The logic control pad group 34 has a plurality of terminals (pads) corresponding to a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals RE, / RE, and a write protect signal / WP in order to transmit and receive various signals to and from the interface chip 2A.

[0036] The power input terminal group 35 includes a plurality of terminals for inputting power supply voltages Vcc, VccQ, Vpp, and a ground voltage Vss in order to supply various operating power supplies from the outside to the nonvolatile memory 2B. The power supply voltage Vcc is a circuit power supply voltage that is generally provided from the outside as an operating power supply, and a voltage of, for example, about 3.3 V is input. The power supply voltage VccQ is a voltage of, for example, 1.2 V. The power supply voltage VccQ is used as a power supply for driving an input / output system for transmitting and receiving signals between the memory controller 1 and the nonvolatile memory 2B.

[0037] The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, and for example, a voltage of 12 V is input. For example, when the nonvolatile memory 2B is used in an environment where a high voltage cannot be supplied, no voltage may be supplied to the power supply voltage Vpp. Even when the power supply voltage Vpp is not supplied, the nonvolatile memory 2B can perform various operations as long as the power supply voltage Vcc is supplied. In other words, the power supply voltage Vcc is a power supply that is normally supplied to the nonvolatile memory 2B, and the power supply voltage Vpp is a power supply that is additionally or optionally supplied depending on, for example, the usage environment.

[0038] When reading data, the sense unit 24 detects data read from the NAND memory cell array 23. When writing data, the sense unit 24 temporarily stores write data input from the memory controller 1 via the interface chip 2 and transfers it to the NAND memory cell array 23. (1-3. DCC circuit configuration) 3 is a block diagram showing an example of the configuration of a DCC circuit 20 according to an embodiment of the present invention. The DCC circuit 20 includes a DCD (Duty Cycle Detector) circuit 41, an arithmetic circuit 42, a DCA (Duty Cycle Adjuster) circuit 43, and a waveform generating circuit 44.

[0039] The DCD circuit 41 is a circuit that observes the duty error of the clock signal that is the target of duty correction and converts it into the number of stages of delay elements. The DCD circuit 41 detects (measures) the pulse width of the input clock DCD_IN (period during which it is at high level) and the pulse width of the input clock / DCD_IN, and outputs a signal DCD_CODE that indicates the pulse width of the input clock DCD_IN and the pulse width of the input clock / DCD_IN. The signal DCD_CODE has multiple bits (for example, 32 bits).

[0040] The arithmetic circuit 42 is a circuit that calculates a delay setting value of a clock signal to be subjected to duty correction based on the output signal from the DCD circuit 41. The arithmetic circuit 42 receives the signal DCD_CODE output from the DCD circuit 41, and compares the pulse width of the input clock DCD_IN with the pulse width of the input clock / DCD_IN. Then, based on the comparison result, the arithmetic circuit 42 generates a signal DCA_CODE.

[0041] The DCA circuit 43 generates a delayed clock CDLY_T of the input clock IN, which is a duty correction target, and a delayed clock CDLY_B of the input clock / IN, based on the signal DCA_CODE.

[0042] The waveform generating circuit 44 receives the delayed clocks CDLY_T, CDLY_B output from the DCA circuit 43, and generates the output clocks OUT, / OUT. That is, the output clocks OUT, / OUT are output signals after the duty cycle of the input clocks IN, / IN has been adjusted. The output clocks OUT, / OUT generated in the waveform generating circuit 44 are output from the DCC circuit 20 and input to the DCD circuit 41. (1-3-1. DCD circuit configuration) 4 is a block diagram showing an example of the configuration of a DCD circuit. The DCC circuit 41 of the embodiment includes a signal generating circuit 51, a delay element array circuit 52, and an edge detecting circuit 53.

[0043] Input clocks DCD_IN and / DCD_IN are input to the signal generation circuit 51. The signal generation circuit 51 generates signals CLK_DLY and CLK_DET from the input clocks DCD_IN and / DCD_IN.

[0044] The high-level period of the signal CLK_DLY and the high-level period of the signal CLK_DET are set to the same length as one period of the input clock DCD_IN (=the same length as one period of the input clock / DCD_IN).

[0045] The rising edges of the signal CLK_DLY in even-numbered cycles are set to coincide with the rising edges of the input clock DCD_IN, and the rising edges of the signal CLK_DLY in odd-numbered cycles are set to coincide with the rising edges of the input clock / DCD_IN.

[0046] The rising edges of the signal CLK_DET in even-numbered cycles are set to coincide with the falling edges of the input clock DCD_IN, and the rising edges of the signal CLK_DET in odd-numbered cycles are set to coincide with the falling edges of the input clock / DCD_IN.

[0047] That is, the signals CLK_DLY and CLK_DET are generated so that the period from the rising edge of the signal CLK_DLY in an even-numbered cycle to the rising edge of the signal CLK_DET is the same length as the high-level period of the input clock DCD_IN, and the period from the rising edge of the signal CLK_DLY in an odd-numbered cycle to the rising edge of the signal CLK_DET is the same length as the high-level period of the input clock / DCD_IN. Therefore, by continuously measuring the period from the rising edge of the input clock DCD_IN to the rising edge of the input clock DCD_IN, the high-level period of the input clock DCD_IN and the high-level period of the input clock / DCD_IN can be observed alternately.

[0048] In addition, in the signals CLK_DLY and CLK_DET, the period from the rising edge of the nth cycle to the rising edge of the (n+1)th cycle is set to be a sufficient period from measuring the high level period of the input clock DCD_IN or / DCD_IN to generating DCD_CODE.

[0049] The delay element array circuit 52 generates an n-bit (n is a natural number equal to or greater than 2) signal Dn (D1 to Dn) using the signal CLK_DLY input from the signal generation circuit 51. The set of signals Dn is latched by an edge detection circuit 53 (described later) to indicate the pulse width or period of the input clock.

[0050] FIG. 5 is a circuit diagram showing an example of a delay element array circuit. The delay element array circuit 52 includes n delay elements 521_1 to 521_n. In each case where α (α is a natural number between 1 and n) is between 1 and n, the delay element 521_α receives a signal D(α-1) and outputs a signal Dα. Note that the signal D0 is a signal equal to the signal CLK_DLY. Hereinafter, notations including "α" collectively indicate all cases where α is between 1 and n. That is, notations including "α" collectively indicate the cases where α is 1, α is 2, ..., α is n. The signal Dα is a signal obtained by delaying the signal D(α-1) by a certain time. The delay element 521_α receives the signal CLK_DLY, holds the logic level of the signal Dα when the signal CLK_DLY transitions to a high level, and continues to output the signal Dα at the same logic level as the logic level of the held signal Dα.

[0051] The delay amount in each of the delay elements 521_1 to 521_n may vary due to unintended variations in the performance of the delay elements 521_1 to 521_n, but is intended to be time Tw. In the following description, the delay amounts of the delay elements 521_1 to 521_n are assumed to be the same time Tw. The delay element 521_α includes, for example, three NAND gates. The first NAND gate receives a signal D(α-1) at one input. The first NAND gate is also grounded at another input, that is, connected to a node of the ground potential Vss. The second NAND gate is grounded at two inputs, that is, connected to a node of the ground potential Vss. The third NAND gate receives the output of the first NAND gate and the output of the second NAND gate, and outputs a signal Dα. The delay element 521_α generates a delay of time Tw.

[0052] The edge detection circuit 53 as the semiconductor integrated circuit of this embodiment receives the signals D1 to Dn output from the delay element array circuit 52 and the signal CLK_DET output from the signal generation circuit 51, and outputs a signal DCD_CODE. FIG. 6 is a circuit diagram showing an example of the edge detection circuit of the first embodiment. The edge detection circuit 53 has a delay line group 530 as a first delay circuit. The delay line group 530 includes m (m is a natural number of 2 or more) delay lines 531 to 53m (delay element group). Each delay line 53β (β is a natural number of 1 to m) includes n D-type flip-flops (hereinafter simply referred to as flip-flops) 53β_1 to 53β_n as first delay elements. Hereinafter, notation including "β" collectively indicates all cases where β is a value of 1 to m. That is, notation including "β" collectively indicates the case where β is 1, the case where β is 2, ..., the case where β is m. The edge detection circuit 53 also has a delay element group 540 as a second delay circuit. The delay element group 540 also includes m delay elements 54β (third delay elements). The delay amount of each delay element 54β is set to be the time {1.0+(β-1) / m}×Tw.

[0053] Moreover, the edge detection circuit 53 has a delay unit 55 that generates an input signal CLK_DETa to the delay element 54β. The delay unit 55 as a variable delay circuit includes s delay elements 55δ (δ is a natural number between 1 and s) and a selector 56. Hereinafter, notation including "δ" collectively indicates the case where δ is 1, the case where δ is 2, ..., the case where δ is s. The delay amount of each delay element 55δ is set to be the time {1.0+(δ-1) / (m×s)}×Tw.

[0054] Each delay element 55δ (second delay element) receives the signal CLK_DET output from the signal generating circuit 51, delays it by a set time, and outputs it to the selector 56. The delay element 55δ includes, for example, three NAND gates. The first NAND gate receives the signal CLK_DET at one input. The first NAND gate has another input grounded, that is, connected to a node of the ground potential Vss. The second NAND gate has two inputs grounded, that is, connected to a node of the ground potential Vss. The third NAND gate receives the output of the first NAND gate and the output of the second NAND gate, and outputs the signal CLK_DETaδ. The delay element 55δ generates a delay of time {1.0+(δ-1) / (m×s)}×Tw. The selector 56 selects and outputs one signal from the signals CLK_DETaδ input from the s delay elements 55δ.

[0055] Each delay element 54β receives the signal CLK_DETa output from the selector 56, delays it by a set time, and outputs it to the delay line 53β. The delay element 54β includes, for example, three NAND gates. The first NAND gate receives the signal CLK_DETa at one input. The first NAND gate also has another input grounded, i.e., connected to a node at the ground potential Vss. The second NAND gate has two inputs grounded, i.e., connected to a node at the ground potential Vss. The third NAND gate receives the output of the first NAND gate and the output of the second NAND gate, and outputs the signal CLK_DETm. The delay element 54β generates a delay of time {1.0+(β-1) / m}×Tw.

[0056] 6 shows an edge detection circuit 53 in the case of s=2 and m=4 as an example. The delay amount of the delay element 551 is time {1.0+(1-1) / (4×2)}Tw=1.0Tw. The delay element 551 receives the signal CLK_DET, delays it by time 1.0Tw, and outputs the signal CLK_DETa1. The delay amount of the delay element 552 is time {1.0+(2-1) / (4×2)}Tw=1.125Tw. The delay element 552 receives the signal CLK_DET, delays it by time 1.125Tw, and outputs the signal CLK_DETa2. The selector receives the signal CLK_DETa1 and the signal CLK_DETa2, and outputs one of the signals (signal CLK_DETa).

[0057] The delay amount of the delay element 541 is time {1.0+(1-1) / 4}Tw=1.0Tw. The delay element 541 receives the signal CLK_DETa, delays it by time 1.0Tw, and outputs the signal CLK_DET1. The delay amount of the delay element 542 is time {1.0+(2-1) / 4}Tw=1.25Tw. The delay element 542 receives the signal CLK_DETa, delays it by time 1.25Tw, and outputs the signal CLK_DET2. The delay amount of the delay element 543 is time {1.0+(3-1) / 4}Tw=1.5Tw. The delay element 543 receives the signal CLK_DETa, delays it by time 1.5Tw, and outputs the signal CLK_DET3. The delay amount of the delay element 544 is time {1.0+(4-1) / 4}Tw=1.75Tw. A delay element 544 receives the signal CLK_DETa, delays it by a time 1.75Tw, and outputs a signal CLK_DET4.

[0058] When the selector 56 selects the signal CLK_DETa1, the signal CLK_DETa is a signal obtained by delaying the signal CLK_DET by a time of 1.0Tw. In this case, the signal CLK_DET1 is a signal obtained by delaying the signal CLK_DET by a time of (1.0+1.0)Tw=2.0Tw. The signal CLK_DET2 is a signal obtained by delaying the signal CLK_DET by a time of (1.0+1.25)Tw=2.25Tw. The signal CLK_DET3 is a signal obtained by delaying the signal CLK_DET by a time of (1.0+1.5)Tw=2.5Tw. The signal CLK_DET4 is a signal obtained by delaying the signal CLK_DET by a time of (1.0+1.75)Tw=2.75Tw.

[0059] When the selector 56 selects the signal CLK_DETa2, the signal CLK_DETa is a signal obtained by delaying the signal CLK_DET by a time of 1.125Tw. In this case, the signal CLK_DET1 is a signal obtained by delaying the signal CLK_DET by a time of (1.125+1.0)Tw=2.125Tw. The signal CLK_DET2 is a signal obtained by delaying the signal CLK_DET by a time of (1.125+1.25)Tw=2.375Tw. The signal CLK_DET3 is a signal obtained by delaying the signal CLK_DET by a time of (1.125+1.5)Tw=2.625Tw. The signal CLK_DET4 is a signal obtained by delaying the signal CLK_DET by a time of (1.125+1.75)Tw=2.875Tw.

[0060] The flip-flop 53β_α of the delay line 53β receives the signal Dα output from the delay element 521_α of the delay element array circuit 52 at its data input, receives the signal CLK_DETβ at its clock input, and outputs a signal Fβα. For example, the flip-flop 531_1 of the delay line 531 receives the signal D1 at its data input, receives the signal CLK_DET1 at its clock input, and outputs a signal F11. The flip-flop 534_n of the delay line 534 receives the signal Dn at its data input, receives the signal CLK_DET4 at its clock input, and outputs a signal F4n. That is, the edge detection circuit 53 generates an m×n-bit signal Fmn and outputs it as the signal DCD_CODE. (1-3-2. Configuration of the arithmetic circuit) The arithmetic circuit 42 is a circuit that calculates a delay setting value of a clock signal to be subjected to duty correction based on an output signal from the DCD circuit 41. The arithmetic circuit 42 receives the signal DCD_CODE output from the DCD circuit 41, and compares the pulse width (high level period) of the input clock DCD_IN with the pulse width (high level period) of the input clock / DCD_IN. Then, based on the comparison result, the arithmetic circuit 42 generates a signal DCA_CODE. The code signal DCA_CODE is composed of code signals DN_F and DN_C for correcting the timing of the rising edge of the input clock IN, and code signals UP_F and UP_C for correcting the timing of the rising edge of the input clock / IN. The code signal DCA_CODE is output, for example, in the order of a (m×s+1)-bit code signal DN_F, a 1-bit code signal DN_C, a (m×s+1)-bit code signal UP_F, and a 1-bit code signal UP_C. The generation of the signal DCA_CODE in the arithmetic circuit 42 will be described in detail later. (1-3-3. DCA circuit configuration) 7 is a block diagram showing a configuration example of a DCA circuit. The DCA circuit 43 of the embodiment is composed of two delay block circuits 61 and 62. The delay block circuit 61 is a delay circuit that corrects the timing of the rising edge of the input clock IN. The delay block circuit 61 receives the input clock IN and the code signals DN_F and DN_C that constitute the signal DCA_CODE, and generates a delayed clock CDLY_T. The delay block circuit 62 is a delay circuit that corrects the timing of the rising edge of the input clock / IN. The delay block circuit 62 receives the input clock / IN and the code signals UP_F and UP_C that constitute the signal DCA_CODE, and generates a delayed clock CDLY_B.

[0061] First, a description will be given of the delay block circuit 61. Fig. 8 is a circuit diagram showing an example of the configuration of the delay block circuit. The delay block circuit 61 includes two sets of FINE delay circuits 611e and 611o, a COARSE delay circuit 612, and a code control circuit 613.

[0062] The FINE delay circuits 611e and 611о are delay circuits that correct the rising timing of the input clock IN with a resolution of 1.0Tw time or less (specifically, in (1.0 / (m×s))Tw time units). The FINE delay circuits 611e and 611о are delay circuits having four input terminals CKIN_A, CKIN_B, FI_T, and FI_B, and one output terminal CKOUT.

[0063] FIG. 9 is a circuit diagram showing a configuration example of a FINE delay circuit. The FINE delay circuit 611e includes two inverter circuits 614a and 614b. The inverter circuit 614a includes (m×s) P-side switches 71_1, 71_2, ..., 71_(m×s) and one N-side switch 72. FIG. 9 shows the case where s=2 and m=4. The P-side switch 71_ε includes two PMOS transistors connected in series. Hereinafter, notation including "ε" collectively indicates all cases where ε is a value between 1 and (m×s). That is, notation including "ε" collectively indicates the cases where ε is 1, ε is 2, ..., ε is (m×s). The (m×s) P-side switches 71_ε are connected in parallel between the output terminal CKOUT_T of the inverter circuit 614a and a node of the power supply potential Vcc. The N-side switch 72 is configured by connecting two NMOS transistors in series, and is connected between the output terminal CKOUT_T of the inverter circuit 614a and a node of the ground potential Vss.

[0064] Of the two PMOS transistors constituting the P-side switch 71_ε, the gate of the PMOS transistor (hereinafter referred to as the first PMOS transistor) whose drain is connected to the output terminal CKOUT_T of the inverter circuit 614a is connected to the input terminal CKIN_A. The gate of the other PMOS transistor (hereinafter referred to as the second PMOS transistor) constituting the P-side switch 71_ε receives a set 1-bit data of the (m×s)-bit code signal input from the input terminal FI_T. That is, starting from the P-side switch 71 closest to the output terminal CKOUT_T, the 1st bit data, the 2nd bit data, ..., the (m×s)th bit data of the code signal input from the input terminal FI_T are input.

[0065] 9, the first bit of data of the code signal input from the input terminal FI_T is input to the P-side switch 71_8, the second bit of data of the signal is input to the P-side switch 71_7, the third bit of data of the signal is input to the P-side switch 71_6, and the fourth bit of data of the signal is input to the P-side switch 71_5. Furthermore, the fifth bit of data of the signal is input to the P-side switch 71_4, the sixth bit of data of the signal is input to the P-side switch 71_3, the seventh bit of data of the signal is input to the P-side switch 71_2, and the eighth bit of data of the signal is input to the P-side switch 71_1. Specifically, when the 8-bit code signal input from the input terminal FI_T is "11100000," "1 (=H)" is input to the gates of the P-side switches 71_1, 71_2, and 71_3, and "0 (=L)" is input to the gates of the second PMOS transistors of the P-side switches 71_4, 71_5, 71_6, 71_7, and 71_8.

[0066] Of the two NMOS transistors constituting the N-side switch 72, the gate of the NMOS transistor (hereinafter referred to as the first NMOS transistor) whose drain is connected to the output terminal CKOUT_T of the inverter circuit 614a is connected to the input terminal CKIN_A. The gate of the other NMOS transistor (hereinafter referred to as the second NMOS transistor) constituting the N-side switch 72 is connected to the input terminal CKIN_B.

[0067] The inverter circuit 614b is composed of (m×s) P-side switches 73_1, 73_2, ..., 73_(m×s) and one N-side switch 74. The P-side switch 73_ε is composed of two PMOS transistors connected in series. The (m×s) P-side switches 73_ε are connected in parallel between the output terminal CKOUT_B of the inverter circuit 614a and a node of the power supply potential Vcc. As with the P-side switch 71_ε, of the two PMOS transistors constituting the P-side switch 73_ε, the PMOS transistor whose drain is connected to the output terminal CKOUT_B of the inverter circuit 614b is referred to as a first PMOS transistor, and the other PMOS transistor is referred to as a second PMOS transistor. The N-side switch 74 is composed of two NMOS transistors connected in series. The N-side switch 74 is connected between the output terminal CKOUT_B of the inverter circuit 614b and a node of the ground potential Vss. As with the N-side switch 72, of the two NMOS transistors constituting the N-side switch 74, the NMOS transistor whose drain is connected to the output terminal CKOUT_B of the inverter circuit 614b is referred to as the first NMOS transistor, and the other NMOS transistor is referred to as the second NMOS transistor.

[0068] Of the two PMOS transistors constituting the P-side switch 73_ε, the gate of the first PMOS transistor is connected to the input terminal CKIN_B. A set 1-bit data of the (m×s)-bit code signal input from the input terminal FI_B is input to the gate of the second PMOS transistor of the P-side switch 73_ε. That is, starting from the P-side switch 73 closest to the output terminal CKOUT_B, the 1st bit data, the 2nd bit data, ..., the (m×s)th bit data of the code signal input from the input terminal FI_B are input.

[0069] 9, the first bit of data of the code signal input from the input terminal FI_B is input to the P-side switch 73_8, the second bit of data of the signal is input to the P-side switch 73_7, the third bit of data of the signal is input to the P-side switch 73_6, and the fourth bit of data of the signal is input to the P-side switch 73_5. Furthermore, the fifth bit of data of the signal is input to the P-side switch 73_4, the sixth bit of data of the signal is input to the P-side switch 73_3, the seventh bit of data of the signal is input to the P-side switch 73_2, and the eighth bit of data of the signal is input to the P-side switch 73_1. Specifically, when the 8-bit code signal input from input terminal FI_B is "00011111," "1 (=H)" is input to the gates of P-side switches 73_4, 73_5, 73_6, 73_7, and 73_8, and "0 (=L)" is input to the gates of the second PMOS transistors of P-side switches 73_1, 73_2, and 73_3.

[0070] Of the two NMOS transistors constituting the N-side switch 74, the gate of the first NMOS transistor is connected to the input terminal CKIN_B. The gate of the second NMOS transistor of the N-side switch 72 is connected to the input terminal CKIN_A.

[0071] The output terminal CKOUT_T of the inverter circuit 614a and the output terminal CKOUT_B of the inverter circuit 614b are electrically connected. That is, the output terminal CKOUT_T and the output terminal CKOUT_B are shorted. A signal PI_CLKB obtained by merging the output signal from the inverter circuit 614a and the output signal from the inverter circuit 614b is logically inverted by the inverter and output from the output terminal CKOUT.

[0072] The FINE delay circuit 611e receives a signal (clock INB) obtained by inverting the logic of the input clock IN at its input terminal CKIN_A, and receives a signal (clock INB1) obtained by delaying the clock INB by 1.0Tw at its input terminal CKIN_B. The FINE delay circuit 611e also receives a code signal DN_FD at its input terminal FI_T. Furthermore, the FINE delay circuit 611e receives a code signal DN_FDB, which is a signal obtained by inverting the logic of the code signal DN_FD, at its input terminal FI_B.

[0073] FINE delay circuit 611e receives clocks INB, INB1, code signals DN_FD, and DN_FDB, and generates clock FOUTB_EVN. Clock FOUTB_EVN is a signal obtained by delaying the rising edge of input clock IN in the range of 0 to 1.0 TW based on code signals DN_FD and DN_FDB, and then logically inverting the resulting signal.

[0074] The FINE delay circuit 611о receives a signal (clock INB) obtained by inverting the logic of the input clock IN at its input terminal CKIN_B, and receives a signal (clock INB1) obtained by delaying the clock INB by 1.0Tw at its input terminal CKIN_A. The FINE delay circuit 611e receives a code signal DN_FD at its input terminal FI_T. Furthermore, the code signal DN_FDB, which is a signal obtained by inverting the logic of the code signal DN_FD, is input at its input terminal FI_B.

[0075] The FINE delay circuit 611o receives the clocks INB, INB1, code signals DN_FD, and DN_FDB, and generates a clock FOUTB_ODD. The clock FOUTB_ODD is a signal obtained by delaying the rising edge of the input clock IN in the range of 0 to 1.0 TW based on the code signals DN_FD and DN_FDB, and then logically inverting the signal. The generation of the clocks FOUTB_EVN and FOUTB_ODD in the FINE delay circuits 611e and 611o will be described in detail later.

[0076] The code control circuit 613 receives the code signals DN_C and DN_F, and generates a code signal DN_FD to be input to an input terminal FI_T of the FINE delay circuit 611e and an input terminal FI_T of the FINE delay circuit 611o. The code signal DN_FD is an (m×s)-bit thermometer code. The generation of the code signal DN_FD in the code control circuit 613 will be described in detail later.

[0077] The COARSE delay circuit 612 is a delay circuit that corrects the rising timing of the input clock IN in 1.0 Tw time units. The COARSE delay circuit 612 receives the signals FOUTE_EVN, FOUTE_ODD, and the code signal DN_C, and delays either the clock FOUTB_EVN or the clock FOUTB_ODD based on the code signal DN_C by an amount based on the code signal DN_C, and outputs the delayed signal as the output clock CDLYOUT.

[0078] The COARSE delay circuit 612 includes l+1 delay elements 615_0 to 615_l. The delay elements 615_0 to 615_l are arranged in the order of delay elements 615_0, 615_1, 615_2, ..., 615_l from the side closer to the output terminal. In each case of γ (γ is 0 and a natural number between 1 and l) being between 0 and l, the delay element 615_γ includes, for example, three NAND gates. Hereinafter, notation including "γ" refers to all cases in which γ is between 0 and l. That is, notation including "γ" refers to the cases in which γ is 0, γ is 1, ..., γ is l. The delay element 615_γ generates a delay of time 1.0Tw.

[0079] The COARSE delay circuit 612 also includes a code conversion circuit 616. The code conversion circuit 616 receives and decodes the code signal DN_C included in the signal DCA_CODE output from the arithmetic circuit 42, converts the binary code into a thermometer code, and generates a code signal DN_CD. The code signal DN_CD is an 1-bit code signal. For example, when a binary code "100" indicating a decimal number "4" is received as the code signal DN_C, the code conversion circuit 616 generates "0...01111" as the code signal DN_CD. That is, the code conversion circuit 616 generates a code signal DN_CD in which bits from the first bit to the number of bits indicated by the code signal DN_C are set to "1" and the other bits are set to "0". The code conversion circuit 616 outputs the generated code signal DN_CD to the delay element 615.

[0080] The first NAND gate of the delay element 615_γ receives either the clock FOUTB_EVN or the clock FOUTB_ODD at one input. Specifically, when γ is an even number, it receives the clock FOUTB_EVN, and when γ is an odd number, it receives the clock FOUTB_ODD. The first NAND gate also receives the code signal DN_CDγ (the value of the γth bit of the code signal DN_CD) at the other input. However, in the delay element 615_0, the first NAND gate has the other input connected to a node of the power supply potential Vcc.

[0081] The second NAND gate of the delay element 615_γ receives the signal FOUTB_(γ+1) output from the delay element 615_(γ+1) at one input and is connected at another input to a node at the power supply potential Vcc. However, the second NAND gate of the delay element 615_n has two inputs grounded, i.e., connected to a node at the ground potential Vss.

[0082] The third NAND gate of the delay element 615_γ receives the output of the first NAND gate and the output of the second NAND gate, and outputs the signal FOUTB_γ.

[0083] When the value of the code signal DN_CDγ input to the first NAND gate is "0 (=L)", the delay element 615_γ outputs "0 (=L)" as the signal FOUTB_γ. On the other hand, when the value of the code signal DN_CDγ input to the first NAND gate is "1 (=H)" and the value of the code signal DN_CD(γ+1) is "0 (=L), the delay element 615_γ outputs a signal obtained by delaying the signal FOUTB_ODD or FOUTB_EVN input to the first NAND gate by a time of 1.0Tw as the signal FOUTB_γ. When the value of the code signal DN_CDγ is "1 (=H)" and the value of the code signal DN_CD(γ+1) is "1 (=H), the delay element 615_γ outputs a signal obtained by delaying the signal FOUTB_(γ+1) input to the second NAND gate by a time of 1.0Tw as the signal FOUTB_γ. The signal FOUTB_0 output from the delay element 615_0 is output from the COARSE delay circuit 612 as the output clock CDLYOUT.

[0084] The output clock CDLYOUT is logically inverted by an inverter and output from the delay block circuit 61 as the delayed clock CDLY_T.

[0085] The delay block circuit 62 has the same configuration as the above-mentioned delay block circuit 61. However, the input and output signals are different from those of the delay block circuit 61. That is, the delay block circuit 61 receives an input clock IN and code signals DN_F and DN_C that constitute the signal DCA_CODE, and generates a delayed clock CDLY_T, whereas the delay block circuit 62 receives an input clock / IN and code signals UP_F and UP_C that constitute the signal DCA_CODE, and generates a delayed clock CDLY_B.

[0086] The waveform generating circuit 44 is a circuit that generates an output clock OUT that maintains a high level over a period from the rising edge (rising edge) of the delayed clock CDLY_T to the rising edge (rising edge) of the delayed clock CDLY_B. The waveform generating circuit 44 is configured, for example, as a two-input, one-output multiplexer (a multiplexer that outputs the logical product of the delayed clock CDLY_T and the inverted signal of the delayed clock CDLY_B) that receives two signals, the delayed clock CDLY_T and the delayed clock CDLY_B, and outputs the output clock OUT. (1-3-4. Configuration of the waveform generation circuit) 10 is a block diagram showing an example of the configuration of a waveform generating circuit 44 according to an embodiment of the present invention, which includes an inverter INV1, an inverter group INVG1 and INVG2 in which a plurality of inverters are connected in series, PMOS transistors P1 and P2, NMOS transistors N1 and N2, and a latch circuit LAT1.

[0087] The PMOS transistors P2 and P1 and the NMOS transistors N1 and N2 are connected in series. The source of the PMOS transistor P2 is connected to the power supply potential Vcc, and the source of the NMOS transistor N2 is connected to the ground potential Vss. The delayed clock CDLY_B is logically inverted via the inverter IN1 and input to the gate of the PMOS transistor P1 and the inverter group INVG1. The output of the inverter group INVG1 is input to the gate of the PMOS transistor P2. The delayed clock CDLY_T is input to the gate electrode of the NMOS transistor N2 and the inverter group INVG2. The output of the inverter group INVG2 is input to the gate of the NMOS transistor N2.

[0088] The connection point between the drain of the PMOS transistor P1 and the drain of the NMOS transistor N2 is connected to the input of the latch circuit LAT1. The latch circuit LAT2 has a configuration in which two inverters are positively fed back.

[0089] When the delayed clock CDLY_B input to the waveform generation circuit 44 switches from a low level to a high level, the PMOS transistors P1 and P2 turn on, and the power supply potential Vcc is input to the latch circuit LAT1. On the other hand, when the delayed clock CDLY_T input to the waveform generation circuit 44 switches from a low level to a high level, the NMOS transistors N1 and N2 turn on, and the ground potential Vss is input to the latch circuit LAT1. Therefore, the signal (= output clock OUT) output from the latch circuit LAT1 switches from a low level to a high level at the rising edge of the delayed clock CDLY_T, and switches from a high level to a low level at the rising edge of the delayed clock CDLY_B, becoming a clock signal.

[0090] The waveform generation circuit 44 outputs the signal output from the latch circuit LAT1 as the output clock OUT. Also, a signal (output clock / OUT) obtained by inverting the logic of the output clock OUT is generated and output. Note that the output clocks OUT and / OUT are output from the DCC circuit 20 and input to the DCD circuit 41. The output clock OUT is input to the DCD circuit 41 as the input clock DCD_IN, and the output clock / OUT is input to the DCD circuit 41 as the input clock / DCD_IN. (2. Operation) (2-1. Operation of DCC Circuit) FIG. 11 is a timing chart for explaining an example of the operation of the DCC circuit. As shown in FIG. 11, the input clock IN input to the DCC circuit 20 has a certain duty cycle. For example, the duty cycle is not 50%, and the high level period (period CINH) is shorter than the low level period (period CINL). The input clock IN has a period CIN, is high level over the period CINH, and is low level over the period CINL. That is, the input clock IN has the relationship of CIN = CINH + CINL, CINH < CINL.

[0091] The DCD circuit 41 detects the duty of the input clock IN input to the DCC circuit 20 in the first few cycles (for example, 12 cycles). A specific detection method will be described below. First, in the first cycle of the input clock DCD_IN, the selector 56 of the edge detection circuit 53 is set to select the signal CLK_DETa1 output from the delay element 551 and output it as the signal CLK_DETa. The DCD circuit 41 measures the pulse width (high level period) of the first cycle of the input clock DCD_IN, generates a signal DCD_CODE, and outputs it to the arithmetic circuit 42. The DCD circuit 41 also measures the pulse width of the input clock DCD_IN in the fourth cycle, generates a signal DCD_CODE, and outputs it to the arithmetic circuit 42.

[0092] In the seventh cycle of the input clock / DCD_IN, the selector 56 of the edge detection circuit 53 is switched to select the signal CLK_DETa2 output from the delay element 551 and output it as the signal CLK_DETa. The DCD circuit 41 measures the pulse width (high level period) of the eighth cycle of the input clock DCD_IN, generates a signal DCD_CODE, and outputs it to the arithmetic circuit 42. The DCD circuit 41 also measures the pulse width of the eleventh cycle of the input clock / DCD_IN, generates a signal DCD_CODE, and outputs it to the arithmetic circuit 42.

[0093] That is, each time the selector 56 switches the output signal CLK_DETa, it measures the high-level period of the input clock DCD_IN and the high-level period of the input clock / DCD_IN, generates the signal DCD_CODE, and outputs it to the arithmetic circuit 42. If the measurement of the high-level period of the input clock DCD_IN and the measurement of the high-level period of the input clock / DCD_IN are considered as one set, then s sets of measurements are executed.

[0094] In the cycle before the duty correction of the input clocks IN and / IN is performed, the output clocks OUT and / OUT have the same duty as the input clocks IN and / IN. Therefore, the duty of the input clocks DCD_IN and / DCD_IN is equal to the duty of the input clocks IN and / IN. That is, the signal DCD_CODE output from the DCC circuit 20 is a value generated based on the detection result of the pulse width of the first cycle of the clock IN during the period from the falling edge of the first cycle of the input clock IN (= the rising edge of the first cycle of the input clock / IN) to the falling edge of the fourth cycle of the input clock / IN (= the rising edge of the fifth cycle of the input clock IN) in each set, and is a value generated based on the detection result of the pulse width of the fourth cycle of the input clock / IN during the period from the falling edge of the fourth cycle of the input clock / IN (= the rising edge of the fifth cycle of the input clock IN) to the falling edge of the eighth cycle of the input clock IN (= the rising edge of the eighth cycle of the input clock / IN).

[0095] In other words, the signal DCD_CODE output from the DCC circuit 20 is output in the order of "the high level period of the input clock DCD_IN measured using the signal CLK_DETa1 (= the high level period of the input clock DCD_IN in the first set)", "the high level period of the input clock / DCD_IN measured using the signal CLK_DETa1 (= the high level period of the input clock / DCD_IN in the first set)", "the high level period of the input clock DCD_IN measured using the signal CLK_DETa2 (= the high level period of the input clock DCD_IN in the second set)", and "the high level period of the input clock / DCD_IN measured using the signal CLK_DETa2 (= the high level period of the input clock / DCD_IN in the second set)".

[0096] The arithmetic circuit 42 receives the detection result of the pulse width of the input clock IN measured using the signal CLK_DETa1 and the detection result of the pulse width of the input clock IN measured using the signal CLK_DETa2 by the signal DCD_CODE, and calculates the pulse width of the input clock IN using these. Also, when the arithmetic circuit 42 receives the detection result of the pulse width of the input clock / IN measured using the signal CLK_DETa1 and the detection result of the pulse width of the input clock / IN measured using the signal CLK_DETa2 by the signal DCD_CODE, it calculates the pulse width of the input clock / IN using these. Then, it compares the calculated pulse width of the input clock IN with the calculated pulse width of the input clock / IN. Then, it generates the signal DCA_CODE based on the comparison result. For example, as described above, when it receives the detection result of the pulse width of the input clock / IN measured using the signal CLK_DETa2 from the rising edge of the 12th cycle of the input clock IN, it generates and outputs the signal DCA_CODE during the 12th cycle of the input clock IN.

[0097] Then, in the DCA circuit 43 and the waveform generating circuit 44, the duty of the input clocks IN, / IN is corrected based on the signal DCA_CODE, and is output from the DCC circuit 20 as the output clocks OUT, / OUT. Note that, for cycles (1st to 12th cycles) before the signal DCA_CODE is generated, the input clocks IN, / IN become the output clocks OUT, / OUT without being corrected. The duty of the input clock IN is corrected based on the signal DCA_CODE received during the 12th cycle of the input clock IN. Then, from the 13th cycle of the output clock OUT, the corrected clock signal is output from the DCC circuit 20.

[0098] The output clocks OUT and / OUT are fed back to the DCD circuit 41 as input clocks DCD_IN and / DCD_IN, respectively. The DCD circuit 41 measures the pulse width of the input clocks DCD_IN and / DCD_IN at set appropriate intervals and updates the signal DCD_CODE. When the signal DCD_CODE is updated, the arithmetic circuit 42 updates the signal DCA_CODE. Then, the DCA circuit 43 and the waveform generation circuit 44 correct the duty of the input clocks IN and / IN based on the updated signal DCA_CODE, and output them from the DCC circuit 20 as the output clocks OUT and / OUT.

[0099] In this way, according to the present embodiment, even after the duty correction of the input clocks IN and / IN, the output clocks OUT and / OUT are fed back to the DCD circuit 41 to continue monitoring, and the signal DCD_CODE is continuously updated. As a result, even if the duty of the input clocks IN and / IN changes due to temperature or voltage fluctuations while the semiconductor memory device 2 is in operation, the duty can be appropriately corrected by following these fluctuations. Furthermore, even if an error temporarily occurs due to disturbances such as noise when detecting the signal DCD_CODE, by continuously detecting the signal DCD_CODE, the number of detections of the signal DCD_CODE can be increased, and the error can be averaged to reduce the influence. Furthermore, an error caused by a characteristic difference between the delay element 521_α provided in the DCD circuit 41 and the delay element 615_γ provided in the DCA circuit 43 can be eliminated. (2-1-1. Operation of DCD circuit) 12, 13A, and 13B are timing charts for explaining an example of the operation of the DCD circuit. Input clocks DCD_IN and / DCD_IN are input to the DCD circuit 41. The signal generating circuit 51 detects the rising edge of the first cycle of the input clock DCD_IN in each set, and maintains the signal CLK_DLY at a high level for the same period as the period from this rising edge to the rising edge of the next cycle of the input clock DCD_IN. Also, the signal generating circuit 51 detects the rising edge of the fourth cycle of the input clock / DCD_IN (=the falling edge of the fourth cycle of the input clock DCD_IN) in each set, and maintains the signal CLK_DLY at a high level for the same period as the period from this rising edge to the rising edge of the next cycle of the input clock / CLK_DLY.

[0100] That is, in the first set, the signal generating circuit 51 detects the rising edge of the first cycle of the input clock DCD_IN and maintains the signal CLK_DLY at a high level for the same period as the period from this rising edge to the rising edge of the next cycle of the input clock DCD_IN. Also, the signal generating circuit 51 detects the rising edge of the fourth cycle of the input clock / DCD_IN (= the falling edge of the fourth cycle of the input clock DCD_IN) and maintains the signal CLK_DLY at a high level for the same period as the period from this rising edge to the rising edge of the next cycle of the input clock / DCD_IN.

[0101] Furthermore, the signal generating circuit 51 detects the rising edge of the eighth cycle, which is the first cycle after the selector 56 of the edge detecting circuit 53 is switched and the signal output as the signal CLK_DETa is changed, i.e., after switching to the second set, and maintains the signal CLK_DLY at a high level for the same period as the period from this rising edge to the rising edge of the next cycle of the input clock DCD_IN. The signal generating circuit 51 also detects the fourth cycle of the second set of the input clock / DCD_IN, i.e., the rising edge of the 11th cycle of the input clock / DCD_IN (=the falling edge of the 11th cycle of the input clock DCD_IN), and maintains the signal CLK_DLY at a high level for the same period as the period from this rising edge to the rising edge of the next cycle of the input clock / CLK_DLY.

[0102] In each set, the signal generating circuit 51 detects the falling edge of the first cycle of the input clock DCD_IN, and maintains the signal CLK_DET at a high level for the same period as the period from this falling edge to the falling edge of the next cycle of the input clock DCD_IN. The signal generating circuit 51 also detects the falling edge of the fourth cycle of the input clock / DCD_IN (=the rising edge of the fifth cycle of the input clock DCD_IN), and maintains the signal CLK_DET at a high level for the same period as the period from this falling edge to the falling edge of the next cycle of the input clock / DCD_IN.

[0103] That is, in the first set, the signal generating circuit 51 detects the falling edge of the first cycle of the input clock DCD_IN, and maintains the signal CLK_DET at a high level for the same period as the period from this falling edge to the falling edge of the next cycle of the input clock DCD_IN. Also, the signal generating circuit 51 detects the falling edge of the fourth cycle of the input clock / DCD_IN (=the rising edge of the fifth cycle of the input clock DCD_IN), and maintains the signal CLK_DET at a high level for the same period as the period from this falling edge to the falling edge of the next cycle of the input clock / DCD_IN.

[0104] Furthermore, the signal generating circuit 51 detects the falling edge of the first cycle (=8th cycle) of the input clock DCD_IN, which is the first cycle after the selector 56 of the edge detecting circuit 53 is switched and the signal output as the signal CLK_DETa is changed, i.e., after switching to the second set, and maintains the signal CLK_DET at a high level for the same period from this falling edge to the falling edge of the next cycle of the input clock DCD_IN. The signal generating circuit 51 also detects the falling edge of the 11th cycle of the input clock / DCD_IN, which is the 4th cycle of the input clock / DCD_IN of the second set (=rising edge of the 12th cycle of the input clock DCD_IN), and maintains the signal CLK_DET at a high level for the same period from this falling edge to the falling edge of the next cycle of the input clock / DCD_IN.

[0105] The signal generating circuit 51 repeats the above-mentioned operation for the signals CLK_DLY and CLK_DET at each specified timing or each time duty adjustment is requested. That is, the high-level period of the signal CLK_DLY in odd-numbered cycles is the same length as one cycle of the input clock CLK_IN, and the high-level period of the signal CLK_DLY in even-numbered cycles is the same length as one cycle of the input clock / CLK_IN. Also, the high-level period of the signal CLK_DET in odd-numbered cycles is the same length as one cycle of the input clock CLK_IN, and the high-level period of the signal CLK_DET in even-numbered cycles is the same length as one cycle of the input clock / CLK_IN.

[0106] In the signals CLK_DLY and CLK_DET generated as described above, the period from the rising edge of the odd-numbered cycle of the signal CLK_DLY to the rising edge of the signal CLK_DET is the same as the pulse width of the input clock DCD_IN. Also, the period from the rising edge of the even-numbered cycle of the signal CLK_DLY to the rising edge of the signal CLK_DET is the same as the pulse width of the input clock DCD_IN.

[0107] The delay element array circuit 52 receives the signal CLK_DLY from the signal generating circuit 51 as the signal D0, and generates and outputs a signal Dα in each delay element 521_α based on the signal D0. That is, the delay element 521_α outputs a signal obtained by delaying the signal D(α-1) by the time Tw as the signal Dα. In this way, signals D1 to Dn delayed by the time Tw are obtained in ascending order of the value of α. FIG. 13A shows some of the signals D1 to D(k+1) (k is a natural number equal to or less than n-1).

[0108] A signal obtained by delaying the clock signal CLK_DETa by a time {1.0+(β-1) / m}×Tw is supplied to the delay line 53β of the edge detection circuit 53 as the clock signal DLK_DETβ.

[0109] For example, as shown in Fig. 6, when the edge detection circuit 53 is provided with four delay lines (m = 4), a signal (clock signal CLK_DET1) obtained by delaying the clock signal CLK_DETa by a time of 1.0Tw is supplied to the delay line 531. Similarly, a signal (clock signal CLK_DET2) obtained by delaying the clock signal CLK_DET by a time of 1.25Tw is supplied to the delay line 532, and a signal (clock signal CLK_DET3) obtained by delaying the clock signal CLK_DET by a time of 1.5Tw is supplied to the delay line 533. In addition, a signal (clock signal CLK_DET4) obtained by delaying the clock signal CLK_DET by a time of 1.75Tw is supplied to the delay line 534.

[0110] The flip-flop 53β_α provided in the delay line 53β latches the signal Dα in response to the transition of the clock signal CLK_DETβ to a high level, and outputs the latched signal Dα as a signal Fβα.

[0111] For example, as shown in FIG. 13A, in the delay line 531, when signals D1 to D(k-1) are at high level and signals Dk to Dn are at low level at the timing when clock signal CLK_DET1 switches to high level, high level signals are output from flip-flops 531_1 to 531_(k-1) as signals F11 to F1(k-1), and low level signals are output from flip-flops 531_k to 531_n as signals F1k to F1n.

[0112] In the delay line 532, when the signals D1 to D(k-1) are at high level and the signals Dk to Dn are at low level at the timing when the clock signal CLK_DET2 switches to high level, the flip-flops 532_1 to 532_(k-1) output high level signals as the signals F21 to F2(k-1), and the flip-flops 532_k to 532_n output low level signals as the signals F2k to F2n.

[0113] In the delay line 533, when the signals D1 to D(k-1) are at high level and the signals Dk to Dn are at low level at the timing when the clock signal CLK_DET3 switches to high level, high level signals are output as the signals F31 to F3(k-1) from the flip-flops 533_1 to 533_(k-1) although not shown in the figure. Low level signals are output as the signals F3k to F3n from the flip-flops 533_k to 533_n.

[0114] In the delay line 534, when the signals D1 to Dk are at high level and the signals D(k+1) to Dn are at low level at the timing when the clock signal CLK_DET4 switches to high level, the flip-flops 5343_1 to 534_k output high level signals as the signals F41 to F4k. Although not shown in the figure, the flip-flops 534_(k+1) to 534_n output low level signals as the signals F4(k+1) to F4n.

[0115] The signal Fβα output from the delay line 53β is output as the signal DCD_CODE.

[0116] Here, as shown in Fig. 13B, the clock signal CLK_DETa (=clock signal CLK_DETa2) in the second set is delayed by {1 / (m x s)} x Tw with respect to the clock signal CLK_DETa (clock signal CLK_DETa1) in the first set. Therefore, the clock signal DLK_DETβ in the second set is delayed by {1 / (m x s)} x Tw from the clock signal DLK_DETβ in the first set. For example, in the case of n = 8 and k = 5, the signal Fβα obtained in accordance with the timing chart shown in Fig. 13A for the clock signal CLK_DETa (clock signal CLK_DETa1) in the first set is as follows: That is, signals F1n to F11 are "00001111", signals F2n to F21 are "00001111", signals F3n to F31 are "00001111", and signals F4n to F41 are "00011111", resulting in a signal of 8 bits x 4 = 32 bits. The edge detection circuit 53 sequentially arranges the signals Fβα to generate and output a 32-bit (=n x m bits) signal DCD_CODE. For example, in the above case, the signal DCD_CODE becomes "00001111000011110000111100011111".

[0117] In the second set of clock signal CLK_DETa (clock signal CLK_DETa2), the signal Fβα obtained according to the timing chart shown in FIG. 13A is as follows. That is, signals F1n to F11 are "00001111", signals F2n to F21 are "00001111", signals F3n to F31 are "00011111", and signals F4n to F41 are "00011111", resulting in a signal of 8 bits×4=32 bits. That is, since the clock signal CLK_DETa in the second set is delayed by {1 / (m×s)}×Tw with respect to the first set, the signal F34 changes from "0" to "1". The edge detection circuit 53 sequentially arranges the signals Fβα to generate a 32-bit (=n×m bits) signal DCD_CODE and outputs it. For example, in the above case, the signal DCD_CODE would be "00001111000011110001111100011111". (2-1-2. Operation of the arithmetic circuit) The arithmetic circuit 42 counts the number of high-level bits (iδ) of the signal DCD_CODE received from the DCD circuit 41 in the first cycle of the clock signal CLK_DET in each set. For example, when the signal DCD_CODE in the first set is "00001111000011110000111100011111", the number of high-level bits is counted as "i1=17". When the signal DCD_CODE in the second set is "00001111000011110001111100011111", the number of high-level bits is counted as "i2=18".

[0118] The arithmetic circuit 42 counts the number of high-level bits (jδ) of the signal DCD_CODE received from the DCD circuit 41 in the next cycle of the clock signal CLK_DET in each set. For example, when the signal DCD_CODE in the first set is "011111111111111111111111111111111", the number of high-level bits is counted as "j1=31". When the signal DCD_CODE in the second set is "0111111111111111111111111111111", the number of high-level bits is counted as "j2=31".

[0119] The number i represents the pulse width (high-level period) of the input clock IN. Specifically, the product of the average value of the number ik of each set divided by m and the delay time Tw represents the high-level width of the input clock IN. For example, when s=2, m=4, i1=17, and i2=18, the high-level width of the input clock IN is {(17+18) / 2} / 4×Tw=4.375Tw.

[0120] The number j represents the pulse width (high-level period) of the input clock / IN. Specifically, the product of the average value of the number jk of each set divided by m and the delay time Tw represents the high-level width of the input clock / IN. The high-level width of the input clock / IN is equal to the low-level width of the input clock IN. Therefore, the number j represents the low-level width of the input clock IN. For example, when s = 2, m = 4, j1 = 31, and j2 = 31, the low-level width of the input clock IN is {(31 + 31) / 2} / 4 × Tw = 7.75 Tw.

[0121] 14 is a flow chart for explaining the operation of the arithmetic circuit. First, the arithmetic circuit 42 initializes various variables used in the calculation of the number i and the number j (S1). Specifically, the arithmetic circuit 42 sets 1 to the variable k representing the number of cycles of the clock signal CLK_DET, sets 0 to the variable isum storing the integrated value of the number ik, and sets 0 to the variable jsum storing the integrated value of the number jk. The arithmetic circuit 42 counts the number of high-level bits of the signal DCD_CODE in the first cycle of the clock signal CLK_DET, and obtains the number ik, which is the counting result (S2). The arithmetic circuit 42 adds the number ik obtained in S2 to the integrated value isum of the number ik, and increments the number of cycles k by one (S3), and then counts the number of high-level bits of the signal DCD_CODE in the next cycle of the clock signal CLK_DET, and obtains the number jk, which is the counting result (S4). The arithmetic circuit 42 adds the number jk acquired in S4 to the integrated value jsum of the number jk, increments the number of cycles k by one (S5), and then judges whether or not the planned number of sets has been acquired for the pulse width of the input clock DCD_IN and the pulse width of the input clock / DCD_IN (S6). Specifically, it judges whether or not the number k of cycles of the clock signal CLK_DET to be acquired next divided by 2 is greater than the set number of sets (s).

[0122] If the number of cycles k divided by 2 is less than or equal to the set number of sets (s) (S6, No), return to S2 and repeat steps S2 to S5 to obtain data for two cycles in the next set (number i, which is the number of high-level bits of signal DCD_CODE, and number j).

[0123] On the other hand, if the number obtained by dividing the number of cycles k by 2 is greater than the set number (s) (S6, Yes), the integrated value isum of number i and the integrated value jsum of number j are each divided by the number of sets s to calculate the number i which is the average value of number ik and the number j which is the average value of number jk (S7). The arithmetic circuit 42 uses the number i and number j acquired in S7 to calculate Δ=(ij) / 2 (S8). FIG. 15 is a waveform diagram showing an example of the input clock and output clock of the DCC circuit. As described above and shown in FIG. 15, the number i indicates the high level period of the input clock IN, and the number j indicates the low level period of the input clock IN. Therefore, the difference ij is the difference between the high level period and the low level period of the input clock IN. And, Δ is equal to the difference between the high level (or low level) period TOUTH of the target output clock OUT, which has the same period CIN as the period CIN of the input clock IN and a duty ratio of 50%, and the high level period CINH (or low level period CINL) of the input clock IN. Note that FIG. 15 shows an example in which i and j are different.

[0124] Returning to FIG. 14, the arithmetic circuit 42 judges whether Δ is 0 or not (S9). If Δ is 0 (S9, Yes), the arithmetic circuit 42 outputs the signal DCA_CODE as it is without changing it (S10). The signal DCA_CODE is composed of code signals DN_F, DN_C, and code signals UP_F, UP_C. The code signals DN_F, DN_C are signals for setting the amount of delay of the falling edge of the input clock IN, and the code signals UP_F, UP_C are signals for setting the amount of delay of the rising edge of the input clock IN. The code signal DN_F is a (m×s+1)-bit signal, and instructs to delay the falling edge of the input clock IN with a resolution of 1.0Tw time or less (specifically, {1.0 / (m×s)}Tw time units). The code signal DN_C is a 1-bit signal, and instructs to delay the falling edge of the input clock IN with a resolution of 1.0Tw time or less (specifically, {1.0 / (m×s)}Tw time units). The code signal UP_F is an (m×s+1)-bit signal, and instructs to delay the rising edge of the input clock IN with a resolution of 1.0Tw time or less (specifically, {1.0 / (m×s)}Tw time units). The code signal UP_C is an 1-bit signal, and instructs to delay the rising edge of the input clock IN in 1.0Tw time units. In the default state, the code signals DN_F, DN_C, and the code signals UP_F, UP_C are all set to "0" (setting to instruct a delay of the minimum delay time Tf in the FINE delay circuit 611).

[0125] In this embodiment, the delay adjustment of the signal DCD_IN (=output clock OUT) is repeatedly performed in the DCC circuit 20. In the second or subsequent delay adjustment, if some delay has already been set in the signal DCA_CODE (if one or more bits are set to "1" in any of the code signals DN_F, DN_C, and the code signals UP_F, UP_C), in S10, the arithmetic circuit 42 outputs the signal DCA_CODE as is without returning it to the default state.

[0126] On the other hand, if Δ is not 0 (S9, No), the arithmetic circuit 42 judges whether Δ is a positive number (Δ>0) or not (S11). If Δ is a positive number (S11, Yes), the arithmetic circuit 42 changes the code signals DN_F, DN_C to values ​​based on Δ (S12). Specifically, the code signals DN_F, DN_C are set to values ​​that instruct the rising edge of the input clock IN to be delayed by the period represented by Δ. Then, the arithmetic circuit 42 outputs a signal DCA_CODE consisting of the changed code signals DN_F, DN_C and the unchangeable code signals UP_F, UP_C.

[0127] If Δ is not a positive number (Δ<0) (S11, No), the arithmetic circuit 42 changes the code signals UP_F, UP_C to values ​​based on Δ (S13). Specifically, the code signals UP_F, UP_C are set to values ​​that instruct the falling edge of the input clock IN to be delayed by the period represented by Δ. Then, the arithmetic circuit 42 outputs a signal DCA_CODE consisting of the changed code signals UP_F, UP_C and the unchangeable code signals DN_F, DN_C.

[0128] Although not shown in Figure 14, in the second or subsequent delay adjustments, if some delay has already been set in UP_F and UP_C when Δ>0, adjustments may be made to decrease the values ​​of UP_F and UP_C.

[0129] Fig. 16 shows an example of the value of the code signal DN_F. Fig. 17 shows an example of the value of the code signal DN_C. Fig. 16 relates to an example where s=2 and m=4, and Fig. 17 relates to an example where l is 7. As shown in Fig. 16, the code signal DN_F is composed of four bits. The value of each bit of the code signal DN_F indicates that the rising edge of the input clock IN input to the FINE delay circuit 611 of the delay block circuit 61 is delayed by a time (u×Tw) obtained by multiplying the value u of the code signal expressed in decimal by the unit delay time (0.125Tw when s=2 and m=4) in the FINE delay circuit 611.

[0130] For example, the value "0000" of the code signal DN_F is a value that instructs the rising edge of the input clock IN input to the FINE delay circuit 611 of the delay block circuit 61 to be delayed by 0.000Tw with respect to the minimum delay time Tf. Also, the value "0001" of the code signal DN_F is a value that instructs the rising edge of the input clock IN in the FINE delay circuit 611 of the delay block circuit 61 to be delayed by 0.125Tw with respect to the minimum delay time Tf. Similarly, the values ​​"0010", "0011", and "0100" of the code signal DN_F are values ​​that instructs the rising edge of the input clock IN input to the FINE delay circuit 611 of the delay block circuit 61 to be delayed by 0.250Tw, 0.375Tw, and 0.500Tw, respectively, with respect to the minimum delay time Tf. Furthermore, the values ​​of the code signal DN_F "0101", "0110", "0111", and "1000" are values ​​that indicate that the rising edge of the input clock IN input to the FINE delay circuit 611 of the delay block circuit 61 is delayed by 0.625Tw, 0.750Tw, 0.875Tw, and 1.000Tw, respectively, with respect to the minimum delay time Tf.

[0131] 17, the code signal DN_C is composed of three bits. The value of each bit of the code signal DN_C instructs delaying the rising edge of the clock signals (clocks FOUTB_EVN and FOUTB_ODD) input to the CORSE delay circuit 612 by a time (v×Tw) obtained by multiplying the unit delay time (=1Tw) in the COURSE delay circuit 612 by a value v, which is a decimal representation of the value of the code signal.

[0132] For example, the value "000" of the code signal DN_C is a value that instructs delaying the rising edge of the clock signal input to the COURSE delay circuit 612 of the delay block circuit 61 by 0Tw. Also, the value "001" of the code signal DN_C is a value that instructs delaying the rising edge of the clock signal input to the COURSE delay circuit 612 of the delay block circuit 61 by 1Tw. Similarly, the values ​​"010", "011", "100", "101", "110", and "111" of the code signal DN_C are values ​​that instructs delaying the rising edge of the clock signal input to the COURSE delay circuit 612 of the delay block circuit 61 by 2Tw, 3Tw, 4Tw, 5Tw, 6Tw, and 7Tw, respectively.

[0133] The code signal UP_F is composed of the same number of bits as the code signal DN_F. The value of each bit of the code signal UP_F indicates that the rising edge of the input clock / IN input to the FINE delay circuit of the delay block circuit 62 is delayed by a time (u×Tw) obtained by multiplying the value u of the code signal expressed in decimal by the unit delay time (0.125Tw when s=2 and m=4) in the FINE delay circuit of the delay block circuit 62.

[0134] For example, the value "0000" of the code signal UP_F is a value that instructs the rising edge of the input clock / IN input to the FINE delay circuit of the delay block circuit 62 to be delayed by 0.000Tw with respect to the minimum delay time Tf. Also, the value "0001" of the code signal UP_F is a value that instructs the FINE delay circuit of the delay block circuit 62 to delay the rising edge of the input clock / IN by 0.125Tw with respect to the minimum delay time Tf. Similarly, the values ​​"0010", "0011", and "0100" of the code signal UP_F are values ​​that instructs the rising edge of the input clock / IN input to the FINE delay circuit of the delay block circuit 62 to be delayed by 0.250Tw, 0.375Tw, and 0.500Tw, respectively, with respect to the minimum delay time Tf. Furthermore, the values ​​of the code signal UP_F "0101", "0110", "0111", and "1000" are values ​​that indicate that the rising edge of the input clock IN input to the FINE delay circuit of the delay block circuit 62 is delayed by 0.625Tw, 0.750Tw, 0.875Tw, and 1.000Tw, respectively, with respect to the minimum delay time Tf.

[0135] The code signal UP_C is composed of bits with the same number of digits as the code signal DN_C. The value of each bit of the code signal UP_C indicates that the rising edge of the clock signal (clock FOUTB_EVN and clock FOUTB_ODD) input to the CORSE delay circuit is delayed by a time (v×Tw) obtained by multiplying the unit delay time (=1Tw) in the COURSE delay circuit by the value v, which is the value of the code signal expressed in decimal. In other words, the values ​​"000", "001", "010", "011", "100", "101", "110", and "111" of the code signal UP_C indicate that the rising edge of the clock signal input to the COURSE delay circuit of the delay block circuit 62 is delayed by 0Tw, 1Tw, 2Tw, 3Tw, 4Tw, 5Tw, 6Tw, and 7Tw, respectively.

[0136] Here, a method of setting the signal DCA_CODE from Δ will be described. First, the absolute value of the value obtained by multiplying Δ by s is divided by (m×s) to calculate the quotient (q) and remainder (r). Then, if Δ>0, the code signal UP_C is set from the value q, and the code signal UP_F is set from the value r. Also, if Δ<0, the code signal DN_C is set from the value q, and the code signal DN_F is set from the value r. For example, if s=2, m=4, and Δ=7.5, then Δ×s=15, and 15 / (4×2)=1 with a remainder of 7, so the code signal UP_C is set to the binary code "001" representing the decimal number "1", and the code signal UP_F is set to the binary code "0111" representing the decimal number "7". Also, for example, when m = 4 and Δ = -9, |(-9) × 2| = 18, and 18 / (4 × 2) = 2 with a remainder of 2, so code signal DN_C is set to the binary code "010" indicating the decimal value "2", and code signal DN_F is set to the binary code "0010" indicating the decimal value "2".

[0137] In addition, since the values ​​of i and j have a resolution of 0.125Tw, Δ calculated by Δ=(ij) / 2 can have a resolution of 0.0625Tw. In that case, by increasing the number of bits of DN_F and UP_F and creating a FINE delay circuit that can realize 2×(m×s)+1 combinations, adjustment with a resolution of 0.0625Tw is possible. (2-1-3. Operation of DCA circuit) The DCA circuit 43 receives the signal DCA_CODE output from the arithmetic circuit 42 and generates code signals DN_FD, DN_CD and code signals UP_FD, UP_CD. Specifically, the delay block circuit 61 receives the code signals DN_F, DN_C and sets the code signals DN_FD, DN_CD. In addition, the delay block circuit 62 receives the code signals UP_F, UP_C and sets UP_FD, UP_CD. First, the code setting in the delay block circuit 61 will be described.

[0138] The setting of the code signal DN_FD in the code control circuit 613 will be described with reference to FIG. 18. FIG. 18 shows an example of the value of the code signal DN_FD. FIG. 18 relates to an example in which s=2 and m=4. As shown in FIG. 18, the code signal DN_FD is composed of eight bits. The code signal DN_FD is expressed by a thermometer code. When the code signal DN_C is an even number (0, 2, 4, ...), the code signal DN_FD is set as follows according to the value of the code signal DN_F. That is, when the code signal DN_F is "0000", the code signal DN_FD is set to "00000000". When the code signal DN_F is "0001", the code signal DN_FD is set to "00000001". Similarly, when the code signal DN_F is "0010", "0011", "0100", "0101", "0110", "0111", "1000", the code signal DN_FD is set to "00000011", "00000111", "00001111", "00011111", "00111111", "01111111", "11111111".

[0139] On the other hand, when the code signal DN_C is an odd number (1, 3, 5, ...), the code signal DN_FD is set as follows according to the value of the code signal DN_F. That is, when the code signal DN_F is "0000", the code signal DN_FD is set to "11111111". When the code signal DN_F is "0001", the code signal DN_FD is set to "01111111". Similarly, when the code signal DN_F is "0010", "0011", "0100", "0101", "0110", "0111", "1000", the code signal DN_FD is set to "00111111", "00011111", "00001111", "00000111", "00000011", "00000001", "00000001", "00000000".

[0140] Next, the setting of the code signal DN_CD in the code conversion circuit 616 of the COURSE delay circuit 612 will be described with reference to Fig. 19. Fig. 19 shows an example of the value of the code signal DN_CD. Note that Fig. 19 relates to an example in which l is 7. As shown in Fig. 19, the code signal DN_CD is composed of 7 bits. The code signal DN_CD is set to a value obtained by converting the decimal value represented by the code signal DN_C, which is a binary code, into a thermometer code. That is, when the code signal DN_C is "000", the code signal DN_CD is set to "0000000". Also, when the code signal DN_C is "001", the code signal DN_CD is set to "0000001". Similarly, when the code signal DN_C is "010", "011", "100", "101", "110", "111", the code signal DN_CD is set to "0000011", "0000111", "0001111", "0011111", "0111111", "1111111".

[0141] The delay block circuit 62 receives the code signals UP_F and UP_C and sets UP_FD and UP_CD, similar to the delay block circuit 61. That is, in the above description, the code signals DC_F, DN_C, DN_FD, and DN_CD are replaced with the code signals UP_F, UP_C, UP_FD, and UP_CD, respectively, and the code signals UP_FD and UP_CD are set in the delay block circuit 62.

[0142] Next, the operation of the FINE delay circuit 611 will be described. First, the operation of the FINE delay circuit 611e will be described. FIG. 20 is a timing chart for explaining the operation of the FINE delay circuit. FIG. 20 relates to the case where s=2 and m=4. A signal (clock INB) obtained by inverting the logic of the input clock IN is input to the input terminal CKIN_A of the FINE delay circuit 611e, and a signal (clock INB1) obtained by delaying the clock INB by 1.0Tw is input to the input terminal CKIN_B of the FINE delay circuit 611e. Furthermore, the code signal DN_FD is input to the input terminal FI_T of the FINE delay circuit 611e. Furthermore, a code signal DN_FDB, which is a signal obtained by inverting the logic of the code signal DN_FD, is input to the input terminal FI_B.

[0143] The value of the first bit of the code signal DN_FD is input to the input terminal FI_T1. The value of the second bit of the code signal DN_FD is input to the input terminal FI_T2. Similarly, the values ​​of the third, fourth, fifth, sixth, seventh, and eighth bits of the code signal DN_FD are input to the input terminals FI_T3, FI_T4, FI_T5, FI_T6, FI_T7, and FI_T8, respectively.

[0144] The value of the first bit of the code signal DN_FDB is input to the input terminal FI_B1. The value of the second bit of the code signal DN_FDB is input to the input terminal FI_B2. Similarly, the values ​​of the third, fourth, fifth, sixth, seventh, and eighth bits of the code signal DN_FDB are input to the input terminals FI_B3, FI_B4, FI_B5, FI_B6, FI_B7, and FI_B8, respectively.

[0145] For example, when the value of code signal DN_FD is "00000111", "1" "1" "1" "0" "0" "0" "0" "0" are input to input terminals FI_T1, FI_T2, FI_T3, FI_T4, FI_T5, FI_T6, FI_T7, and FI_T8, respectively. Also, when the value of code signal DN_FD is "00000111", the value of code signal DN_FDB is "11111000". Therefore, "0" "0" "0" "1" "1" "1" "1" "1" "1" are input to input terminals FI_B1, FI_B2, FI_B3, FI_B4, FI_B5, FI_B6, FI_B7, and FI_B8, respectively.

[0146] During a period when the clock INB is at a high level, the first NMOS transistor of the inverter circuit 614a and the second NMOS transistor of the inverter circuit 614b are turned on. Also, during a period when the clock INB1 is at a high level, the second NMOS transistor of the inverter circuit 614a and the first NMOS transistor of the inverter circuit 614b are turned on. Therefore, during a period when the clocks INB and INB1 are both at a high level, the N-side switch 72 of the inverter circuit 614a and the N-side switch 72 of the inverter circuit 614b are turned on, so that the signal PI_CLKB (a signal obtained by merging the output signal from the inverter circuit 614a and the output signal from the inverter circuit 614b) is at a low level.

[0147] At time t1, when the clock INB is switched to a low level, the first NMOS transistor of the inverter circuit 614a and the second NMOS transistor of the inverter circuit 614b are turned off. That is, the N-side switch 72 of the inverter circuit 614a and the N-side switch 74 of the inverter circuit 614b are turned off. Also, the second PMOS transistors provided in each of the four P-side switches 71_β of the inverter circuit 614a are turned on.

[0148] Here, the first PMOS transistors provided in the eight P-side switches 71_β of the inverter circuit 614a are turned on when a low-level signal ("0") is input to their gates. Therefore, the first PMOS transistors are turned on the same number as the number of bits whose value is "0" in the code signal DN_FD. For example, when the value of the code signal DN_FD is "00000111", "1" is input to the input terminals FI_T1, FI_T2, and FI_T3, so that the first PMOS transistors whose gates are connected to these terminals are turned off. On the other hand, "0" is input to the input terminals FI_T4, FI_T5, FI_T6, FI_T7, and FI_T8, so that the first PMOS transistors whose gates are connected to these terminals are turned on.

[0149] Therefore, at time t1, of the four P-side switches 71_β, the number of switches equal to the number of bits whose value is "0" in the code signal DN_FD are turned on, and the level of the signal output to the output terminal CKOUT_T of the inverter circuit 614a increases according to the number of switches turned on. That is, the more P-side switches 71_β are turned on, the steeper the rising slope of the signal output to the output terminal CKOUT_T of the inverter circuit 614a becomes.

[0150] When the clock INB1 is switched to a low level at time t2 after the lapse of time Tw from time t1, the second NMOS transistor of the inverter circuit 614a and the first NMOS transistor of the inverter circuit 614b are turned off, and the second PMOS transistors provided in each of the four P-side switches 73_β of the inverter circuit 614b are turned on.

[0151] The first MOS transistors provided in the eight P-side switches 73_β of the inverter circuit 614b are turned on when a low-level signal ("0") is input to their gates. Therefore, the number of first PMOS transistors that are on is equal to the number of bits whose value is "0" in the code signal DN_FDB. For example, when the code signal DN_FDB is "11111000", "0" is input to the input terminals FI_B1, FI_B2, and FI_B3, so that the first PMOS transistors whose gates are connected to these terminals are turned on. On the other hand, "1" is input to the input terminals FI_B4 to FI_B8, so that the first PMOS transistors whose gates are connected to these terminals are turned off.

[0152] Therefore, at time t2, of the eight P-side switches 73_β, the number of switches equal to the number of bits whose value is "0" in the code signal DN_FDB are turned on, and the level of the signal output to the output terminal CKOUT_B of the inverter circuit 614b increases according to the number of switches turned on. That is, the more P-side switches 73_β are turned on, the steeper the rising slope of the signal output to the output terminal CKOUT_B of the inverter circuit 614b becomes.

[0153] That is, the signal PI_CLKB obtained by merging the output signal from the inverter circuit 614a and the output signal from the inverter circuit 614b has a different rise time depending on the values ​​of the code signals DN_FD and DN_FDB.

[0154] The clock INB switches to a high level at time t3. Here, the period from time t2 to time t3 is equal to the high level period CINH of the input clock IN. Then, at time t4, which is Tw time after time t3, the clock INB1 switches to a high level. When both the clocks INB and INB1 switch to a high level, the N-side switch 72 of the inverter circuit 614a and the N-side switch 74 of the inverter circuit 614b are turned on, and the signal PI_CLKB switches to a low level.

[0155] The clock FOUTB_EVN shown in FIG. 20 is a signal obtained by logically inverting the signal PI_CLKB via an inverter, and is a signal output from the FINE delay circuit 611e.

[0156] Here, the relationship between the code signals DN_FD and DN_FDB and the delay time of the clock FOUTB_EVN in the FINE delay circuit 611e will be summarized. First, when the value of the code signal DN_FD is "00000000" (the value of the code signal DN_FDB is "11111111"), eight P-side switches 71 of the inverter circuit 614a are on, and zero P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay amount of the falling edge of the clock FOUTB_EVN is a value that reflects 100% of the delay amount of the clock INB in ​​the inverter circuit 614a. Therefore, the delay time of the falling edge of the clock FOUTB_EVN relative to the falling edge of the clock INB is the minimum delay time Tf.

[0157] When the value of the code signal DN_FD is "00000001" (the value of the code signal DN_FDB is "11111110"), seven P-side switches 71 of the inverter circuit 614a are on, and one P-side switch 73 of the inverter circuit 614b is on. Therefore, the delay amount of the falling edge of the clock FOUTB_EVN is a sum of 87.5% of the delay amount of the clock INB when all the P-side switches 71 of the inverter circuit 614a are on, and 12.5% ​​of the delay amount of the clock INB1 when all the P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay time of the falling edge of the clock FOUTB_EVN relative to the falling edge of the clock INB is 0.875Tf+0.125(Tw+Tf)=Tf+0.125Tw.

[0158] When the value of the code signal DN_FD is "00001111" (the value of the code signal DN_FDB is "11110000"), the four P-side switches 71 of the inverter circuit 614a are on, and the four P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay amount of the falling edge of the clock FOUTB_EVN is a value obtained by adding 50% of the delay amount of the clock INB when all the P-side switches 71 of the inverter circuit 614a are on and 50% of the delay amount of the clock INB1 when all the P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay time of the falling edge of the clock FOUTB_EVN relative to the falling edge of the clock INB is 0.500Tf+0.500(Tw+Tf)=Tf+0.500Tw.

[0159] When the value of the code signal DN_FD is "00111111" (the value of the code signal DN_FDB is "11000000"), the two P-side switches 71 of the inverter circuit 614a are on, and the six P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay amount of the falling edge of the clock FOUTB_EVN is a sum of 25% of the delay amount of the clock INB when all the P-side switches 71 of the inverter circuit 614a are on and 75% of the delay amount of the clock INB1 when all the P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay time of the falling edge of the clock FOUTB_EVN relative to the falling edge of the clock INB is 0.250Tf+0.750(Tw+Tf)=Tf+0.750Tw.

[0160] When the value of the code signal DN_FD is "11111111" (the value of the code signal DN_FDB is "00000000"), zero P-side switches 71 of the inverter circuit 614a are on, and eight P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay amount of the falling edge of the clock FOUTB_EVN is a value that reflects 100% of the delay amount of the clock INB1 in the inverter circuit 614b. Therefore, the delay time of the rising edge of the clock FOUTB_EVN relative to the falling edge of the clock INB is Tf+1.000Tw.

[0161] The rising edge of the clock FOUTB_EVN output from the FINE delay circuit 611e occurs when both the clocks INB and INB1 are at high level, regardless of the values ​​of the code signals DN_FD and DN_FDB. In other words, the rising edge of the clock FOUTB_EVN occurs at the same timing as the rising edge of the clock INB1, so the delay time with respect to the rising edge of the clock INB is Tw.

[0162] In this manner, the FINE delay circuit 611e receives the clock IN, and generates and outputs the clock FOUTB_EVN whose falling edge delay time varies according to the value of the code signal DN_FD.

[0163] Next, the operation of the FINE delay circuit 611о will be described. In the FINE delay circuit 611о, a signal (clock INB) in which the logic of the input clock IN is inverted is input to the input terminal CKIN_B, and a signal (clock INB1) in which the clock INB is delayed by 1.0Tw is input to the input terminal CKIN_A. That is, the signal (clock INB) input to the input terminal CKIN_A in the FINE delay circuit 611e is input to the input terminal CKIN_B in the FINE delay circuit 611о, and the signal (clock INB1) input to the input terminal CKIN_B in the FINE delay circuit 611e is input to the input terminal CKIN_A in the FINE delay circuit 611о. Therefore, the relationship between the code signals DN_FD, DN_FDB and the delay time of the clock FOUTB_ODD generated in the FINE delay circuit 611о is as follows:

[0164] First, when the value of the code signal DN_FD is "00000000" (the value of the code signal DN_FDB is "11111111"), the eight P-side switches 71 of the inverter circuit 614a are on, and the zero P-side switch 73 of the inverter circuit 614b is on. Therefore, the delay amount of the falling edge of the clock FOUTB_ODD is a value that reflects 100% of the delay amount of the clock INB1 in the inverter circuit 614a. Therefore, the delay time of the falling edge of the clock FOUTB_ODD relative to the falling edge of the clock INB is Tf+1.00Tw.

[0165] When the value of the code signal DN_FD is "00000011" (the value of the code signal DN_FDB is "11111100"), the six P-side switches 71 of the inverter circuit 614a are on, and the two P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay amount of the falling edge of the clock FOUTB_ODD is a sum of 75% of the delay amount of the clock INB1 when all the P-side switches 71 of the inverter circuit 614a are on and 25% of the delay amount of the clock INB when all the P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay time of the falling edge of the clock FOUTB_ODD relative to the falling edge of the clock INB is 0.75(Tw+Tf)+0.25Tf=Tf+0.75Tw.

[0166] When the value of the code signal DN_FD is "00001111" (the value of the code signal DN_FDB is "11110000"), the four P-side switches 71 of the inverter circuit 614a are on, and the four P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay amount of the falling edge of the clock FOUTB_ODD is a value obtained by adding 50% of the delay amount of the clock INB1 when all the P-side switches 71 of the inverter circuit 614a are on and 50% of the delay amount of the clock INB when all the P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay time of the falling edge of the clock FOUTB_ODD relative to the rising edge of the clock INB is 0.50(Tw+Tf)+0.50Tf=Tf+0.50Tw.

[0167] When the value of the code signal DN_FD is "00111111" (the value of the code signal DN_FDB is "11000000"), the two P-side switches 71 of the inverter circuit 614a are on, and the six P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay amount of the falling edge of the clock FOUTB_ODD is the sum of 25% of the delay amount of the clock INB1 when all the P-side switches 71 of the inverter circuit 614a are on and 75% of the delay amount of the clock INB when all the P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay time of the rising edge of the clock FOUTB_ODD relative to the falling edge of the clock INB is 0.25(Tw+Tf)+0.75Tf=Tf+0.25Tw.

[0168] When the value of the code signal DN_FD is "11111111" (the value of the code signal DN_FDB is "00000000"), zero P-side switches 71 of the inverter circuit 614a are on, and eight P-side switches 73 of the inverter circuit 614b are on. Therefore, the delay amount of the falling edge of the clock FOUTB_ODD is a value that reflects 100% of the delay amount of the clock INB in ​​the inverter circuit 614b. Therefore, the delay time of the falling edge of the clock FOUTB_EVN relative to the falling edge of the clock INB is Tf.

[0169] The rising edge of the clock FOUTB_ODD output from the FINE delay circuit 611о occurs when both the clocks INB and INB1 are at high level, regardless of the values ​​of the code signals DN_FD and DN_FDB. In other words, the rising edge of the clock FOUTB_EVN occurs at the same timing as the rising edge of the clock INB1, so the delay time with respect to the rising edge of the clock INB is Tw.

[0170] 21 shows the relationship between the code signals DN_FD, DN_FDB and the delay times of the clocks FOUTB_EVN and FOUTB_ODD. That is, when the value of the code signal DN_FD is "00000000", the falling delay time of the clock FOUTB_EVN is Tf, and the falling delay time of the clock FOUTB_ODD is Tf+1.00Tw. When the value of the code signal DN_FD is "00000011", the falling delay time of the clock FOUTB_EVN is Tf+0.25Tw, and the falling delay time of the clock FOUTB_ODD is Tf+0.75Tw. When the value of the code signal DN_FD is "00001111", the falling delay time of the clock FOUTB_EVN is Tf+0.50Tw, and the falling delay time of the clock FOUTB_ODD is Tf+0.50Tw. When the value of the code signal DN_FD is "00111111", the falling delay time of the clock FOUTB_EVN is Tf+0.74Tw, and the falling delay time of the clock FOUTB_ODD is Tf+0.25Tw. When the value of the code signal DN_FD is "11111111", the falling delay time of the clock FOUTB_EVN is Tf+1.00Tw, and the falling delay time of the clock FOUTB_ODD is Tf.

[0171] In this way, the clocks FOUTB_EVN and FOUTB_ODD are complementary, and are generated so that the sum of the delay times is constant (1.00Tw) regardless of the value of the input code signal DN_FD. Note that the "sum of delay times" mentioned above refers to the sum of delay times excluding the longest delay time Tf. In other words, if the falling delay time of the clock FOUTB_EVN is lengthened, the delay time of FOUTB_ODD is shortened. Conversely, if the falling delay time of the clock FOUTB_EVN is shortened, the delay time of FOUTB_ODD is lengthened.

[0172] Next, the operation of the COURSE delay circuit 612 will be described. FIG. 22 shows an example of one state during the operation of the COURSE delay circuit. Also, FIG. 23 is a timing chart for explaining the operation of the COURSE delay circuit in the state of FIG. 22. In the example shown in FIG. 22, the high-level period of the input clock IN is longer than the low-level period by 2.50 Tw. In the example of FIG. 22, Δ is 1.25 Tw. Therefore, the code signal DN_C has a value of "001". As a result, the code conversion circuit 616 outputs "0000001" as the code signal DN_CD. That is, only the code signal DN_CD1 is a high-level signal, and the code signals DN_CD2 to DN_CDl are low-level signals. As a result, the falling edge of the clock FOUTB_ODD output from the FINE delay circuit 611о is delayed by the delay elements 615_1 and 615_0. Therefore, the falling edge of the output clock CDLYOUT is delayed by 1Tw in addition to the minimum delay time Tc (ie, the delay time of the delay element 615_0) in the COURSE delay circuit 612 relative to the falling edge of the clock FOUTB_ODD (see the thick line path in FIG. 23).

[0173] On the other hand, the rising edge of the output clock CDLYOUT is delayed by the delay element 615_0 from the rising edge of the clock FOUTB_EVN output from the FINE delay circuit 611e, regardless of the code signal DN_C. Therefore, the rising edge of the output clock CDLYOUT is delayed by the minimum delay time Tc in the COURSE delay circuit 612 with respect to the rising edge of the clock FOUTB_EVN (see the thick dashed line path in FIG. 23).

[0174] When Δ is 1.25Tw, the code signal DN_F has a value of "0010". Since the code signal DN_C is "001", that is, an odd number, the code control circuit 613 converts the code signal DN_F and outputs "00111111" as the code signal DN_FD. When the value of the code signal DN_FD is "00111111", the signal output from the FINE delay circuit 611о is a signal in which the clock IN is delayed by 0.25Tw in addition to the minimum delay time Tf in the FINE delay circuit 611. When the value of the code signal DN_FD is "00111111", the signal output from the FINE delay circuit 611e is a signal in which the clock IN is delayed by 0.75Tw in addition to the minimum delay time Tf in the FINE delay circuit 611.

[0175] As a result, the falling edge of the output clock CDLYOUT is a signal in which the clock IN is delayed by 1.25Tw in addition to the minimum delay time (Tf+Tc). Also, the rising edge of the output clock CDLYOUT is a signal in which the input clock is delayed by Tw+Tc. Note that in FIG. 23, the waveforms of each signal are shown assuming that the minimum delay time Tf in the FINE delay circuit 611 is 0Tw, and the minimum delay time Tc in the COURSE delay circuit 612 is 1Tw.

[0176] Next, the operation of the COURSE delay circuit 612 will be described using another specific example. FIG. 24 shows an example of one state during the operation of the COURSE delay circuit. Also, FIG. 25 is a timing chart for explaining the operation of the COURSE delay circuit in the state of FIG. 24. In the example shown in FIG. 24, the high-level period of the input clock IN is longer than the low-level period by 4.50 Tw. In the example of FIG. 24, Δ is 2.25 Tw. Therefore, the code signal DN_C has a value of "010". As a result, the code conversion circuit 616 outputs "0000011" as the code signal DN_CD. That is, the code signals DN_CD1 and DN_CD2 are high-level signals, and the code signals DN_CD3 to DN_CD1 are low-level signals. As a result, the falling edge of the clock FOUTB_EVN output from the FINE delay circuit 611e is delayed by the delay elements 615_2 to 615_0. Therefore, the falling edge of the output clock CDLYOUT is delayed by 2Tw in addition to the minimum delay time Tc in the COURSE delay circuit 612 relative to the falling edge of the clock FOUTB_EVN (see the thick line path in FIG. 24).

[0177] On the other hand, the rising edge of the output clock CDLYOUT is delayed by the delay element 615_0 from the rising edge of the clock FOUTB_EVN output from the FINE delay circuit 611e, regardless of the code signal DN_C. Therefore, the rising edge of the output clock CDLYOUT is delayed by the minimum delay time Tc in the COURSE delay circuit 612 with respect to the rising edge of the clock FOUTB_EVN (see the thick dashed line path in FIG. 24).

[0178] When Δ is 2.25Tw, the code signal DN_F has a value of "0010". Since the code signal DN_C is "010", that is, an even number, the code control circuit 613 converts the code signal DN_F and outputs "00000011" as the code signal DN_FD. When the value of the code signal DN_FD is "00000011", the signal output from the FINE delay circuit 611e is a signal in which the clock IN is delayed by 0.25Tw in addition to the minimum delay time Tf in the FINE delay circuit 611. Note that when the value of the code signal DN_FD is "00000011", the signal output from the FINE delay circuit 611e is a signal in which the clock IN is delayed by 0.75Tw in addition to the minimum delay time Tf in the FINE delay circuit 611.

[0179] As a result, the rising edge of the output clock CDLYOUT is a signal in which the clock IN is delayed by 2.25Tw in addition to the minimum delay time (Tf+Tc). Also, the falling edge of the output clock CDLYOUT is a signal in which the input clock is delayed by Tw+Tc. Note that in FIG. 25, the waveforms of each signal are shown assuming that the minimum delay time Tf in the FINE delay circuit 611 is 0Tw and the minimum delay time Tc in the COURSE delay circuit 612 is 1Tw.

[0180] The output clock CDLYOUT output from the COURSE delay circuit 612 is logically inverted by an inverter and output from the delay block circuit 61 as a clock CDLY_T.

[0181] The delay block circuit 62 receives the input clock / IN and the code signals UP_F and UP_C that constitute the signal DCA_CODE, and generates a delayed clock CDLY_B. The operation of each component of the delay block circuit 62 is similar to that of the delay block circuit 61. That is, in the above description, the code signals DC_F, DN_C, DN_FD, and DN_CD are replaced with the code signals UP_F, UP_C, UP_FD, and UP_CD, respectively, and the delay block circuit 62 generates and outputs the clock CDLY_B from the input clock / IN. (2-1-4. Operation of the waveform generation circuit) The waveform generating circuit 44 receives the two clocks (clocks CDLY_T, CDLY_B) output from the DCA circuit 43 and generates an output clock OUT. Fig. 26 is a timing chart for explaining an example of the operation of the waveform generating circuit. Fig. 26 is a timing chart in which the high-level period CINH of the clock IN is 8Tw and the low-level period CINL is 5.5Tw. In Fig. 26, the minimum delay time Tf in the FINE delay circuit 611 is 0Tw, and the minimum delay time Tc in the COURSE delay circuit 612 is 1Tw.

[0182] In this case, the clock CDLY_T output from the DCA circuit 43 is generated by delaying the rising and falling edges of the clock IN by a predetermined amount by the delay block 61. Specifically, since Δ=(8-5.5) / 2=1.25Tw, the rising edge of the clock CDLY_T is delayed by 2.25Tw (=Tf+Tc+1.25Tw) from the rising edge of the clock IN, and the falling edge of the clock CDLY_T is delayed by 2Tw from the falling edge of the clock IN.

[0183] Moreover, the clock CDLY_B is generated by delaying the rising and falling edges of the clock / IN by a predetermined amount by the delay block 62. Specifically, the rising edge of the clock CDLY_B is delayed by 1Tw (=Tf+Tc) from the rising edge of the clock / IN, and the falling edge of the clock CDLY_B is delayed by 2Tw from the falling edge of the clock IN.

[0184] The waveform generating circuit 44 generates, as the output clock OUT, a signal that rises at the timing when the clock CDLY_T rises and falls at the timing when the clock CDLY_B rises. That is, the output clock OUT rises 2.25 Tw after the rising edge of the clock IN and falls 1 Tw after the rising edge of the clock / IN. The high-level period COUTH of the clock OUT thus generated is 6.75 Tw, and the low-level period COUTL is also 6.75 Tw. That is, the output clock OUT has a duty cycle of 50%. The waveform generating circuit 44 also generates a signal / OUT that is the logical inversion of the output clock OUT, and outputs it together with the output clock OUT. (3. Effects) According to this embodiment, when the edge detection circuit 53 measures the pulse width of the input clock DCD_IN (the period during which it is at high level) and the pulse width of the input clock / DCD_IN, the measurement can be performed with high resolution while suppressing an increase in area and current consumption.

[0185] Fig. 27 is a circuit diagram showing an example of an edge detection circuit of a comparative example. The edge detection circuit shown in Fig. 27 has the same measurement resolution as the edge detection circuit 53 of the embodiment shown in Fig. 6. The edge detection circuit of the comparative example includes (m x s) delay lines 53m. The edge detection circuit 53 also includes (m x s) delay elements 54β. The delay amount of each delay element 54β is set to be the time {1.0 + (β - 1) / (m x s)} x Tw.

[0186] For example, when m=4 and s=2, as shown in Fig. 27, the edge detection circuit of the comparative example has eight delay lines 531 to 538. The delay amounts of eight delay elements 541 to 548 provided on the input side of each of the delay lines 531 to 538 are set in increments of 0.125 Tw.

[0187] According to the edge detection circuit configuration of the comparative example, in order to double the measurement resolution, it is necessary to double the number of delay lines 53m. Since the delay line 53m is composed of many flip-flops, it occupies a large area and consumes a large current. When the measurement resolution is increased by the configuration of the comparative example, the area increases and the current consumption also increases. In addition, as the area increases, the difference in the length of the wiring that transmits the signal CLK_DET to each delay element 54β increases. For example, the difference between the length of the wiring that transmits the signal CLK_DET to the delay element 541 and the length of the wiring that transmits the signal CLK_DET to the delay element 548 increases. When the difference in the wiring length increases, the influence of the wiring delay cannot be ignored. Therefore, the signal CLK_DET output from each delay element 54β is influenced by the wiring delay in addition to the set delay amount, so it becomes difficult to equalize the delay difference of the signal CLK_DET input to each delay line 53m.

[0188] On the other hand, the edge detection circuit 53 of this embodiment is provided with a delay unit 55 that generates a delay difference on the input side of the delay element 54β. The delay unit 55 generates two types of signals CLK_DETa1 and CLK_DETa2 with a delay difference of 0.125Tw. Either the signal CLK_DETa1 or the signal CLK_DETa2 is input to the delay element 54β. When the signal CLK_DETa1 is input and the signal (signal CLK_DET1) output from the delay element 541 is used as a reference, the delay amount of the signal (signal CLK_DET1) output from the delay element 541 with the signal CLK_DETa2 input is 0.125Tw. Similarly, the delay amount of the signal (signal CLK_DET2) output from the delay element 542 with the signal CLK_DETa1 input is 0.25Tw, and the delay amount of the signal (signal CLK_DET2) output from the delay element 542 with the signal CLK_DETa2 input is 0.375Tw. The delay amount of the signal (signal CLK_DET3) output from delay element 543 using signal CLK_DETa1 as input is 0.500Tw, and the delay amount of the signal (signal CLK_DET3) output from delay element 543 using signal CLK_DETa2 as input is 0.625Tw. Furthermore, the delay amount of the signal (signal CLK_DET4) output from delay element 544 using signal CLK_DETa1 as input is 0.750Tw, and the delay amount of the signal (signal CLK_DET4) output from delay element 544 using signal CLK_DETa2 as input is 0.875Tw.

[0189] That is, the edge detection circuit 53 of the embodiment generates the delay amount of the signal input to the delay line 53m using a two-stage circuit consisting of the delay element 54β and the delay unit 55. As a result, by adding the delay unit 55 (delay element 55δ and selector 56) without changing the number of delay lines 53m, it is possible to double the signals with different delay differences in a time-division manner. As a result, it is possible to reduce the delay difference of the signals input to the delay element 54β. Therefore, it is possible to improve the measurement resolution while suppressing an increase in area and an increase in current consumption due to an increase in flip-flops.

[0190] As described above, the present embodiment can provide a semiconductor integrated circuit, a semiconductor memory device, and a memory system that can increase the measurement resolution of a pulse signal while suppressing the area and current consumption.

[0191] The DCC circuit 20 may be provided not only in the interface chip 2A but also in the non-volatile memory 2B. The signals to be corrected are not limited to the duty cycles of the read enable signals RE and / RE and the data strobe signals DQS and / DQS. The DCC circuit 20 may be provided in a portion where correction is performed for signals that require highly accurate duty cycle adjustment with a high-speed clock. Second embodiment Next, a second embodiment will be described. Fig. 28 is a circuit diagram showing an example of an edge detection circuit of the second embodiment. In the second embodiment shown in Fig. 28, the configuration of a delay unit 57 that adjusts the delay amount of a signal input to a delay line 53β is different from that of the first embodiment shown in Fig. 6. The same components as those in the edge detection circuit of the first embodiment shown in Fig. 6 are given the same reference numerals and will not be described.

[0192] In the edge detection circuit shown in FIG. 28, a delay unit 57 is formed between the output side of a delay element 54β and the input side of a delay line 53β. In addition to the delay element 54β, one delay element 54(m+1) is added. The delay unit 57 includes m PI (Phase Interpolator) circuits 57β. The PI circuit 57β receives an output signal from the delay element 54β and an output signal from the delay element (β+1). The PI circuit 57β also receives a control signal CTL for adjusting the amount of delay. The PI circuit 57β outputs a signal CLK_DETβ whose delay amount has been adjusted in accordance with the control signal CTL.

[0193] 29 is a circuit diagram showing an example of a PI circuit. The PI circuit 57β includes two inverter circuit groups 58a and 58b. The inverter circuit group 58a is composed of s inverter circuits 58a_δ. The inverter circuit 58a_δ is composed of two PMOS transistors and two NMOS transistors connected in series. The s inverter circuits 58a_δ are connected in parallel between a node of the power supply potential Vcc and a node of the ground potential Vss.

[0194] Of the two PMOS transistors constituting the inverter circuit 58a_δ, one PMOS transistor (hereinafter referred to as the third PMOS transistor) has a source connected to the power supply potential Vcc, and a set bit of the s-bit code signal (=control signal CTL) input from the input terminal CTLA is input to the gate of the other PMOS transistor (hereinafter referred to as the fourth PMOS transistor) via the input terminal IN_A, a signal input from the delay element 54β (a signal obtained by delaying the signal CLK_DET by the delay element 54β) is input to the gate of the other NMOS transistor (hereinafter referred to as the third NMOS transistor) has a drain connected to the ground potential Vss, and a set bit of the s-bit code signal (=control signal CTL) input from the input terminal CTLA is input to the gate of the other NMOS transistor (hereinafter referred to as the third NMOS transistor). The gate of the other NMOS transistor (hereinafter referred to as the fourth NMOS transistor) receives a signal (a signal obtained by delaying the signal CLK_DET by the delay element 54β) input from the delay element 54β via the input terminal IN_A. That is, of the s-bit code signal (=control signal CTL) input from the input terminal CTLA, a set one bit is input to the gate of the third PMOS transistor and the gate of the third NMOS transistor. Also, the signal (a signal obtained by delaying the signal CLK_DET by the delay element 54β) input from the delay element 54β via the input terminal IN_A is input to the gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor.

[0195] Of the two PMOS transistors constituting the inverter circuit 58b_δ, one PMOS transistor (hereinafter referred to as the fifth PMOS transistor) has a source connected to the power supply potential Vcc, and a set bit of the s-bit code signal (=control signal CTL) input from the input terminal CTLB is input to the gate of the other PMOS transistor (hereinafter referred to as the sixth PMOS transistor) via the input terminal IN_B, which is a signal input from the delay element 54(β+1) (a signal obtained by delaying the signal CLK_DET by the delay element 54(β+1)). Of the two NMOS transistors constituting the inverter circuit 58a_δ, one NMOS transistor (hereinafter referred to as the fifth NMOS transistor) has a drain connected to the ground potential Vss, and a set bit of the s-bit code signal (=control signal CTL) input from the input terminal CTLB is input to the gate of the other NMOS transistor (hereinafter referred to as the fifth NMOS transistor). A signal input from the delay element 54(β+1) via the input terminal IN_B (a signal obtained by delaying the signal CLK_DET by the delay element 54(β+1)) is input to the gate of the other NMOS transistor (hereinafter, referred to as the sixth NMOS transistor). That is, of the s-bit code signal (=a signal obtained by logically inverting the control signal CTL) input from the input terminal CTLB, a set 1 bit is input to the gate of the fifth PMOS transistor and the gate of the fifth NMOS transistor. Also, a signal input from the delay element 54(β+1) via the input terminal IN_B (a signal obtained by delaying the signal CLK_DET by the delay element 54(β+1)) is input to the gate of the sixth PMOS transistor and the gate of the sixth NMOS transistor.

[0196] A signal obtained by merging the output from the inverter circuit group 58a and the output from the inverter circuit group 58b is inverted and output from the output terminal OUT. That is, a signal obtained by merging and inverting the output from the inverter circuit 58a_δ and the output from the inverter circuit 58b_δ is output from the output terminal OUT as the clock signal CLK_DETβ.

[0197] The operation of the above-mentioned PI circuit 57β will be described with reference to Fig. 30A, Fig. 30B, and Fig. 31. Fig. 30A and Fig. 30B are circuit diagrams for explaining an example of the operation of the PI circuit. Note that Fig. 30A and Fig. 30B show an example of the PI circuit when s=2. Fig. 31 is a timing chart for explaining an example of the operation of the PI circuit.

[0198] When s=2, the PI circuit 57β has an inverter circuit group 58a consisting of two inverter circuits 58a_1 and 58a_2, and an inverter circuit group 58b consisting of two inverter circuits 58b_1 and 58b_2. The control signal CTL is a 2-bit code signal. The first bit of data of the control signal CTL is input to the two inverter circuits 58a_1 and 58b_1, and the second bit of data is input to the two inverter circuits 58a_2 and 58b_2.

[0199] FIG. 30A shows a case where the 2-bit control signal CTL is "11". When the value of the control signal CTL is "11", "11" is input as a 2-bit code signal from the input terminal CTLA. Specifically, "1" is input from the input terminal CTLA_1, and "1" is input from the input terminal CTLA_2. Also, "00" is input as a 2-bit code signal from the input terminal CTLB. Specifically, "0" is input from the input terminal CTLB_1, and "0" is input from the input terminal CTLB_2.

[0200] The gate of the third PMOS transistor of the inverter circuit 58a_1 receives "0 (=L)", which is an inverted value of the input value from the input terminal CTLA_1. The gate of the third NMOS transistor of the inverter circuit 58a_1 receives "1 (=H)", which is an input value from the input terminal CTLA_1. That is, the third PMOS transistor and the third NMOS transistor of the inverter circuit 58a_1 are turned on. Therefore, a clock signal is output that rises when the fourth PMOS transistor is turned on and falls when the fourth NPMOS transistor is turned on. That is, a signal that inverts the rising and falling edges of the signal input from the delay element 54β via the input terminal IN_A (the signal obtained by delaying the signal CLK_DET by the delay element 54β) is output from the inverter circuit 58a_1. Similarly, in the inverter circuit 58a_2, the third PMOS transistor and the third NMOS transistor are turned on, so that a signal with inverted rising and falling edges of the signal input from the delay element 54β via the input terminal IN_A (the signal CLK_DET delayed by the delay element 54β) is output.

[0201] On the other hand, the gate of the third PMOS transistor of the inverter circuit 58b_1 receives "1 (=H)", which is an inverted value of the input value from the input terminal CTLB_1. Also, the gate of the third NMOS transistor of the inverter circuit 58b_1 receives "0 (=L)", which is an input value from the input terminal CTLB_1. That is, the third PMOS transistor and the third NMOS transistor of the inverter circuit 58b_1 are in the off state. Therefore, no signal is output from the inverter circuit 58b_1. Similarly, the third PMOS transistor and the third NMOS transistor of the inverter circuit 58b_2 are in the off state, so that no signal is output.

[0202] As a result, when the value of the control signal CTL is "11", the signal input from the delay element 54β via the input terminal IN_A (the signal obtained by delaying the signal CLK_DET by the delay element 54β) is output from the output terminal OUT of the PI circuit 57β.

[0203] FIG. 30B shows a case where the 2-bit control signal CTL is "10". When the value of the control signal CTL is "10", "10" is input from the input terminal CTLA as a 2-bit code signal. Specifically, "1" is input from the input terminal CTLA_1, and "0" is input from the input terminal CTLA_2. Also, "01" is input from the input terminal CTLB as a 2-bit code signal. Specifically, "0" is input from the input terminal CTLB_1, and "1" is input from the input terminal CTLB_2.

[0204] The gate of the third PMOS transistor of the inverter circuit 58a_1 receives "0 (=L)", which is an inverted value of the input value from the input terminal CTLA_1. The gate of the third NMOS transistor of the inverter circuit 58a_1 receives "1 (=H)", which is an input value from the input terminal CTLA_1. That is, the third PMOS transistor and the third NMOS transistor of the inverter circuit 58a_1 are turned on. Therefore, a clock signal is output that rises when the fourth PMOS transistor is turned on and falls when the fourth NPMOS transistor is turned on. That is, a signal that inverts the rising and falling edges of the signal input from the delay element 54β via the input terminal IN_A (the signal obtained by delaying the signal CLK_DET by the delay element 54β) is output from the inverter circuit 58a_1.

[0205] On the other hand, the gate of the third PMOS transistor of the inverter circuit 58a_2 receives "1 (=H)", which is an inverted value of the input value from the input terminal CTLA_2. Also, the gate of the third NMOS transistor of the inverter circuit 58a_2 receives "0 (=L)", which is an input value from the input terminal CTLA_2. That is, the third PMOS transistor and the third NMOS transistor of the inverter circuit 58a_2 are in the OFF state. Therefore, no signal is output from the inverter circuit 58a_2.

[0206] The gate of the third PMOS transistor of the inverter circuit 58b_1 receives "1 (=H)", which is an inverted value of the input value from the input terminal CTLB_1. The gate of the third NMOS transistor of the inverter circuit 58b_1 receives "0 (=L)", which is an input value from the input terminal CTLB_1. That is, the third PMOS transistor and the third NMOS transistor of the inverter circuit 58b_1 are in the OFF state. Therefore, no signal is output from the inverter circuit 58b_1.

[0207] On the other hand, a value "0 (=L)" which is an inverted value of the input value from the input terminal CTLB_2 is input to the gate of the third PMOS transistor of the inverter circuit 58b_2. Also, a value "1 (=H)" which is an input value from the input terminal CTLB_2 is input to the gate of the third NMOS transistor of the inverter circuit 58b_2. That is, the third PMOS transistor and the third NMOS transistor of the inverter circuit 58b_2 are turned on. That is, a signal obtained by inverting the rising and falling edges of the signal input from the delay element 54(β+1) via the input terminal IN_B (the signal obtained by delaying the signal CLK_DET by the delay element 54(β+1)) is output from the inverter circuit 58b_2.

[0208] From the above, when the value of the control signal CTL is "10", the signal output from the inverter circuit 58a_1 is an inverted signal of the signal input from the delay element 54β via the input terminal IN_A (the signal obtained by delaying the signal CLK_DET by the delay element 54β), and the signal output from the inverter circuit 58b_2 is an inverted signal of the signal input from the delay element 54(β+1) via the input terminal IN_B (the signal obtained by delaying the signal CLK_DET by the delay element 54(β+1)). That is, the signal obtained by delaying the signal CLK_DET by the delay element 54β and the signal obtained by delaying the signal CLK_DET by the delay element 54(β+1) are merged at a 1:1 ratio. The merged signal is inverted by the inverter and output from the output terminal OUT of the PI circuit 57β. As described above, the PI circuit 57β adjusts the delay time of the signal CLK_DET between the delay time by the delay element 54β and the delay time by the delay element 54(β+1) according to the value of the control signal CTL, and outputs the adjusted delay time. As shown in Fig. 31, when the difference between the delay time by the delay element 54β and the delay time by the delay element 54(β+1) is 0.25Tw, the signal CLK_DETβ with a delay time in increments of 0.125Tw can be generated by setting the value of the control signal CTL to "10".

[0209] As described above, the edge detection circuit of the embodiment generates the delay amount of the signal input to the delay line 53m using a two-stage circuit consisting of the delay element 54β and the delay unit 57. As a result, by adding the delay unit 57 (m PI circuits 57β) without changing the number of delay lines 53m, it is possible to double the signals with different delay differences in a time-division manner. As a result, it is possible to reduce the delay difference of the signals input to the delay element 54β. Therefore, it is possible to improve the measurement resolution while suppressing an increase in area and an increase in current consumption due to an increase in flip-flops.

[0210] It is also possible to further improve the measurement resolution by increasing the number of inverter circuits 58a_δ of the PI circuit 57β and the number of bits of the control signal CTL to 3 or more bits and increasing the number of inverter circuits 58b_γ in accordance with the increase in bits.

[0211] Also, the PI circuit can be configured using the configuration of the FINE delay circuit 611 in the DCA circuit. Third embodiment Next, a third embodiment will be described below, in which the edge detection circuits shown in the first and second embodiments are used in a DLL (Delay Lock Loop) circuit.

[0212] 32 is a block diagram showing an example of the configuration of a DLL circuit in the third embodiment. The DLL circuit of the embodiment includes a DCD circuit 41, an arithmetic circuit 102, and a delay generation circuit 103. The DCD circuit 41 is a circuit that observes one cycle width and two cycle widths of a clock signal and converts the difference between them into the number of stages of delay elements for one cycle. The DCD circuit 41 outputs a signal DCD_CODE that indicates the width of one cycle of the input clock DCD_IN as the signal DCD_CODE.

[0213] The arithmetic circuit 102 receives the signal DCD_CODE output from the DCD circuit 41, and compares the one-cycle width with the two-cycle width of the input clock DCD_IN, and converts one cycle of the clock signal into the number of delay elements based on the comparison result.

[0214] The delay generation circuit 103 calculates the number of delay elements by which to delay the clock signal CLK_IN, based on the number of delay elements output from the calculation circuit 102. Based on the result of the calculation, the delay generation circuit 103 delays the clock signal CLK_IN to generate the output clock signal CLK_OUT.

[0215] FIG. 33 is a timing chart for explaining an example of the operation of the DCD circuit in the third embodiment. The input clock DCD_IN is input to the DCD circuit 41. The signal generating circuit 51 detects the rising edge of the first cycle of the input clock DCD_IN in each set, and maintains the signal CLK_DLY at a high level for the same period as the period from this rising edge to the rising edge of the second cycle of the input clock DCD_IN. That is, the signal generating circuit 51 maintains the signal CLK_DLY at a high level for two cycles of the input clock DCD_IN from the rising edge of the first cycle of the input clock DCD_IN. Also, the signal generating circuit 51 detects the rising edge of the fourth cycle of the input clock DCD_IN in each set, and maintains the signal CLK_DLY at a high level for the same period as the period from this rising edge to the rising edge of the third cycle of the input clock DCD_IN. That is, the signal generating circuit 51 maintains the signal CLK_DLY at a high level for three cycles of the input clock DCD_IN from the rising edge of the fourth cycle of the input clock DCD_IN.

[0216] The signal generating circuit 51 detects the rising edge of the second cycle of the input clock DCD_IN in each set, and maintains the signal CLK_DET at a high level for the same period as the period until the rising edge of the next cycle of the input clock DCD_IN. Also, the signal generating circuit 51 detects the rising edge of the sixth cycle of the input clock DCD_IN in each set, and maintains the signal CLK_DET at a high level for the same period as the period until the rising edge of the next cycle of the input clock DCD_IN.

[0217] In the signals CLK_DLY and CLK_DET generated as described above, the period from the rising edge of the signal CLK_DLY in an odd cycle to the rising edge of the signal CLK_DET is the same as one period of the input clock DCD_IN. Also, the period from the rising edge of the signal CLK_DLY in an even cycle to the rising edge of the signal CLK_DET is the same as two periods of the input clock DCD_IN.

[0218] Using the signals CLK_DLY and CLK_DET thus generated, the edge detection circuit 53 generates a signal DCD_CODE and outputs it for each set.

[0219] The arithmetic circuit 102 uses a plurality of sets of the signal DCD_CODE output from the DCD circuit 41 to calculate the number of delay elements for one cycle of the input clock DCD_IN. Specifically, the arithmetic circuit 102 integrates the number of high-level bits of the signal DCD_CODE in odd-numbered cycles of the signal CLK_DET for the number of sets to calculate an average (first average value). The arithmetic circuit 102 also integrates the number of high-level bits of the signal DCD_CODE in even-numbered cycles of the signal CLK_DET for the number of sets to calculate an average (second average value). The difference between the second average value and the first average value is calculated, and the width of one cycle of the input clock is converted into the number of delay elements.

[0220] The delay generation circuit 103 calculates the number of delay elements by which to delay the clock signal CLK_IN based on the number of delay elements output from the arithmetic circuit 102. Fig. 34 is a timing chart explaining the phase adjustment of a clock signal in DDR communication. For example, when a semiconductor device performs DDR (Double Data Rate) communication, it is necessary to adjust the phase of the clock so that the rising and falling edges of the clock signal coincide with the center timing of the data. When a clock CLK_IN and a data signal DATA_IN having the same rising timing are input, the delay generation circuit 103 delays the clock CLK_IN by ¼ the number of delay elements output from the arithmetic circuit 102 to generate an output clock CLK_OUT.

[0221] As described above, the edge detection circuit of the embodiment can be used not only in DCC circuits but also in DLL circuits, and can improve the measurement resolution of the period to be measured while suppressing an increase in area and an increase in current consumption that accompanies an increase in flip-flops.

[0222] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0223] 1...memory controller, 2...semiconductor memory device, 2A...interface chip, 2B...non-volatile memory, 11...RAM, 12...processor, 13...host interface, 14...ECC circuit, 15...memory interface circuit, 16...internal bus, 20...DCC circuit, 21...memory cell array, 22...input / output circuit, 24...logic control circuit, 26...register, 27...sequencer, 28...voltage generation circuit, 30...row decoder, 31...sense amplifier unit, 32...group of input / output pads, 34...group of logic control pads, 35...group of power supply input terminals, 41 ...DCD circuit, 42...arithmetic circuit, 43...DCA circuit, 44...waveform generation circuit, 51...signal generation circuit, 52...delay element array circuit, 53...edge detection circuit, 55, 57...delay section, 551, 552...delay element, 56...selector, 58a, 58b...inverter circuit group, 61, 62...delay block circuit, 530...delay line group, 531 to 534...delay line, 540...delay element group, 571 to 574...PI circuit, 611e, 611о...FINE delay circuit, 612...COURSE delay circuit, 613...code control circuit, 615...delay element, 616...code conversion circuit,

Claims

1. a first delay circuit including a plurality of delay element groups each including a plurality of first delay elements each having a first delay amount connected in series; a second delay circuit that generates a plurality of output clock signals having delay differences of a second delay amount smaller than the first delay amount from one input clock signal; a variable delay circuit capable of setting a third delay amount smaller than the second delay amount; having a second delay circuit and a variable delay circuit connected in series between an output terminal of a reference clock and an input terminal of the first delay circuit, the second delay circuit and the variable delay circuit being connected in series between the output terminal of the reference clock and an input terminal of the first delay circuit;

2. 2. The semiconductor integrated circuit according to claim 1, wherein the variable delay circuit has a plurality of second delay elements whose difference in delay amount is set to the third delay amount, and a selector, and the plurality of second delay elements are connected in parallel between an input terminal of the variable delay circuit and an input terminal of the selector.

3. 2. The semiconductor integrated circuit according to claim 1, wherein the variable delay circuit is configured with a phase interpolation circuit to which the two output clock signals having the second delay amount output from the second delay circuit are input.

4. the second delay circuit includes a plurality of third delay elements, the difference between the delay amounts of which is set to the second delay amount; the number of the third delay elements is equal to the number of the delay element groups, and output terminals of the third delay elements are connected to input terminals of the delay element groups in a one-to-one relationship; 3. The semiconductor integrated circuit according to claim 2, wherein the number of said second delay elements is smaller than the number of said third delay elements.

5. A semiconductor memory device connected to a controller and configured to transfer commands, addresses, and transfer data other than the commands and addresses, The semiconductor memory device includes: an interface chip provided with a duty adjustment circuit that measures a pulse width of a clock signal using the semiconductor integrated circuit according to claim 1; a non-volatile memory chip in which a memory cell array having a plurality of memory cells is formed; having The duty adjustment circuit adjusts the duty ratio of a read enable signal or a data strobe signal transmitted and received between a controller and the nonvolatile memory chip.

6. 6. A memory system comprising: the semiconductor memory device according to claim 5; and the controller according to claim 5.

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