Adaptive receiver with pre-cursor elimination

Abstract

The present disclosure relates to an adaptive receiver with pre-cursor elimination. A data receiver circuit includes an adder circuit, the adder circuit being configured to receive an input signal encoding a plurality of data symbols and combine the input signal with a feedback signal to generate an equalized input signal, the equalized input signal being used to generate a clock signal. The data receiver circuit also includes a plurality of data clipper circuits, the data clipper circuits using the clock signal and a plurality of voltage offsets to perform sampling to generate a plurality of samples of a particular data symbol. A pre-cursor compensation circuit included in the data receiver circuit can use the plurality of samples to generate an output value of the particular data symbol. The data receiver circuit also includes a post-cursor compensation circuit, the post-cursor compensation circuit using at least one of the plurality of samples and a value of a previously received sample to generate the feedback signal.

Description

[0001] This application is a divisional application of invention patent application 202011187643.3, filed on October 30, 2020, and entitled “Adaptive Receiver with Pre-Cursor Elimination”. Technical Field

[0002] Embodiments described herein relate to the field of high-speed interface design, and more particularly, to eliminating inter-symbol interference. Background Art

[0003] Computing systems often contain many interconnected integrated circuits. In some cases, the integrated circuits can communicate using communication channels or links to transmit and receive data bits. The communication channels can support parallel communication, where multiple data bits are transmitted in parallel, or serial communication, where one data bit is transmitted at a time in a serial manner.

[0004] Data transmitted between integrated circuits can be encoded to aid in transmission. For example, in the case of serial communication, the data can be encoded to provide transitions between logic states sufficient to allow clock and data recovery circuits to operate. Alternatively, in the case of parallel communication, the data can be encoded to reduce switching noise or improve signal integrity.

[0005] During data transmission, the physical characteristics of the communication channel may cause the transmit signal associated with a particular data symbol to attenuate. For example, line impedance contained in a communication channel or link may cause certain frequency ranges of the transmit signal to be attenuated. In addition, impedance mismatches between wiring contained in the communication channel and devices coupled to the communication channel may cause reflections of the transmit signal, which may also degrade subsequent transmit signals corresponding to other data symbols. Summary of the invention

[0006] Various embodiments of an apparatus and method for eliminating inter-symbol interference in serial data transmission are disclosed. Broadly speaking, a method and apparatus are contemplated in which an adder circuit may be configured to receive an input signal encoding a plurality of data symbols and combine the input signal with a feedback signal to generate an equalized signal. A clock generator circuit may be configured to generate a clock signal using the equalized signal. A data clipper circuit may be configured to sample the equalized signal using a plurality of voltage offsets and the clock signal to generate a plurality of samples of a particular data symbol in a plurality of data symbols. A precursor compensation circuit may be configured to generate an output value of a particular data symbol using the plurality of samples, and a post cursor compensation circuit may be configured to generate the feedback signal using at least one sample of the plurality of samples and the value of a previously received data symbol. In another non-limiting embodiment, the data clipper circuit may also be configured to sample the equalized input signal using the plurality of voltage offsets to generate a plurality of error samples. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0008] Figure 1 is a block diagram showing an embodiment of a receiver circuit with pre-cursor elimination.

[0009] Figure 2 shows the input signal waveform.

[0010] Figure 3 is a block diagram showing an embodiment of a post-cursor compensation circuit.

[0011] Figure 4 is a block diagram showing an embodiment of a data clipper circuit.

[0012] Figure 5 is a block diagram showing different embodiments of a data clipper circuit.

[0013] Figure 6 is a block diagram showing another embodiment of a data clipper circuit.

[0014] Figure 7 is a block diagram showing an embodiment of a pre-cursor compensation circuit.

[0015] Figure 8 is a flow chart describing an embodiment of a method for operating a data receiver circuit including pre-cursor elimination.

[0016] Fig. 9A is a flow chart describing an embodiment of a method for adapting clock recovery.

[0017] Fig. 9B is a flow chart describing another embodiment of a method for adapting clock recovery.

[0018] Fig.10 is a flow chart describing an embodiment of a method for performing clock recovery.

[0019] Fig.11 is a block diagram depicting two devices coupled by a communication channel.

[0020] Fig.12 An embodiment of a computer system is presented.

[0021] Although the present disclosure is susceptible to various modifications and alternative forms, its specific embodiments are shown in the drawings by way of example and will be described in detail herein. However, it should be understood that the drawings and embodiments of the present disclosure are not intended to limit the present disclosure to the disclosed specific forms, but on the contrary, the purpose is to cover all modifications, equivalents and alternatives within the spirit and scope of the present disclosure defined by the appended claims. The titles used herein are only used for organizational purposes and are not intended to limit the scope of the specification. As used throughout this application, the word "may" is used in an allowed sense (i.e., meaning that it is possible), rather than a mandatory sense (i.e., meaning that it must). Similarly, the words "include, including and includes" mean including but not limited to.

[0022] Various units, circuits, or other components may be described as being "configured to" perform one or more tasks. In such a context, "configured to" is a broad statement of a structure that generally means "having a circuit system that performs one or more tasks during operation." In this way, a unit / circuit / component may be configured to perform a task even when the unit / circuit / component is not currently connected. In general, the circuit system that forms the structure corresponding to "configured to" may include a hardware circuit. Similarly, for ease of description, various units / circuits / components may be described as performing one or more tasks. Such descriptions should be interpreted as including the word "configured to." The enumeration of units / circuits / components configured to perform one or more tasks is explicitly not intended to invoke the interpretation of the unit / circuit / component in paragraph (f) of 35 U.S.C. §112. More broadly, the recitation of any element is explicitly not intended to invoke the interpretation of the element in paragraph (f) of 35 U.S.C. §112 unless there is a specific description of "device for..." or "step for...".

[0023] As used herein, the term "based on" is used to describe one or more factors that influence a decision. This term does not exclude the possibility that additional factors may influence the decision. That is, a decision may be based only on specified factors or on specified factors and other unspecified factors. When considering the phrase "determine A based on B", this phrase specifies that B is a factor used to determine A or influence the decision of A. This phrase does not exclude that the decision of A may also be based on some other factors, such as C. This phrase is also intended to cover embodiments in which A is decided based only on B. The phrase "based on" is therefore synonymous with the phrase "based at least in part on". DETAILED DESCRIPTION

[0024] A computing system may include one or more devices or integrated circuits, such as, for example, a central processing unit (CPU) and a memory. Each integrated circuit of a computing system may communicate via a serial or parallel interface. In a parallel interface, multiple data bits are communicated simultaneously, while in a serial interface, data is communicated as a series of consecutive individual data bits (commonly referred to as "symbols"). When a serial interface is used to transfer data between two devices or integrated circuits included in a computing system, the data may be transmitted according to different protocols. For example, data may be transmitted using return to zero (RZ), non-return to zero (NRZ), pulse amplitude modulation (PAM), or any suitable combination thereof.

[0025] When symbols are transmitted, the signal encoding the symbols may be distorted. In some cases, the distortion accumulates from the medium in which the signal propagates in a linearly predictable form, which is called "inter-symbol interference" or "ISI". As used herein, ISI is the impairment of the currently transmitted symbol caused by previous and future symbols. Previous symbols cause ISI for the following symbol, and future symbols cause ISI for the preceding symbol.

[0026] To reduce the effects of ISI in computer systems, various techniques can be employed, such as using a decision feedback equalizer (DFE). A DFE generates a series of data symbols by sampling an input signal. The series of data symbols, some of which may be scaled, can be used to generate a signal that is combined with the input signal to eliminate post-cursor ISI. This type of DFE has a causal relationship that prevents the elimination of pre-cursor ISI. By eliminating only post-cursor ISI, pre-cursor ISI still has a significant impact on the channel performance between the transmitter circuit and the receiver circuit.

[0027] Various techniques (e.g., pre-cursor pre-emphasis) may be employed to reduce the effects of pre-cursor ISI, but these techniques make adaptation within the receiver circuit difficult because the transmitter circuit has no information about the channel response without communication from the receiver circuit. Embodiments shown in the figures and described herein may provide techniques for mitigating the pre-cursor effect while providing for adaptation within the receiver circuit.

[0028] Figure 1 An embodiment of a data receiver circuit is shown. As shown in the figure, the data receiver circuit 100 includes an adder circuit 101, a data sampling circuit 102, a clock generator circuit 103, a front cursor compensation circuit 104 and a rear cursor compensation circuit 105.

[0029] The adder circuit 101 is configured to receive an input signal 106 encoding a plurality of data symbols 107 and to combine the input signal 106 with a feedback signal 113 to produce an equalized signal 109. In various embodiments, the adder circuit 101 may be a specific embodiment of a summing amplifier configured to combine the voltage levels of two or more input signals into a single voltage level on an output signal. In various embodiments, the adder circuit 101 may include a differential amplifier circuit or any other suitable amplifier circuit that may be used as a gain stage in a summing amplifier.

[0030] The clock generator circuit 103 is configured to generate a clock signal 110 using the equalized signal 109. In some embodiments, the clock generator circuit 103 may be configured to perform a process commonly referred to as "clock recovery" using the equalized signal 109 to generate the clock signal 110. In various embodiments, the clock generator circuit 103 may employ phase detector circuits, as well as phase-locked loop or delay-locked loop circuits, latch circuits, flip-flop circuits, and any other suitable combination of analog or digital circuits.

[0031] The phase detector circuit employed by the clock generator circuit (such as clock generator circuit 103) can be linear or nonlinear. For example, the clock generator circuit 103 can use a nonlinear bang-bang phase detector, which is configured to compare the negative edge of the clock signal 110 with a specific transition on the equalized signal 109 of the current data symbol and a different transition on the equalized signal 109 of the previous data symbol. Using the results of the comparison, the timing of the clock signal 110 can be adjusted using a delay lock or a phase-locked loop. Alternatively, the clock generator circuit 103 can use a Mueller-Muller phase detector circuit, which is configured to equalize the respective amplitudes of samples taken before and after the pulse of the clock signal 110 by adjusting the timing of the clock signal 110. Note that although only two types of phase detector circuits are described, in other embodiments, any suitable phase detector circuit can be used.

[0032] The data sampling circuit 102 is configured to sample the equalized signal 109 using the voltage offset 108 and the clock signal 110 to produce samples 111 of particular ones of the data symbols 107. Note that some of the samples 111 may be used to determine the output data bits 112 (data samples), while other samples 111 (error samples) may be used to perform adaptation within the data receiver circuit 100. As described in more detail below, the data sampling circuit 102 may include a plurality of data clipper circuits, each coupled to a respective one of the voltage offsets 108. The particular data clipper circuit may be a particular embodiment of a differential amplifier or other suitable circuit that may be configured to compare the voltage level of the equalized signal 109 to the voltage level of the corresponding voltage offset signal of the data clipper circuit when the clock signal 110 is asserted.

[0033] The pre-cursor compensation circuit 104 is configured to generate an output data bit 112 for a particular data symbol of the data symbols 107 using the samples 111. As described in more detail below, the pre-cursor compensation circuit 104 may be a particular embodiment of an unfolded loop decision feedback equalizer circuit that selects between different samples 111. In some cases, the selection is made using samples from one or more data symbols 107 received prior to the particular data symbol.

[0034] The post-cursor compensation circuit 105 is configured to use at least one of the samples 111 associated with the particular data symbol and a different sample associated with a different one of the data symbols 107 received prior to the particular data symbol to generate the feedback signal 113. In various embodiments, the post-cursor compensation circuit 105 may be a specific embodiment of a decision feedback equalizer (DFE) or other suitable circuit configured to adjust the voltage level of the feedback signal 113 using the value of the previously received data symbol.

[0035] Notice, Figure 1 The embodiment shown is only one example. In other embodiments, different circuit blocks or different circuit block arrangements may be used.

[0036] As described above, when a specific data symbol is transmitted from a transmitter circuit to a receiver circuit, the signal encoding the specific data symbol may be affected by the previously transmitted data symbols and the data symbols transmitted after the specific data symbol. Figure 2 An example waveform is depicted as shown.

[0037] As shown, the voltage level of the input signal 200 is depicted as a function of time. In various embodiments, the input signal 200 may correspond to: Figure 1 The input signal 106 is shown. The contribution from the preceding cursor symbol is represented by hm1 offset 202 and the contribution from the succeeding cursor symbol is represented by h1 offset 203.

[0038] In some cases, prior to transmission, the input signal 200 may be modified using a finite impulse response (FIR) filter to remove pre-cursor contributions to the input signal 200. The usefulness of such filtering is limited because it may reduce the dynamic range of the input signal 200 at the transmitter circuitry, as well as introduce other pre-cursor contributions to the input signal 200.

[0039] The residual pre-cursor contribution may adversely affect the performance of the communication channel or link. The amount by which the input signal 200 can be modified by the FIR filter to eliminate the pre-cursor effect is limited because more emphasis for the first pre-cursor symbol produces larger residuals for other pre-cursor symbols. The residual pre-cursor contribution may cause the clock data recovery circuit to lock prematurely, or produce an edge / data offset that is less than half of the unit interval (UI) 204.

[0040] The post-cursor compensation circuit 105 may be a specific embodiment of a FIR filter. Figure 3 A block diagram showing an embodiment of the post-cursor compensation circuit 105 is depicted in FIG. As shown, the post-cursor compensation circuit 105 includes a delay circuit 301, a weighting circuit 302, and an adder circuit 303.

[0041] Delay circuit 301 receives sample 111 and generates tapped signals 304. Each tapped signal 304 is a replica of sample 111 that is delayed by a specific time period. For example, an initial tapped signal in tapped signals 304 is delayed from sample 111 by the specific time period. The next tapped signal after initial tapped signal 304 is delayed from initial tapped signal 304 by the specific time period. Delay circuit 301 may include a plurality of latch circuits, flip-flop circuits, or any other circuit suitable for generating a desired delay between tapped signals.

[0042] The weighting circuit 302 is configured to generate a weighted signal 305 using the tapped signal 304 and the voltage offset 108. In various embodiments, the weighting circuit 302 can generate a specific voltage on a given one of the weighted signals 305 using the value of a corresponding one of the tapped signals 304 and a corresponding one of the voltage offsets 108. The weighting circuit 302 can include a plurality of amplifier circuits that can be configured to buffer based at least in part on the corresponding voltage levels of the tapped signal 304 and the voltage offset 108.

[0043] The adder circuit 303 may be a specific embodiment of a summing amplifier circuit configured to add the respective voltage levels of the weight signals 305 to generate the feedback signal 113. In various embodiments, the adder circuit 303 may be implemented as an operational amplifier or other suitable amplifier circuit configured to generate an output signal having a voltage level that is the sum of the respective voltage levels of two or more input signals.

[0044] The data sampling circuit 102 may be implemented according to various circuit topologies using different numbers of data clipper circuits (or simply “clipper circuits”) and offset voltages. Figure 4-6 Different circuit topologies that may be used for the data sampling circuit 102 are shown.

[0045] Steering Figure 4 , depicts a block diagram of an embodiment of data sampling circuit 102. As shown, data sampling circuit 102 includes clipper circuits 401-410. Each of clipper circuits 401-410 is coupled to equalized signal 109 and a corresponding one of offsets 413-422. Clipper circuits 401-406 are configured to use offsets 413-418 to generate samples 423-428, respectively. Clipper circuits 407-410 are configured to use offsets 419-422 to generate samples 429-432, respectively. Note that offsets 413-422 can be included in voltage offset 108, and samples 423-432 can be included in sample 111.

[0046] Can be combined Figure 4The illustrated embodiment uses various offset values. Table 1 shows a specific set of voltage offset values. As used herein, H0 is a voltage level corresponding to the target amplitude of the equalized signal 109, H1 is a voltage level corresponding to the effective amplitude of the first post-cursor value, and Hm1 is a voltage level corresponding to the effective amplitude of the first pre-cursor value.

[0047] Table 1 - Figure 4 The offset value

[0048] Offset value 413 H1 414 -H1 415 H1+Hm1 416 -H1-Hm1 417 H1-Hm1 418 -H1+Hm1 419 -H0+H1+Hm1 420 -H0+H1-Hm1 421 H0+H1+Hm1 422 H0+H1-Hm1

[0049] Using the offset values ​​listed in Table 1, samples 423 and 424 may be used to generate raw bit decisions within pre-cursor compensation circuit 104. In addition, clipper circuits 407-410 provide coverage of 50% of possible voting patterns for a particular symbol value, which allows good tracking of changes in channel response for clock / data recovery purposes.

[0050] Each of the clipper circuits 401-406 can be a specific embodiment of a clock-controlled differential amplifier circuit configured to generate a digital value using a comparison result of an input signal when a clock signal is set. For example, the clipper circuit 401 can be configured to generate a sample 423 by comparing the equalized signal 109 with the offset 413 when the clock signal 110 is set. If the voltage level of the equalized signal 109 is greater than the voltage level of the offset 413 when the clock signal 110 is set, the sample 423 can be set to a specific logic value. Alternatively, if the voltage level of the equalized signal 109 is less than the voltage level of the offset 413 when the clock signal 110 is set, the sample 423 can be a different logic value. In some embodiments, the clipper circuits 401-406 can include a latch or other suitable storage circuit configured to store a specific value of the sample until the next setting of the clock signal 110 occurs.

[0051] The clipper circuits 407-410 may be specific embodiments of differential amplifier circuits configured to generate digital values ​​using comparison results of the corresponding input signals and the equalized signal 109. Unlike the clipper circuits 401-406, the clipper circuits 407-410 do not use the clock signal 110, thereby providing samples that vary as the voltage level of the equalized signal 109 varies relative to the offsets 419-422.

[0052] Figure 5 Another embodiment of the data sampling circuit 102 is depicted in FIG. In this embodiment, the data sampling circuit 102 includes clipper circuits 501-507. Note that the clipper circuits 501-505 can be configured similar to Figure 4The illustrated clipper circuits 401 - 406 operate in a similar manner, and clipper circuits 506 and 507 may be configured to operate in a similar manner to clipper circuits 407 - 410 .

[0053] exist Figure 5 In the case of an embodiment of the present invention, the clock generator circuit 103 is configured to lock when H1 is equal to Hm1, which results in a lock point close to the peak in the pulse response received from the communication link. Because H1 and Hm1 are equal, fewer clipper circuits are required. For example, one less data clipper circuit is used, and two less error clipper circuits are used. In addition, the reference voltage digital-to-analog converter (DAC) can be eliminated. By using fewer clipper circuits and reference DACs, circuit complexity, area, and power consumption can be reduced.

[0054] Table 2 shows Figure 5 Voltage offsets of the depicted embodiment of data sampling circuit 102 . As described above, offsets 510 - 516 may be included in voltage offset 108 .

[0055] Table 2 - Figure 5 The offset value

[0056]

[0057]

[0058] In some cases, the data sampling circuit 102 may be further simplified at the expense of performance. An example of such a modification is Figure 6 The data sampling circuit 102 is shown in the embodiment shown. As shown in the figure, Figure 6 The embodiment of the data sampling circuit 102 includes the clipper circuits 601-605. Note that the clipper circuits 601-602 can be configured similar to Figure 4 The clipper circuits 401-406 are shown to operate in a similar manner, and the clipper circuits 604 and 605 may be configured to operate in a similar manner to the clipper circuits 407-410.

[0059] As shown in Table 3 below, the offset used in the original bit slicer circuits (i.e., slicer circuits 601 and 602) is a function of H1 and Hm1. Figure 4 The need for three additional data clipper circuits is reduced in the embodiment, but for certain modes processed by the pre-cursor compensation circuit 104, the error is an H1 tap error of 2Hm1.

[0060] Table 3 shows Figure 6 Voltage offsets of the depicted embodiment of data sampling circuit 102 . As described above, offsets 606 - 610 may be included in voltage offset 108 .

[0061] Offset value 606 H1+Hm1 607 -H1-Hm1 608 0 609 -H0 610 -H0+H1-Hm1

[0062] Steering Figure 7 , depicts a block diagram of an embodiment of the pre-cursor compensation circuit 104. As shown in the figure, the pre-cursor compensation circuit 104 includes latch circuits 701-703 and an N-bit carry lookahead processing circuit 704.

[0063] Each of latch circuits 701-703 represents multiple instances of latch circuits, each coupled to a different clock signal to capture a corresponding one of Hm1 samples <7:0> 705, -Hm1 samples <7:0> 706, and 0 samples <7:0> 707, all of which may be included in samples 111. Each of Hm1 samples <7:0> 705 is sampled during a corresponding unit interval using a voltage level corresponding to Hm1. In a similar manner, -Hm1 samples <7:0> 706 and 0 samples <7:0> 707 are sampled in a similar manner using a negative version of the voltage corresponding to Hm1 and a voltage level at or near ground potential, respectively. Note that although Figure 7 The use of eight samples for each input is depicted, but in various embodiments any suitable number of samples may be used.

[0064] The N-bit carry lookahead processing circuit 704 may be configured to select the value of a particular data symbol based on the value of future data symbols. In various embodiments, the N-bit carry lookahead processing circuit 704 may use a different number of future bits when determining the value of a particular data symbol.

[0065] In one case, the N-bit carry lookahead processing circuit 704 may employ a 1-bit carry lookahead, wherein the immediately future data symbol is used to select which of the preceding cursor bits, i.e., one of the Hm1 samples <7:0> 705 or one of the -Hm1 samples <7:0> 706. Alternatively, the N-bit carry lookahead processing circuit 704 may employ a 2-bit future data symbol to select the appropriate one of the Hm1 samples <7:0> 705 or -Hm1 samples <7:0> as output. Note that any suitable number of future data symbols may be employed.

[0066] In various embodiments, the N-bit carry lookahead processing circuit 704 may include a plurality of selection circuits coupled to Hm1 sample <7:0> 705, -Hm1 sample <7:0> 706 and 0 sample <7:0> 707 and signals 708 - 710. The selection circuits may be arranged in parallel, in series or any suitable combination thereof.

[0067] In various embodiments, the selection circuit may be a specific embodiment of a multiplexer or other suitable circuit configured to generate an output signal by selecting a specific one of a plurality of inputs using respective control signals. In some embodiments, a given selection circuit may include one or more transmission gates, or a plurality of logic gates, or any suitable combination thereof.

[0068] like Figure 1-7 The structures for eliminating inter-symbol interference shown in can be referenced using functional language. In some embodiments, these structures can be described as including "means for receiving an input signal encoding a plurality of data symbols", "means for combining the input signal with a feedback signal to generate an equalized signal", "means for generating a clock signal using the equalized signal", and "means for sampling using a plurality of voltage offsets and a clock signal", equalizing the signal to generate a plurality of samples of a specific data symbol among a plurality of data symbols, "means for generating an output value of a specific data symbol using the plurality of samples", and "means for generating a feedback signal using at least one of the plurality of samples and a value of a previously received data symbol".

[0069] The corresponding structure of the “means for receiving an input signal encoding a plurality of data symbols” is the adder circuit 101 and its equivalent. The corresponding structure of the “means for combining the input signal and the feedback signal to generate an equalized signal” is the adder circuit 101 and other equivalent circuits. The corresponding structure of the “means for generating a clock signal using the equalized signal” is the clock generator circuit 103 and its equivalent. The data sampling circuit 102 and its equivalent are the corresponding structures of the “means for sampling the equalized signal using a plurality of voltage offsets and clock signals to generate a plurality of samples of a specific data symbol among a plurality of data symbols”. The corresponding structures of the “means for generating an output value of a specific data symbol using a plurality of samples” are the latch circuits 701-703 and the N-bit carry lookahead processing circuit 704 and their equivalents. The delay circuit 301, the weighting circuit 302 and the adder circuit 303 and their equivalents are the corresponding structures of the “means for generating a feedback signal using at least one of the plurality of samples and the value of a previously received data symbol”.

[0070] Steering Figure 8 , a flow chart describing an embodiment of a method for operating a data receiver circuit including pre-cursor compensation is shown. This method can be applied to Figure 1 The receiver circuit 100 is shown starting at block 801 .

[0071] The method includes receiving an input signal encoding a plurality of data symbols (block 802). In various embodiments, the method may include receiving the input signal from a transmitter circuit over a channel. In some embodiments, the value of a particular one of the plurality of data symbols may correspond to a plurality of bits.

[0072] The method further includes combining the input signal with the feedback signal to generate an equalized signal (block 803). In various embodiments, the method may further include adding respective voltage levels of the input signal and the feedback signal to generate the equalized signal.

[0073] The method also includes generating a clock signal using the equalized signal (block 804). In various embodiments, the method may also include receiving a reference clock signal and generating the clock signal using the reference clock signal. In some cases, the method may include phase locking the clock signal to one or more transitions included in the equalized signal.

[0074] The method also includes sampling the equalized signal using the plurality of voltage offsets and the clock signal to generate a plurality of samples of a particular data symbol in the plurality of data symbols (block 805). In various embodiments, the method may also include sampling the equalized input signal using the plurality of voltage offsets to generate a plurality of error samples. In some cases, the method may include generating a clock signal using the equalized signal and the plurality of error samples.

[0075] The method also includes generating an output value for a particular data symbol using the plurality of samples (block 806). In some embodiments, the method may include predicting one or more future data symbols using the plurality of samples. In various embodiments, the method may include adapting a plurality of voltage offsets using at least one future data symbol of the one or more future data symbols.

[0076] In various embodiments, the plurality of voltage offsets may include a voltage offset corresponding to a contribution to the voltage level of the input signal produced by a particular future data symbol of the one or more future data symbols. In some cases, the voltage offset corresponding to the contribution of the particular future data symbol to the voltage level of the input signal is equal to the contribution of the particular past data symbol to the voltage level of the input signal.

[0077] The method also includes generating a feedback signal using at least one of the plurality of samples and a value of a previously received data symbol (block 807). In some embodiments, the method may include comparing the equalized signal with the sum of a voltage offset corresponding to a contribution to the voltage level of the input signal generated by a particular future data symbol and a voltage offset corresponding to a contribution to the voltage level of the input signal generated by a particular past data symbol. In this case, the method may also include comparing the equalized signal with a negative version of a voltage offset corresponding to a contribution to the voltage level of the input signal generated by a particular future data symbol and a voltage offset corresponding to a contribution to the voltage level of the input signal generated by a particular past data symbol. The method ends at block 808.

[0078] As described above, when receiving data, the operating parameters of the clock generator circuit 103 may be adjusted or adapted based on the time at which the equalized signal 109 is sampled during the unit interval. This adaptation process may allow the sampling point to be adjusted to maintain the sampling point at or near the peak of the impulse response received over the communication channel or link. Fig. 9A An embodiment of a method for adapting a clock generator circuit is shown. This method can be applied to a data receiver circuit 100 and can be used with Figure 8 The method shown is used in combination, and this method begins at box 901.

[0079] This method includes using samples generated using a voltage level associated with a first rear cursor symbol to adapt clock data recovery (block 902). As described above, different clipper circuits use different comparison voltage levels to generate respective samples. The various samples can be used not only to determine the value of a received symbol, but also to adjust the clock data recovery operation. In this embodiment, only samples generated using a voltage level associated with a first rear cursor symbol can be used. Symbols generated using other voltage levels (which can correspond to other pre-cursor or post-cursor symbols) can be ignored.

[0080] In some embodiments, the method may include adjusting one or more operating parameters of the clock generator circuit 103. Adjusting the parameters may include writing one or more values ​​to corresponding control registers included in the clock generator circuit 103. The method ends at block 903.

[0081] There are a number of methods that can be used to tune clock data recovery in data receiver circuits. Fig. 9B Another embodiment of a method for adjusting clock data recovery is described in the flowchart of FIG. This method can be applied to the data receiver circuit 100 and is used in conjunction with Figure 8 The method shown is used in conjunction with the method, which begins at box 904.

[0082] This method includes collecting post-DFE error samples (block 905). As described above, the data sampling circuit 102 generates not only data samples but also error samples. In some cases, the post-cursor compensation circuit 105 further processes the data samples and the error samples to generate the feedback signal 113. The error samples that have been processed by the post-cursor compensation circuit 105 can be stored in a latch, register, or other suitable storage circuit for later use.

[0083] This method also includes using the post-DFE error samples to adapt the clock data recovery (block 906). In this case, the error samples operated after the post-cursor compensation circuit 105 operates can be used to adjust the operating parameters of the clock generator circuit 103. Other processed samples or other samples not processed by the post-cursor compensation circuit 105 can be ignored.

[0084] as Fig. 9A The method shown in FIG. 9A may include adjusting one or more operating parameters of the clock generator circuit 103. In some cases, the adjustment may include writing one or more values ​​to corresponding control registers included in the clock generator circuit 103. The method ends at block 907.

[0085] Steering Fig.10 , depicts a flow chart illustrating an embodiment of a method for performing clock data recovery. This method may be applied to a data receiver circuit 100, starting at block 1001.

[0086] This method includes setting an edge / data offset to half of a unit interval (block 1002). In various embodiments, the edge / data offset is used to sample the equalized signal 109 and is selected to be half of a unit interval based on the assumption that the equalized signal 109 will be at a maximum value for a particular symbol halfway through the unit interval of the particular symbol.

[0087] The method also includes adapting clock / data recovery circuitry parameters (block 1003). As the characteristics of the communication link or channel change, the peak location of the equalized signal 109 may move away from the middle of the unit interval of a particular symbol. When this occurs, the edge / data offset may be adjusted to move toward the peak of the equalized signal 109. In various embodiments, the method may include writing one or more values ​​to registers used by or included in the clock generator circuit 103. Note that block 1003 may correspond to Fig. 9A or Fig. 9B Any of the methods described in . This method ends at box 1004.

[0088] Fig.11An example of two computer systems coupled via a communication channel in a computer network is described. As shown, computer network 1100 includes computer systems 1101 and 1102, each coupled to communication channel 1105. Note that although Fig.11 In the illustrated embodiment, only two computer systems are depicted, but in other embodiments, any suitable number of computer systems may be included in computer network 1100 .

[0089] Computer system 1101 includes transmitter circuitry 1103. In various embodiments, the transmitter circuitry may transmit data to computer system 1102 using communication channel 1105. Transmitter circuitry 1103 may reformat the data prior to transmission. Such reformatting may include converting parallel data into a serial stream of data symbols, and adding error detection and correction data bits.

[0090] Communication channel 1105 may include one or more wires, circuit board traces, optical cables, or any other suitable medium capable of propagating a signal encoding a plurality of data symbols. In some cases, the medium may be selected to provide a particular impedance between the two computer systems. In such cases, transmitter circuit 1103 and data receiver circuit 100 may include circuit elements to match the impedance of the medium used in communication channel 1105. Although in Fig.11 In the embodiment shown, only a single communication channel is depicted, but in other embodiments, any suitable number of communication channels between computer systems 1101 and 1102 may be employed.

[0091] As described above, the data receiver circuit 100 may be configured to receive a signal transmitted by the transmitter circuit 1103 via the communication channel 1105. The data receiver circuit 100 may also be configured to compensate for pre-cursor and post-cursor interference caused by the signal transmission through the communication channel 1105 in order to recover the data bits encoded in the signal.

[0092] Fig.12 1 shows a block diagram of a computer system. In the illustrated embodiment, computer system 1200 includes processor circuit 1202, memory circuit 1203, input / output circuit 1204, and analog / mixed signal circuit 1205, each of which can be configured to send and receive data using communication bus 1206. In various embodiments, computer system 1200 can be configured for desktop computers, servers, or mobile computing applications (such as tablet computers or laptop computers), and can correspond to, for example, Fig.11 Either computer system 1101 or computer system 1102 is shown.

[0093] In various embodiments, the processor circuit 1202 may represent a general purpose processor that performs computing operations. For example, the processor circuit 1202 may be a central processing unit (CPU) (such as a microprocessor), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other suitable processing circuits.

[0094] In various embodiments, the memory circuit 1203 may include any suitable type of memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Fig.12 In the illustrated embodiment, a single memory circuit is depicted. In other embodiments, any suitable number of memory circuits may be employed.

[0095] Input / output circuitry 1204 includes data receiver circuitry 100 and may be configured to coordinate data transfers between computer system 1200 and one or more devices using communication channel 1207. In various embodiments, communication channel 1207 may employ a serial data transfer protocol, and data receiver circuitry 100 may determine the value of received data symbols as described above. Such devices may include, but are not limited to, storage devices (e.g., magnetic or optical media based storage devices, including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, input / output circuitry 1204 may be configured to implement a Universal Serial Bus (USB) protocol or IEEE 1394. In various embodiments, communication channel 1207 may correspond to Fig.11 Communication channel 1105 is shown.

[0096] Input / output circuitry 1204 may also be configured to coordinate data transfers between computer system 1200 and other computer systems or integrated circuits coupled to computer system 1200 via a network. In one embodiment, input / output circuitry 1204 may be configured to perform data processing required to implement an Ethernet (IEEE 802.3) network standard (e.g., Gigabit Ethernet or 10 Gigabit Ethernet), although it is contemplated that any suitable network standard may be implemented. In some embodiments, input / output circuitry 1204 may be configured to implement multiple discrete network interface ports.

[0097] Analog / mixed signal circuit 1205 may include various circuits including, for example, a crystal oscillator, a phase-locked loop (PLL), an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC) (all not shown). In other embodiments, analog / mixed signal circuit 1205 may be configured to perform power management tasks including on-chip power supplies and voltage regulators.

[0098] It should be noted that Fig.12 The embodiment of the computer system depicted in is only one example. In other embodiments, different numbers of circuit blocks and different circuit block arrangements may be used.

[0099] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even in the case where only a single embodiment is described with respect to a particular feature. Unless otherwise stated, the examples of features provided in the present disclosure are intended to be illustrative rather than restrictive. The above description is intended to cover such alternatives, modifications, and equivalents that are obvious to those skilled in the art having the benefit of this disclosure.

[0100] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly) or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during the prosecution of the present application (or an application claiming priority thereto) to any such combination of features. Specifically, with reference to the attached claims, features of the dependent claims may be combined with features of the independent claims, and features of the respective independent claims may be combined in any appropriate manner, and not merely in the specific combinations listed in the attached claims.

Claims

1. A device comprising: The adder circuit is configured as: receiving an input signal encoding a plurality of data symbols; as well as combining the input signal with a feedback signal to produce an equalized signal; a clock generator circuit configured to generate a clock signal using the equalized signal; a data sampling circuit configured to sample the equalized signal using a plurality of voltage offsets and the clock signal to generate a plurality of samples of a particular data symbol of the plurality of data symbols; The front cursor compensation circuit is configured as: determining a value of at least one future data symbol; as well as selecting a given one of the plurality of samples to produce an output value for the particular data symbol using the value of the at least one future data symbol; as well as a post-cursor compensation circuit configured to generate the feedback signal using at least one sample of the plurality of samples and a value of a previously received data symbol; and wherein the clock generator circuit is further configured to adjust an operating parameter of the clock signal using a particular sample obtained from the plurality of samples; The specific samples include samples generated using a voltage level associated with a first post-cursor symbol or post-decision feedback equalizer (DFE) error samples.

2. The device according to claim 1, wherein: The clock generator circuit comprises a plurality of register circuits, and wherein, to adjust the operating parameter of the clock signal, the clock generator circuit is further configured to store an updated value in at least one register circuit of the plurality of register circuits.

3. The device according to claim 2, wherein: The operating parameters associated with the clock signal include data offset parameters.

4. The device according to claim 1, wherein: The data sampling circuit includes a plurality of error clipper circuits configured to sample the equalized signal using one or more of the plurality of voltage offsets to generate a plurality of error samples.

5. The device according to claim 1, wherein: The multiple voltage offsets further include a specific voltage offset and a different voltage offset, wherein the specific voltage offset corresponds to a first contribution to the voltage level of the input signal generated by a past data symbol, and the different voltage offset corresponds to a second contribution to the voltage level of the input signal generated by the at least one future data symbol, and wherein the different voltage offset is the same as the specific voltage offset.

6. A method comprising: receiving an input signal encoding a plurality of data symbols; combining the input signal with a feedback signal to produce an equalized signal; generating a clock signal using the equalized signal; comparing the equalized signal to a plurality of voltage offsets using the clock signal to produce a corresponding plurality of samples of a particular data symbol of the plurality of data symbols; determining a value of at least one future data symbol; selecting, using said value of said at least one future data symbol, a given one of said corresponding plurality of samples to produce an output value for said particular data symbol; generating the feedback signal using at least one sample of the corresponding plurality of samples and a value of a previously received data symbol; and adjusting the clock signal using a particular sample obtained from the corresponding plurality of samples, The specific samples include samples generated using a voltage level associated with a first post-cursor symbol or post-decision feedback equalizer (DFE) error samples. 7 . The method of claim 6 , further comprising sampling the equalized signal using the plurality of voltage offsets to produce a plurality of error samples.

8. The method according to claim 6, wherein: Adjusting the clock signal includes modifying one or more operating parameters associated with the clock signal.

9. The method of claim 8, further comprising storing modified operating parameters associated with the clock signal in a register circuit.

10. The method according to claim 8, wherein: The one or more operating parameters include a data offset parameter.

11. The method according to claim 6, further comprising: The value of at least one voltage offset of the plurality of voltage offsets is adjusted using the value of the at least one future data symbol.

12. The method according to claim 6, wherein: The multiple voltage offsets further include a specific voltage offset and a different voltage offset, wherein the specific voltage offset corresponds to a first contribution to the voltage level of the input signal generated by a past data symbol, and the different voltage offset corresponds to a second contribution to the voltage level of the input signal generated by the at least one future data symbol, and wherein the different voltage offset is the same as the specific voltage offset.

13. An apparatus comprising: A first computer device configured to transmit a signal encoding a plurality of data symbols; A second computer device is configured to: receiving the signal; combining the signal with a feedback signal to produce an equalized signal; generating a clock signal using the equalized signal; sampling the equalized signal using a plurality of voltage offsets and the clock signal to generate a plurality of samples of a particular data symbol of the plurality of data symbols; determining a value of at least one future data symbol; selecting a given one of the plurality of samples to produce an output value for the particular data symbol using the value of the at least one future data symbol; generating the feedback signal using at least one sample of the plurality of samples and a value of a previously received data symbol; as well as adjusting the clock signal using a particular sample obtained from the plurality of samples, The specific samples include samples generated using a voltage level associated with a first post-cursor symbol or post-decision feedback equalizer (DFE) error samples.

14. The device according to claim 13, wherein: The second computer device is further configured to sample the equalized signal using the plurality of voltage offsets to generate a plurality of error samples.

15. The device according to claim 13, wherein: To adjust the clock signal, the second computer device is further configured to modify one or more operating parameters associated with the clock signal.

16. The device according to claim 15, wherein: The second computer device comprises a plurality of register circuits, and wherein the second computer device is configured to store modified operating parameters associated with the clock signal in a particular register circuit of the plurality of register circuits.

17. The device according to claim 15, wherein: The one or more operating parameters include a data offset parameter.

18. The device according to claim 13, wherein: The second computer device is further configured to adjust a value of at least one voltage offset of the plurality of voltage offsets using the value of the at least one future data symbol.

19. The device according to claim 13, wherein: The multiple voltage offsets further include a specific voltage offset and a different voltage offset, wherein the specific voltage offset corresponds to a first contribution to the voltage level of the signal generated by a past data symbol, and the different voltage offset corresponds to a second contribution to the voltage level of the signal generated by the at least one future data symbol, and wherein the different voltage offset is the same as the specific voltage offset.

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