Lateral power device with reduced on-resistance

Abstract

A lateral power semiconductor device is provided with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each including a source bar and a drain bar. The source bars of the first, second, and third metal layers are electrically connected. The drain bars of the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layers are parallel, and the second metal layer is perpendicular to the first and third metal layers. A non-conductive layer electrically connects the solder bumps to only the source bars or only the drain bars. As a result, multiple available paths exist, allowing current to take any of the multiple available paths.

Description

[Technical field]

[0001] The present invention relates generally to the field of semiconductor devices, and more particularly to gallium nitride (GaN) power semiconductor devices, and to methods of interconnecting such devices. [Background technology]

[0002] Conventional lateral power field effect transistors (FETs) include long, thin metal interconnects used to connect the transistor cells to the external leads of the semiconductor device. However, these interconnects increase the parasitic resistance of the semiconductor device and the on-resistance of the device. As the die size of FETs increases and more transistor cells are connected in parallel to withstand more power, the parasitic resistance of these interconnects and therefore the on-resistance of the device also increases. Therefore, there is a need to provide lateral power devices with interconnects that have reduced parasitic resistance to reduce the on-resistance. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention addresses the shortcomings of conventional metal interconnects in lateral power FETs described above by providing a metal interconnect layout with multiple available current paths to reduce parasitic resistance and reduce on-resistance of lateral power devices such as GaN FET semiconductor devices. [Means for solving the problem]

[0004] The present invention includes a first metal layer of source and drain metal bars, a second metal layer of source and drain metal bars, and a third metal layer of source and drain metal bars, as described herein. The source metal bars of the first, second and third metal layers are electrically connected. The drain metal bars of the first, second and third metal layers are electrically connected. In one embodiment, the first and second metal layers are substantially parallel and the third metal layer is substantially perpendicular to the first and second metal layers. In another embodiment, the first and third metal layers are substantially parallel and the second metal layer is substantially perpendicular to the first and third metal layers. The non-conductive layer ensures that the solder bump electrically connects to only one of the source or drain metal bars. As a result, there are multiple available paths, allowing the current to take any of the multiple available paths.

[0005] These and other preferred features described herein, including various novel details of implementation and combination of elements, will be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the specific methods and apparatus are shown by way of example only and not as limitations on the scope of the claims. As will be appreciated by those skilled in the art, the principles and features of the teachings herein can be employed in numerous and varied embodiments without departing from the scope of the claims.

[0006] The features, objects and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0007] [Figure 1A] 1 shows a GaN transistor device according to a first embodiment of the present invention. [Figure 1B] 1 shows a GaN transistor device according to a first embodiment of the present invention. [Figure 1C] 1 shows a GaN transistor device according to a first embodiment of the present invention. [Figure 2A] 1A-C illustrate a process for forming the transistor device shown in FIG. [Figure 2B] 1A-C illustrate a process for forming the transistor device shown in FIG. [Figure 2C] 1A-C illustrate a process for forming the transistor device shown in FIG. [Figure 2D] 1A-C illustrate a process for forming the transistor device shown in FIG. [Figure 2E] 1A-C illustrate a process for forming the transistor device shown in FIG. [Figure 2F] 1A-C illustrate a process for forming the transistor device shown in FIG. [Figure 2G] 1A-C illustrate a process for forming the transistor device shown in FIG. [Figure 2H] 1A-C illustrate a process for forming the transistor device shown in FIG. [Figure 2I] 1A-C illustrate a process for forming the transistor device shown in FIG. [Figure 3A] 1 shows a GaN transistor device according to a first embodiment of the present invention. [Figure 3B] 1 shows a GaN transistor device according to a first embodiment of the present invention. [Figure 4A] 2 shows a GaN transistor device according to a second embodiment of the present invention. [Figure 4B] 2 shows a GaN transistor device according to a second embodiment of the present invention. [Figure 4C] 2 shows a GaN transistor device according to a second embodiment of the present invention. [Figure 5A] 4A-C show the layout of metal interconnects within the transistor device shown in FIG. [Figure 5B] 4A-C show the layout of metal interconnects within the transistor device shown in FIG. [Figure 5C] 4A-C show the layout of metal interconnects within the transistor device shown in FIG. [Figure 5D] 4A-C show the layout of metal interconnects within the transistor device shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In the following detailed description, reference is made to specific embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed and that various structural, logical and electrical changes may be made. The combinations of features disclosed in the following detailed description are not required to practice the teachings in their broadest sense, but are instead taught only to illustrate particularly representative examples of the present teachings.

[0009] Although the embodiments described herein include GaN semiconductor devices, it should be understood that the present invention is not limited to GaN semiconductor devices. For example, the described embodiments may be applicable to semiconductor devices and other devices that use various conductive materials, such as silicon (Si) or silicon carbide (SiC) semiconductor devices and germanium (Ge) material semiconductor devices.

[0010] Additionally, while buried or diffused conductive regions or layers are described, it should be understood that these are examples of regions of opposite polarity within a substrate. Thus, while the described embodiments may refer to particular methods of fabricating opposite polarity regions, it should be understood that other types of opposite polarity regions and methods of fabrication thereof may be used.

[0011] The described embodiments include integrated circuits having a conductive substrate and including transistors or other semiconductor devices, e.g., GaN transistors or transistors, where regions of the substrate are doped with a conductivity opposite to that of the regions of the substrate. The regions of opposite polarity can be, for example, n-type material in a p-type substrate. The devices have electrical connections from the front contacts to the regions of opposite polarity, such as through vias. In other embodiments, the regions can have the same doping type as the substrate and can be surrounded by one or more insulating layers. In other embodiments, the substrate can be substantially non-conductive, but the regions have either p-type or n-type doping. In other embodiments, silicon-on-insulator (SOI) embodiments and embodiments including parallel conductive channels are also described.

[0012] 1A-C show a GaN transistor device 100 according to a first embodiment of the present invention. FIG. 1A shows a cross-sectional view of the GaN transistor device 100 including a substrate 186 composed of one or more of Si, SiC, GaN, gallium arsenide (GaAs), aluminum nitride (AlN), and / or sapphire-based materials. A buffer layer 184 is formed on the substrate 186 and may be composed of one or more layers of a compound semiconductor material (e.g., an AlN material). A channel layer 182 is formed on the buffer 184 and may be composed of one or more layers of GaN having a thickness between 0.05 and 5 micrometers (μm). In some implementations, the channel layer 182 is composed of indium gallium nitride (InGaN) or other suitable material having sufficient electron density and electron mobility to facilitate the flow of current through the channel layer 182. The barrier layer 180 is formed on the channel layer 182 and may be composed of aluminum gallium nitride (AlGaN) having a thickness of 0.005 to 0.03 μm and 12-28% Al.

[0013] A gate layer 194 is selectively formed in parallel lines directly on the barrier layer 180 and may be composed of a III-V compound having a thickness of 0.05 to 0.2 μm. In some implementations, the gate layer 194 may be a p-type compound such as GaN doped with magnesium (Mg). A gate electrode 198 is formed directly on the gate layer 194 and may be a refractory metal or a compound thereof, such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), palladium (Pd), tungsten (W), tungsten nitride (WSi 2 ), etc. An insulator 190 covers the gate layer 194 and the gate electrode 198, insulating them and the barrier layer 180 from the components above them.

[0014] The first metal layer 110 includes source metal bars 115 and drain metal bars 120 selectively formed in substantially parallel lines on the barrier layer 180 between the gate electrodes 198, which may be comprised of aluminum copper (AlCu). The second metal layer 130 includes a source metal bar 135 selectively formed substantially parallel on the source metal bar 115 of the first metal layer 110. The source metal bars 135 and 115 are electrically connected by a via 125A, as shown more clearly in FIG. 2C. The second metal layer 130 also includes a drain metal bar 140 selectively formed substantially parallel on the drain metal bar 120 of the first metal layer 110. The drain metal bars 140 and 120 are electrically connected by a via 125B, as shown more clearly in FIG. 2C. The metal bars 135 and 140 of the second metal layer 130 may be comprised of AlCu.

[0015] The third metal layer 150 includes a source metal bar 155 and a drain metal bar 160, which may be composed of AlCu. Figure 1A shows the source metal bar 155 selectively formed substantially perpendicular to the first metal layer 110 and the second metal layer 130. The source metal bars 155 and 135 are electrically connected by vias 125A, as shown more clearly in Figure 2E. The vias 125A may be spaced such that the source metal bar 155 is not electrically connected to the drain metal bar 140 of the second metal layer 130.

[0016] 1B, which shows a top view of device 100, third metal layer 150 also includes drain metal bar 160 selectively formed substantially perpendicular to first metal layer 110 and second metal layer 130 and substantially parallel to source metal bar 155. As shown more clearly in FIG. 2F, drain metal bars 160 and 140 are electrically connected by via 125B. Via 125B may be spaced apart such that drain metal bar 160 is not electrically connected to source metal bar 135 of second metal layer 130. Vias 125A-B are further described with reference to FIGS. 2E-F.

[0017] Returning to FIG. 1A, the spaces between the source metal bars 115, 135, and 155 and the drain metal bars 120, 140, and 160 are filled with silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 The third metal layer 150 is filled with a dielectric film 165, which may be composed of a silicon nitride (SiN) or the like. A non-conductive layer 170 is selectively formed on the third metal layer 150 and the dielectric film 165, such that each solder bump 175 is electrically connected only to the source metal bar 155 or only to the drain metal bar 160, but not to both. The non-conductive layer 170 may be formed of one or more Si 3 N 4 , SiO 2 1B shows that solder bump 175A is electrically connected to source metal bar 155 rather than drain metal bar 160, and solder bump 175B is electrically connected to drain metal bar 160 rather than source metal bar 155. Solder bumps 175A-B may be composed of tin-silver alloy (SnAg) and an under-bump metal such as titanium (Ti) and / or copper (Cu), having a thickness of 50-400 μm.

[0018] FIG. 1C shows a perspective view of the device 100. The first metal layer 110 and the second metal layer 130 are substantially parallel. The source metal bar 135 covers the source metal bar 115 and is electrically connected to the source metal bar 115 by a via 125A. The drain metal bar 140 covers the drain metal bar 120 and is electrically connected to the drain metal bar 120 by a via 125B. The third metal layer 150 is substantially perpendicular to the first metal layer 110 and the second metal layer 130. The source metal bar 155 is perpendicular to the source metal bars 115 and 135 and is electrically connected to the source metal bar 135 by a via 125A. The drain metal bar 160 is perpendicular to the drain metal bars 120 and 140 and is electrically connected to the drain metal bar 140 by a via 125B.

[0019] The non-conductive layer 170 is formed on the third metal layer 150 and prevents the solder bump 175A from electrically connecting to the drain metal bar 160. The solder bump 175A electrically connects to two or more source metal bars 155 by directly contacting the source metal bars 155 and may include under-bump metal to ensure good electrical connection. The first metal layer 110, the second metal layer 130 and the third metal layer 150 create multiple available current paths and reduce the on-resistance of the device 100 by allowing the current through the device 100 to take any of the multiple available current paths. Furthermore, the non-conductive layer 170 ensures that the solder bump 175 is electrically connected only to the source metal bar 155 or only to the drain metal bar 160, allowing the solder bump 175 to function as a conventional source and drain pad and reducing the metal resistance.

[0020] 2A-H show the layout of device 100 in more detail. In FIG. 2A, a substrate 186 is provided, such as on a wafer substrate, and a buffer layer 184, a channel layer 182 and a barrier layer 180 are layered on the substrate 186. A channel layer 182, comprised of InGaN or other suitable material, is layered on the buffer layer 184 and has a thickness between 0.01 and 0.5 μm. A barrier layer 180, comprised of AlGaN, is layered on the channel layer 182 and has a thickness between 0.005 and 0.03 μm. The AlGaN can be 12-28% Al.

[0021] The gate layer 194 forms substantially parallel lines on the barrier layer 180 and has a thickness between 0.05 and 0.2 μm. The gate layer 194 may be composed of, for example, Mg-doped GaN material. The gate electrode 198 is layered on the gate layer 194. In some embodiments, the gate layer 194 and the gate electrode 198 each have a thickness between about 0.01 and about 1.0 μm. The insulator 190 selectively covers the barrier layer 180, the gate layer 194, and the gate electrode 198. The insulator 190 separates the gate layer 194 and the gate electrode 198 from other components above them on the device 100 and covers selected portions of the barrier layer 180, leaving an opening 205 for the source metal bar 115 and an opening 210 for the drain metal bar 120 formed directly above the barrier layer 180.

[0022] The first metal layer 110 forms substantially parallel lines across the barrier layer 180 between the insulator 190 in the opening 205 and the gate electrode 198. The space between the source metal bar 115 and the gate electrode 198 is smaller than the space between the drain metal bar 120 and the gate electrode 198. The metal layer 110 may include a titanium aluminum alloy. Figure 2B shows the parallel lines of the gate electrode 198, metal bars 115 and 120, and the relative spacing between each.

[0023] As shown in FIG. 2C, the second metal layer 130 forms substantially parallel lines on the metal layer 110. The source metal bar 135 is layered on the source metal bar 115 and is electrically connected by a via 125A. The drain metal bar 140 is layered on the drain metal bar 120 and is electrically connected by a via 125B. The line 210 shows the boundary between the first metal layer 110 and the second metal layer 130. FIG. 2D shows the overlap of the second metal layer 130 and the first metal layer 110, and the via 125A electrically connecting the source metal bars 115 and 135, and the via 125B electrically connecting the drain metal bars 120 and 140.

[0024] As shown in Figure 2E, the third metal layer 150 forms a substantially vertical line on the second metal layer 130. Figure 2E shows a source metal bar 155 layered over both the source metal bar 135 and the drain metal bar 140 and electrically connected to the source metal bar 135 by a via 125A. Figure 2F shows a degree line metal bar 160 layered over both the source metal bar 135 and the drain metal bar 140 and electrically connected to the drain metal bar 140 by a via 125B. The empty spaces between the metal layers 110, 130 and 150 may be filled by a dielectric film 165, as can be seen in both Figures 2E and 2F. FIG. 2G shows the vertical overlap of a third metal layer 150 on the parallel metal layers 110 and 130, as well as spaced vias 125A to electrically connect source metal bars 155 and 135, and spaced vias 125B to electrically connect drain metal bars 160 and 140.

[0025] As shown in FIG. 2H, the non-conductive layer 170 is selectively formed on the metal layer 150, leaving openings 220 for the solder bumps 175A to electrically connect to the source metal bar 155 and openings 225 for the solder bumps 175B to electrically connect to the drain metal bar 160, not shown. The solder bumps 175 are formed on the openings 220 and 225 to electrically connect two or more source metal bars 155 or two or more drain metal bars 160, respectively. The solder bumps 175A are in direct contact with the source metal bar 155, while the solder bumps 175B are isolated from the source metal bar 155. FIG. 2I shows a top view of the solder bumps 175 on the third metal layer 150, as well as the openings 220 for the solder bumps 175A to electrically connect to the source metal bar 155 and the openings 225 for the solder bumps 175B to electrically connect to the drain metal bar 160.

[0026] 3A-B show a GaN transistor device 300 according to a variation of the first embodiment of the present invention. The device 300 is similar to the device 100 shown in FIGS. 1A-C, except that the metal bars 355 and 360 of the third metal layer 350 are not of constant width. FIG. 3A shows a top view illustrating the overlap of the third metal layer 350 on the metal layers 310 and 330. The source metal bar 355 is wider at portion 355A and narrower at portion 355B. Conversely, the drain metal bar 360 is narrower at portion 360A and wider at portion 360B. The wider offset portions of the source metal bar 355 and the drain metal bar 360 can be interleaved while the threshold distance between the ends of the source metal bar 355 and the drain metal bar 360 is maintained. In some implementations, the threshold distance between the ends of the source metal bar 355 and the drain metal bar 360 is 2 μm.

[0027] 3B shows a top view of device 300. Solder bump 375 covers the interleaved, wider portions of metal bars 355 and 360. Solder bump 375A covers wider portion 355A of source metal bar 355, and solder bump 375B covers wider portion 360B of drain metal bar 360. The increased width of portion 355A of source metal bar 355 and portion 360B of drain metal bar 360 increases the contact area for solder bumping and allows for better current spreading. Additionally, the wider portions of metal bars 355 and 360 increase the distance between the contact area for the bump and the ends of metal bars 355 and 360, which enlarges the contact area of ​​solder bump 375 and reduces the current density and contact resistance of metal bars 355 and 360.

[0028] 4A-C show a GaN transistor device 400 according to a second embodiment of the present invention. The device 400 is similar to the device 100 shown in FIGS. 1A-C, including similar parameters and similar fabrication processes, but implementing a different layout of source and drain metal bars in the first, second and third metal layers. FIG. 4A shows a cross-sectional view of the GaN transistor device 400, including a substrate 486, a buffer layer 484, a channel layer 482, a barrier layer 480, a gate layer 494 and a gate electrode 498, and an insulator 490 similar to the corresponding components of the device 100. The first metal layer 410 includes source metal bars 415 and drain metal bars 420 selectively formed in substantially parallel lines on the barrier layer 480 between the gate electrodes 498.

[0029] The second metal layer 430 includes a source metal bar 435, not shown in FIG. 4, and a drain metal bar 440, one of which is shown in FIG. 4A. The source metal bar 435 and the drain metal bar 440 are selectively formed substantially perpendicular to the first metal layer 410. The drain metal bars 440 and 420 are electrically connected by vias 425B, as shown more clearly in FIG. 5B. The vias 425B can be spaced apart such that the drain metal bar 440 is not electrically connected to the source metal bar 415. The source metal bar 435, not shown in the cross-sectional view of FIG. 4A, is electrically connected to the source metal bar 415 by vias 425A. The vias 425A can be spaced apart such that the source metal bar 435 is not electrically connected to the drain metal bar 420 of the first metal layer 410.

[0030] The third metal layer 450 includes source metal bars 455 and drain metal bars 460 selectively formed substantially parallel to the first metal layer 410 and substantially perpendicular to the second metal layer 430. The source metal bars 455 are selectively formed substantially perpendicular to the second metal layer 430 and are electrically connected to the source metal bars 435 by vias 425A. The vias 425A can be spaced apart such that the source metal bars 455 are not electrically connected to the drain metal bars 440. The drain metal bars 460 are selectively formed substantially perpendicular to the second layer 430 and are electrically connected to the drain metal bars 440 by vias 425B, as shown more clearly in FIG. 5C. The vias 425B can be spaced apart such that the drain metal bars 460 are not electrically connected to the source metal bars 435. The width of metal bars 455 and 460 in the third metal layer 450 is greater than the width of metal bars 415 and 420 in the first metal layer 410. A dielectric film 465 fills the empty spaces between the metal layers 410, 430 and 450.

[0031] Device 400 also includes a non-conductive layer 470 and solder bumps 475 similar to the corresponding components of device 100. Referring now to FIG. 4B, which shows a top view of device 400, the widths of metal bars 455 and 460 of third metal layer 450 are greater than the widths of metal bars 415 and 420 of first metal layer 410, metal bars 435 and 440 of second metal layer 430, and metal bars 155 and 160 of first metal layer 110 of device 100 shown in FIGS. 1A-C. The increased width of metal bars 455 and 460 increases the contact area for the bumps, allowing for better current spreading. Additionally, the increased width of metal bars 455 and 460 increases the distance between the contact area for the bumps and the ends of metal bars 455 and 460, which reduces on-chip stresses induced by temperature changes.

[0032] 4C shows a perspective view of device 400. Second metal layer 430 is substantially perpendicular to first metal layer 410, and third metal layer 450 is substantially perpendicular to second metal layer 430 and substantially parallel to first metal layer 410. Source metal bars 435 and 415 are electrically connected by via 425A, and drain metal bars 440 and 420 are electrically connected by via 425B. Source metal bars 455 and 435 are electrically connected by via 425A, and drain metal bars 460 and 440 are electrically connected by via 425B.

[0033] The non-conductive layer 470 is formed on the third metal layer 450 and prevents the solder bump 475A from electrically connecting to the drain metal bar 460. The solder bump 475A electrically connects to the source metal bar 455 by directly contacting the source metal bar 455 and may include under-bump metal to ensure good electrical connection. The first metal layer 410, the second metal layer 430 and the third metal layer 450 create multiple available current paths and reduce the on-resistance of the device 400 by allowing the current through the device 400 to take any of the multiple available current paths. Furthermore, the non-conductive layer 470 ensures that the solder bump 475 is electrically connected only to the source metal bar 455 or only to the drain metal bar 460, allowing the solder bump 475 to function as a conventional source and drain pad and reducing the metal resistance.

[0034] 5A-D show the layout of the first metal layer 410, second metal layer 430, third metal layer 450 and solder bumps 475 of the device 400 shown in FIGS. 4A-C. In FIG. 5A, which shows a top view of the first metal layer 410, the metal bars 415 and 420 are substantially parallel to and between the gate electrode 498. The space between the source metal bar 415 and the gate electrode 498 is smaller than the space between the drain metal bar 420 and the gate electrode 498. FIG. 5B shows a top view of the second metal layer 430, which is substantially vertically overlaid on the first metal layer 410. The source metal bar 435 covers both the source metal bar 415 and the drain metal bar 420 and is electrically connected to the source metal bar 415 by via 425A. The drain metal bar 440 covers both the source metal bar 415 and the drain metal bar 420 and is electrically connected to the drain metal bar 425 by via 425B. The width of metal bars 435 and 440 may be greater than the width of metal bars 415 and 420 .

[0035] 5C shows a top view of a third metal layer 450 overlaid substantially perpendicular to the second metal layer 430 and substantially parallel to the first metal layer 410. A source metal bar 455 covers both the source metal bar 435 and the drain metal bar 440 and is electrically connected to the source metal bar 435 by a via 425A. A drain metal bar 460 covers both the source metal bar 435 and the drain metal bar 440 and is electrically connected to the drain metal bar 445 by a via 425B. The width of the metal bars 455 and 460 may be greater than the width of the metal bars 435 and 440.

[0036] 5D shows a top view of solder bumps 475 stacked substantially perpendicular to the third metal layer 450 and the first metal layer 410, and substantially parallel to the second metal layer 430. Solder bump 475A directly contacts source metal bars 455 through openings 520 in the non-conductive layer 470, electrically connecting two or more source metal bars 455. Solder bump 475B directly contacts drain metal bars 460 through openings 525 in the non-conductive layer 470, electrically connecting two or more drain metal bars 460.

[0037] The above description and drawings should be considered as illustrative of specific embodiments that achieve the features and advantages described herein. Modifications and substitutions of specific process conditions can be made. Thus, the embodiments of the present invention should not be considered as limited by the above description and drawings. [Explanation of symbols]

[0038] 100 GaN transistor devices 110 First metal layer 115 Sauce Metal Bar 120 Drain metal bar 125A Via 125B via 130 Beer 135 Sauce Metal Bar 140 Drain metal bar 150 3rd metal layer 155 Sauce Metal Bar 160 Drain metal bar 165 Dielectric Film 170 Non-conductive layer 175 Solder Bumps 175A solder bumps 175B solder bumps 180 Barrier Layer 182 Channel Layer 184 Buffer Layer 186 Board 190 Insulators 194 Gate Layer 198 Gate electrode 210 Opening 220 Opening 225 Opening 300 GaN transistor devices 350 3rd metal layer 355 Sauce Metal Bar 355A Wide area 355B Narrow section 360 Drain Metal Bar 360A Narrow section 360B wide part 375A solder bumps 375B Solder Bumps 400 GaN transistor devices 410 First Metal Layer 415 Sauce Metal Bar 420 Drain metal bar 425A Via 425B Via 430 Second Metal Layer 435 Sauce Metal Bar 440 Drain metal bar 450 3rd metal layer 455 Sauce Metal Bar 460 Drain metal bar 465 Dielectric Film 470 Non-conductive layer 475 Solder Bumps 475A solder bumps 475B Solder Bumps 480 Barrier Layer 484 Buffer Layer 486 Board 490 Insulator 494 Gate Layer 498 Gate electrode

Claims

1. one or more gate electrodes; a first metal layer including a plurality of first source bars and a plurality of first drain bars interleaved with the one or more gate electrodes; a second metal layer formed on the first metal layer and separated from the first metal layer by a dielectric, the second metal layer including a plurality of second source bars and a plurality of second drain bars, the first and second source bars being electrically connected and the first and second drain bars being electrically connected; a third metal layer formed on the second metal layer and separated from the second metal layer by the dielectric, the third metal layer including a plurality of third source bars and a plurality of third drain bars, the second and third source bars being electrically connected and the second and third drain bars being electrically connected; a first solder bump electrically connected to the third source bar; a second solder bump electrically connected to the third drain bar; a non-conductive layer between the third metal layer and the first and second solder bumps, the first solder bump directly contacts the third source bar through an opening in the non-conductive layer; the second solder bump directly contacts the third drain bar through an opening in the non-conductive layer; the width of the first and second source bars is smaller than the width of the third source bar, the width of the first and second drain bars is smaller than the width of the third drain bar, the third source bar includes a wider portion and a narrower portion, the third drain bar includes a wider portion and a narrower portion, the wider portion of the third source bar is interleaved with the narrower portion of the third drain bar, and the narrower portion of the third source bar is interleaved with the wider portion of the third drain bar; the first solder bump is electrically connected to the wider portion of the third source bar and the second solder bump is electrically connected to the wider portion of the third drain bar; the first, second and third plurality of source bars and drain bars and their respective electrical connections in the first, second and third metal layers create a plurality of current paths such that current flows through the electrical path having the least resistance, thereby reducing an on-resistance of the lateral power semiconductor device; 11. A lateral power semiconductor device, wherein the first and second metal layers are substantially parallel to one another and the third metal layer is substantially perpendicular to the first and second metal layers.

2. 2. The lateral power semiconductor device of claim 1, wherein said third source bar and said third drain bar are a threshold distance apart.

3. The lateral power semiconductor device of claim 2 , wherein the threshold distance is 2 micrometers apart.

4. A lateral power semiconductor device as described in claim 1, wherein the non-conductive layer separates the first solder bump from the third drain bar and separates the second solder bump from the third source bar.

5. 2. The lateral power semiconductor device of claim 1, wherein the first and second solder bumps are comprised of under-bump metallurgy.

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