Qubit Array

Abstract

A qubit array is disclosed. In an embodiment, the qubit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit in the qubit array, a bit line, and a first transistor channel connecting the bit line to the control gate. The array further includes at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further includes a capacitor coupled to selectively store charge in the first transistor channel.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit under 35 U.S.C. § 119 of U.S. Provisional Application No. 62 / 992,989, filed March 22, 2020, entitled "QUANTUM BIT ARRAY," which is hereby incorporated by reference in its entirety.

[0002] Exemplary embodiments of the present invention relate generally to the field of semiconductors and integrated circuits, and more specifically to the design and operation of qubit arrays. [Background technology]

[0003] In quantum computing, a qubit, or quantum bit, is the basic unit of quantum information. A qubit is a two-state (i.e., two-level) quantum mechanical system. Examples include the spin of an electron, where the two levels can be thought of as spin-up and spin-down, or the polarization of a single photon, where the two states can be thought of as vertical and horizontal polarization. Quantum machines allow a qubit to be a coherent superposition of both states simultaneously, a property that is fundamental to quantum computing.

[0004] Qubit arrays consist of a large number of qubits. Because the qubits are very small, they can be spaced very close to each other in the array. This has the potential to make very large and powerful qubit arrays possible. However, there are limitations to the control structures used to utilize the qubits in qubit arrays. Summary of the Invention

[0005] In various exemplary embodiments, a quantum bit ("qubit") array is provided that includes a control structure that can be used to enable the qubits in the array to be used to construct very closely spaced and very large, high performance quantum bit arrays.

[0006] In an embodiment, a qubit array is provided that includes a control gate coupled to the qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit in the qubit array, a bit line, and a first transistor channel connecting the bit line to the control gate. The array further includes at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further includes a capacitor coupled to selectively store charge in the first transistor channel.

[0007] In an embodiment, a method of operating a quantum array is provided, the method comprising applying one or more first voltages to one or more Y-direction word lines coupled to at least one vertical transistor, and applying one or more second voltages to one or more X-direction word lines coupled to at least one vertical transistor, the method further comprising applying a third voltage to a capacitor coupled to the at least one vertical transistor, and applying one or more bit line voltages to the at least one vertical transistor to control operation of a qubit of the quantum array.

[0008] Additional features and advantages of the present invention will become apparent from the following detailed description, drawings and claims.

[0009] Exemplary embodiments of the present invention will be more fully understood from the detailed description given below of various embodiments of the invention and the accompanying drawings, which should not be construed as limiting the invention to the specific embodiments, but are for purposes of illustration and understanding only. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 shows the substructure of a qubit array. [Figure 2A]FIG. 2A illustrates an exemplary embodiment of a basic unit of a qubit array constructed according to aspects of the present invention. [Figure 2B] FIG. 2B shows an equivalent circuit of the basic unit shown in FIG. 2A. [Figure 2C] FIG. 2C illustrates an exemplary embodiment of a method for operating a qubit array. [Figure 3A] FIG. 3A shows a cross-sectional view of an embodiment of the base unit shown in FIG. 2A. [Figure 3B] FIG. 3B shows a cross-sectional view of an embodiment of the base unit shown in FIG. 2A. [Figure 3C] FIG. 3C shows a cross-sectional view of the embodiment of the base unit shown in FIG. 2A. [Figure 3D] FIG. 3D shows a cross-sectional view of an embodiment of the building block shown in FIG. 2A. [Figure 4A] FIG. 4A illustrates an exemplary embodiment of a basic unit of a qubit array. [Figure 4B] FIG. 4B shows an equivalent circuit of the basic unit shown in FIG. 4A. [Figure 4C] FIG. 4C illustrates an exemplary embodiment of a method for operating a qubit array. [Figure 5A] FIG. 5A shows another embodiment of a basic unit of a qubit array. [Figure 5B] FIG. 5B shows an equivalent circuit of the basic unit shown in FIG. 5A. [Figure 6] FIG. 6 shows another embodiment of a basic unit of a qubit array. [Figure 7A] FIG. 7A illustrates an additional embodiment of a qubit array constructed in accordance with the present invention. [Figure 7B] FIG. 7B illustrates an additional embodiment of a qubit array constructed in accordance with the present invention. [Figure 7C] FIG. 7C illustrates an additional embodiment of a qubit array constructed in accordance with the present invention. [Figure 7D] FIG. 7D illustrates an additional embodiment of a qubit array constructed in accordance with the present invention. [Figure 7E]FIG. 7E illustrates an additional embodiment of a qubit array constructed in accordance with the present invention. [Figure 8A] FIG. 8A illustrates an example operation of the qubit array shown in FIG. 7C. [Figure 8B] FIG. 8B illustrates an example operation of the qubit array shown in FIG. 7C. [Figure 8C] FIG. 8C illustrates an example operation of the qubit array shown in FIG. 7C. [Figure 8D] FIG. 8D illustrates an example operation of the qubit array shown in FIG. 7C. [Figure 9A] FIG. 9A shows an exemplary embodiment of a qubit array that uses three groups of data lines. [Figure 9B] FIG. 9B shows an exemplary embodiment of a qubit array that allows three groups of qubits to be entangled, shuttled, or controlled to perform other operations together. [Figure 10A] FIG. 10A shows an exemplary embodiment of a qubit array that uses four groups of data lines. [Figure 10B] FIG. 10B illustrates another embodiment of a qubit array constructed in accordance with the present invention. [Figure 10C] FIG. 10C illustrates another embodiment of a qubit array constructed in accordance with the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In various exemplary embodiments, methods and apparatus are provided for the design, construction and operation of quantum bit arrays. The embodiments are applicable to any suitable quantum technology, including but not limited to technologies that use qubits such as atoms, photons, electrons, atomic nuclei, ions, optical lattices, Josephson junctions, quantum dots, quantum dot pairs, etc. Furthermore, application of the disclosed quantum bit array structures is not limited to quantum bit arrays, but may be applied to other technologies, such as magnetic memory.

[0012] Those skilled in the art should realize that the following detailed description is for purposes of illustration only and is not intended to be limiting in any manner. Other embodiments of the present invention will readily suggest themselves to those skilled in the art having the benefit of this disclosure. Reference will now be made in detail to examples of illustrative embodiments of the present invention that are illustrated in the accompanying drawings. The same reference characters (or numbers) are used throughout the drawings and the following detailed description to refer to the same or similar parts.

[0013] 1 shows the substructure of a quantum bit array (QBA) 100. The QBA 100 comprises quantum bits 101a-e, also referred to as "qubits." In an embodiment, the qubits 101a-e are formed by implanting one or more atoms of a donor material, such as phosphorus, into a silicon substrate 102. Each qubit has a control gate 104, such as control gates 104a-b. A dielectric layer 103, such as an oxide, or barrier layer, is located over the qubits and between the silicon substrate 102 and the control gate 104. Each control gate 104 is coupled to control a corresponding qubit to read, write, or perform other logical operations.

[0014] The data of a qubit is represented by its "quantum state." A qubit can be read or written in a number of ways. A common approach is to apply radio frequency (RF) or magnetic fields through the control gate 104 to sense or switch the quantum state of a selected qubit. Additionally, a voltage can be supplied to a selected control gate to attract or repel the electron of the associated qubit, initializing the quantum state of that qubit.

[0015] QBA 100 also includes X-direction passgates 105, such as passgates 105a-b, and Y-direction passgates 106, such as passgates 106a-b. When an X-direction passgate, such as passgate 105a, is turned on, it will "entangle" adjacent X-direction qubits 101a-b to perform a "logical operation" or "computation" between those qubits. Similarly, when a Y-direction passgate, such as passgate 106b, is turned on, it will entangle adjacent Y-direction qubits 101d-e to perform a logical operation or computation between those qubits.

[0016] It should be noted that in quantum computing, the distance between adjacent qubits is an important consideration. If the distance is too far, the qubits will not entangle. Typically, the maximum distance between qubits is about 20 nanometers (nm). Because the control gates 104, the X-direction pass gates 105, and the Y-direction pass gates 106 need to be individually controlled, all gates can be connected to a decoder circuit. As a result, it becomes very difficult to integrate a large number of decoder circuits in a qubit array with such closely spaced qubits. In various exemplary embodiments, methods and apparatus for designing, selecting, and controlling the control gates and pass gates of a qubit array are disclosed herein.

[0017] FIG. 2A illustrates an exemplary embodiment of a basic unit of a qubit array 200 constructed according to an aspect of the present invention. As shown in FIG. 2A, the array 200 is built on the substructure illustrated in FIG. 1. For simplicity and clarity of illustration, only a portion of the substructure is illustrated in FIG. 2A. The basic unit illustrated in FIG. 2A can be replicated multiple times and combined to form a larger qubit array. The array 200 includes a control gate 104, an X-direction pass gate 105, and a Y-direction pass gate 106, also as illustrated in the substructure 100 illustrated in FIG. 1. The array 200 also includes silicon or polysilicon channels of three vertical transistors 107a-c. The drains of the vertical transistors 107 are connected to the control gate 104 and the X-direction pass gate 105 and the Y-direction pass gate 106, respectively, through corresponding contacts 109a-c. In other embodiments, the drains of the vertical transistors 107 are directly connected to the control gate 104 and the X-direction pass gate 105 and the Y-direction pass gate 106 without the contacts 109a-c. The sources of the vertical transistors 107 are connected to the bit lines 111a to 111c via corresponding contacts 110a to 110c. The bit lines 111 are made of a conductor such as metal or polysilicon.

[0018] Vertical transistor 107 is coupled to three conductors 112, 113, and 114, which are made of materials such as metal or polysilicon. First conductor 112 is connected to a Y-word line (WLy) and forms a first gate that selectively controls the current through transistors 107a-c. Second conductor 113 is connected to an X-word line (WLx) and forms a second gate that selectively controls the current through transistors 107a-c. In other embodiments, the connections of the WLx and WLy word lines to the conductors are swapped. Word lines WLx and WLy selectively enable the current through transistors 107a-c, thereby allowing selection and operation of one basic unit of the qubit array. Transistors 107a-c connect control gate 104 and pass gates 105 / 106 to bit lines 111b, 111c, and 111a, respectively. In an embodiment, an external programming circuit can control the control gates 104 and pass gates 105 / 106 of a selected unit via bit lines 111a-c to read, write, or perform other logical operations.

[0019] The third conductor 114 forms the third gate, i.e. the "capacitor" gate. In an embodiment, the conductor 114 is connected to a voltage source (VC) to turn on the channels of the transistors 107a-c. The third conductor 114 thus forms a MOS capacitor as described with reference to the cross-sectional views shown in Figures 3A-D. For example, the detailed structure of the MOS capacitor is similar to the planar MOS capacitor, except that vertical transistors are used. Referring now to Figure 3A, the conductor 114 forms a first conductive plate of the capacitor. Additionally, a gate dielectric layer 118 is shown. The channel below the dielectric layer 118 forms the second conductive plate of the capacitor. In operation, a voltage across the channel can be held by the capacitor.

[0020] Referring again to FIG. 2A, the conductors 114 are configured to couple to the transistors 107a-c over a selected length of the channel to increase the channel capacitance. Thus, when WLx 113 and WLy 112 select a unit of the quantum array, the bit line voltage of the selected unit passes through the channel of the capacitor gate 114 to the control gate 104 and the pass gate 105 / 106. When WLx 113 and WLy 112 deselect the unit, the voltages of the control gate 104 and the pass gate 105 / 106 will be held or maintained by the channel capacitance of the capacitor gate 114. The next elementary unit can then be selected to load a voltage into the control gate and the pass gate of the next unit. Using this process, multiple elementary units can be selected and the desired voltages loaded therein to perform the desired operation. Additionally, the capacitor gate 114 also prevents the voltages of the control gate 104 and the pass gate 105 / 106 from being disturbed by noise or coupling from adjacent array units.

[0021] The embodiment of the basic unit of QBA200 shown in FIG. 2A is suitable for random bit selection, row selection, or column selection operations. For random bit selection, the basic unit is selected by both word lines WLx113 and WLy112. For row selection, the Y-direction word lines WLy112 of multiple units may be turned on together. Then, one row of the unit may be selected by the X-direction word line WLx113. Similarly, for column selection, the X-direction word lines WLx113 of multiple units may be turned on together. Then, one column of the unit may be selected by the Y-direction word line WLy112.

[0022] The basic unit 200 structure disclosed in Figure 2A requires only three vertical transistors 107a-c to control the control gate 104 and pass gates 105 / 106 of a qubit, and therefore by replicating this structure very high density qubit arrays are possible.

[0023] In other embodiments, where a qubit array only requires row-select or column-select operations, the basic unit structure shown in Figure 2A can be configured to include only WLx113 or WLy112, as appropriate. Also, in Figure 2A, the connections to WLy112 and WLx113 can be swapped such that WLy112 becomes an X-direction word line and WLx113 becomes a Y-direction word line.

[0024] Figure 2B shows an equivalent circuit of the basic unit 200 shown in Figure 2A. The circuit shown in Figure 2B shows the connections of bit lines 111a-c to control gate 104, X-direction pass gate 105 and Y-direction pass gate 106. Qubit 101 is located below control gate 104. The circuit also shows gates formed at the intersections of transistor channels 107a-c with the WLy 112, WLx 113 and VC 114 conductors.

[0025] 2C illustrates an exemplary embodiment of a method 210 for operating a qubit array. For example, the method 210 is suitable for use in operating the array 200 illustrated in FIG.

[0026] In block 212, a Y-direction word line voltage is applied, for example, a voltage is applied to WLy 112 to enable transistors 107a-c.

[0027] In block 214, an X-direction word line voltage is applied, for example, a voltage is applied to WLx 113 to enable transistors 107a-c.

[0028] In block 216, the VC line voltage is applied, for example, a voltage is applied to VC 114 to enable transistors 107a-c.

[0029] In block 218, bit line voltages are applied to enable / disable control gate 104 and pass gates 105 / 106. For example, when WLy 112, WLx 113, and VC 114 lines are set to enable transistor 107, bit lines 111a-c are connected to control gate 104 and pass gates 105 / 106. Thus, the bit line voltages are applied to those gates to control the operation of qubit 101.

[0030] In block 220, the X-direction and Y-direction word line voltages are applied to turn off the vertical transistors, for example, the X-direction word line WLx 113 and the Y-direction word line WLy 112 are supplied with appropriate voltages to turn off the transistors 107a-c.

[0031] In block 222, the VC line voltage is set to allow the capacitors to store the voltages on the control gate 104 and the pass gates 105 / 106, thus maintaining the previous bit line voltages applied to the control gate 104 and pass gates 105 / 106.

[0032] After maintaining the voltages on control gates 104 and pass gates 105 / 106 for the current unit, another unit can be selected by applying the appropriate voltages to WLy 112 and WLx 113. The voltages on bit lines 111a-c can then be applied to the control gates and pass gates of the next unit.

[0033] Thus, method 210 performs operations to control a qubit array, although operations of method 210 may be combined, added, deleted, rearranged, or modified within the scope of the embodiments.

[0034] 3A illustrates a cross-sectional view of an embodiment of a basic unit 200 along the cross-sectional indication line AA′ shown in FIG. 2A. In an embodiment, a silicon or polysilicon transistor channel 107a includes a gate dielectric layer 118 that includes a material such as an oxide or a high-k material. In the embodiment illustrated in FIG. 3A, the basic unit 200 includes a “junctionless” transistor that does not have a source or drain junction. Thus, the source of the transistor channel 107a is directly connected to the pass gate 106.

[0035] Figure 3B shows a cross-sectional view of another embodiment of basic unit 200 along section indication line AA' shown in Figure 2A. In the embodiment shown in Figure 3B, the source of transistor channel 107a is connected to pass gate 106 through contact 109a.

[0036] 3C shows a cross-sectional view of another embodiment of the basic unit 200 along the cross-sectional indication line AA′ shown in FIG. 2A. In the embodiment shown in FIG. 3C, the transistor channel 107a includes a source junction 113a and a drain junction 113b. In one embodiment, the junctions 113a and 113b are of the same doping type as the transistor channel 107a. In this case, the transistor channel 107a functions as a junctionless transistor. In another embodiment, the junctions 113a and 113b are of the opposite doping type as the transistor channel 107a. In this case, the transistor channel 107a functions as a conventional junction transistor.

[0037] 3D shows a cross-sectional view of another embodiment of the basic unit 200 along the cross-sectional indication line AA′ shown in FIG. 2A. In the embodiment shown in FIG. 3D, the transistor channel 107a includes an insulating core 114 in the center of the channel silicon 107a. In this configuration, the diameter of the transistor channel 107a is relaxed to reduce manufacturing costs, while the thickness of the channel 107a is maintained within the requirements for a junctionless transistor.

[0038] 2A-3D, word lines WLx 113 and WLy 112 select one fundamental unit of the qubit array. The control gate 104 and pass gate 105 / 106 of the selected unit are both selectively connected to a bit line. The embodiment does not allow for individual control of the connection of the control gate and pass gate to the bit line.

[0039] 4A shows an exemplary embodiment of a basic unit of qubit array 400. This embodiment provides for individual control of the connections between bit lines 111a-c and control gate 104 and pass gates 105 and 106. Individual control is achieved by selectively connecting bit lines 111a-c to control gate 104 and pass gates 105 / 106 using word lines 112a, 112b, 113a, and 113b.

[0040] In the embodiment shown in FIG. 4A, each base unit has two X-direction wordline conductors (e.g., WLx1 113a and WLx2 113b) and two Y-direction wordline conductors (e.g., WLy1 112a and WLy2 112b). Vertical transistor channels 107a-c cross the X-direction and Y-direction wordlines as shown. For example, channel 107a crosses WLy1 112a and WLx1 113a. Channel 107b crosses WLy1 112a and WLx2 113b. Channel 107c crosses WLy2 112b and WLx2 113b.

[0041] In operation, when Wlx1 113a and WLy1 112a are selected, pass gate 106 is connected to bit line 111a. When WLx2 113b and WLy1 112a are selected, control gate 104 is connected to bit line 111b. When WLx2 113b and WLy2 112b are selected, pass gate 105 is connected to bit line 111c. Using this process, individual connections between bit lines and control gates and pass gates can be made by selecting the appropriate two word lines.

[0042] Thus, by performing multiple word line selections, any combination of control gates and pass gates can be connected to bit lines. For example, three word lines are selected to connect control gates 104 and pass gates 106 to their associated bit lines. When WLx1, WLx2, and WLy1 are selected, control gates 104 and pass gates 106 are connected to their associated bit lines. When WLx2, WLy1, and WLy2 are selected, control gates 104 and pass gates 105 are connected to their associated bit lines. When WLx1, WLx2, WLy1, and WLy2 are selected, control gates 104 and pass gates 105 / 106 are connected to their associated bit lines.

[0043] In this embodiment, the sources of transistors 107a, 107b, and 107c may be located in locations that cannot be directly connected to bitlines 111a, 111b, and 111c, as shown. For example, because node 107b is at the bottom of bitline 111a and cannot be directly connected to bitline 111b by a vertical contact, metal layer 115b is used to "twist" or adapt the location of contact 107b so that the bitline voltage can be applied from 111b to 115b to 107b. Thus, interconnect layers 115a, 115b, and 115c, including materials such as metal or polysilicon, can be used to connect the sources of the transistors to the bitlines.

[0044] Figure 4B shows an equivalent circuit of the basic unit 400 shown in Figure 4A. The circuit shown in Figure 4B shows the connections of bit lines 111a-c to control gate 104, X-direction pass gate 105 and Y-direction pass gate 106. Qubit 101 is located below control gate 104. The circuit also shows gates formed at the intersections of transistor channels 107a-c and WLy1 112a, WLy2 112b, WLx1 113a and WLx2 113b conductors.

[0045] 4C illustrates an exemplary embodiment of a method 410 for operating a qubit array. For example, the method 410 is suitable for use in operating the array 400 illustrated in FIG.

[0046] At block 412, a determination is made of the desired individual connections between the bit lines and the control and pass gates. For example, a determination is made as to which bit lines should be connected to their corresponding control and pass gates.

[0047] In block 414, two Y-direction word line voltages are applied. For example, two voltages are applied to WLy1 112a and WLy2 112b, respectively, to enable transistors 107a-c and obtain the desired connections determined in block 412.

[0048] In block 416, two X-direction word line voltages are applied, e.g., two voltages are applied to WLx1 113a and WLx2 113b, respectively, to enable transistors 107a-c and obtain the desired connections determined in block 412.

[0049] At block 418, a VC line voltage is applied, for example, a voltage is applied to VC 114 to enable transistors 107a-c.

[0050] In block 420, bit line voltages are applied to enable / disable control gates 104 and pass gates 105 / 106 according to the desired connections determined in block 412. For example, based on the voltage settings of WLy1, WLy2, WLx1, and WLx2, one or more of bit lines 111a-c are connected to corresponding control gates 104 and pass gates 105 / 106. Thus, the desired bit line voltages are applied to those individually selected gates to control the operation of qubit 101.

[0051] In block 422, voltages are provided to word lines WLy1, WLy2, WLx1, and WLx2 to turn off transistors 107a-c.

[0052] In block 424, the VC line voltage is set to allow the capacitors to store the voltages on the control gate 104 and the pass gates 105 / 106, thus maintaining the bit line voltages applied to the control gate 104 and the pass gates 105 / 106.

[0053] Thus, method 410 performs operations to individually control the control gates and pass gates of a qubit array, although operations of method 410 may be combined, added, deleted, rearranged, or modified within the scope of the embodiments.

[0054] Figure 5A shows another embodiment of a basic unit of qubit array 500. Like the basic unit of array 400, this embodiment can also connect one or more of the control gates and pass gates to their associated bit lines. This embodiment is similar to the embodiment shown in Figure 2A except that it has three Y-direction word line conductors 112a-c instead of just one. The Y-direction word line conductors 112a-c provide individual controls connecting one or more of the control gates and pass gates to their associated bit lines 111a-c.

[0055] Figure 5B shows an equivalent circuit of the basic unit of qubit array 500 shown in Figure 5A. Figure 5B shows three word line conductors WLy1 112a, WLy2 112b and WLy3 112c that operate to allow any combination of control gates 104 and pass gates 105 / 106 to be selectively connectable to their associated bit lines 111a-c.

[0056] 2A-5B, the control gates and pass gates are connected to their associated bit lines via vertical transistors. In the embodiment described below, only the control gate 104 is connected to its bit line using a vertical transistor channel.

[0057] FIG. 6 shows another embodiment of a basic unit of the qubit array 600. In this embodiment, only the control gate 104 is connected to its associated bit line 111b via a vertical transistor 107b. The X-direction pass gate 105 and the Y-direction pass gate 106 are directly connected to the decoder circuitry. In an embodiment, the pass gate 106 is directly connected to the pass gate of an adjacent unit. The pass gate 105 is connected to the pass gate of an adjacent unit via a contact 109c and a metal line 117. Thus, the pass gates of different units are not randomly selected or set to different conditions. Instead, the pass gates are selected by the decoder to perform row selection or column selection operations.

[0058] 7A-E show additional embodiments of qubit arrays constructed in accordance with the present invention.

[0059] 7A shows an example embodiment of an underlying structure of a qubit array, comprising a substrate layer 701 formed from any suitable material, such as silicon (Si), silicon-germanium (SiGe), sapphire, diamond, or a combination of multiple layers of the above materials.

[0060] On top of the underlying structure 701 is an insulating layer 702 or dielectric layer, such as an oxide (SiO2), nitride or high-k material. Barrier gates 703a-c and 704a-c are formed from a conductive material, such as a metal, polysilicon, micromagnet or superconducting material. Barrier gates 704a-c are separated from barrier gates 703a-c by an insulator 705 or dielectric layer, which may include a material such as an oxide, nitride or high-k material. Barrier gates 703a-c and 704a-c extend in different directions to form an array of grid areas, such as grid areas 700a and 700b.

[0061] A qubit is located beneath each grid area. For example, qubit 706a is located within substrate 701 beneath grid area 700a, and qubit 706b is located within substrate 701 beneath grid area 700b. The qubits are implanted within substrate layer 701 using any suitable technique, such as atoms, ions, photons, nuclei, or electrons. In an exemplary embodiment, the qubits are the electrons and nuclei of a single phosphorus atom.

[0062] For purposes of explanation, barrier gates 703a-c and 704a-c are referred to herein as the "X-lines" and "Y-lines," respectively. By applying a first select voltage to the X-lines or Y-lines, the potential of the substrate 701 below the barrier gate creates a potential barrier that prevents adjacent qubits from "entangling" or "shutting." Meanwhile, by applying a second select voltage or RF magnetic field to the X-lines and Y-lines, a potential or magnetic field is created that allows adjacent qubits to entangle or shuttle. Using this process, quantum logic computations can be performed using qubits.

[0063] FIG. 7B illustrates an exemplary embodiment of a superstrate structure added to the qubit array shown in FIG. 7A. This embodiment includes a control gate, such as control gates 707a-g, formed on top of the grid area. Control gate 707 comprises a suitable electrical conductor, such as metal, polysilicon, a micromagnet, or a superconductor. By applying an appropriate voltage or RF magnetic field to control gate 707, the electric field underneath the gate attracts the qubit's electrons towards the gate or repels the qubit's electrons away from the gate to initialize or preserve the qubit's spin state. For readout, control gate 707 can be connected to a sensing circuit, such as a resonator circuit, that senses the qubit's spin state.

[0064] FIG. 7C shows a top view of the array shown in FIG. 7B, including an exemplary embodiment of the top layer connections. FIG. 7C shows control gates 707, such as control gates 707a-d, located on the top of X-lines 703a-f, Y-lines 704a-f, and qubits. Control gates 707 are connected to conductor lines 708a-g and 709a-g via contacts 711, such as contacts 711a-d. Conductive lines 708a-g and 709a-g are referred to as "data lines." The data lines are formed from a suitable conductor, such as metal, polysilicon, micromagnets, or superconductors. In an embodiment, contacts 711, such as contacts 711a-d, are staggered to provide even and odd data lines, as shown by the alternating connections of data lines 708g and data lines 709g to control gates 707a-d.

[0065] Figure 7D shows an exemplary three-dimensional (3D) view of the qubit array structure shown in Figure 7C. The 3D view was taken along data lines 708g and 709g, where contacts 711a-d are staggered to connect data lines 708g and 709g to control gates 707a-d in an alternating manner.

[0066] Figure 7E shows a top view of the array shown in Figure 7B, including an exemplary embodiment of the top layer connections. As shown in Figure 7E, data lines 708a-g and 709a-g are configured to form a zigzag pattern. The zigzag pattern allows even and odd data lines, such as 708g and 709g, to connect to control gates 707a-d in an alternating manner.

[0067] 8A-D illustrate an exemplary operation of the qubit array shown in FIG. 7C.

[0068] FIG. 8A illustrates how voltages are applied to selected Y-lines to enable quantum logic operations. In an embodiment, selected Y-line 704d is supplied with a selected voltage or RF magnetic field to enable the qubits in groups 712a and 712b to be entangled, shuttled, or perform other quantum logic operations, while other voltages or RF magnetic fields are supplied to other unselected Y-lines and X-lines to form potential barriers at the bottom of the gates to separate the qubits. By using the disclosed array structure, each qubit in groups 712a and 712b is connected to one individual data line. For example, each of the qubits in group 712a is connected to one data line in the first group of data lines 709b-f, and each of the qubits in group 712b is connected to one data line in the second group of data lines 708c-g. Each data line can be supplied with the appropriate voltage conditions or connected to other circuitry. This allows all of the qubits in groups 712a and 712b to perform quantum logic operations together, greatly increasing the performance of the quantum computer.

[0069] FIG. 8B shows how voltages are applied to selected X-lines to enable quantum logic operations. In an embodiment, selected X-lines 703d are supplied with selected voltages or RF magnetic fields to enable the qubits in groups 713a and 713b to be entangled, shuttled, or perform other operations, while other unselected Y-lines and X-lines are supplied with other voltages or RF magnetic fields to form potential barriers at the bottom of the gates to separate the qubits. By using the disclosed array structure, each qubit in groups 713a and 713b is connected to one individual data line. This allows all qubits in groups 713a and 713b to perform operations together. This greatly enhances the performance of the quantum computer.

[0070] 8C illustrates how voltages can be applied to multiple Y-lines to enable quantum logic operations. In an embodiment, multiple selected Y-lines, such as Y-lines 704b, 704d, and 704f, are supplied with selected voltages or RF magnetic fields to enable the qubits in each of the groups (712a / 712b, 712c / 712d, and 712e / 712f) to be entangled, shuttled, or perform other operations, while other voltages are supplied to other unselected Y-lines and X-lines to form barriers at the bottom of the gates to separate the qubits.

[0071] 8D shows how voltages can be applied to multiple X-lines to enable quantum logic operations. In an embodiment, multiple selected X-lines, such as X-lines 703b, 703d, and 703f, are supplied with appropriate voltages or RF fields to allow the qubits in each of the groups (713a / 713b, 713c / 713d, and 713e / 713f) to be entangled, shuttled, or perform other operations, while other voltages are supplied to other unselected Y-lines and X-lines to form barriers at the bottom of the gates to separate the qubits.

[0072] Note that while the embodiment of the qubit array shown in FIG. 7C shows two groups of data lines 708a-g and 709a-g connected in an alternating fashion to the control gates, in other embodiments the data lines are separated into any number of groups, such as three, four or more groups.

[0073] 9A shows an exemplary embodiment of a qubit array that uses three groups of data lines. For example, the array includes a first group of data lines 708a-g, a second group of data lines 709a-g, and a third group of data lines 710a-g. The three groups of data lines are connected in an alternating manner to control gates 707. For example, data lines 708g, 709g, and 710g are connected in an alternating manner to control gates 707a, 707b, and 707c.

[0074] The array shown in FIG. 9A allows three groups of qubits to be entangled together, shuttled, or controlled to perform other operations, as described with respect to FIG. 9B.

[0075] 9B shows an exemplary embodiment of a qubit array that allows three groups of qubits to be entangled together, shuttled, or controlled to perform other operations. In an embodiment, two Y-lines 704c and 704d are supplied with the appropriate voltages or RF fields to entangle the qubits in groups 714a, 714b, and 714c. Each qubit in groups 714a, 714b, and 714c is connected to an individual data line. This allows the appropriate conditions to be provided to the data lines, or the data lines to be connected to a circuit, to allow the qubits in groups 714a, 714b, and 714c to be entangled together, shuttled, or configured to perform other quantum logic operations.

[0076] 10A shows an exemplary embodiment of a qubit array that uses four groups of data lines. For example, the array includes a first group of data lines 708a-g, a second group of data lines 709a-g, a third group of data lines 710a-g, and a fourth group of data lines 715a-g. In this embodiment, the four groups of data lines are connected to control gates 707 in an alternating manner as shown in FIG. 10A.

[0077] The array shown in FIG. 10A, like the array shown in FIG. 9B, allows groups of four qubits to entangle, shuttle and perform other quantum logic operations together.

[0078] According to an embodiment of the present invention, the number of groups of data lines alternately connected to the control gates is not limited. It depends on the pitch of the data lines and the pitch of the qubits. For example, if the pitch of the qubits is 100 nm, when the pitch of the data lines is 50 nm, a double group of data lines can be implemented as shown in FIG. 7C. When the pitch of the data lines is 30 nm, a triple group of data lines can be implemented as shown in FIG. 9A. When the pitch of the data lines is 25 nm, a triple group of data lines can be implemented as shown in FIG. 10A. The smaller the pitch between the data lines or the larger the pitch of the qubits, the more groups of data lines can be implemented.

[0079] 10B illustrates another embodiment of a qubit array constructed in accordance with the present invention. In this embodiment, the array includes multiple groups of data lines that extend in different directions. For example, as shown, a first group of data lines 1008a-d extend in the Y direction and a second group of data lines 1009a-c extend in the X direction. In this embodiment, data lines 1008a-d are formed as a first layer of conductors and data lines 1009a-c are formed as a second layer of conductors.

[0080] FIG. 10C illustrates another embodiment of a qubit array constructed in accordance with the present invention. In this embodiment, the array includes multiple groups of data lines that extend in different directions. For example, a first group of data lines 1008a-d extend in the same direction as X-lines 703a-f. A second group of data lines 1009a-e extend in the same direction as Y-lines 704a-f. In an embodiment, data lines 1008a-c are formed by a first layer of conductors, and data lines 1009a-e are formed by a second layer of conductors. Black dots, such as black dot 1016, represent contacts or vias that connect the first layer of conductor lines 1008a-c to the control gates. White dots, such as white dot 1017, represent contacts or vias that connect the second layer of conductor lines 1009a-e to the control gates 707. By using the disclosed qubit array structures and methods, high density and high performance quantum computers can be realized.

[0081] While exemplary embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that based on the teachings herein, changes and modifications may be made without departing from the exemplary embodiments and their broader aspects. It is therefore intended that the appended claims encompass within their scope all such changes and modifications that are within the true spirit and scope of the exemplary embodiments of the present invention.

Claims

1. 1. A quantum bit array, comprising: a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit for controlling operation of the qubit of the quantum bit array; A first bit line; a first transistor channel connecting the first bit line to the control gate; at least one word line coupled to the first transistor channel, the at least one word line selectively controlling a flow of charge through the first transistor channel; a capacitor coupled to selectively maintain a charge in the first transistor channel when the at least one word line is deselected; Array comprising:

2. 2. The array of claim 1, wherein said first transistor channel forms a vertical transistor channel and said at least one word line forms at least one horizontal word line.

3. The array of claim 1 , wherein the capacitor comprises a vertical MOS capacitor.

4. The array of claim 1 , wherein the first transistor channel is directly connected to the control gate.

5. 2. The array of claim 1, further comprising a contact connecting the first transistor channel to the control gate.

6. The array of claim 1 , wherein the first transistor channel comprises a gate dielectric layer.

7. The array of claim 1 , wherein the first transistor channel forms a junctionless transistor.

8. The array of claim 1 , wherein the first transistor channel comprises a source junction and a drain junction.

9. The array of claim 1 , wherein the first transistor channel comprises an insulating core.

10. 2. The array of claim 1, wherein the at least one word line comprises an X-direction word line and a Y-direction word line.

11. a second transistor channel connecting a second bit line to the first pass gate; a third transistor channel connecting a third bit line to the second pass gate; The array of claim 1 further comprising:

12. a second capacitor configured to store a charge in the second transistor channel; a third capacitor configured to store a charge in the third transistor channel; The array of claim 11 further comprising:

13. 13. The array of claim 12, wherein the at least one word line comprises an X-direction word line coupled to the first, second, and third transistor channels, and a Y-direction word line coupled to the first, second, and third transistor channels.

14. 13. The array of claim 12, wherein the at least one word line comprises two X-direction word lines coupled to the first, second, and third transistor channels, and two Y-direction word lines coupled to the first, second, and third transistor channels.

15. 13. The array of claim 12, wherein the at least one word line comprises first, second and third X-direction word lines coupled one-to-one to the first, second and third transistor channels, respectively, and one Y-direction word line coupled to the first, second and third transistor channels.

16. 1. A method of operating a quantum array, comprising: applying one or more first voltages to one or more Y-direction word lines coupled to at least one vertical transistor, respectively; applying one or more second voltages to one or more X-direction word lines coupled to the at least one vertical transistor, respectively; applying a third voltage to a capacitor coupled to the at least one vertical transistor to selectively maintain charge in the at least one transistor channel when a word line coupled to the at least one vertical transistor is deselected; applying one or more bit line voltages to the at least one vertical transistor connecting a bit line to a control gate coupled to a qubit of the quantum array to control operation of the qubit of the quantum array; A method for providing the above.

17. 17. The method of claim 16, wherein the act of applying one or more first voltages comprises applying a selected first voltage to an X-direction word line coupled to the at least one vertical transistor, and the act of applying one or more second voltages comprises applying a selected second voltage to a Y-direction word line coupled to the at least one vertical transistor.

18. 17. The method of claim 16, wherein the act of applying one or more first voltages includes applying two selected first voltages to two X-direction word lines coupled to the at least one vertical transistor, and the act of applying one or more second voltages includes applying two selected second voltages to two Y-direction word lines coupled to the at least one vertical transistor.

19. 17. The method of claim 16, wherein the act of applying one or more first voltages comprises applying at least one selected voltage to at least one X-direction word line coupled to the at least one vertical transistor, respectively, and the act of applying one or more second voltages comprises applying a selected second voltage to a Y-direction word line coupled to the at least one vertical transistor.

20. 1. A method of operating a quantum array, comprising: applying one or more first voltages to one or more Y-direction word lines coupled to at least one vertical transistor, respectively; applying one or more second voltages to one or more X-direction word lines coupled to the at least one vertical transistor, respectively; applying a third voltage to a capacitor coupled to the at least one vertical transistor; applying one or more bit line voltages to the at least one vertical transistor connecting a bit line to a control gate coupled to a qubit of the quantum array to control operation of the qubit of the quantum array; Equipped with removing the one or more first voltages from the one or more Y-direction word lines; removing the one or more second voltages from the one or more X-direction word lines, where the capacitors are isolated to respectively maintain charge in at least one channel of the at least one vertical transistor; The method further comprises:

21. 1. A quantum bit array, comprising: a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit for controlling operation of the qubit of the quantum bit array; A first bit line; a first transistor channel connecting the first bit line to the control gate; at least one word line coupled to the first transistor channel, the at least one word line selectively controlling a flow of charge through the first transistor channel; a capacitor coupled to selectively store charge in the first transistor channel; a second transistor channel connecting a second bit line to the first pass gate; a third transistor channel connecting a third bit line to the second pass gate; Array comprising:

22. a second capacitor configured to store a charge in the second transistor channel; a third capacitor configured to store a charge in the third transistor channel; 22. The array of claim 21 further comprising:

23. 23. The array of claim 22, wherein the at least one word line comprises an X-direction word line coupled to the first, second, and third transistor channels, and a Y-direction word line coupled to the first, second, and third transistor channels.

24. 23. The array of claim 22, wherein the at least one word line comprises two X-direction word lines coupled to the first, second, and third transistor channels, and two Y-direction word lines coupled to the first, second, and third transistor channels.

25. 23. The array of claim 22, wherein the at least one word line comprises first, second and third X-direction word lines coupled one-to-one to the first, second and third transistor channels, respectively, and one Y-direction word line coupled to the first, second and third transistor channels.

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