Compressed Metadata Aided Computing

Abstract

The method includes, in response to receiving an instruction to perform a first operation on first data stored in the storage device, retrieving first compressed metadata from the storage device based on an address of the first data, and reducing a number of operations in a set of operations based on the first operation and one or more matching addresses, where the one or more matching addresses correspond to second compressed metadata that matches the first compressed metadata.

Description

[Background technology]

[0001] In addition to the main memory within the computing device, many modern computing devices include at least one level of cache memory (or "cache"). In general, a cache is a smaller capacity, faster access memory used to store a limited number of copies of data and instructions used to perform various operations (e.g., computational operations, etc.) closer to the functional blocks within the computing device that perform the operations. Caches are typically implemented using faster memory circuits, such as static random access memory (SRAM) integrated circuits and other types of memory circuits. Data compression within a cache allows larger amounts of data to be accessed with lower latency, thus further improving the overall performance of the computing system.

[0002] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. [Brief description of the drawings]

[0003] [Figure 1] FIG. 1 illustrates an embodiment of a computing device. [Figure 2A] FIG. 2 illustrates an embodiment of a redundant address calculation unit. [Figure 2B] FIG. 2 illustrates an embodiment of a redundant address calculation unit. [Diagram 3] FIG. 2 illustrates components within a processing unit, according to one embodiment. [Figure 4] FIG. 2 illustrates components within a processing unit, according to one embodiment. [Diagram 5] FIG. 2 illustrates a process for performing compressed metadata-assisted computing, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] In the following description, numerous specific details are described, such as examples of specific systems, components, methods, etc., to enhance understanding of the embodiments. However, it will be apparent to those skilled in the art that at least some of the embodiments can be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simplified block diagram form to avoid unnecessarily obscuring the embodiments. Thus, the specific details described are merely exemplary. A particular implementation may differ from these example details and still be considered to be within the scope of the embodiments.

[0005] Compressing data stored in a cache effectively increases the capacity of the cache and the link bandwidth to and from the cache. In one embodiment, the process for compressing data into a cache generates compression metadata associated with the compressed data. The compression metadata includes information indicating which values ​​in a compressed data block are similar or identical to each other and which values ​​match constant values ​​(e.g., 0 or -1) from some small set.

[0006] In one embodiment, the cache compression metadata serves as the basis for de-duplication of redundant operations, such as register loads and arithmetic operations, when the compression metadata indicates that the data values ​​involved in the operations are identical. The computational cost of identifying similar or identical data values ​​is already incurred by the compression mechanism, and thus de-duplication is performed at little additional computational cost by comparing existing compressed metadata values ​​associated with different addresses. Once a set of identical values ​​is identified, redundant operations involving the identical values ​​are removed, and operations dependent on the removed operations are updated to depend on the remaining equivalent operations. Removal of redundant operations reduces the number of calculations and / or load operations performed. This reduces the burden on the arithmetic logic unit (ALU) and physical register file, effectively increasing link bandwidth, ultimately improving throughput and reducing power consumption.

[0007] FIG. 1 illustrates one embodiment of a computing system 100 in which the above-described compressed metadata assisted computing mechanism is implemented. Generally, the computing system 100 may be embodied as any of a number of different types of devices, including, but not limited to, a laptop or desktop computer, a mobile device, a server, and the like. The computing system 100 includes a number of components 102-108 that communicate with each other via a bus 101. In the computing system 100, each of the components 102-108 may communicate with any of the other components 102-108 directly via the bus 101 or through one or more of the other components 102-108. The components 101-108 in the computing system 100 are contained within a single physical enclosure, such as the chassis of a laptop or desktop computer or the casing of a mobile phone. In an alternative embodiment, some of the components of the computing system 100 are embodied as peripheral devices such that the entire computing system 100 is not present within a single physical enclosure.

[0008] Computing system 100 also includes user interface devices for receiving information from a user or providing information to a user. Specifically, computing system 100 includes input devices 102, such as a keyboard, mouse, touch screen, or other devices for receiving information from a user. Computing system 100 displays information to the user via display 105, such as a monitor, light emitting diode (LED) display, liquid crystal display, or other output device.

[0009] Computing system 100 further includes a network adapter 107 for transmitting and receiving data over a wired or wireless network. Computing system 100 also includes one or more peripheral devices 108. Peripheral devices 108 may include mass storage devices, location devices, sensors, input devices, or other types of devices used by computing system 100.

[0010] Computing system 100 includes one or more processing units 104, which in the case of multiple processing units 104 can operate in parallel. Processing units 104 are configured to receive and execute instructions 109 stored in a memory subsystem 106. In one embodiment, each of processing units 104 includes multiple computing nodes residing on a common integrated circuit substrate. Memory subsystem 106 includes storage devices used by computing system 100, such as random-access memory (RAM) modules, read-only memory (ROM) modules, hard disks, and other non-transitory computer-readable media.

[0011] Some embodiments of computing system 100 may include fewer or more components than the embodiment shown in Figure 1. For example, certain embodiments are implemented without display 105 or input device 102. Other embodiments have more than one of certain components, for example, an embodiment of computing system 100 may have multiple buses 101, network adapters 107, storage devices 106, etc.

[0012] 2A and 2B are block diagrams illustrating the functionality of redundant address calculation logic 200 and 250, according to one embodiment. Redundant address calculation logic units 200 and 250 calculate addresses associated with redundant operations indicated by two exemplary types of compression metadata, C-Pack and Base-Delta-Immediate (BDI), which are cache compression schemes implemented in computing system 100. Apart from the C-Pack and BDI compression schemes described herein, other compression schemes are used in alternative embodiments, which provide compression metadata indicating which compressed data values ​​are similar or identical.

[0013] The C-Pack compression scheme represents data in the cache with a compact encoding scheme, replacing frequently occurring data words. Words that frequently occur in the data being compressed are stored in a dictionary. Commonly occurring data words (e.g., all zeros) are encoded using a single compact code without explicitly storing the value in the dictionary, so that no dictionary lookup is used to decode these values. For other values, the C-Pack compression scheme represents the value in the cache using a compact encoding scheme and a pointer to an entry in the dictionary that contains the complete word. In this way, memory space is saved when multiple identical data words are represented in the cache using compact references to the same data word in the dictionary. Also, partially matching words can be represented in the cache by referencing the matching portion of the word stored in the dictionary, or by multiple portions of different words in the dictionary.

[0014] Thus, similarity between data words in the cache is encoded in the metadata (including codes and pointers) used to represent the data words. In particular, identical codes and pointers refer to the same constants or dictionary entries and therefore encode the same values. Similarity is determined by comparing metadata values ​​without accessing the actual values ​​in the dictionary.

[0015] 2A, the redundant address calculation logic 200 receives C-Pack metadata 201, which includes codes and pointers, and compares the metadata values ​​to identify duplicate addresses 204 (i.e., addresses that store duplicate values) and zero addresses 206 (i.e., addresses that store zeros). In one embodiment, the C-Pack metadata 201 includes a code for each 4-byte value, and the calculation logic 200 identifies addresses 204 and 206 based on three of the possible codes: "00", "01", and "10". The code "00" indicates that the value of the corresponding address is zero. The code "01" indicates that a dictionary index for the 4-byte value is calculated based on the number of previously occurring "10" codes calculated in block 202. The code "10" indicates that the index is included directly in the metadata.

[0016] Once the indices corresponding to the "01" codes have been calculated in block 202, they are compared to the explicitly included indices corresponding to the "10" codes in block 203. The set of duplicate addresses 204 are the addresses corresponding to the matching indices found by block 203. Block 205 identifies addresses associated with "00" encodings in metadata 201; these addresses contain a value of zero.

[0017] Codes other than "00", "01", and "10" indicate that the represented value partially matches one or more values ​​in the dictionary, and therefore a dictionary lookup is performed to identify the matching value. These codes are ignored by the computation logic 200 because dictionary lookups incur a performance penalty similar to a regular cache access.

[0018] A data block stored according to the BDI compression scheme includes a base value and a set of delta values, each representing a word in the original data block. Each delta value is also associated with a value indicating whether the base of the delta is zero or a recorded base value. Referring to FIG. 2B, the redundant address calculation logic 250 finds delta values ​​that have a value of zero in block 252, and then identifies a zero address 254 (i.e., an address that stores a value of zero) by comparing the resulting set with the deltas that have a base of zero in block 253. The resulting zero address 254 has a delta of zero relative to the base of zero, and therefore has a value of zero.

[0019] In block 255, deltas having zero deltas and non-zero bases are identified, and those addresses 256 have zero deltas relative to the same base and therefore contain matching values. In one embodiment, similar calculations are performed for delta values ​​other than zero. Addresses having the same delta value relative to the same base value are identified as matching each other. A first value represented by a first delta value and a first base value is equal to a second value represented by a second delta value and a second base value if the first delta value is equal to the second delta value and the first base value is equal to the second base value.

[0020] 3 illustrates components in an out-of-order execution pipeline of a processing unit 300 that utilizes matching address information (including duplicate addresses and / or addresses of constant values, such as the zero address) to reduce the number of redundant data cache accesses performed, according to one embodiment. Processing unit 300 corresponds to processing unit 104 in computing system 100. In the illustrated configuration, processing unit 300 reduces the number of data cache accesses by identifying addresses that contain duplicate data values. Data is read from the cache once and duplicated for each of the duplicate addresses.

[0021] In processing unit 300, instruction fetch unit 301 retrieves the instruction to be executed (e.g., instruction 109). The instruction specifies the operation to be performed as well as where to find the data values ​​on which the operation is to be performed. Decode unit 302 converts the instruction into signals for executing the operation within the processing circuitry.

[0022] A register and re-order buffer (ROB) allocation unit 303 facilitates out-of-order execution of instructions by allocating registers in a ROB / physical register file 305 to store operands and results of specified operations. Allocation unit 303 also updates a register alias table (RAT) 304 to map logical registers to physical registers allocated in physical register file 305.

[0023] Arithmetic logic unit (ALU) 306 performs logical and arithmetic operations according to the opcode of the received instruction. For load and store operations, addresses are calculated in address calculation unit 307 and the operations are queued in load / store queue 308. Operations in the load / store queue transfer data between data cache 309 and physical register file 305.

[0024] The data cache 309 is a storage device that stores data that is likely to be used by incoming instructions that can access the data in the rest of the memory hierarchy (e.g., main memory 106). Data stored in the data cache 309 is compressed when written by the compression engine 310. For each data block stored in the cache 309, the compression engine 310 generates compression metadata that represents the data, such as a compact compression code, deltas, and / or other metadata values, depending on the compression scheme used. The metadata is stored in the data cache 309 in place of the original data. In an alternative embodiment, some or all of the compressed metadata is stored in another storage device instead of the data cache 309. Also, compressed cache data is decompressed by the compression engine 310 when it is read by the compression engine 310, by reconstructing the original data based on the stored compression metadata.

[0025] The load / store queue 308 contains a list of load operations, each of which specifies an address in the data cache 309 from which data is to be retrieved and loaded into a register in the physical register file 305. When a load operation is to be executed from the queue 308, an address 321 associated with the load operation is provided to the data cache 309. The compression engine 310 decompresses the data 322 stored at the provided address and returns the decompressed data 322 to the load / store queue 308. The load / store queue 308 loads the data 322 into a register in the physical register file 305 as specified by the load operation.

[0026] The processing unit 300 includes a redundant address calculation unit 311 that receives compressed metadata 323 corresponding to the address 321 being accessed. The compressed metadata 323 is provided by a compression engine 310, which reads the compressed metadata 323 as part of the decompression process.

[0027] In one embodiment, the redundant address calculation unit 311 receives compressed metadata 323 that includes metadata about the current load operation in the load / store queue 308 and metadata about one or more addresses associated with other load operations in the queue 308. The redundant address calculation unit 311 compares values ​​of the metadata 323 to find a set of matching addresses 324, as described above with reference to Figures 2A and 2B. Thus, every request to the data cache 309 will result in any matching addresses 324 being returned along with the data 322.

[0028] Each set of two or more duplicate addresses in matching addresses 324 represents a set of load operations in which one or more operations are redundant. The matching addresses 324 are received by de-duplication logic 320 in load / store queue 308, which removes the redundant load operations. After load / store queue 308 receives data 322 from data cache 309 according to the first arriving load operation in queue 308, the same data 322 is used to complete the removed redundant load operations in queue 308 without repeatedly accessing cache 309. De-duplication logic 320 removes redundant operations from queue 308, thereby reducing data cache access times.

[0029] In an alternative embodiment, when a load operation is processed from the queue 308, metadata 323 associated with the load address is preserved. The de-duplication logic 320 compares the compressed metadata retrieved for each load operation processed from the queue 308 with the stored metadata value from the preceding load operation. If the compressed metadata of the subsequent load operation matches the previously stored metadata, this indicates that the data value for the load was previously retrieved from the cache 309, and a repeated access to the data cache 309 would be redundant. Thus, instead of retrieving the same value from a different address in the data cache 309, the already retrieved value is used to complete the subsequent load operation.

[0030] In either case, because the redundant load operations are directed to addresses containing identical data values, the same data resulting from a single data cache access is copied to multiple registers in physical register file 305 to complete multiple redundant load operations. In alternative embodiments, the redundant data values ​​are not necessarily identical, but are similar enough for the application being executed. In such applications, data values ​​that differ within a certain tolerance are treated as redundant values. Thus, such embodiments are implemented with a compression scheme that generates compressed metadata indicative of the similarity. For example, when using a BDI compression scheme, small delta values ​​below a threshold can be treated as representing redundant values ​​if they reference the same base.

[0031] In one embodiment, matching addresses 324 include addresses of constant values ​​identified as storing constant values, such as zero addresses 206 and 254 described in Figures 2A and 2B. De-duplication logic 320 eliminates unnecessary cache accesses by forcing load / store queue 308 to use the detected constant value instead of retrieving the value from data cache 309.

[0032] 4 illustrates components in an out-of-order execution pipeline of a processing unit 400 that utilizes matching address information to reduce the number of redundant register writes and arithmetic operations performed, according to one embodiment. Processing unit 400 corresponds to processing unit 104 in computing system 100. In the illustrated configuration, processing unit 400 reduces the number of arithmetic operations performed in ALU 306 and / or the number of write operations performed in physical register file 305 by identifying addresses that contain duplicate data values ​​based on associated compressed metadata values.

[0033] Compared to processing unit 300, data cache 409 in processing unit 400 includes an additional port for receiving addresses 421 and providing metadata 323 as soon as addresses 421 are ready, instead of waiting to receive addresses 321 from load / store queue 308. Redundant address calculation unit 411 determines matching addresses based on compressed metadata 323, as described above with reference to Figures 2A and 2B. Upon determining a set of matching addresses, redundant address calculation unit 411 provides the matching addresses to deduplication logic 420 in allocation unit 403.

[0034] The matching address information includes duplicate addresses that indicate to the deduplication logic 420 whether two or more load instructions in the pipeline are requesting data from addresses that hold the same value, so that one or more of the load instructions are redundant. The deduplication logic 420 eliminates the redundant load operations by replacing them with a single load operation directed to a single destination register in the ROB / physical register file 305. Other instructions that were dependent on the eliminated load operation are updated in their execution dependencies to depend on the remaining single load operation. The deduplication logic 420 also instructs the allocation unit 403 to update the RAT 304 so that aliases that originally pointed to the registers associated with the eliminated load operation now refer instead to the single loaded physical register in the ROB / physical register file 305. As a result, fewer load operations are performed and a single register is used to store the data value instead of multiple registers to store the same data value. This reduces the strain on the physical register file 305 and the cache 409, thus improving application performance.

[0035] In one embodiment, the de-duplication logic 420 further de-duplicates instructions that become duplicates due to de-duplication of redundant load operations. Instructions that depend on the same de-duplicated load operation as an operand are identified, and any other operands in these instructions also depend on the de-duplicated load operation or depend on the same physical register. Duplicate instructions are de-duplicated in a manner similar to the load operations. All but one of the duplicate instructions are eliminated, so that one output register is used to store the output of the single remaining instruction. Any dependent instructions are updated to depend on a single instruction instead of multiple duplicate instructions. This instruction de-duplication further reduces the burden on the physical register file and reduces the burden on the operation execution logic (e.g., ALU 306), which has fewer instructions to execute.

[0036] In one embodiment, the compression metadata is used to eliminate unnecessary operations by determining when the data stored at an address matches a particular constant value. As an example, for many instructions (such as multiplication or addition), if one operand is known to be zero, the result is either a constant or a simpler function of the other operand. The deduplication logic 420 identifies these instructions based on information received from the redundant address calculation unit 411 (e.g., zero address 206 or 254) and replaces the instruction with a simpler equivalent operation. The replacement operation is determined based on the original instruction and a constant value associated with an appropriate replacement function in table 412. For example, the replacement function table indicates that a multiplication instruction is replaced with an identity function or a zero output if one of its operands is 1 or 0, respectively. Table 412 is located in a dedicated memory, or in an alternative embodiment, in the physical register file 305, cache 409, or other storage device.

[0037] Any operations that were originally dependent on the eliminated instruction have their dependencies updated to the corresponding equivalent replacement operation. For example, if an add operation is performed that adds zero to another operand, the result will be the other operand. Thus, an instruction is eliminated and dependencies on the eliminated add operation are updated to depend on an instruction that produces a non-zero operand instead. Similarly, performing a logical AND with a zero always results in an output of zero. Thus, a logical AND operation is eliminated and all dependencies on the eliminated logical AND are replaced with dependencies on an immediate zero.

[0038] In one embodiment, components of processing units 300 and 400 are combined. For example, alternative embodiments of the processing units include de-duplication logic units 320 and 420 that support multiple mechanisms for de-duplication of redundant operations in the pipeline.

[0039] 5 illustrates a process 500 for eliminating redundant constant-valued operations based on compression metadata, according to one embodiment. Process 500 is performed by components of computing system 100, including load / store queue 308, data cache 309 or 409, compression engine 310, redundant address calculation unit 311 or 411, etc.

[0040] The process 500 operates within a processing unit (e.g., processing unit 300 or 400) to perform load and store operations between a data cache (e.g., 309 or 409) and physical registers 305 while eliminating redundant operations (e.g., load and arithmetic instructions) and replacing constant value operations with their simpler equivalents. The load / store queue 308 includes a queue of load and / or store operations that are processed in order. At block 501, if the next operation in the load / store queue 308 is a store operation, the data to be stored is compressed by the compression engine 310 and stored in the data cache, as provided at block 502. For each data value, the compression engine 310 generates associated compression metadata that represents the data value. For example, when using the C-Pack compression scheme, the compression engine 310 generates compact code that references one or more dictionary entries or frequently used constant values. When using the BDI compression scheme, the compression engine 310 generates a delta value along with an indication of whether the delta is relative to a zero base or a non-zero base. From block 502 , the process 500 returns to block 501 to process the next operation in the load / store queue 308 .

[0041] At block 501, if the next operation in the load / store queue 308 is a load operation, the process 500 continues to block 503. At block 503, the compression engine 310 reads compressed metadata associated with the address specified by the load instruction from the data cache 409. The compressed metadata 323 is provided to the redundant address calculation unit 411. From block 503, the process 500 continues to block 505.

[0042] In block 505, the compressed metadata 323 is compared to the compressed metadata against known constant values, such as 0 and 1. Depending on the compression scheme used, when such constant values ​​are compressed, particular metadata values ​​are produced.

[0043] For example, when the C-Pack compression scheme is used, the redundant address calculation unit 411 maintains a list containing a predetermined subset of compressed codes and their associated constant values ​​(e.g., a constant value of 0 is represented by the code "00"). The metadata 323 associated with a specified load address is compared to each code of the constant value to determine whether the load address contains that constant value.

[0044] When the BDI compression scheme is used, the redundant address calculation unit 411 maintains a list containing a predetermined subset of the delta and base values ​​and their associated constant values. The value of the metadata 323 is compared to the known delta and base values ​​for each detectable constant value. For example, the constant 0 is encoded with a delta value of 0 with a base of 0, so a delta value of 0 and a base of 0 in the metadata 323 indicates that the address contains a 0 value. If the metadata 323 indicates that the address does not contain any of the constant values, the process 500 continues to block 507.

[0045] In block 507, the compressed metadata 323 for the address is compared to compressed metadata associated with other addresses. In one embodiment, the compressed metadata 323 is compared to compressed metadata obtained for a prior load operation. Alternatively, the compressed metadata 323 is compared to compressed metadata for load operations still in the queue 308 that have not yet been executed. In some embodiments, depending on the compression scheme used, compressed metadata values ​​are equal if the data values ​​they represent are also equal. In the C-Pack compression scheme, identical values ​​are represented by identical compact codes, and possibly by pointers to the same dictionary entries. In the BDI compression scheme, identical values ​​are represented by the same delta values, referencing the same base values. Thus, block 507 determines whether the compressed metadata 323 is equal to other known compressed metadata for other addresses previously loaded or obtained for load operations still in the queue 308. In one embodiment, the compressed metadata comparisons in blocks 505 and 507 are performed in parallel as shown in Figures 2A and 2B.

[0046] If no duplicate address or a constant (e.g., zero) address is found, the data specified in the load operation is retrieved from the data cache 309 or 409 and loaded into a register in the physical register file 305. In block 509, the data is read from the cache 309 or 409 and decompressed by the compression engine 310. The decompressed data value is loaded into the destination register specified by the load operation.

[0047] In one embodiment, at block 511, the compressed metadata 323 for the retrieved data value is stored with the data value if it can be reused later (e.g., at block 507) for a future load operation with matching metadata. From block 511, process 500 returns to block 501 to continue processing remaining operations in the load / store queue 308. In an alternative embodiment, process 500 instead continues from block 509 to block 501 without saving the metadata and retrieved value.

[0048] At block 505, if the compressed metadata 323 retrieved for the load operation matches the metadata of the constant value, the process 500 continues to block 513. At block 513, the de-duplication logic 420 identifies one or more instructions in the pipeline that depend on the data value of the load operation as an operand. For each of these instructions, the de-duplication logic 420 performs a lookup in the replacement function table 412 to identify an equivalent replacement function. For example, for an add instruction having two operands where one operand is determined to be zero based on the compressed metadata 323, the replacement function outputs the other operand. In the replacement function table 412, the replacement function is associated with the original addition function and a constant value of zero. At block 515, the de-duplication logic 420 replaces the original function with the equivalent function identified from the replacement function table 412. Because the constant value has been identified based on its metadata 323, the original load operation to read the value from the cache 409 is redundant and is eliminated.

[0049] At block 507, if the compressed metadata 323 retrieved for the load operation matches compressed metadata associated with a different load operation, process 500 continues to block 517. At block 517, redundant address calculation unit 311 or 411 calculates one or more duplicate addresses based on which addresses are associated with compressed metadata that matches compressed metadata 323. A duplicate address is an address in the data cache that stores the same value as the data cache address of the load operation, and is therefore redundant.

[0050] The compressed metadata values ​​of the C-Pack and BDI compression schemes are compared as described above with reference to Figures 2A and 2B. In alternative embodiments, other compression schemes may be used instead of the C-Pack or BDI compression schemes, provided that the compressed metadata values ​​reliably indicate whether the original uncompressed values ​​are equal.

[0051] From block 517, process 500 continues to block 519. In the processing unit 300, de-duplication logic 320 of the load / store queue 308 receives the matching address 324 from the redundant address calculation unit 311 and removes one or more redundant load operations from the queue 308. In one embodiment, the matching address 324 is provided to the de-duplication logic 320 by the redundant address calculation unit 311. The de-duplication logic 320 removes from the load / store queue 308 any queued load operations that are redundant because they are directed to a duplicate address. Instead of accessing the cache to perform the removed load operation, the load / store queue 308 eliminates one or more redundant cache accesses by using a data value read from the cache when performing the current load operation.

[0052] In an alternative embodiment, the deduplication logic 320 eliminates cache accesses for a current load operation by identifying a previous load operation directed to a duplicate address, i.e., the metadata values ​​of the current load address and the previous load address indicate that the addresses store the same value, and therefore the current load operation is processed using the data previously retrieved for the matching previous load operation.

[0053] Alternatively, in the processing unit 400, the deduplication logic 420 reduces the number of data cache accesses by replacing multiple loads of the same data value with a single load of the data value to a single register. The allocation unit 403 updates the RAT 304 such that multiple register aliases associated with the removed load operations are remapped to the single loaded register. From block 519, the process 500 continues to block 521.

[0054] In block 521, the deduplication logic 320 or 420 updates dependencies for any operations that were originally dependent on the operation eliminated in block 515 or 519. If the original operation is replaced by an equivalent operation, the dependencies of the original operation are updated to depend on the equivalent operation. For example, in the case of an add operation where one operand is determined to be zero, the add operation is replaced with a simpler equivalent operation that outputs the other operand. Thus, any operations that originally depended on the result of the add operation are updated to depend on the other operand instead.

[0055] If multiple load operations are redundant because they load the same data value and are therefore eliminated in block 519, any operations that depend on the destination register of the eliminated load operations are updated to depend on the destination register loaded by the remaining load operations.

[0056] By eliminating an operation, other operations may also become redundant. Thus, at block 523, if additional operations (e.g., instructions) are made redundant by the previous elimination, the process 500 continues to block 525. At block 525, the additional redundant operations are eliminated in a manner similar to that described at blocks 513-515 and 519. At block 521, the dependencies for these eliminated operations are updated. Blocks 521-525 repeat to eliminate redundant operations until no more operations are redundant at block 523. From block 523, the process 500 continues to block 509 where the load operation is performed.

[0057] The method includes, in response to receiving an instruction to perform a first operation on first data stored in a storage device, obtaining first compressed metadata from the storage device based on an address of the first data, and reducing a number of operations in a set of operations based on the first operation and one or more matching addresses, where the one or more matching addresses correspond to second metadata that matches the first compressed metadata.

[0058] In the method, the first compressed metadata comprises a first compressed code and the second compressed metadata comprises a second compressed code equal to the first compressed code, and reducing the number of operations is performed in response to identifying the first compressed code as any of a predetermined subset of compressed codes in a set of compressed codes for compressing data in the storage device.

[0059] In the method, the first compressed metadata includes a first delta value representing a difference between the first data and a base value, the second compressed metadata comprises a second delta value, and the reducing the number of operations is performed in response to determining that the first delta value is equal to the second delta value and that the second delta value is associated with the same base value as the first delta value.

[0060] In the method, the storage device is a data cache device, and the method includes generating first compressed metadata when compressing first data in the data cache device, and generating second compressed metadata when compressing second data in the data cache device.

[0061] In the method, the first operation comprises a load operation retrieved from a load / store queue of the data cache device, and reducing the number of operations in the set of operations includes removing one or more queued accesses of the data cache device from the load / store queue.

[0062] The method also includes, in response to determining that the second compressed metadata matches the first compressed metadata, for each duplicate address of the one or more matching addresses, copying the first data to a register associated with each duplicate address.

[0063] The method also includes loading the first data into a physical register and, in response to determining that the second compressed metadata matches the first compressed metadata, updating a dependency associated with the one or more matching addresses to be dependent on the load of the physical register.

[0064] The method also includes identifying a constant value corresponding to the second compressed metadata; and in response to identifying the constant value, replacing the first operation with an equivalent operation based on the first operation and the identified constant value; and updating dependencies of operations that depend on the first operation to depend on the equivalent operation.

[0065] The computing device includes compression logic that, in response to receiving an instruction to perform a first operation on first data stored on the storage device, retrieves first compressed metadata from the storage device based on an address of the first data. The computing device also includes address calculation logic coupled to the compression logic that, in response to identifying second compressed metadata that matches the first compressed metadata, determines one or more matching addresses corresponding to the second compressed metadata. The computing device also includes deduplication logic coupled to the address calculation logic that reduces a number of operations in the set of operations based on the first operation and the one or more matching addresses.

[0066] In the computing device, the first compressed metadata includes a first compressed code and the second compressed metadata comprises a second compressed code equal to the first compressed code, and the deduplication logic reduces a number of operations in response to the address calculation logic identifying the first compressed code as any of a predetermined subset of compressed codes in a set of compressed codes for compressing data in the storage device.

[0067] In the computing device, the first compressed metadata includes a first delta value representing a difference between the first data and a base value, and the second compressed metadata includes a second delta value, and the deduplication logic reduces a number of operations in response to the address calculation logic determining that the first delta value is equal to the second delta value and that the second delta value is associated with the same base value as the first delta value.

[0068] In the computing device, the storage device includes a data cache device, and the compression logic generates first compressed metadata when compressing first data in the data cache device and generates second compressed metadata when compressing second data in the data cache device.

[0069] In a computing device, a first operation includes a load operation obtained from a load / store queue of a data cache device, and deduplication logic reduces the number of operations in the set of operations by eliminating one or more queue accesses of the data cache device from the load / store queue.

[0070] In the computing device, the deduplication logic copies the first data to a register associated with the duplicate address in response to determining that the second compressed metadata matches the first compressed metadata, for each duplicate address of the one or more matching addresses.

[0071] The computing device also includes a load / store queue coupled to the address calculation logic that loads data into the physical registers. The deduplication logic, in response to the address calculation logic identifying second compressed metadata that matches the first compressed metadata, updates dependencies of operations associated with the one or more matching addresses to be dependent on the loading of the physical registers.

[0072] In the computing device, the redundant address calculation logic identifies a constant value corresponding to the second compressed metadata, and the deduplication logic, in response to identifying the constant value, replaces the first operation with an equivalent operation based on the first operation and the constant value and updates dependencies of operations that are dependent on the first operation to be dependent on the equivalent operation.

[0073] The computing system includes a storage device and a compression engine coupled to the storage device. The compression engine generates first compressed metadata for compressing first data for storing in the storage device and generates second compressed metadata for compressing second data for storing in the storage device. The computing system also includes redundant address calculation logic coupled to the storage device. In response to receiving an instruction to perform a first operation on first data stored in the storage device, the redundant address calculation logic retrieves the first compressed metadata based on an address of the first data, and in response to determining that the second compressed metadata matches the first compressed metadata, calculates one or more matching addresses of the second data based on the second compressed metadata. The computing system includes deduplication logic coupled to the redundant address calculation logic that reduces a number of operations in a set of operations based on the first operation and the one or more matching addresses.

[0074] In the computing system, the storage device includes a cache memory device, and the first compressed metadata and the second compressed metadata are stored in the cache memory device.

[0075] The computing system also includes a physical register file coupled to de-duplication logic, the de-duplication logic reducing the number of operations by reducing the number of register write operations in the physical register file.

[0076] The computing system also includes an arithmetic logic unit coupled to the de-duplication logic, the de-duplication logic reducing the number of operations by reducing the number of calculations performed in the arithmetic logic unit.

[0077] As used herein, the term "coupled to" may mean directly or indirectly coupled through one or more intervening components. Any of the signals provided via the various buses described herein may be time-shared with other signals and provided via one or more common buses. Additionally, the interconnections between circuit components and blocks may be depicted as buses or single signal lines. Each of the buses may alternatively be one or more single signal lines, and each of the single signal lines may alternatively be a bus.

[0078] Certain embodiments may be implemented as a computer program product that may include instructions stored on a non-transitory computer-readable storage medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations. A computer-readable storage medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer). Non-transitory computer-readable storage media may include, but are not limited to, magnetic storage media (e.g., floppy diskettes), optical storage media (e.g., CD-ROMs), magneto-optical storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or another type of medium suitable for storing electronic instructions.

[0079] Additionally, some embodiments may be implemented in a distributed computing environment where a computer-readable storage medium is stored on and / or executed by two or more computer systems. Further, information transferred between computer systems may be pulled or pushed through a transmission medium connecting the computer systems.

[0080] In general, the data structures representing computing system 100 and / or portions thereof embodied in a computer-readable storage medium may be databases or other data structures that may be read by a program and used directly or indirectly to manufacture hardware including computing system 100. For example, the data structures may be behavioral or register-transfer level (RTL) descriptions of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The descriptions may be read by a synthesis tool that may synthesize the descriptions to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including computing system 100. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture semiconductor circuit(s) corresponding to computing system 100. Alternatively, the database on the computer readable storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, as desired.

[0081] Although the operations of the method(s) herein are shown and described in a particular order, the order of operations of each method may be changed such that certain operations may be performed in the reverse order, or such that certain operations may be performed at least in part concurrently with other operations. In alternative embodiments, instructions or sub-operations of individual operations may be performed intermittently and / or alternatingly.

[0082] In the foregoing specification, the embodiments have been described with reference to certain exemplary embodiments thereof. It will be apparent, however, that various modifications and changes can be made thereto without departing from the broader scope of the embodiments as set forth in the appended claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A method comprising: In response to receiving an instruction to load first data into a physical register, obtaining first compressed metadata from a storage device based on an address of the first data stored in the storage device, the first compressed metadata including a compressed representation of the first data stored at the address; reducing a number of operations of the set of operations in a load / store queue based on one or more addresses of the set of instructions and operations for loading the first data into the physical register, the one or more addresses corresponding to second compressed metadata, the second compressed metadata including a compressed representation of second data, the second compressed metadata matching within a threshold value the first compressed metadata including a compressed representation of the first data; mapping the one or more addresses to the physical registers based on a register alias table associated with the physical registers. method.

2. the first compressed metadata includes a first compressed code, and the second compressed metadata includes a second compressed code that is equal to the first compressed code; reducing the number of operations is performed in response to identifying the first compression code as one of a predetermined subset of compression codes in a set of compression codes for compressing data in the storage device.

2. The method of claim 1.

3. the first compressed metadata includes a first delta value representing a difference between the first data and a base value; the second compressed metadata includes a second delta value; reducing the number of operations is performed in response to determining that the first delta value is equal to the second delta value, and the second delta value is associated with the same base value as the first delta value.

2. The method of claim 1.

4. the storage device is a data cache device, The method comprises: generating the first compressed metadata when compressing the first data in the data cache device; generating the second compressed metadata when compressing the second data in the data cache device.

2. The method of claim 1.

5. The method of claim 1, wherein an instruction to load the first datum into a physical register includes a load operation obtained from the load / store queue of the data cache device; reducing the number of operations in the set of operations includes removing one or more queued accesses of the data cache device from the load / store queue. The method of claim 4.

6. and copying, for each address of the one or more addresses, the first data to a register associated with the respective address in response to determining that the second compressed metadata matches the first compressed metadata within the threshold. The method of claim 4.

7. loading the first data into the physical register; and updating a dependency relationship associated with the one or more addresses to be dependent on loading the first data into the physical register in response to determining that the second compressed metadata matches the first compressed metadata within the threshold.

2. The method of claim 1.

8. identifying a constant value corresponding to the second compressed metadata; in response to identifying the constant value, replacing any operation of a set of operations in the load / store queue with an equivalent operation based on the any operation and the identified constant value, the any operation including a calculation; updating a dependency relationship of an operation that depends on any of the operations to depend on the equivalent operation; 2. The method of claim 1.

9. 1. A computing device comprising: compression logic configured to, in response to receiving an instruction to load first data into a physical register, retrieve first compressed metadata from a storage device based on an address of the first data stored in the storage device, the first compressed metadata including a compressed representation of the first data stored at the address; address calculation logic coupled to the compression logic and configured to, in response to identifying second compressed metadata, determine one or more addresses corresponding to the second compressed metadata, the second compressed metadata including a compressed representation of second data; de-duplication logic coupled to the address calculation logic; The deduplication logic comprises: reducing a number of operations of the set of operations in a load / store queue based on the one or more addresses of the set of instructions and operations for loading the first data into the physical register; mapping the one or more addresses to the physical registers based on a register alias table associated with the physical registers; 4. The method of claim 3, Computing device.

10. the first compressed metadata includes a first compressed code, and the second compressed metadata includes a second compressed code that is equal to the first compressed code; the deduplication logic is configured to reduce a number of operations in response to the address calculation logic identifying the first compression code as one of a predetermined subset of compression codes in a set of compression codes for compressing data in the storage device.

10. The computing device of claim 9.

11. the first compressed metadata includes a first delta value representing a difference between the first data and a base value; the second compressed metadata includes a second delta value; the deduplication logic is configured to reduce a number of operations in response to the address calculation logic determining that the first delta value is equal to the second delta value and the second delta value is associated with a same base value as the first delta value.

10. The computing device of claim 9.

12. the storage device includes a data cache device; The compression logic includes: generating the first compressed metadata when compressing the first data in the data cache device; generating the second compressed metadata when compressing the second data in the data cache device; 4. The method of claim 3, 10. The computing device of claim 9.

13. The method of claim 12, wherein the instruction to load the first data into the physical register is obtained from the load / store queue of the data cache device; the deduplication logic is configured to reduce the number of operations in the set of operations by removing one or more queued accesses of the data cache device from the load / store queue; 13. The computing device of claim 12.

14. the deduplication logic is configured to, for each address of the one or more addresses, in response to determining that the second compressed metadata matches the first compressed metadata within a threshold, copy the first data to a register associated with the duplicate address.

10. The computing device of claim 9.

15. The load / store queue, coupled to the address calculation logic, configured to load the first data into the physical register; The deduplication logic comprises: updating dependencies of operations associated with the one or more addresses to be dependent on loading the physical register in response to the address calculation logic identifying the second compressed metadata as matching the first compressed metadata within a threshold; reducing a number of operations in the set of operations in the load / store queue based on one or more operation dependencies of updated operation dependencies associated with one or more addresses of the set of operations; 4. The method of claim 3, 10. The computing device of claim 9.

16. the address calculation logic is configured to identify a constant value corresponding to the second compressed metadata; The deduplication logic comprises: responsive to identifying the constant value, replacing any operation of a set of operations in the load / store queue with an equivalent operation based on the any operation and the constant value; updating a dependency relationship of an operation that depends on the one of the operations so that the operation depends on the equivalent operation; 4. The method of claim 3, 10. The computing device of claim 9.

17. 1. A computing system comprising: A storage device; a compression engine coupled to the storage device; address calculation logic coupled to the storage device; deduplication logic coupled to the address calculation logic; The compression engine comprises: generating first compressed metadata for compressing first data for storage in the storage device, the first compressed metadata including a compressed representation of the first data stored at an address; generating second compressed metadata for compressing second data for storage on the storage device, the second compressed metadata including a compressed representation of the second data, the second compressed metadata matching within a threshold with the first compressed metadata including a compressed representation of the first data; The device is configured to: The address calculation logic comprises: In response to receiving an instruction to load the first data into a physical register, obtaining the first compressed metadata based on an address of the first data; responsive to determining that the second compressed metadata matches the first compressed metadata within the threshold, calculating one or more addresses of the second data based on the second compressed metadata; The device is configured to: The deduplication logic comprises: reducing a number of operations of the set of operations in a load / store queue based on the one or more addresses of the set of instructions and operations for loading the first data into the physical register; mapping the one or more addresses to the physical registers based on a register alias table associated with the physical registers; 4. The method of claim 3, Computing system.

18. the storage device includes a cache storage device; the first compressed metadata and the second compressed metadata are stored in the cache storage device.

20. The computing system of claim 17.

19. a physical register file coupled to the deduplication logic; the deduplication logic is configured to reduce the number of operations by reducing a number of register write operations in the physical register file; 20. The computing system of claim 17.

20. an arithmetic logic unit coupled to the deduplication logic; the deduplication logic is configured to reduce a number of operations by reducing a number of calculations performed in the arithmetic logic unit; 20. The computing system of claim 17.

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