Silicon photonics device for LIDAR sensor and manufacturing method

Abstract

The silicon photonics device structure for LIDAR includes a first insulating structure and a second insulating structure disposed on one or more etched silicon structures disposed on a substrate member. A metal layer is disposed on the first insulating structure without prior deposition of a diffusion barrier and adhesion layer. A thin insulating structure is disposed on the second insulating structure. The first arrangement of the metal layer, the first insulating structure, and the one or more etched silicon structures forms a free space coupler. The second arrangement of the thin insulating structures on the second insulating structure forms an edge coupler.

Description

[Technical field]

[0001] TECHNICAL FIELD This disclosure relates generally to Silicon Photonics Devices, and more particularly to Silicon Photonics Devices for Light Detection and Ranging (LIDAR) applications and methods for fabricating the same. [Background technology]

[0002] LIDAR, also known as Laser Radar (RADAR), is used for various applications including imaging and collision avoidance. The various components used in LIDAR systems such as modulators, optical filters, optical switches, optical waveguides, photodiodes, phase shifters, and wavelength converters are implemented on complementary metal-oxide semiconductor (CMOS) compatible silicon photonics chips such as silicon-on-insulator (SOI) platforms. One of the main challenges facing the development of LIDAR systems is the inadequacies related to the coupling efficiency, wavelength sensitivity, reliability, and link budget performance of the various components. Summary of the Invention

[0003] According to an embodiment, the present disclosure describes a structure of a silicon photonics device for LIDAR. The silicon photonics device includes a substrate member, an antenna formed on the substrate member, and a photodiode formed on the substrate member and coupled to the antenna. The antenna is a one-dimensional grating coupler. The antenna includes a primary formation of a first grating structure on top of the substrate member, a secondary formation of a first metal layer on top of the first grating structure, and a tertiary formation of a diffusion barrier and adhesion layer on top of the first metal layer, where the diffusion barrier and adhesion layer and the first metal layer form a reflective mirror structure. For example, the first metal layer is an MT0 (Metal0) layer. For example, the first metal layer is any of the group consisting of aluminum, gold, silver, and copper. The antenna includes a first dielectric structure coupled to the first grating structure. For example, the first dielectric structure is any of the group consisting of silicon nitride and silicon. The antenna includes a second grating structure coupled to the substrate member, and a first metal layer coupled to the second grating structure. The antenna includes an intermediate formation of an oxide layer between the substrate member and the first formation of the first lattice structure and between the first formation of the first lattice structure and the second formation of the first metal layer. The silicon photonics device further includes a second dielectric structure coupled to a third dielectric structure, the second dielectric structure and the third dielectric structure forming an edge coupler. For example, the first dielectric structure and the third dielectric structure are coplanar. For example, the diffusion barrier and adhesion layer are any of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. For example, the first distance between the bottom of the first dielectric structure and the top of the first lattice structure is in a range between 100 nanometers and 500 nanometers, the second distance between the bottom of the first metal layer and the top of the first lattice structure is in a range between 800 nanometers and 1200 nanometers, and the third distance between the top of the first dielectric structure and the bottom of the first metal layer is in a range between 500 nanometers and 1600 nanometers. For example, a fourth distance between the bottom end of the second dielectric structure and the top end of the third dielectric structure is about 450 nanometers. For example, the first dielectric structure and the third dielectric structure have the same height. For example, the height of the second dielectric structure is about three times or less than the height of the third dielectric structure. For example, the height of the first metal layer is twice the height of the diffusion barrier and adhesion layer.The present disclosure describes a LIDAR sensor that includes a silicon photonics device as described herein.The present disclosure describes an autonomous vehicle control system that includes a silicon photonics device as described herein.

[0004] According to one embodiment, the present disclosure describes a structure of a silicon photonics device. The silicon photonics device includes a substrate member and a first antenna formed on the substrate member. The first antenna includes a first lattice structure coupled to the substrate member, a first dielectric structure coupled to the first lattice structure, and a first metal layer coupled to the first dielectric structure. The silicon photonics device further includes a second antenna formed on the substrate member. The second antenna includes a second lattice structure coupled to the substrate member, and the first metal layer is coupled to the second lattice structure. The silicon photonics device further includes a photodiode formed on the substrate member and coupled to the second antenna. The first antenna further includes a diffusion barrier and adhesion layer on top of the first metal layer, and the diffusion barrier and adhesion layer and the first metal layer form a reflective mirror structure. The first antenna further includes intermediate oxide layers between the first lattice structure and the first dielectric structure and between the first dielectric structure and the first metal layer. For example, the first antenna is a one-dimensional lattice coupler. For example, the first metal layer is a MT0 (Metal0) layer. For example, the first metal layer is any of the group consisting of aluminum, gold, silver, and copper. For example, the first dielectric structure and the second dielectric structure are on the same plane. For example, the first dielectric structure, the second dielectric structure, and the third dielectric structure are formed using any of silicon nitride and silicon. For example, the diffusion barrier and adhesion layer are any of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. For example, the first distance between the bottom end of the first dielectric structure and the top end of the first lattice structure is in the range between 100 nanometers and 500 nanometers, the second distance between the bottom end of the first metal layer and the top end of the first lattice structure is in the range between 800 nanometers and 1200 nanometers, and the third distance between the top end of the first dielectric structure and the bottom end of the first metal layer is in the range between 500 nanometers and 1600 nanometers. For example, a fourth distance between the top of the second dielectric structure and the bottom of the third dielectric structure is about 450 nanometers. For example, the first dielectric structure and the second dielectric structure have the same height. For example, the height of the third dielectric structure is about three times or less than the height of the second dielectric structure. For example, the height of the first metal layer is twice the height of the diffusion barrier and adhesion layer.The present disclosure describes a LIDAR sensor that includes a silicon photonics device as described herein.The present disclosure describes an autonomous vehicle control system that includes a silicon photonics device as described herein.

[0005] According to one embodiment, the present disclosure describes a method for fabricating a silicon photonics device for LIDAR. The method includes the steps of obtaining a substrate member, forming a silicon structure on the substrate member, forming a first dielectric structure and a second dielectric structure on the silicon structure, disposing a first oxide layer on the first dielectric structure and the second dielectric structure, forming a third dielectric structure on the first oxide layer and the second dielectric structure, forming a metal layer on the first oxide layer and the first dielectric structure, and forming a diffusion barrier and adhesion layer on the metal layer. For example, the silicon structure is a grating. For example, the diffusion barrier and adhesion layer on the metal layer forms a reflective mirror structure. For example, the diffusion barrier and adhesion layer is any of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. For example, the metal layer is any of the group consisting of aluminum, gold, silver, and copper. For example, the first dielectric structure and the second dielectric structure are coplanar with each other. The method further includes forming a first dielectric structure by disposing a first layer of an insulating compound on the silicon structure and etching the first layer of the insulating compound to form a first dielectric structure. The method further includes disposing a second layer of an insulating compound on the lower surface of the substrate member before etching the first layer of the insulating compound, and removing the second layer of the insulating compound disposed on the lower surface of the substrate member after forming the first dielectric structure. For example, the first and second layers of the insulating compound are any of the group consisting of silicon nitride (Si3N4) and silicon. For example, the method of disposing the first layer of an insulating compound on the silicon structure and disposing the second layer of an insulating compound on the lower surface of the substrate member is performed by any of the group consisting of a low pressure chemical vapor deposition (LPCVD) process and a plasma enhanced chemical vapor deposition (PECVD) process. The method further includes disposing a film of a resistive metal alloy heater on the silicon structure. The method further includes forming a third dielectric structure by disposing a second oxide layer over the metal layer, etching an opening in the second oxide layer over the second dielectric structure, and forming a third dielectric structure on the second dielectric structure in the opening.The method further includes forming a second silicon structure on the substrate member, doping a portion of the second silicon structure to form a photodiode, and forming a metal contact for the photodiode on the doped portion of the second silicon structure. The method further includes forming a second silicon structure on the substrate member, forming a second diffusion barrier and adhesion layer on the second silicon structure, forming a second metal layer on the second diffusion barrier and adhesion layer and the second silicon structure, and forming a third diffusion barrier and adhesion layer on the second metal layer. The present disclosure describes silicon photonics devices fabricated by the methods described herein. The present disclosure also describes LIDAR sensor systems including silicon photonics devices fabricated by the methods described herein.

[0006] According to one embodiment, the present disclosure describes a method for manufacturing a silicon photonics device for a vehicle. The method includes the steps of obtaining a substrate member and forming a first silicon structure bonded to the substrate member, forming a first oxide layer on the first silicon structure, forming a metal layer on the first oxide layer and the first silicon structure, and forming an adhesion layer on the metal layer configured to act as a diffusion barrier and adhere to the metal layer. The method further includes forming a first dielectric structure on the first oxide layer and the first silicon structure, and forming a second oxide layer on the first dielectric structure, the second oxide layer being formed between the first oxide layer and the metal layer. The method further includes chemical mechanical polishing of the first oxide layer, and forming a spacer between the first silicon structure and the first dielectric structure. The method further includes forming a second silicon structure on the first oxide layer, but the second oxide layer is formed on the second silicon structure, and forming a third silicon structure on the second silicon structure and the second oxide layer. For example, the first dielectric structure and the second silicon structure are coplanar with each other. The method further includes forming a first dielectric structure on the first oxide layer and the first silicon structure by forming a first layer of an insulating compound on the first oxide layer and etching the first layer of the insulating compound down to the first oxide layer to form a first dielectric structure on the first silicon structure. The method further includes forming a second layer of an insulating compound on the lower surface of the substrate member before etching the first layer of the insulating compound and removing the second layer of the insulating compound formed on the lower surface of the substrate member after forming the first dielectric structure. The method further includes forming a third silicon structure on the second silicon structure and the second oxide layer by etching an opening in the second oxide layer formed on the second silicon structure and forming a third silicon structure in the opening. The method further includes forming a fourth silicon structure on the substrate member, doping certain one or more portions of the fourth silicon structure to form a photodiode, and forming one or more metal contacts for the photodiode on portions of the fourth silicon structure.For example, the first and second layers of the insulating compound include any of the group consisting of silicon nitride (Si3N4) and silicon. For example, the method of forming the first layer of the insulating compound on the first oxide layer and the second layer of the insulating compound on the bottom surface of the substrate member is performed by any of the group consisting of low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). For example, the first silicon structure is a lattice structure. For example, the metal layer includes any of the group consisting of aluminum, gold, silver, and copper. For example, the adhesion layer includes any of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. The present disclosure describes a silicon photonics device manufactured by the method described herein. The present disclosure also describes a LIDAR sensor system including a silicon photonics device manufactured by the method described herein.

[0007] Those skilled in the art will appreciate that the summary is merely illustrative and is not intended to be limiting in any manner. Any of the features described herein may be used with any other features, and any subset of such features may be used in combination, according to various embodiments. Other aspects, inventive features, and advantages of the apparatus and / or processes described herein, as defined solely by the claims, will become apparent from the detailed description presented herein in conjunction with the accompanying drawings. Moreover, the language used in this disclosure has been selected primarily for purposes of readability and explanation, and not to limit the scope of the subject matter disclosed in this disclosure. [Brief description of the drawings]

[0008] Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:

[0009] [Figure 1a] FIG. 1 is a block diagram illustrating an example of a hardware and software environment for an autonomous vehicle according to one embodiment.

[0010] [Figure 1b] FIG. 1 is a high-level system diagram of a silicon photonics device for a coherent LIDAR system according to one embodiment.

[0011] [Diagram 2] 1 shows a schematic cross-sectional view illustrating the structure of the silicon photonics device shown in FIG. 1b according to one embodiment.

[0012] [Diagram 3] ~ [Figure 17] 1A-1C show schematic cross-sectional views illustrating a method of fabricating the silicon photonics device shown in FIG. 1b according to one embodiment.

[0013] It should be understood that alternative embodiments of the structures and methods described herein may be employed without departing from the principles described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In the following description, for purposes of explanation, numerous specific details are presented to provide a thorough understanding of the various aspects of various exemplary embodiments. It should be noted that any particular exemplary embodiment may be practiced in various cases without all of the specific details and / or with variations, permutations, and combinations of the various features and elements described herein. Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers used in the drawings and description refer to the same or similar parts.

[0015] Also, relative terms such as "lower" or "bottom" or "rear" or "lower" and "upper" or "top" or "front" or "top" can be used to describe the relationship of one element to other elements as depicted in the figures. It will be understood that the relative terms are intended to include various orientations of the device in addition to the orientation depicted in the figures. For example, if the device is inverted in one of the figures, an element described as being on the "lower" side of the other element would then be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" can include both a "lower" and an "upper" orientation, depending on the particular orientation of the figure. Similarly, if the device is inverted in one of the figures, an element described as being "below" or "bottom" of the other element would then be oriented "upper" of the other element. Thus, the exemplary term "lower" or "bottom" can include both an upper and lower orientation.

[0016] Referring to the drawings, in which like numbers indicate like parts throughout the several views, FIG. 1a illustrates an exemplary hardware and software environment for an autonomous vehicle 100 in which various techniques disclosed herein may be implemented. For example, vehicle 100 may include a powertrain 102 including a prime mover 104 that may be driven by an energy source 106 and provide power to a drivetrain 108, as well as a control system 110 including directional control 112, powertrain control 114, and brake control 116. It should be understood that vehicle 100 may be implemented in any number of different types of vehicles, including vehicles capable of transporting people and / or cargo and traveling overland, and that the aforementioned components 102-116 may vary significantly depending on the type of vehicle in which these components are utilized.

[0017] For simplicity, the embodiments discussed below focus on wheeled land vehicles such as cars, vans, trucks, buses, etc. In such embodiments, prime mover 104 may include (among others) one or more electric motors and / or an internal combustion engine. Energy source 106 may include, for example, a fuel system (e.g., providing gasoline, diesel, hydrogen, etc.), a battery system, solar panels or other renewable energy sources, and / or a fuel cell system. Drive train 108 includes wheels and / or tires along with a transmission and / or any other mechanical drive components suitable for converting the power output of prime mover 104 into vehicle motion, one or more brakes configured to controllably stop or slow vehicle 100, and a steering or steering component suitable for controlling the trajectory of vehicle 100 (e.g., a rack and pinion steering linkage that allows one or more wheels of vehicle 100 to pivot about a generally vertical axis to change the angle of the plane of rotation of the wheel relative to the vehicle's longitudinal axis). In one embodiment, a combination of powertrain and energy source can be used (e.g., in the case of an electric / gas hybrid vehicle), while in other embodiments, multiple electric motors (e.g., dedicated to individual wheels or axles) can be used as prime mover 104. In the case of a hydrogen fuel cell implementation, prime mover 104 can include one or more electric motors and energy source 106 can include a fuel cell system powered by hydrogen fuel.

[0018] Directional control 112 may include one or more actuators and / or sensors for controlling and receiving feedback from directional or steering components so that vehicle 100 can follow a desired trajectory. Powertrain control 114 controls the speed and / or direction of vehicle 100 by being configured to control the output of powertrain 102, such as by controlling the output power of prime mover 104 and controlling the gears of a transmission in drivetrain 108. Brake control device 116 may be configured to control one or more brakes, such as disc or drum brakes coupled to the wheels of the vehicle, to slow or stop vehicle 100.

[0019] Other vehicle types, including, but not limited to, all-terrain or tracked vehicles and construction equipment, may utilize various powertrains, drivetrains, energy sources, directional control, powertrain control, and brake control. Also, in one embodiment, some of the components may be combined, for example, directional control of the vehicle is primarily handled by modifying the output of one or more prime movers. Thus, the embodiments disclosed herein are not limited to the specific application of the technology described herein in autonomous ground vehicles.

[0020] In the illustrated embodiment, full or semi-autonomous control of vehicle 100 is implemented in vehicle control system 120, which may include one or more processors 122 and one or more memories 124, with each processor 122 configured to execute program code instructions 126 stored in memory 124. The multiple processors may include, for example, multiple graphics processing units ("GPUs") and / or multiple central processing units ("CPUs").

[0021] The sensors 130 may include various sensors suitable for collecting information from the vehicle's surrounding environment for use in controlling the operation of the vehicle 100. For example, the sensors 130 may include one or more detection and distance measurement sensors (e.g., a RADAR sensor 134, a LIDAR sensor 136, or both), a 3D positioning sensor 138, such as a satellite navigation system such as a Global Positioning System (GPS), a Globalnaya Navigazionnaya Sputnikovaya Sistema (GLONASS), or Global Navigation Satellite System (GLONASS), a BeiDou navigation satellite system (BDS), Galileo, Compass, etc. The 3D positioning sensor 138 may be used to determine the vehicle's position on Earth using satellite signals. The sensors 130 may optionally include a camera 140 and / or an inertial measurement unit (IMU) 142. The camera 140 may be a monographic or stereographic camera and may record still and / or video images. The IMU 142 may include multiple gyroscopes and accelerometers capable of detecting linear and rotational motion of the vehicle 100 from three directions. One or more encoders 144, such as wheel encoders, may be used to monitor the rotation of one or more wheels of the vehicle 100. In one embodiment, the LIDAR sensor 136 may include a silicon photonics device structure for a coherent LIDAR system, as described in more detail below.

[0022] The output of the sensors 130 may be provided to a set of control subsystems 150, including a position estimation subsystem 152, a perception subsystem 154, a planning subsystem 156, and a control subsystem 158. The position estimation subsystem 152 is primarily responsible for accurately determining the position and orientation (sometimes also referred to as "pose" or "pose estimation") of the vehicle 100 within the surrounding environment, and generally within some frame of reference. The perception subsystem 154 is primarily responsible for detecting, tracking, and / or identifying objects within the surrounding environment of the vehicle 100. Machine learning models according to an embodiment may be utilized to track the objects. The planning subsystem 156 is primarily responsible for planning a trajectory or travel path of the vehicle 100 over some time frame given a desired destination, as well as static and moving objects in the environment. Machine learning models according to an embodiment may be utilized to plan the vehicle trajectory. The control subsystem 158 is primarily responsible for generating appropriate control signals for controlling various controls of the vehicle control system 120 to implement the planned trajectory of the vehicle 100. Similarly, machine learning models may be utilized to generate one or more signals for controlling the autonomous vehicle 100 to execute a planned trajectory.

[0023] It should be understood that the collection of components for vehicle control system 12 shown in FIG. 1a is merely one example. In one embodiment, individual sensors may be omitted. Additionally or alternatively, in one embodiment, multiple sensors of the same type shown in FIG. 1a may be used redundantly and / or to cover various areas around the vehicle. Also, there may be additional sensors of other types other than those previously described to provide actual sensor data related to the operation and environment of the wheeled land vehicle. Similarly, various types and / or combinations of control subsystems may be used in other embodiments. Also, although subsystems 152-158 are illustrated as being separate from processor 122 and memory 124, in one embodiment, some or all of the functionality of subsystems 152-158 may be implemented as program code instructions 126 resident in one or more memories 124 and executed by one or more processors 122, and these subsystems 152-158 may be implemented using the same processor and / or memory, in some cases. The subsystems may be implemented at least in part using various special purpose circuit logic, various processors, various field programmable gate arrays ("FPGAs"), various application specific integrated circuits ("ASICs"), various real time controllers, etc., and as previously discussed, multiple subsystems may use circuits, processors, sensors, and / or other components. Additionally, the various components of vehicle control system 120 may be networked in various ways.

[0024] In one embodiment, vehicle 100 may also include a secondary vehicle control system (not shown) that may be used as a redundant or backup control system for vehicle 100. In one embodiment, the secondary vehicle control system is capable of fully operating autonomous vehicle 100 in the event of an adverse event occurring in vehicle control system 120, while in other embodiments the secondary vehicle control system may have only limited functionality, such as performing a controlled stop of vehicle 100 in response to an adverse event detected in primary vehicle control system 120. In still other embodiments, the secondary vehicle control system may be omitted.

[0025] In general, various architectures including various combinations of software, hardware, circuit logic, sensors, networks, etc., can be used to implement the various components shown in FIG. 1a. Each processor can be implemented, for example, as a microprocessor, and each memory can include a random access memory ("RAM") device including main storage, as well as any supplemental levels of memory, such as cache memory, non-volatile or backup memory (e.g., programmable or flash memory), read-only memory, etc. Each memory can also be considered to include memory storage physically located elsewhere in the vehicle 100, such as any cache memory within the processor, as well as any storage capacity used as virtual memory, such as to be stored in a mass storage device or other computer controller. One or more of the processors 122 shown in FIG. 1a, or separate processors entirely, can be used to implement additional functions within the vehicle 100 other than for autonomous control purposes, such as the operation of entertainment system control, doors, lights, convenience functions, etc.

[0026] For additional storage, vehicle 100 may also include one or more mass storage devices, such as a removable disk drive, a hard disk drive, a direct access storage device ("DASD"), an optical drive (e.g., CD drive, DVD drive, etc.), a solid state storage drive ("SSD"), network attached storage, a storage area network, and / or a tape drive.

[0027] Additionally, vehicle 100 may include a user interface 118 that enables vehicle 100 to receive inputs from a user or operator and generate outputs therefor, e.g., one or more displays, touch screens, voice and / or gesture interfaces, buttons and tactile controls, etc. Alternatively, user inputs may be received via an app or web interface of another computer or electronic device, e.g., a mobile device.

[0028] Vehicle 100 may also include one or more network interfaces (e.g., network interface 162) suitable for communicating with one or more networks 176 to enable communication of information with other computers or electronic devices, including, for example, a central service such as a cloud service, to receive information including trained machine learning models and other data for use in autonomous control. One or more networks 176 may be, for example, a communications network and may include a wide area network ("WAN") such as the Internet, one or more local area networks ("LAN") such as a Wi-Fi LAN, a mesh network, and one or more bus subsystems. One or more networks 176 may selectively utilize one or more standard communications technologies, protocols, and / or inter-process communication technologies. In one embodiment, data collected by one or more sensors 130 may be uploaded to computing system 172 via network 176 for further processing.

[0029] In the illustrated embodiment, the vehicle 100 can communicate with a computing system 172 via a network 176 and signal lines 178. In one embodiment, the computing system 172 is a cloud-based computing device. A machine learning engine 166 operable on the computing system 172 generates machine learning models based on the simulation scenarios and simulated sensor data for use in autonomous control of the vehicle 100. The machine learning models are transmitted from the computing system 172 to the vehicle 100 for use by the appropriate control subsystems 152-158 to perform their functions.

[0030] 1a, as well as various additional controllers and subsystems disclosed herein, generally operate under the control of an operating system and execute or rely on various computer software applications, components, programs, objects, modules, data structures, etc., as described in more detail below. The various applications, components, programs, objects, modules, etc. may also run on one or more processors of other computers (e.g., computing system 172) connected to vehicle 100 via network 176, e.g., in a distributed, cloud-based, or client-server computing environment, where processing required to carry out the functions of a computer program is allocated across multiple computers and / or services via the network.

[0031] In general, the routines executed to implement the various embodiments described herein are referred to herein as "program code," whether implemented as part of an operating system or as a specific application, component, program, object, module, or instruction sequence, or a subset thereof. Program code generally consists of one or more instructions that reside at various times in various memory and storage devices, and that, when read and executed by one or more processors, perform the steps necessary to execute the steps or elements implementing the various aspects of the present disclosure. Also, while the embodiments are described in the context of fully functional computers and systems, it should be understood that the various embodiments described herein can be distributed as program products in a variety of forms, and that such embodiments can be implemented regardless of the particular type of computer-readable medium used to actually effect the distribution.

[0032] Examples of computer readable media include non-transitory media such as types of volatile and non-volatile memory devices, floppy and other removable disks, solid state drives, hard disk drives, magnetic tape, and optical disks (e.g., CD-ROMs, DVDs, etc.).

[0033] Also, various program codes described below can be identified based on the application in which they are implemented in a particular embodiment. However, it should be understood that the specific program nomenclature that follows is used merely for convenience, and thus the present disclosure should not be limited to use only with any particular application identified and / or implied by such nomenclature. Furthermore, it should be understood that the manner in which a computer program may be organized into routines, procedures, methods, modules, objects, etc. is generally limitless, and that the present disclosure is not limited to the particular structure and allocation of program functions described herein when considering the various ways in which program functions are allocated to various software layers that reside within a typical computer (e.g., operating system, libraries, APIs, applications, applets, etc.).

[0034] The exemplary environment illustrated in Figure 1a is not intended to limit the embodiments disclosed herein, and indeed, other alternative hardware and / or software environments may be used without departing from the scope of the embodiments disclosed herein.

[0035] FIG. 1b is an exemplary high-level diagram of a silicon photonics device 105 for a coherent LIDAR system according to one embodiment. The silicon photonics device 105 includes a configuration of a photodiode (PD) 125, a grating coupler 145, an edge coupler 165, and a 2×2 mixer 180. In one embodiment, the PD 125 can be a germanium (Ge) PD. In other embodiments, the PD 125 can be a silicon PD, an indium gallium arsenide PD, a mercury cadmium telluride PD, a lead (II) sulfide PD, a molybdenum disulfide PD, a graphene PD, and / or combinations thereof. The grating coupler 145 can be used to couple light into and out of the silicon photonics device 105. The operation of the grating coupler 145 is related to refractive index changes caused by etching or deposition on a silicon-on-insulator (SOI) wafer during the manufacturing process. In one embodiment, the grating coupler 145 may be a one-dimensional grating coupler. For example, if the refractive index of the grating coupler 145 changes only in one direction, it is a one-dimensional grating coupler, and light couples in the direction of the refractive index change. In another embodiment, the grating coupler 145 may be a two-dimensional grating coupler. The grating couplers 145a, 145b, 145c may be free space couplers. The grating couplers 145a, 145b are associated with the receiver antenna, and the grating coupler 145c is associated with the transmitter antenna. Each 2×2 mixer 180 is a frequency mixer that receives as input one of the local oscillator (LO) signals (e.g., LOS and LOP) and a signal received via one of the grating couplers (e.g., 145a and 145b) associated with the receiver antenna. The output signal from the mixer 180 is then directed to the photodiode 125 for detection and sensing. The edge coupler 165 is coupled to an amplifier 170. The amplifier 170 is a light source for the silicon photonics device 105. For example, the amplifier 170 generates light that is coupled to the silicon photonics device 105 via the edge coupler 165.The transmit (TX) port connected to the grid coupler 145c associated with the transmitter antenna is directly or indirectly connected to an edge coupler 165.

[0036] FIG. 2 shows a schematic cross-sectional view illustrating a structure of a silicon photonics device 200 for a coherent LIDAR system according to an embodiment. The structure of the silicon photonics device 200 is fabricated using a SOI wafer. As shown in FIG. 3, the SOI wafer 300 may include a SOI layer 202, a Buried Oxide (BOX) layer 206, and a bulk silicon substrate member 204 that provides support for the SOI wafer. The BOX layer 206 resides between the SOI layer 202 and the bulk silicon substrate member 204. The SOI layer 202 can be etched and patterned with one or more silicon structures 402, 404, 406, 408 bonded to the bulk silicon substrate member 204. For example, the SOI layer 202 can be a crystalline silicon (c-Si) layer. The portion of the c-Si layer disposed on the BOX layer 206 can be selectively and partially etched to pattern one or more silicon structures 402, 404, 406, and 408. The silicon structures 402, 404, 406 and 408 may include one or more of an island structure, a rib structure, a grat structure, and a slab structure. The silicon structures may include one or more non-uniform lattice structures that form optical waveguides used for optical input and output. In addition to optical waveguides, other optical device structures such as lasers, optical modulators, photodetectors, and optical switches may also be fabricated in the SOI layer 202. The depth of the edge of the silicon structures partially etched in the SOI layer 202 may range between about 50 nm and about 300 nm. The thickness of the BOX layer 206 is, for example, about 3000 nm, but may have a range between about 1500 nm and about 3500 nm. As described in more detail below, a dielectric material or insulator compound layer may be disposed and etched on the silicon structures to pattern one or more insulating or dielectric structures. For example, a first insulating structure 702 is patterned and etched in an insulating compound layer to bond to the isolated silicon structure 404. In this embodiment, the first insulating structure 702 is coplanar with the second insulating structure 704. The thickness or height of the insulating structures 702 and 704 is about 400 nm in FIG. 2, but can range between about 300 nm and about 600 nm.In some embodiments, the insulator compound layer can be a dielectric material with a higher optical index than the cladding material it contacts. For example, the insulator compound layer can be a silicon nitride (Si3N4) layer. One advantage of using a Si3N4 layer in a silicon photonics chip for a coherent LIDAR system is the ability to handle higher optical power. In other examples, the insulator compound layer can be an amorphous silicon (a-Si) layer, a crystalline silicon (c-Si) layer, etc. The distance between the bottom surface of the first insulating structure 702 and the top of the silicon structure is, for example, about 240 nm, but can have a range of about 100 nm to about 500 nm. A germanium (Ge) photodiode 125 can be fabricated on the silicon structure via doping.

[0037] The structure of the silicon photonics device 200 may include multiple metal routing layers, metal 1 (MT1) layer 1002, metal 2 (MT2) layer 1402, and metal 3 (MT3) layer 1404, for forming interconnects. After the formation of the MT1 layer 1002, the metal 0 (MT0) layer 1108 may be bonded to the first insulating structure 702. In one embodiment, the diffusion barrier and adhesion layer 1106 may be bonded to the metal layer 1104. The diffusion barrier and adhesion layer 1106 may be disposed on the top or top of the metal layer 1104. The MT0 layer 1108, consisting of the metal layer 1104 and the diffusion barrier and adhesion layer 1106, may form a reflective mirror structure that is bonded to the first insulating structure 702. In another embodiment, the diffusion barrier and adhesion layer 1106, which has good optical properties such as reflectivity, may be disposed on the top and bottom of the metal layer 1104. The diffusion barrier and adhesion layer 1106 may be tantalum nitride, indium oxide, copper silicide, tungsten nitride, titanium nitride, and / or combinations thereof. There is an oxide layer or cladding 1408 that fills the space between the different structures formed on the silicon photonics device 200. The distance separating the top of the first insulating structure 702 and the bottom of the MT0 layer 1108 is, for example, about 900 nm, but may have a range between about 500 nm and about 1600 nm. The distance separating the bottom of the MT0 layer 1108 and the top of the silicon structure 404 is, for example, about 1140 nm, but may have a range between about 800 nm and about 1200 nm. In one embodiment, the thickness of the metal layer 1104 may be twice the thickness of the diffusion barrier and adhesion layer 1106. For example, the thickness of the metal layer 1104 may be about 100 nm, and the thickness of the diffusion barrier and adhesion layer 1106 may be about 50 nm. Also, the second insulating structure 704 may be coupled with a thin insulating structure 1302 made of the same insulating material as the first insulating structure 702 and the second insulating structure 704. For example, the thin insulating structure 1302 may be disposed on the second insulating structure 704. In one embodiment, the thickness of the thin insulating structure 1302 may be less than or equal to about 3.6 times the thickness of the second insulating structure 704. For example, when the thickness of the second insulating structure 704 is about 400 nm, the thickness of the thin insulating structure 1302 is about 110 nm. The distance between the bottom end of the thin insulating structure 1302 and the top end of the second insulating structure 704 may be about 450 nm.

[0038] In FIG. 2, the MT0 layer 1108, the first insulating structure 702, and one or more of the partially etched silicon structures 402, 404 form a grating coupler 145 for coupling to free space. For example, the MT0 layer 1108 and the silicon structure 402 form a grating coupler 145 associated with a receiver antenna of the silicon photonics device 200 for a coherent LIDAR system. In another example, the MT0 layer 1108, the first insulating structure 702, and the silicon structure 404 form a grating coupler 145 associated with a transmitter antenna of the silicon photonics device 200 for a coherent LIDAR system. The MT0 layer 1108 serves as a silicon photonics chip-free space interface. The BOX layer 206 serves as a low optical index cladding material. The oxide layer cladding 1408 also serves as a low optical index cladding material. The cladding can be one or more layers of lower optical index material in contact with a higher optical index core material such as silicon structures 402, 404 and insulating structures 702, 704. The thin insulating structure 1302 disposed on top of and overlapping the second insulating structure 704 forms the edge coupler 165 for coupling to other semiconductor devices such as the amplifier 170 or silicon photonics devices. The coupling of the thin insulating structure 1302 and the second insulating structure 704 serves as an amplifier-silicon photonics chip interface. Although FIG. 2 shows the thin insulating structure 1302 and the second insulating structure 704 overlapping edge to edge, it should be understood that there may be an offset in their overlap. In one embodiment, the edge coupler 165 can be fabricated with a single insulating structure. The edge coupler 165 made with a configuration of double insulating structures 704 and 1302 provides a higher coupling efficiency (CE) than a configuration of a single insulating structure and better matches the optical mode of a coherent LIDAR system. In other embodiments, the edge coupler 165 structures can be patterned into the crystalline silicon (c-Si) layer itself, without the need to use an insulating compound such as Si3N4.

[0039] In one embodiment, the structure of the lattice coupler 145 may be constructed using another upper insulating structure (not shown in FIG. 2 ) on the first insulating structure 702. This upper insulating structure may be made of the same insulating material as the insulating material of the first insulating structure 702. The upper insulating structure or the first insulating structure 702 below it may be etched and patterned to form a plurality of isolated bars of the insulating structure and coupled with the MT0 layer 1108 to form the lattice coupler 145. For example, when a plurality of isolated bars of the insulating structure are patterned on the upper insulating structure, these isolated bars may form a lattice coupler associated with the receiver antenna together with the MT0 layer 1108. In another example, when a plurality of isolated bars of the insulating structure are patterned on the first insulating structure 702, these isolated bars may form a lattice coupler associated with the transmitter antenna together with the upper insulating structure and the MT0 layer 1108. In other embodiments, isolated bars of insulating structures patterned on the silicon structures 402, 404 and the upper insulating structure or the first insulating structure 702 may be mixed and matched with the MT0 layer 1108 to form the grating coupler 145.

[0040] An advantage of the grating coupler 145 structure etched and patterned into the silicon photonics device 200 of FIG. 2 is that it helps meet the link budget requirements for use in automotive grade LIDAR systems. For example, the grating coupler 145 structure can reduce the insertion loss at the interface between the silicon photonics device 200 for coherent LIDAR and free space in both the transmit and receive paths, resulting in an improvement of about 2 dB to 6 dB in the overall link budget. The optical loss of a transmitter or output type grating coupler is calculated twice in the link budget because the light exits such a coupler, reflects off the target, and returns to the grating coupler. The grating coupler 145 structure can facilitate achieving a coupling loss of about 0.25 dB without lithography constraints. With lithography constraints, the grating coupler 145 structure can facilitate achieving a coupling loss of about 0.5 dB to about 1.0 dB.

[0041] 3-17 show schematic cross-sectional views illustrating a method of fabricating a silicon photonics device according to one embodiment.

[0042] As shown in Figure 3, an SOI wafer 300 is provided. In one embodiment, the SOI wafer 300 may be a three-layer wafer including a bulk silicon substrate member 204 as a first or base layer, a buried oxide (BOX) layer 206 of an electrically insulating material such as silicon dioxide (SiO2) having a thickness of about 3000 nm as a second or middle layer, and an active crystalline silicon (c-Si) SOI layer 202 having a thickness of about 220 nm as a third or top layer.

[0043] As shown in FIG. 4, the c-Si layer or SOI layer 202 shown in FIG. 3 can be precisely patterned and etched to form non-uniform silicon structures such as grat 402, rib 404, island 406, and slab 408 disposed on the BOX layer 206. The remaining portion of the SOI layer 202 shown in FIG. 3 can be etched down to the BOX layer 206. The grat 402 silicon structure is etched to a depth of about 70 nm, and the slab 408 silicon structure is etched to a depth of about 130 nm from the top. The rib 404 structure is patterned and etched into an isolated full thickness (e.g., 220 nm) bar of silicon structure.

[0044] 5, an oxide layer or cladding 502 is deposited on the silicon structures 402, 404, 406, 408 to a height of about 240 nm from the top of the silicon structures 402, 404, 406, 408. After oxide deposition, the top of the SOI wafer 300 undergoes a chemical mechanical polishing (CMP) or planarization process. Such oxide layer deposition and planarization process is performed to form a spacer between the silicon structures 402, 404, 406, 408 and the insulating compound or material that is subsequently deposited on the top of the SOI wafer 300.

[0045] As shown in FIG. 6, a first layer 602 and a second layer 604 of an insulating compound or material, such as silicon nitride (Si3N4), are deposited on top of the oxide layer 502 and on the bottom of the substrate member 204. Such deposition can be achieved using a chemical vapor deposition method. The thickness of the first layer 602 deposited on the top of the SOI wafer 300 is about 400 nm. In one embodiment, the chemical vapor deposition method used can be a low pressure chemical vapor deposition (LPCVD) method. In the LPCVD method, Si3N4 is deposited on both sides (top and bottom) of the SOI wafer 300. The LPCVD method can apply strong tensile stress to the SOI wafer 300 to cause deformation. Such double-sided deposition of Si3N4 is performed to eliminate the effect of tensile stress and prevent warping of the SOI wafer 300 structure. In one embodiment, plasma enhanced chemical vapor deposition (PECVD) can be used as a method for depositing an insulating compound layer on the top of the SOI wafer 300. In the PECVD method, double-sided deposition of the insulating compound may not be necessary. In one embodiment, amorphous silicon (a-Si) can be used as the insulating compound.

[0046] As shown in FIG. 7, the deposited layer 602 on top of the oxide layer 502 of FIG. 6 is patterned and etched to form two coplanar insulating structures or dielectric elements 702 and 704 disposed on top of the oxide layer 502. The insulating structure 702 can overlap and be bonded to the silicon structure 404. The remaining part of the deposited layer 602 on top of the oxide layer 502 is etched down to the oxide layer 502. The thickness of the two coplanar insulating structures 702 and 704 is, for example, about 400 nm. After the deposited layer 602 on top of the SOI wafer 300 is patterned and etched, the SOI wafer 300 can be washed to remove all photoresist.

[0047] As shown in Fig. 8, the layer 604 deposited on the bottom of the substrate member 204 in Fig. 7 is removed after forming two coplanar insulating structures 702, 704. The deposited layer 604 on the top of the SOI wafer 300 in Fig. 6 is patterned and etched to release the tensile stress applied to the top of the SOI wafer 300. To balance the tensile stress applied to the bottom of the SOI wafer 300, the layer 604 deposited on the bottom of the SOI wafer 300 in Fig. 7 is removed. After the layer 604 deposited on the bottom of the SOI wafer 300 is removed, the top of the SOI wafer 300 can be deep cleaned to remove any contaminants that may have been transferred to the top of the SOI wafer 300.

[0048] As shown in Figure 9, the etched silicon structure 406 disposed on the BOX layer 206 is doped to form the photodiode 125. For example, germanium can be used as a material to form the photodiode 125 of Figure 9. It should be understood that other materials such as silicon, indium gallium arsenide, lead (II) sulfide, mercury cadmium telluride, or combinations thereof can also be used to form the respective photodiodes. Following the formation of the photodiode 125, another oxide layer 902 is deposited on top of the SOI wafer 300.

[0049] As shown in FIG. 10, three conductive vias are formed on the MT1 layer 1002 and the terminals of the photodiode 125. The MT1 layer 1002 and the conductive vias are formed by first depositing and patterning a first diffusion barrier and adhesion layer 1004a. Then, a metal 1001 is deposited and patterned in the middle. Finally, a second diffusion barrier and adhesion layer 1004b is deposited and patterned. That is, the metal 1001 is sandwiched between two thin diffusion barrier and adhesion layers 1004a and 1004b. In one embodiment, the metal 1001 can be deposited using one or more of aluminum, copper, gold, silver, or a combination thereof. In one embodiment, the diffusion barrier and adhesion layers 1004a, 1004b can be deposited using tantalum nitride (TaN). The thickness of the diffusion barrier and adhesion layers 1004a, 1004b is about 50 nm. The thickness of the metal 1001 deposited to form the MT1 layer 1002 is about 750 nm. The distance between the MT1 layer 1002 and the top of the silicon structure 402 is about 740 nm.

[0050] As shown in FIG. 11, an MT0 layer 1108 is formed. The purpose of this new MT0 layer 1108 is to form a highly reflective mirror structure in the silicon photonics device 105. After the formation of the MT1 layer 1102 shown in FIG. 10, an oxide layer 1102 having a thickness of about 300 nm is deposited on top of the SOI wafer 300 as shown in FIG. 11. A metal layer 1104 is deposited and patterned on top of the first insulating structure 702. The thickness of this metal layer 1104 deposition is about 100 nm. A diffusion barrier and adhesion layer 1106 can be deposited and patterned on top of the metal layer 1104 to improve adhesion. The thickness of this top diffusion barrier and adhesion layer 1106 is about 50 nm. Thus, the deposited metal layer 1104 and diffusion barrier and adhesion layer 1106 form the MT0 layer 1108 as shown in FIG. 11. The formation of the MT0 layer 1108 is different in that the base diffusion barrier and adhesion layer is not deposited before depositing the metal layer 1104. That is, the metal layer 1104 is deposited first without a diffusion barrier and adhesion layer underneath it. For example, a diffusion barrier and adhesion layer of a tantalum nitride (TaN) material has a low reflectivity. If a TaN diffusion barrier and adhesion layer is deposited before the metal layer 1104, this may adversely affect the reflectivity of the MT0 layer 1108 to form a highly reflective mirror structure. In other embodiments, a material with good optical properties in terms of reflectivity may be used as the diffusion barrier and adhesion layer underneath the metal layer 1106. Between the subsequent formation of the MT1 layer 1002 and the MT0 layer 1108, there is an intentional omission of a chemical mechanical polishing (CMP) step for planarization of the SOI wafer 300. The CMP step may introduce uncertainty into the oxide spacing between the two different layers. Such an intentional omission of the CMP step is done to minimize the change in the oxide spacing. In one embodiment, the SOI wafer 300 may undergo a CMP step between the MT1 layer 1002 and the subsequent formation of the MT0 layer 1108. Openings can be etched in the oxide spacing to a desired depth that allows the MT0 layer 1108 to be patterned. The arrangement of the MT0 layer 1108, the insulating structure 702, and the silicon structures 402, 404 forms one or more grating couplers 145, as described herein.The distance between the bottom of the MT0 layer 1108 and the top of the silicon structure 404 is about 1140 nm. The distance between the bottom of the MT0 layer 1108 and the top of the insulating structure 702 is about 900 nm. The distance between the bottom of the first insulating structure 702 and the top of the silicon structure 404 is about 240 nm.

[0051] 12, another oxide layer 1202 is deposited on the MT1 layer 1002, the MT0 layer 1108, the oxide layer 1102, and other structures on top. After oxide deposition, the top of the SOI wafer 300 undergoes a CMP (Chemical Mechanical Polishing) or planarization step.

[0052] As shown in FIG. 13, an opening can be etched in the oxide layer 1202 on top of the second insulating structure 704. A thin layer of an insulating compound, such as Si3N4, is deposited in the opening and patterned to form a thin insulating structure 1302 on top of the second insulating structure 704. The thickness of the thin insulating structure 1302 is about 110 nm. The distance between the bottom of the thin insulating structure 1302 and the top of the second insulating structure 704 is about 450 nm. The configuration of the thin insulating structure 1302 on top of the second insulating structure 704 forms an edge coupler 165 as described herein.

[0053] As shown in FIG. 14, the back end of the line fabrication steps are performed. This includes forming the MT2 layer 1402 and the MT3 layer 1404, adding conductive vias connecting the different metal layers, depositing more oxide layers 1408, depositing heater HTR 1406, and performing CMP processing steps. The thickness of the metal deposited on the MT3 layer 1404 is about twice that of the one deposited on the MT2 layer 1402. For example, the thickness of the metal deposited on the MT2 layer 1402 is about 1000 nm, and the thickness of the metal deposited on the MT3 layer 1404 is about 2000 nm. A thin coating of diffusion barrier and adhesion layer is deposited on the top and bottom of the deposited metal of the MT2 layer 1402 and the MT3 layer 1404. A thin film of resistive metal alloy is deposited as heater HTR 1406 on the silicon structure etched from the SOI layer. An example of a resistive metal alloy is titanium nitride (TiN). The HTR 1406 can be used to heat the silicon photonics device chip. The heater HTR 1406 can also be used to modify the refractive index of a waveguide structure useful for the operation of phase shifters and optical switches. The distance between the top of the MT2 layer 1402 and the bottom of the MT3 layer 1404 is about 800 nm. An opening can be etched in the oxide layer 1408 directly above the MT3 layer 1404 to a depth of about 200 nm to form a contact to the silicon photonics device chip.

[0054] 15, a shallow trench DT_OX 1502 is formed in the BOX layer 206 and a deep trench DT_SI 1504 is formed in the substrate member 204. The formation of the shallow trench DT_OX 1502 removes the oxide layer 1408 and the BOX layer 206 down to the substrate member 204. The depth of the DT_SI 1504 is approximately 150 μm.

[0055] As shown in FIG. 16, an undercut etch is performed to release the suspended structures.

[0056] The backside of the SOI wafer 300 is polished to optical quality, as shown in Figure 17. The thickness of the substrate member or handle 204 is about 600 μm after the SOI wafer 300 is back-polished.

[0057] The schematic diagram above is a portion of an integrated circuit chip design. The chip design is generated in a graphical computer programming language and stored on a computer-readable storage medium (e.g., a disk, tape, physical hard drive, or a virtual hard drive such as a storage access network). If the designer does not manufacture the chip or fabricate the photolithography masks used in chip fabrication, the designer transmits the resulting design directly or indirectly to such an entity by physical means (e.g., providing a copy of the computer-readable storage medium storing the design) or electronically (e.g., over the Internet). The stored design is generally converted into a suitable format (e.g., GDSII) for fabrication of a photolithography mask that contains several copies of the chip design to be formed on a wafer. The photolithography mask is used to define the areas of the wafer (and / or layers thereon) to be etched or processed.

[0058] The foregoing detailed description of the present disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments have been selected to best explain the principles of the present disclosure and its practical application, so that those skilled in the art may best utilize the present disclosure in various implementations and various modifications suited to the particular use contemplated. The scope of the present disclosure is intended to be defined by the claims appended hereto. Although one embodiment of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims. For example, it will be readily apparent to those skilled in the art that many of the features, functions, processes, and materials described herein can be modified within the scope of the present disclosure. Moreover, the scope of the present disclosure is not intended to be limited to the particular implementations of the processes, machines, manufacture, compositions of matter, means, methods and steps described herein. Those skilled in the art will readily recognize from the description of the present disclosure, now existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same functions, and may be utilized by the present disclosure to achieve substantially the same results as the corresponding implementations described herein. Accordingly, it is intended that the appended claims include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. 1. A method for manufacturing a silicon photonics device, the method comprising: obtaining a substrate member including a silicon-on-insulator (SOI) layer and forming a silicon structure in the SOI layer on the substrate member; forming a first dielectric structure and a second dielectric structure on the silicon structure; disposing a first oxide layer over the first dielectric structure and the second dielectric structure; forming a third dielectric structure on the first oxide layer and the second dielectric structure; forming a metal layer over the first oxide layer and the first dielectric structure; forming an adhesion layer over the metal layer, the adhesion layer configured to act as a diffusion barrier and to adhere to the metal layer.

2. The method of claim 1 , wherein the silicon structure is a lattice.

3. The step of forming a first dielectric structure includes: disposing a first layer of an insulating compound over the silicon structure; and e.g. etching the first layer of insulating compound to form the first dielectric structure.

4. disposing a second layer of insulating compound on a bottom surface of the substrate member prior to etching the first layer of insulating compound; 4. The method of claim 3, further comprising the step of removing the second layer of insulator compound disposed on a bottom surface of the substrate member after forming the first dielectric structure.

5. The first and second layers of the insulating compound are made of silicon nitride (Si ３ N ４ 5. The method of claim 4, wherein the metal is selected from the group consisting of silicon.

6. 5. The method of claim 4, wherein the steps of disposing the first layer of insulating compound on the silicon structure and disposing the second layer of insulating compound on the bottom surface of the substrate member are performed by one of a low pressure chemical vapor deposition (LPCVD) process and a plasma enhanced chemical vapor deposition (PECVD) process.

7. The method of claim 1 , wherein the adhesion layer on the metal layer forms a reflective mirror structure.

8. The method of claim 7 , wherein the first dielectric structure and the second dielectric structure are coplanar with each other.

9. The method of claim 8, further comprising the steps of: forming the third dielectric structure on the first oxide layer and the second dielectric structure; disposing a second oxide layer over the first oxide layer and the second dielectric structure; etching an opening in the first oxide layer and the second oxide layer over the second dielectric structure; and forming the third dielectric structure on the second dielectric structure in the opening.

10. The method of claim 1 , wherein the metal layer is selected from the group consisting of aluminum, gold, silver and copper.

11. 2. The method of claim 1, wherein the adhesion layer is selected from the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride.

12. forming a second silicon structure on the SOI layer of the substrate member; doping portions of the second silicon structure to form a photodiode; 2. The method of claim 1, further comprising forming a metal contact for said photodiode on a doped portion of said second silicon structure.

13. forming a second silicon structure in the SOI layer on the substrate member; forming a second adhesion layer on the second silicon structure, the second adhesion layer configured to act as a diffusion barrier and to adhere to the second silicon structure; forming a second metal layer on the second adhesion layer and the second silicon structure; 10. The method of claim 1, further comprising: forming a third adhesion layer over the second metal layer, the third adhesion layer configured to act as a diffusion barrier and to adhere to the second metal layer.

14. The method of claim 1 further comprising disposing a resistive metal alloy heater film on the silicon structure.

15. A method for manufacturing a silicon photonics device, the method comprising: obtaining a substrate member including a silicon-on-insulator (SOI) layer and forming a first silicon structure in the SOI layer coupled to the substrate member; forming a first oxide layer on the first silicon structure; forming a metal layer over the first oxide layer and the first silicon structure; forming an adhesion layer on the metal layer, the adhesion layer configured to act as a diffusion barrier and to adhere to the metal layer, the adhesion layer and the metal layer forming a reflective mirror structure in the silicon photonics device.

16. A method for manufacturing a semiconductor device comprising the steps of: forming a first dielectric structure on said first oxide layer and said first silicon structure; 16. The method of claim 15, further comprising: forming a second oxide layer on the first dielectric structure, the second oxide layer being formed between the first oxide layer and the metal layer.

17. The method of claim 1, further comprising the steps of: chemically and mechanically polishing the first oxide layer; 17. The method of claim 16, further comprising forming a spacer between the first silicon structure and the first dielectric structure.

18. A method for manufacturing a semiconductor device comprising the steps of: forming a second silicon structure on the first oxide layer, the second oxide layer being formed on the second silicon structure; and 17. The method of claim 16, further comprising: forming a third silicon structure on the second silicon structure and the second oxide layer.

19. The method of claim 18, wherein the first dielectric structure and the second silicon structure are coplanar with each other.

20. The step of forming the first dielectric structure on the first oxide layer and the first silicon structure, comprising: forming a first layer of an insulating compound on the first oxide layer; etching the first layer of insulating compound down to the first oxide layer to form the first dielectric structure on the first silicon structure; 17. The method of claim 16, comprising:

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