Technique for accessing non-volatile memory using deck offsets - Patents.com

Abstract

To provide deck offset techniques for multi-deck non-volatile memory that reduces an average raw bit error rate (RBER) for a memory system.SOLUTION: Deck offset can enable accessing different physical decks for the same input deck address. In one example in a system with multiple memory components, different physical decks are accessed across multiple memory components for the same logical deck address. In one example in a system with one memory component, different physical decks are accessed across multiple partitions of the same memory component.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This description relates generally to memory, and more particularly to techniques for accessing multi-deck non-volatile memory using deck offsets. [Background technology]

[0002] Memory resources have countless uses in electronic devices and other computing environments. There is a demand for memory technologies that can be scaled smaller than traditional memory devices. However, the continued drive toward smaller and more energy-efficient devices has posed scaling challenges to traditional memory devices. Three-dimensional memory devices have emerged as a solution to the scaling limitations of traditional memory devices. [Brief explanation of the drawings]

[0003] The following description includes illustrations with diagrams given with examples of implementations of embodiments of the present invention. The drawings should be understood by way of example, not by way of limitation. As used herein, reference to one or more "embodiments" should be understood as describing at least one implementation of the invention incorporating one or more particular features, structures, or characteristics. Thus, phrases such as "one embodiment" or "alternative embodiment" appearing herein are intended to describe various embodiments and implementations of the invention, and do not necessarily all refer to the same embodiment. However, they are also not necessarily mutually exclusive.

[0004] [Figure 1A] 1 is an example of a memory system including a non-volatile memory component.

[0005] [Figure 1B] 1 shows a top-down block diagram of a memory die having multiple partitions.

[0006] [Figure 1C]FIG. 1 shows a block diagram illustrating a multi-deck memory die.

[0007] [Figure 2] 1 shows an example block diagram of a portion of a cross-point memory array.

[0008] [Figure 3] An example of a codeword is shown below.

[0009] [Figure 4A] 1 illustrates different electrical distances between memory cells and drivers in an exemplary tile architecture.

[0010] [Figure 4B] 1 illustrates different electrical distances between memory cells and drivers in an exemplary tile architecture.

[0011] [Figure 5A] 10 is a table showing access by die offset. [Figure 5B] 10 is a table showing accesses independent of die offsets.

[0012] [Figure 6] 10 is a graph showing an example of electrical distances that die offsets are possible.

[0013] [Figure 7A] FIG. 1 is a block diagram illustrating an example of a memory system implementing a deck offset feature.

[0014] [Figure 7B] 1 is an example truth table for a deck offset feature in a system with multiple media components.

[0015] [Figure 7C] 10 is a table showing examples of an eight-component memory system with and without deck offset.

[0016] [Figure 8A] 1 is a table illustrating the deck offset and die offset access possible in a system with multiple media components.

[0017] [Figure 8B] 10 is a graph showing an example of how deck offset improves the average raw bit error rate for a memory system having multiple memory components.

[0018] [Figure 9] 1 is a table showing examples of single component deck offset techniques.

[0019] [Figure 10A] FIG. 1 is a flow diagram illustrating a deck offset technique. [Figure 10B] FIG. 1 is a flow diagram illustrating a deck offset technique. [Figure 10C] FIG. 1 is a flow diagram illustrating a deck offset technique. [Figure 10D] FIG. 1 is a flow diagram illustrating a deck offset technique.

[0020] [Figure 11] FIG. 1 is a block diagram of a system that may implement deck offset techniques, according to examples described herein.

[0021] [Figure 12] 1 provides an exemplary illustration of a computing system in which deck offset techniques may be implemented according to examples described herein.

[0022] A description of specific details and example implementations follows, including illustrations of the figures, which may illustrate some or all of the embodiments described below, as well as descriptions of other possible embodiments or implementations of the inventive concepts presented herein. DETAILED DESCRIPTION OF THE INVENTION

[0023] SUMMARY Techniques are described herein for accessing multi-deck non-volatile memory with deck offsets in a manner that allows for effective raw bit error rate (RBER) reduction.

[0024] Various memory and storage technologies include multiple decks or layers of memory cells as part of a vertical address space. Additional decks or layers of memory cells result in larger memory size for the same die size. Memories with multiple decks or layers (e.g., vertically) are commonly referred to as three-dimensional (3D). Examples of multi-deck or multi-layer memories include multi-deck cross-point memory and 3D NAND memory. Different memory technologies have adopted different terminology. For example, a deck in a cross-point memory device generally refers to a layer of memory cell stack that can be individually addressed. In contrast, a 3D NAND memory device is commonly said to include a NAND array containing many layers, as opposed to a deck. In 3D NAND, a deck may refer to a subset of layers of memory cells (e.g., two decks of X layers to effectively provide a 2X-layer NAND device). The term "deck" will be used throughout this disclosure. However, layer, tier, or other terms may also refer to a layer of memory cells.

[0025] Multi-deck memories typically experience differences in electrical characteristics across decks. For example, different decks may have different RBERs. A typical memory access request results in a single deck being accessed. Therefore, depending on the deck being accessed, the memory access may experience significantly different RBERs. For example, a memory access to one deck may experience a lower-than-average RBER, while a memory access to another deck may experience an RBER that is above average, perhaps even beyond acceptable limits. By distributing memory accesses per codeword across different physical addresses across multiple decks, the RBER can be averaged across decks and reduced at the system level.

[0026] 1A is an example of a memory system 104 that includes non-volatile memory components. Non-volatile memory components are used across a wide variety of systems, including storage-class and memory-class systems. For example, non-volatile memory such as crosspoint memory and 3D NAND memory can be included in solid-state drives (SSDs) to provide storage or in dual in-line memory modules (DIMMs) to provide memory for servers or consumer systems.

[0027] Memory system 104 illustrates how a memory system can be designed using media packages and components. System 104 includes one or more media packages (shown in FIG. 1A as P media packages). Each media package includes one or more media components (shown in FIG. 1A as U memory components). A media component may be or may include a memory die. In one example, each die is partitioned to include multiple partitions. A partition includes a group or unit of memory cells. In one example, the partitions can be processed (read or written) simultaneously to service a given memory access request. In one such example, a partition includes multiple cells or tiles that are physically adjacent to one another.

[0028] FIG. 1B shows a top-down block diagram of a memory die having multiple partitions. The memory die 103 shows k partitions 108. The die also includes peripheral and I / O (input / output) circuitry 106. The peripheral and I / O circuitry typically includes CMOS circuitry that enables operation and control of the partitions 108 of the die 103. The partitions 108 are shown as tiled blocks spanning the length of the die 103; however, the partitions may be configured in various shapes, sizes, or orientations. One or more partitions may be accessed simultaneously. The number of bits accessed simultaneously depends on the design of the memory system 104.

[0029] As briefly mentioned above, modern memory dies typically have multiple layers or decks of memory cells arranged vertically. Figure 1C shows a block diagram of a multi-deck memory die. The die shown in Figure 1C includes n decks 110. Depending on the memory technology, the number of decks or layers of memory cells can be, for example, two, four, eight, or even tens or hundreds. Figure 2 shows an example block diagram of a portion of a cross-point memory array with four decks (decks 0, 1, 2, and 3). Each cross-point memory deck includes a cross-point array. The cross-point array includes a stack of materials, including a memory material and a conductive layer, which are patterned to form an array of memory cells 202 with conductive access lines (e.g., word lines 210 and bit lines 212). The memory cells include a material capable of being in two or more stable states to store a logical value. In one example, the memory cells 202 include a phase-change material and / or a chalcogenide material. However, deck offset technology is not limited to a particular memory material. The word lines 210 and bit lines 212 are typically patterned so that the word lines intersect the bit lines at right angles, creating a grid pattern or "cross points." Cross points are intersections between bit lines, word lines, and active material (e.g., selector and / or storage material). Memory cells are located at the intersections of the bit lines and word lines. Thus, in the example shown in FIG. 2, each deck includes memory cells 202, word lines 210, and bit lines 212. Electrically insulating material 204 separates the access lines 210 on the bottom deck from the bit line sockets 206 and word line sockets 208, which couple the memory cells 202 with access and control circuitry for operation of the memory array. The cross point memory array of FIG. 2 is an example of a multi-deck memory; however, the techniques described herein are not limited to cross point memory, but any memory device having multiple layers or decks of memory cells.

[0030] Thus, a memory system may be designed to have one or more packages, each of which may contain one or more memory dies. Each memory die may contain multiple partitions and multiple decks. Depending on the design of the memory system, memory accesses may have various levels of parallelism in accessing packages, dies, partitions, and decks. In one example, a bit simultaneous access by a memory system in a single access is referred to as a codeword.

[0031] An example codeword is shown in FIG. 3. FIG. 3 shows an example memory system having U components or dies 103-1 through 103-U. Each component includes k partitions. Components 103-1 through 103-U may include one or more packages. In the example shown, two partitions from each component are accessed in a single memory access request (e.g., a read or write request from a host). Thus, assuming each partition is x bits in size, the codeword size is (x × 2 × U (x × 2 × U)) bits. While FIG. 3 shows a memory system with multiple components, other examples may include a single component. Also, in other examples, a single memory access may include access to fewer (e.g., one) or more (e.g., more than two) partitions. In examples where each access includes accessing fewer than all partitions, the accessed partitions may be the same for each component or may be different partitions for different components.

[0032] Some memory systems implement address offset or die offset to spread accesses across different physical addresses (e.g., different physical partitions) within the same deck for the same logical address. Address offset includes accesses to different physical addresses within the same deck for different accesses for the same logical address, which may be on the same media component or across multiple different media components. Die offset is similar to address offset, but includes accesses to different physical addresses within the same deck for different accesses for the same logical address across multiple different media components. Figure 3 shows an example of a codeword 302 accessed in a system in which die offset is implemented. In particular, Figure 3 shows an example in which a memory access includes accesses to partitions 0 and 1 of component 1 and partitions k-2 and k-1 of component U for a given access.

[0033] Die offset is one way to address the different electrical characteristics and features that may be observed for different memory cells located at different physical locations in the array. For example, the location of a memory cell relative to word line and bit line drivers can affect the likelihood and severity of errors resulting from write and read operations. The distance of a memory cell from a driver (e.g., bit line and word line driver) in terms of resistance is referred to as the electrical distance. Figures 4A and 4B show different electrical distances between memory cells and drivers in an exemplary tile architecture.

[0034] FIG. 4A shows a top-down view of a tile architecture that may have one or more word line drivers and one or more bit line drivers. The example of FIG. 4A shows the location of a single memory cell 402A relative to the drivers. Memory cell 402A is accessed by the driver through a word line decoder socket 412A and a bit line decoder socket 410A. In one example, the socket includes conductive interconnects (e.g., vias) in the array to connect metal layers of the CMOS circuitry to metal layers of the memory array. Memory cell 402A is close to the word line driver and bit line driver in terms of the number of memory cells separating cell 402A from sockets 410A and 412A. For example, FIG. 4A shows an example in which memory cell 402A is separated from word line decoder socket 412A by zero memory cells and from bit line decoder socket 410A by X memory cells. Thus, memory cell 402A is separated from the sockets by a total distance of X memory cells. The number of cells can be converted to distance and therefore resistance (depending on the thickness of the WL and BL). In the example shown in Figure 4A, X is a relatively small number, and therefore the electrical distance between memory cell 402A and sockets 410A and 412A is relatively small (referred to as short electrical distance "ED"). On an electrical distance scale of 0-10, the electrical distance between memory cell 402A and sockets 410A and 412A may be said to be 1 (ED1).

[0035] The example of FIG. 4B shows a different location of memory cell 402B relative to the driver. Memory cell 402B is accessed by the driver via word line decoder socket 412B and bit line decoder socket 410B. Compared to memory cell 402A of FIG. 4A, memory cell 402B is farther from decoder sockets 410B and 412B in terms of the number of memory cells separating cell 402B from sockets 410B and 412B. In the example shown in FIG. 4B, memory cell 402B is separated from the word line decoder socket by Y cells and from the bit line decoder socket by Z cells. Thus, memory cell 402B is separated from sockets 410B and 412B by Y+Z memory cells. In the illustrated example, Y+Z is a relatively large number, and therefore, the electrical distance between memory cell 402B and sockets 410B and 412B is greater (referred to as far electrical distance "ED"). On an electrical distance scale of 0-10, the electrical distance between memory cell 402B and sockets 410B and 412B may be said to be 10 (ED10).

[0036] As briefly mentioned above, the electrical distance of a memory cell from a driver can affect the likelihood and severity of errors resulting from write and read operations. In one example, the ideal electrical distance may be between a near ED and a far ED. For example, if ED1 is the shortest electrical distance and ED10 is the farthest electrical distance, a memory cell with an electrical distance of ED5 may exhibit more desirable electrical characteristics than memory cells with near or far electrical distances. For example, memory cells with near EDs experience higher average errors associated with read disturb, while memory cells with far EDs experience higher average errors associated with write disturb. Thus, for a given access, if memory cells with similar electrical distances are accessed from each component, the average electrical distance for the access may trend toward the minimum ED or maximum ED (e.g., near or far ED).

[0037] Address offset and die offset can move the average ED closer to the desired ED by accessing different physical locations (and therefore different EDs) for accesses to the same logical address. Address offset can be used within a single component, while die offset spans multiple components. For example, address offset can enable memory accesses to the same logical address to access different physical addresses (e.g., different physical partitions). Thus, the benefit of address offset is that it can improve the average ED for multiple accesses. In contrast, the benefit of die offset is that a package with multiple components can be viewed as a single access. For example, each die can have a die offset (e.g., 0, 2, 4, 8, etc.). Die offset causes accesses to the same logical address to access different physical addresses on the die.

[0038] 5A and 5B are tables illustrating access with and without a die offset. FIG. 5A shows an example of access without a die offset. FIG. 5B shows an example of access with a die offset. Both FIGS. 5A and 5B show an example of memory access to address 0x0h in a memory system where a package includes eight media components (e.g., media components 1-8). The eight media components are in one or more (e.g., two, four, or eight) media packages. For example, a memory system having eight media components could include eight single-die packages (SDPs), four dual-die packages (DDPs), two quad-die packages (QDPs), or one eight-die package (ODP). While the examples in FIGS. 5A and 5B show eight media components, the die offset may apply to other numbers of dies (e.g., two or more media components).

[0039] 5A and 5B show a memory access request targeting Deck 0, indicated by the "0's" in the Deck row of the tables in FIGS. 5A and 5B. In this example, each memory component is accessed to service the memory access request. For each media component, the tables show two accesses (Access 0 and Access 1), which target Partitions 0 and 1, respectively. A memory access request targets a partition if, for example, the access request includes a logical address that targets a partition. For example, with reference to FIG. 3, codeword 302 would include x bits from Access 0 and 1 (e.g., Partitions 0 and 1). In the example of FIG. 5A, these partitions are accessed simultaneously for a single memory access request; however, a memory system may be designed and configured to access fewer than or more than two partitions per media component for a single memory access request.

[0040] In FIG. 5A, the die offset is disabled, as indicated by the "0's" in the die offset row of the table. Therefore, the partition accessed is the same partition targeted by the memory access request. For example, access 0 targets partition 0, and therefore partition 0 is the physical partition being accessed. Access 1 targets partition 1, and therefore partition 1 is the physical partition being accessed. Each partition is a specific electrical distance from the driver. In the example shown in FIG. 5A, partition 0 has an ED of 4 and partition 1 has an ED of 3. Therefore, the average ED of a memory access request is 3.5.

[0041] In contrast, die offset is enabled in the example shown in FIG. 5B , indicated by the “1” in the die offset row of the table. Therefore, the accessed partition is based on the target partition and die offset for the media component. In the example shown, the partitions accessed for accesses 0 and 1 for media component 1 are the same partitions targeted. Therefore, partitions 0 and 1 are the physical partitions accessed for component 1. However, the partitions accessed for the other media components (2-8) are offset, and therefore the accessed partitions are not the target partitions. For example, for media component 2, partition 2 is accessed for access 0, and partition 3 is accessed for access 1. For media component 3, partition 4 is accessed for access 0, partition 5 is accessed for access 1, and so on. Because more partitions are accessed at various electrical distances from the driver, the average ED is different in the example with die offset compared to the example without die offset. In the example shown in FIG. 5B , the average ED is 5.375, which may approach the desired die offset.

[0042] FIG. 6 is a graph illustrating an example of the electrical distances that die offsets can provide. In the example of FIG. 6, consider a memory system having two single-die packages for two media components. In this example, the die offsets may be set to a value between 0x0h (no offset) and some non-zero maximum offset (max offset), and the possible die offset values ​​may be based on the number of partitions per component and the number of partitions accessed for a single memory access request. In the example of FIG. 6, consider a case where one media component has a die offset of 0x0h while the other media component has a non-zero die offset. In this example, if the logical address is 0x0h (e.g., x=y=0x0h), then partitions 1 and 2 would be accessed when there is no die offset. Therefore, for a component with a die offset of 0x0h, partitions 1 and 2 are accessed. As shown in FIG. 6, partitions 1 and 2 have electrical distances of 4 and 3, as indicated by data points 602-1 and 602-2, respectively.

[0043] Without the die offset, partitions 1 and 2 would be accessed for both media components, resulting in an average ED of 3.5 for memory accesses. However, in the example shown in FIG. 6, the second component has a non-zero die offset. A non-zero die offset would result in partitions other than 1 and 2 (e.g., partitions 3 and 4) being accessed. In the illustrated example, partitions 3 and 4 have EDs of 7 and 8, respectively, as shown by data points 604-1 and 604-2. Because different partitions are accessed for the second component, the average ED for memory accesses is 5.5, as shown by line 604. Assuming a range of possible EDs of 10, the die offset allows for an average ED close to the ideal average ED.

[0044] In addition to variations in ED across partitions on the same deck, variations due to electrical characteristics or features across different decks may also occur. For example, raw bit error rates (RBER) may differ significantly for the same electrical distance across different decks. Deck offset techniques may enable distributing memory accesses across decks to lower the average RBER. Deck offset may be implemented in a single-die memory system or a memory system with multiple dies. In multi-die deck offset, deck offset across different media components may enable access to different physical addresses across multiple decks as a function of one logical address (e.g., a logical address including one logical deck address). In one such example, deck offset techniques include modifying an incoming deck address based on a user register and physically addressing different decks. In single-die deck offset, deck offset across different partitions on a single media component may enable distributing access across multiple decks.

[0045] FIG. 7A is a block diagram illustrating an example of a memory system implementing a deck offset feature. In the example shown in FIG. 7A, system 701 includes one or more media components 703-1 through 703-U. In one example, media components 703-1 through 703-U are non-volatile memory components. One or more media components 703-1 through 703-U are the same as or similar to media component 103 described above with respect to FIGS. 1A through 1C. The non-volatile memory component includes multiple decks. Each of the multiple decks includes an array of non-volatile memory cells. For example, each of media components 703-1 through 703-U includes multiple decks, such as those shown in FIG. 1C. Each deck includes one or more memory arrays (e.g., arrays 702-1 through 702-U). Each media component also includes circuitry (e.g., circuits 706-1 through 706-U) to receive memory access requests and access portions of the memory arrays. For example, each component may include input / output (I / O) circuitry to receive memory access requests and decoding and access circuitry to access the appropriate portion of the memory array based on the received address. In a memory system having one or more multi-deck memory components, the address may include a deck address that indicates which deck to access.

[0046] Unlike in conventional memory systems, where a given deck address results in the same deck being accessed for each memory component and each partition, system 701 implements a deck offset feature. The example of FIG. 7A includes a deck offset register for each component. In one example, such as multi-component deck offset, deck offset registers 704-1 through 704-U allow different physical decks to be accessed for a given logical deck address depending on the value stored in the deck offset register for the media component. The deck offset register includes one or more bits to indicate the target (e.g., offset) physical deck to be accessed for each input deck. The register may be a programmable user register (e.g., programmable via a mode register write command) or a read-only register. In other examples, deck offset may be implemented without a register, such as by fuses or hardwiring.

[0047] Whether or not a register is used to set the deck offset, the deck offset allows for distribution of accesses across different decks. For example, consider an example in which a memory access request is received in a memory system having multiple memory components. The memory access request includes a logical deck address that indicates which deck is targeted by the memory access request. The decode / access circuitry of each component accesses the physical deck based on the deck offset for each component. For example, a first deck of a first component may be accessed, and a second deck of a second component may be accessed in response to receiving a memory access request to the same logical deck.

[0048] FIG. 7B is an example truth table for a deck offset feature in a memory system having multiple memory components. The table in FIG. 7B shows an example of how an incoming deck address can be modified so that a different physical deck is accessed based on a deck offset register. In one example, each memory component in the memory system includes an independent deck offset register. The first two columns of the table indicate the value of the two-bit register. The first row indicates a value of "0x0" (Y deck bit = 0 and X deck bit = 0). In one example, "0x0" indicates there is no offset and the deck accessed will be the same as the input deck of the logical deck address. The last three rows indicate different deck offsets. For example, the second row indicates a deck offset of "0x1" (Y deck bit = 0 and X deck bit = 1). The third row indicates a deck offset of "0x3" (Y deck bit = 1 and X deck bit = 1).

[0049] The last four columns of the table in Figure 7B indicate the physical deck that will be accessed for a given input deck based on the register values. For example, if the input deck is deck 0 and the deck offset register is 0x0, the physical deck addressed will be deck 0. For example, if the input deck is 0 and the deck offset register is 0x1, the physical deck addressed will be deck 1. If the input deck is deck 0 and the deck offset register is 0x2, the physical deck addressed will be deck 3, etc. The table in Figure 7B shows one example of how the physical deck may be determined based on the input deck and the deck offset register; however, other mappings are possible.

[0050] FIG. 7C is a table illustrating an example of an eight-component memory system without deck offsets. The first column of the table in FIG. 7C shows the die number (dies 1-8). The example in FIG. 7C assumes that the input deck is deck 0. The second column of the table shows an example where deck offsets are either not implemented or not enabled. Therefore, the physical deck accessed is deck 0 for all dies. The third column of the table shows an example where deck offsets are implemented and enabled. Therefore, the physical deck accessed for a die varies depending on the die configuration. For example, physical deck 0 is accessed for dies 1 and 5 (no offset). physical deck 1 is accessed for dies 2 and 4. physical deck 3 is accessed for dies 3 and 5. physical deck 2 is accessed for dies 4 and 8. Therefore, different decks are accessed by different dies for the same logical deck address (i.e., the logical deck address for input deck 0). 7C, the number of non-volatile memory components in the memory system (e.g., 8) is a multiple of the number of decks in each of the non-volatile memory components (e.g., 4). In some examples, a memory system in which the number of components is a multiple of the number of decks may enable a greater reduction in average RBER than a memory system in which the number of components is not a multiple of the number of decks.

[0051] 8A is a table illustrating deck offset and die offset accesses allowed in a system having multiple components. The example of FIG. 8A illustrates memory access to address 0x0h (e.g., X address = 0x0h and Y address = 0x0h) in a memory system whose packages include eight media components (e.g., media components 1-8). The eight media components are in one or more (e.g., two, four, or eight) media packages. For example, a memory system with eight media components could include eight single-die packages (SDPs), four dual-die packages (DDPs), two quad-die packages (QDPs), or one eight-die package (ODP). Although the example in FIG. 8A illustrates eight media components, the deck offset may apply to other numbers of dies (e.g., two or more media components).

[0052] 8A shows a memory access request targeting deck 0, indicated by the "0's" in the target deck row of the table. However, because deck offsetting is enabled, the physical deck access for some media components is to a deck other than deck 0. For example, deck 1 is accessed for media components 2 and 6, deck 2 is accessed for media components 4 and 8, and deck 3 is accessed for media components 3 and 7.

[0053] In addition to the deck offset, the example in Figure 8A also shows a die offset. For each media component, the table shows two accesses (Access 0 and Access 1), targeting partitions 0 and 1, respectively. For media components 1-4, there is no die offset, so the accessed partition is the target partition. For media components 5-8, there is a die offset in addition to the deck offset, so the accessed partition for components 5-8 is different from the target partition (e.g., Partition 2 for Access 0, Partition 3 for Access 1).

[0054] Due to the die offset, the electrical distance for the partitions accessed for Access 0 and Access 1 is different for each component. Similar to FIG. 5B, the example shown in FIG. 8A has an average ED of 5.375. Thus, the same improvement in average ED can be realized as when using only die offset. However, the die offset can also enable an improvement in the average raw bit error rate for the memory system.

[0055] FIG. 8B is a graph showing an example of how deck offset can improve the average raw bit error rate for a memory system having more than one memory component. In the example of FIG. 8B, different decks exhibit different RBERs. The x-axis of FIG. 8B is deck number. In the example shown in FIG. 8B, there are four decks (deck 0, deck 1, deck 2, and deck 3). The y-axis is raw bit error rate (RBER). Lines 814-0 through 814-3 show the average RBER for each deck with address offset enabled but deck offset disabled. In this example, each deck exhibits a different average RBER. For example, deck 2 has a relatively high RBER (814-2), deck 3 has a relatively low RBER (814-3), and decks 0 and 1 have RBERs (814-0 and 814-1) that are between the RBERs of decks 2 and 3.

[0056] In one example, the RBER associated with electrical distance may differ for different decks, resulting in a different average RBER for different decks. For example, assuming each deck includes a partition that may have an electrical distance between ED1 and ED10, the RBER of ED1 on deck 3 is significantly lower than the RBER of ED1 on deck 2. Because the RBER varies for different decks, some decks may exhibit unacceptably high error rates. In the example of FIG. 8B, deck 2 may exhibit an error rate that exceeds acceptable limits, while other decks may have acceptable error rates. Thus, although address or die offset may improve the average electrical distance and error rate for a given deck, some decks may still have undesirable average electrical distances and unacceptably high error rates.

[0057] Using deck offset, such as that described above, can enable an improvement in the average RBER while maintaining a desired ED across the decks. For example, dotted line 812 in FIG. 8B shows the average RBER across the decks for a memory system with deck offset enabled. As evident in FIG. 8B, enabling deck offset can result in an average RBER that is lower than the highest deck error rate, and thus bring a deck that might otherwise have an unacceptably high error rate into an acceptable range.

[0058] The deck offset technique described above allows access to multiple decks per codeword when the system has more than one media component. Therefore, the reduction in average RBER that can be achieved by the multi-component deck offset technique is ineffective for memory systems with a single media component. However, the single-component deck offset technique allows access to different decks within the same media component across different partitions.

[0059] FIG. 9 is a table illustrating an example of a single-component deck offset technique. The example of FIG. 9 is for a memory system having a single component with 32 partitions (partitions 0-31). The first column of the table indicates the access or partition. In this example, all 32 partitions are accessed for a given memory access request. The second and third columns indicate the electrical distance (ED) and deck when address and die offsets are possible, but there is no deck offset. As explained above, each partition has a specific ED, which is shown in the second column. Because there is no deck offset, the physical deck accessed is the same as the input deck. In the example shown, input deck = physical deck = deck 0.

[0060] The third and fourth columns show the EDs and decks when single-component deck offset is enabled. As evident in the table of FIG. 9 , memory cell locations that are identical in terms of electrical distance are accessed only on different decks. For example, partition 0 is accessed on deck 0, partition 1 is accessed on deck 1, partition 2 is accessed on deck 3, and so on. Note that in the illustrated example, there are four decks, and therefore the deck offset is repeated every four partitions. For example, partition 0 and partition 4 are accessed from the same deck. Similarly, partitions 1 and 5 are accessed from the same deck. In the illustrated example, this stepping is repeated for all partitions. In one such example, the maximum RBER reduction can be achieved when the number of accesses (partitions) is a multiple of the total number of decks. Other examples may include non-repeating deck offsets (e.g., the deck offset assigned to partitions 0-3 may be different from the deck offset assigned to partitions 4-7). In one example, the deck offset feature may be enabled or disabled (e.g., by a register). The deck offset (eg, which physical deck is accessed for a given input deck for each partition) is hardwired (eg, by a register) or configurable.

[0061] When deck offset is possible, ED is the same because the same physical location is accessed in terms of how far the memory cells are from the word line and bit line drivers. However, in addition to achieving improved ED through address and die offset, RBER can be reduced by distributing accesses across all decks. Thus, because accesses within the same media component will be distributed across different physical locations (including different physical decks), one can have a minimum of one media component and still expect to see a reduction in RBER. This allows the design of a system that uses deck offset features while having a minimum of one media component.

[0062] Both multi-component and single-component deck offset techniques can enable RBER reduction in systems with more than one deck. Both deck offset techniques allow access to different physical decks for the same input deck address. The deck offset techniques are effective for memory systems with different numbers of partitions per media component, different numbers of bit operations per given access (or partition), different numbers of packages in the system, and different numbers of components per package. Existing techniques limit access to the same deck for the same logical address as a subset of all accesses within a codeword. Unlike existing techniques, the deck offset technique allows access to different physical locations of cells across multiple different decks for the same logical address.

[0063] Figures 10A-10D are flow diagrams illustrating deck offset techniques. The methods of Figures 10A-10D can be performed by hardware (e.g., circuitry), firmware, software, or a combination of hardware, firmware, and software.

[0064] 10A is a flow diagram illustrating a deck offset technique that can be implemented in a single-component or multi-component system. For example, referring to FIG. 1A, method 1000A can be applied to a memory system 104 having one or more media components 103. Each media component includes multiple decks. For example, referring to FIG. 1C, each of the one or more media components of the memory system includes multiple decks 110. Each deck includes non-volatile memory cells that can be organized into one or more tiles, arrays, or partitions.

[0065] The memory system receives a memory access request at 1002. For example, a processor (or other device that generates memory access requests) sends a memory access request to the memory system. The memory access request may be, for example, a read or write / program request. In examples where the memory system includes cross-point memory components, the write request may be a set or reset request. Input / output (I / O) circuits at the memory system level, package level, and component level receive signals responsive to the memory access request. The memory access request includes a logical address of a memory cell to be accessed by the request. In memory systems with multi-deck components, the logical address includes a logical deck address that identifies which deck the request targets.

[0066] The physical deck accessed depends on whether the deck offset feature is implemented and / or enabled. Some memory systems may always have deck offset on or off, while other systems may include an option to enable or disable the deck offset feature (e.g., via a deck offset enable / disable register). If deck offset is disabled and 1004 branches NO, then at 1005 the physical deck accessed is the same as the input deck (e.g., the same deck targeted by the logical address). If deck offset is enabled and 1004 branches YES, circuitry on the component determines which deck to access in response to a request to the input deck. The mapping of logical deck addresses to physical decks is configurable (e.g., via one or more registers) or hardwired. If the setting indicates there is no deck offset (e.g., deck offset = 0x0) and 1008 branches YES, then at 1009 the physical deck accessed is the same as the input deck.

[0067] If the settings indicate that a deck offset exists (e.g., the deck offset is something other than 0x0), a deck other than the input deck is accessed at 1010. The deck offset may be based on a component number (e.g., in a multi-component deck offset) or may be based on a target partition (e.g., a single component deck offset).

[0068] FIG. 10B is a flow diagram illustrating an example of a multi-component deck offset technique. Method 1000B may be implemented in a system having multiple media components. For example, referring to FIG. 1A, the method may be implemented in a memory system 104 having two or more media components 103. The two or more media components may be in one or more packages 102. Method 1000B begins at 1022 with receiving a memory access request to a deck. If deck offset is not enabled and 1024 branches to NO, at 1025, for all media components, the physical deck accessed is the input deck. If deck offset is enabled and 1024 branches to YES, different decks may be accessed across different dies, depending on the configuration. In the example of FIG. 10B, the method includes accessing the input deck of a first component (e.g., a component with a deck offset set to 0x0h) at 1026. At 1028, a deck other than the input deck is accessed for a second component (e.g., a component with a deck offset set to a non-zero value).

[0069] FIG. 10C is a flow diagram illustrating an example of a deck offset technique for a single component. Method 1000C of FIG. 10C may be implemented in a system having a single component. For example, referring to FIG. 1A, method 1000C may be implemented by memory system 104 having a single component 103. Method 1000C includes accessing different decks across different partitions in the same component. Method 1000C begins with receiving a memory access request at 1042. If deck offset is disabled and 1044 branches NO, then at 1045, for all partitions, the physical deck accessed will be the same as the input deck. If deck offset is enabled and 1044 branches YES, then the method includes accessing different decks for different partitions. In the example shown in FIG. 10C, a first partition is accessed on the first deck at 1046, and a second partition is accessed from the second deck at 1048. Thus, accesses may be distributed across different decks within the same component.

[0070] 10D is a flow diagram illustrating an example of a method for determining a deck offset setting. Method 1000D may be performed by firmware. In one example, method 1000D is performed during a test and configuration process (e.g., after manufacturing but before the memory system is used in the field). In another example, the method may also be performed in the field (e.g., by a user).

[0071] Method 1000D begins by disabling deck offset (or not enabling the feature if it is disabled by default) at 1062. An average RBER is then determined at 1064 by running a test that exercises the memory system and measuring the RBER resulting from the test. After measuring the RBER with the deck offset feature disabled, the method includes enabling the deck offset feature at 1066.

[0072] After enabling the deck offset feature, different combinations of deck offset settings are tested. For example, the deck offset setting may be set or adjusted at 1066. Setting or adjusting the deck offset setting may include, for example, setting a register to a particular value to reflect the desired deck offset. The RBER is then tested with the new settings at 1070. If there are additional combinations of settings to test, 1072 branches YES and the method continues adjusting settings and measuring RBER at 1068 and 1070. Once the desired combination of settings has been tested, 1072 branches NO and the method includes determining the deck offset setting that results in the lowest average RBER for the memory system. The memory system is configured with the deck offset setting for the lowest RBER at 1074.

[0073] FIG. 11 is a block diagram of a system that may implement deck offset techniques according to examples described herein.

[0074] The system 1100 includes components of a memory subsystem having one or more memory components 1120. In one example, the memory component 1120 is part of a memory system that provides random access memory (RAM) for storage and provides data in response to operations of the processor 1110. The system 1100 receives memory access requests from a host or processor 1110, which performs operations based on or generates data stored in the memory 1120. The processor 1110 may be or include a host processor, a central processing unit (CPU), a microcontroller or microprocessor, a graphics processor, a peripheral processor, an application-specific processor, or other processor or accelerator, and may be single-core or multi-core.

[0075] The system 1100 includes a memory controller 1130, which represents logic that interfaces with the memory 1120 and manages access to data stored in the memory. In one example, the memory controller 1130 is integrated with the hardware of the processor 1110. In one example, the memory controller 1130 is stand-alone hardware separate from the processor 1110. The memory controller 1130 may be a separate circuit on a substrate that includes the processor. The memory controller 1130 may be a separate die or a chip integrated on a common substrate with the processor die (e.g., a system-on-chip (SoC)). In one example, the memory controller 1130 is an integrated memory controller (iMC), integrated as a circuit on the processor die. In one example, at least some of the memory 1120 may be included on an SoC with the memory controller 1130 and / or the processor 1110.

[0076] In the illustrated example, memory controller 1130 includes read / write logic 1134, which includes hardware that interfaces with memory 1120. Logic 1134 enables memory controller 1130 to generate read and write commands to service requests for data access generated by execution of instructions by processor 1110.

[0077] Memory resources or cache lines in memory 1120 are represented by memory cell array 1126, which may include a cross-point array or other non-volatile memory array. One or more memory components each include multiple decks. Memory 1120 includes interface 1124 (e.g., interface logic and / or circuitry) that controls access to memory device array 1126. Interface 1124 may include decode logic, including logic to address a particular row or column, bit line or word line, or otherwise address specific bits of data. Interface logic may apply deck offsets to access different decks according to examples described herein. Controller 1122 represents an on-die controller on memory component 1120 that controls its internal operations to execute commands received from memory controller 1130. For example, controller 1122 may control any of the timing, voltage levels, addressing, I / O (input / output) margining, scheduling, and error correction associated with memory 1120. A power supply 1140 is connected to the memory 1120 to provide one or more voltage rails for operation of the memory 1120 .

[0078] FIG. 12 provides an exemplary illustration of a computing system 1200 (e.g., a smartphone, a tablet computer, a laptop computer, a desktop computer, a server computer, etc.). As seen in FIG. 12, system 1200 may include one or more processors or processing units 1201. Processor 1201 may include one or more central processing units (CPUs), each of which may include, for example, multiple general-purpose processing cores. Processor 1201 may additionally or alternatively include one or more graphics processing units (GPUs) or other processing units. Processor 1201 may include memory management logic (e.g., a memory controller) and I / O control logic. Processor 1201 may be similar to or identical to processor 1110 of FIG. 11.

[0079] System 1200 also includes memory 1202 (e.g., system memory), non-volatile storage 1204, communication interface 1206, and other components 1208. The other components may include, for example, a display (e.g., touch screen, flat panel), a power source (e.g., battery and / or other power source), sensors, power management logic, or other components. Communication interface 1206 may include logic and / or functionality to support the communication interface. By way of example, communication interface 1206 may include one or more communication interfaces operating according to various communication protocols or standards for communicating over a direct communication link or channel or a network communication link or channel. Direct communication may occur using communication protocols or standards (including successors and variations) set forth in one or more industry standards, such as protocols or standards associated with the PCIe specification. Network communication may occur using communication protocols or standards such as those set forth in one or more Ethernet standards promulgated by the IEEE. For example, one such Ethernet standard may include IEEE 802.3. Network communications may also be performed in accordance with one or more OpenFlow specifications, such as the OpenFlow Switch Specification. Other examples of communication interfaces include, for example, a local wired point-to-point link (e.g., USB) interface, a wireless local area network (e.g., WiFi) interface, a wireless point-to-point link (e.g., Bluetooth®) interface, a global positioning system interface, and / or other interfaces.

[0080] The computing system may also include non-volatile storage 1204, which may be a mass storage component of the system. The non-volatile storage 1204 may be similar to or identical to the memory 1120 of FIG. 11 , described above. The non-volatile storage 1204 may include a byte- or block-addressable type of non-volatile memory having a cross-point memory structure. The non-volatile type of memory may also include other types of byte- or block-addressable non-volatile memory, such as, but not limited to, multi-threshold level NAND flash memory (e.g., 3D NAND flash memory), NOR flash memory, single- or multi-level phase-change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) incorporating memristor technology, spin-transfer torque MRAM (STT-MRAM), or any combination of the above. In one example, non-volatile storage 1204 may include mass storage comprised of one or more solid-state drives (SSDs), dual in-line memory modules (DIMMs), or other modules or drives. Memory 1202 and / or non-volatile storage may include deck offset features as described herein.

[0081] Various components described herein may be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. A component may be implemented as a software module, a hardware module, special purpose hardware (e.g., application specific hardware, application specific integrated circuit (ASIC), digital signal processor (DSP), etc.), an embedded controller, a hardwired circuit, etc.

[0082] In addition to what is described herein, various modifications may be made to the disclosed embodiments and implementations of the present invention without departing from the scope of the present invention. Therefore, the descriptions and examples herein should be construed in an illustrative, rather than a limiting, sense. The scope of the present invention should be determined solely by reference to the claims that follow.

Claims

1. A non-volatile memory component, comprising: a plurality of decks, each of the plurality of decks including an array of non-volatile memory cells; receiving a memory access request to access a first deck; accessing a second deck in response to the memory access request accessing the first deck The circuit, Equipped with the non-volatile memory component being a first non-volatile memory component in a memory system having at least a second non-volatile memory component; The second non-volatile memory component accesses a different deck than the first non-volatile memory component for the same logical deck address.

2. A register indicating which physical deck is to be accessed for the logical deck address of the memory access request. The non-volatile memory component of claim 1 further comprising:

3. Each non-volatile memory component in the memory system includes a register indicating which physical deck is to be accessed for the same logical deck address. A non-volatile memory component according to claim 1 or 2.

4. the number of non-volatile memory components in the memory system is a multiple of the number of decks in each of the non-volatile memory components; A non-volatile memory component according to any one of claims 1 to 3.

5. the circuitry is responsive to the memory access request to access a first partition of the first deck and a second partition of the second deck of a same non-volatile memory component. A non-volatile memory component according to any one of claims 1 to 4.

6. the circuitry is configured to access a third partition on a third deck and a fourth partition on a fourth deck of the same non-volatile memory component in response to the memory access request. The non-volatile memory component of claim 5 .

7. the number of partitions in the non-volatile memory component is a multiple of the number of decks in the non-volatile memory component; The non-volatile memory component of claim 6 .

8. the memory access request includes a logical address targeting a partition of the non-volatile memory component; the circuitry accesses a different physical partition than the partition targeted by the logical address. A non-volatile memory component according to any one of claims 1 to 7.

9. A register indicating which partition is the one accessing the partition targeted by the logical address The non-volatile memory component of claim 8 further comprising:

10. each of the plurality of decks includes a cross-point array of non-volatile memory cells; A non-volatile memory component according to any one of claims 1 to 9.

11. each of the plurality of decks includes a NAND array of non-volatile memory cells; A non-volatile memory component according to any one of claims 1 to 10.

12. a plurality of non-volatile memory components, each of the plurality of non-volatile memory components including a plurality of decks, each of the plurality of decks including an array of non-volatile memory cells; receiving a memory access request to the first deck; accessing the first deck of a first one of the plurality of non-volatile memory components in response to receiving the memory access request; accessing a second deck of a second one of the plurality of non-volatile memory components for the same logical deck address in response to receiving the memory access request; The circuit, A system comprising:

13. each of the plurality of non-volatile memory components including a register indicating which deck is to be accessed for the same logical deck address; The system of claim 12.

14. the number of non-volatile memory components in the system is a multiple of the number of decks in each of the plurality of non-volatile memory components; 14. A system according to claim 12 or 13.

15. a plurality of decks, each of the plurality of decks comprising a plurality of partitions of non-volatile memory cells; receiving a memory access request to the first deck; accessing a first partition of the first deck and a second partition of a second deck in response to the memory access request to the first deck; The circuit, A non-volatile memory component comprising:

16. the circuitry is configured to access a third partition on a third deck and a fourth partition on a fourth deck of the non-volatile memory component in response to the memory access request.

16. The non-volatile memory component of claim 15.

17. the number of partitions in the non-volatile memory component is a multiple of the number of decks in the non-volatile memory component; A non-volatile memory component according to claim 15 or 16.

18. the mapping from the first deck to the second deck is based on which of a plurality of partitions a memory access request targets. A non-volatile memory component according to any one of claims 15 to 17.

19. the memory access request includes a logical address targeting one or more of the partitions of the non-volatile memory component; the circuitry accesses one or more physical partitions different from the one or more partitions targeted by the logical address. A non-volatile memory component according to any one of claims 15 to 18.

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