Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device with improved junction reliability between electrodes and wires of semiconductor elements.SOLUTION: A semiconductor device includes a semiconductor element, a surface electrode formed on the semiconductor element, a wire bonded to the surface electrode, and a first resin covering the junction of the surface electrode and the wire, and the surface of the surface electrode includes a Ni layer. Preferably, the wire has a tensile strength of 80 MPa or more and the first resin has an elastic modulus of 5 GPa or more.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Background of this technical field is JP 2007-12831 A (Patent Document 1). Patent Document 1 describes a power semiconductor device in which a creeping portion where a metal circuit is not joined by an insulating substrate and a joining interface portion between a semiconductor element and a metal wire are coated with an electrically insulating resin that has a smaller thermal expansion coefficient, a larger Young's modulus, and a higher dielectric strength than a resin filled to ensure insulation of the entire module, and the thickness of the coated resin is shaped so that an inflection point of the coating resin in the cross-sectional direction of the wire is ¼ or less of the cross-sectional height of the wire. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-12831 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device equipped with a power semiconductor element, stress is repeatedly applied to the junctions between the electrodes of the semiconductor element and the wires during operation of the semiconductor device due to the difference in thermal expansion between the wires and the semiconductor element. This thermal stress can cause cracks in the electrodes or wires of the semiconductor element, which can lead to the destruction of the semiconductor device.

[0005] To address this issue, Patent Document 1 describes a semiconductor device in which the wire joint is reinforced by applying a liquid resin to the joint, thereby improving reliability. However, there is no description of the manufacturing issues and effects of improving the mechanical strength of the resin and wire to further improve reliability, and there is a problem that resin and wire with high mechanical strength cannot be used.

[0006] An object of the present invention is to provide a semiconductor device having improved bonding reliability between the electrodes of a semiconductor element and wires. [Means for solving the problem]

[0007] The semiconductor device of the present invention comprises a semiconductor element, a surface electrode formed on the semiconductor element, a wire bonded to the surface electrode, and a first resin covering the joint between the surface electrode and the wire, the surface of the surface electrode being a Ni layer, and a second resin having a lower elastic modulus than the first resin, the first resin being coated with the second resin, a wiring board supporting the semiconductor element, a wiring pattern formed on an upper surface of the wiring board, a bonding material bonding the wiring board and the semiconductor element, and a third resin covering at least one of the joint between the surface electrode and the wire, the semiconductor element, the bonding material, the wiring pattern, and the wiring board, wherein the elastic modulus of the third resin is configured to be lower than the elastic modulus of the first resin, and the semiconductor device comprises a base plate to which the wiring board is attached, a case attached to the base plate and covering the semiconductor element, the wire, and the wiring board, and a sealing resin for sealing the upper surface of the base plate and an area surrounded by the case.

[0008] The method for manufacturing a semiconductor device of the present invention includes a step of irradiating plasma to at least one of a surface electrode of a semiconductor element or a joint between the surface electrode and a wire, a step of joining the surface electrode of the semiconductor element and a wire, and a step of applying a solution having a first resin dissolved therein to the joint between the wire and the surface electrode, the step of irradiating plasma being performed before the step of applying the solution having the first resin dissolved therein, and is characterized in that in the step of applying the solution having the first resin dissolved therein, the solids ratio of the solution is 0.70 wt% or less. Effect of the Invention

[0009] According to the present invention, it is possible to provide a semiconductor device having improved bonding reliability between the electrodes of the semiconductor element and the wires. Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device in Example 1. FIG. [Diagram 2] 1 is a cross-sectional view showing a structure of a semiconductor device in Example 1. FIG. [Diagram 3] 1 is a schematic plan view showing a structure of a semiconductor device in Example 1. FIG. [Figure 4] 3 is a schematic cross-sectional view of a bonding portion between a surface electrode of a semiconductor element and a wire in a longitudinal direction of the wire in Example 1. FIG. [Diagram 5] 3 is a schematic cross-sectional view of a bonding portion between a surface electrode of a semiconductor element and a wire in a diameter direction of the wire in Example 1. FIG. [Figure 6] 3 is a schematic plan view of a bonding portion between a surface electrode and a wire of a semiconductor element in Example 1. FIG. [Figure 7] 4 is a schematic cross-sectional view in the length direction of the wire when coated with a second resin in Example 1. FIG. [Figure 8] 4 is a schematic cross-sectional view in a diameter direction of a wire when coated with a second resin in Example 1. FIG. [Figure 9]1 is a schematic cross-sectional view of a bonding portion between a surface electrode and a wire of a semiconductor element in Study Example 1. FIG. [Figure 10] 1 is a schematic diagram of a void present in a first resin in a wire bonding portion in Study Example 1. FIG. [Figure 11] 11 is a cross-sectional view showing a structure of a semiconductor device in Example 2. FIG. [Figure 12] 13 is a cross-sectional view showing a structure in which the portion coated with the third resin is changed in the semiconductor device in Example 2. FIG. [Figure 13] FIG. 1 is a diagram of Table 1 showing the relationship between the presence or absence of a plasma treatment step, the solids concentration of the first resin solution in the first resin application step, and the presence or absence of voids in the wire bonded portion. [Figure 14] FIG. 11 is a diagram of Table 2 showing the power cycle life when the surface electrode, the tensile strength of the wire, and the elastic modulus of the first resin are changed. [Figure 15] FIG. 11 is a diagram of Table 3 showing the power cycle life when the thickness of the first resin layer is changed. [Figure 16] 1 is a flow diagram showing a typical method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 10A to 10C are diagrams illustrating a manufacturing method of the semiconductor device according to the first embodiment according to a modified example. [Figure 18] FIG. 11 is a flow diagram showing a typical method for manufacturing a semiconductor device according to a second embodiment. [Figure 19] 10A to 10C are diagrams illustrating a manufacturing method of a semiconductor device according to a modified example of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the following embodiments, for convenience, when necessary, the embodiments will be divided into multiple sections or embodiments, but unless otherwise expressly stated, they are not unrelated to each other and one may be a partial or complete variation, detail, supplementary explanation, etc. of the other.

[0012] In addition, in the following embodiments, when referring to the number of elements (including the number, numerical values, quantities, ranges, etc.), unless specifically stated or clearly limited to a specific number in principle, the number is not limited to that specific number and may be more than or less than a specific number.

[0013] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless specifically stated otherwise or considered to be clearly essential in principle.

[0014] Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of components, etc., it is intended to include those that are substantially similar or similar to those shapes, etc., unless otherwise specified or considered to be obviously different in principle. The same applies to the above numerical values ​​and ranges.

[0015] In addition, in all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand. EXAMPLES

[0016] A first embodiment of the present invention will be described with reference to FIGS.

[0017] Fig. 1 and Fig. 2 are schematic cross-sectional views showing the structure of the semiconductor device in this embodiment, and Fig. 3 is a schematic plan view showing the structure of the semiconductor device in this embodiment. Fig. 1 is a schematic cross-sectional view seen from direction A in Fig. 3, and Fig. 2 is a schematic cross-sectional view seen from direction B in Fig. 3.

[0018] The semiconductor device 10 has a plurality of semiconductor elements 1, a wiring board 3 supporting the semiconductor elements 1, a base plate 4 supporting the wiring board 3, wires 6 electrically connecting the semiconductor elements 1 and the wiring board 3, and terminals 7 electrically connecting the wiring board 3 to an external device (not shown). The semiconductor elements 1 and the wiring board 3 are bonded via a bonding material 2. The wiring board 3 and the base plate 4 are bonded via a bonding material 5.

[0019] The semiconductor element 1 includes, but is not limited to, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a FWD (Free Wheeling Diode), an SBD (Schottky Barrier Diode), etc. The semiconductor element 1 is made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide, diamond, etc. The semiconductor element 1 includes a surface electrode 1a (not shown in FIG. 1 and FIG. 2).

[0020] The wiring board 3 is made of a ceramic plate such as alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc. A plurality of wiring patterns 3aa, 3ab, 3ac are formed on the upper surface 3a of the wiring board 3, and a wiring pattern 3ba is formed on the lower surface 3b of the wiring board 3. The wiring patterns 3aa, 3ab, 3ba are made of a material mainly composed of, for example, copper (Cu) or aluminum (Al).

[0021] 3, the wire 6 is a metal wire containing, for example, aluminum or copper, and electrically connects the surface electrode 1a of the semiconductor element 1 to the wiring patterns 3ab, 3ac on the upper surface 3a of the wiring board 3. The joint between the surface electrode 1a of the semiconductor element 1 and the wire 6 (hereinafter referred to as the wire joint) is covered with a first resin 31 (FIGS. 1 and 3).

[0022] For example, solder or sintered metal can be used for the bonding material 2. For example, solder mainly composed of tin (Sn) and solder mainly composed of lead (Pb) can be used as the solder. For example, sintered metal is copper (Cu) or silver (Ag).

[0023] The base plate 4 is made of, for example, aluminum (Al), Al-C, an aluminum alloy, Cu-C, Cu-Mo, a copper alloy, a composite material of aluminum and SiC, or a composite material of magnesium and SiC, and may be plated with nickel, gold, silver, or the like on its surface. The wiring board 3 is attached to the base plate 4 via a bonding material 5. The bonding material 5 may be, for example, solder. Heat generated from the semiconductor element 1 is transferred from the base plate 4 to the outside of the semiconductor device 10.

[0024] A case 8 that covers the semiconductor elements 1, the wires 6, and the wiring board 3 is attached to the base plate 4. The upper surface of the base plate 4 and the area surrounded by the case 8 are filled with, for example, a sealing resin 9. The resin 9 may be, for example, a gel-like resin material.

[0025] The features of the semiconductor device according to this embodiment will be described in detail below.

[0026] Figures 4 and 5 are schematic cross-sectional views of the bonding portion between the surface electrode 1a of the semiconductor element 1 and the wire 6 in this embodiment, and Figure 6 is a schematic plan view of the bonding portion between the surface electrode 1a of the semiconductor element 1 and the wire 6 in this embodiment. Note that Figure 4 is a schematic cross-sectional view seen from direction C in Figure 6, and Figure 5 is a schematic cross-sectional view seen from direction D in Figure 6.

[0027] In the semiconductor device of this embodiment, the tensile strength of the wire 6 is preferably 80 MPa or more. The higher the strength of the wire 6, the less likely it is that cracks will develop in the wire 6 even if thermal stress is repeatedly applied, and the reliability of the wire bonded portion is improved.

[0028] The wire bonding portion is coated with a first resin 31. In the semiconductor device of this embodiment, the elastic modulus of the first resin 31 is preferably 5 GPa or more. For example, a polyimide resin or a polyamide-imide resin can be used as the resin used for the first resin 31. In order to ensure the dielectric strength voltage of the semiconductor element 1, the content of impurities such as metal ions contained in the first resin 31 is preferably 1 ppm or less. In addition, the linear expansion coefficient of the first resin is preferably in the range of 15 to 60 ppm / °C.

[0029] The thickness of the first resin 31 in the wire length direction at the wire bonding portion is desirably 10 μm or more, particularly 20 μm or more. The thickness of the first resin 31 in the wire length direction at the wire bonding portion is the distance between the surface of the wire 6 in contact with the surface of the first resin 31 and the surface electrode 1a of the semiconductor element 1, which is indicated by t1 in FIG.

[0030] The thickness of the first resin 31 in the wire diameter direction at the wire bonding portion is desirably 10 μm or more. The thickness of the first resin 31 in the wire diameter direction at the wire bonding portion is the distance between the surface of the wire 6 in contact with the surface of the first resin 31 and the surface electrode 1a of the semiconductor element 1, which is indicated by t2 in FIG.

[0031] FIG. 7 is a schematic cross-sectional view in the wire length direction when the wire bonding portion is coated with the second resin 32 in addition to the first resin 31. FIG. 8 is a schematic cross-sectional view in the wire length direction when the wire bonding portion is coated with the second resin 32 in addition to the first resin 31. The wire bonding portion may be coated with the second resin 32 having a lower elastic modulus than the first resin 31 in addition to the first resin 31. A resin solution of the first resin 31 having an elastic modulus of more than 5 GPa has a high viscosity, and it is costly to dilute it in order to apply it. A resin solution of the second resin 32 having a lower elastic modulus than the first resin 31 has a lower viscosity than the resin solution of the first resin, and the dilution cost can be reduced. For example, by coating the first resin having a thickness of 10 μm and the second resin having a thickness of 10 to 50 μm, the reliability of the bonding portion can be further improved while keeping costs low. For example, a polyimide resin or a polyamide-imide resin can be used as the resin used for the second resin layer 32.

[0032] A surface electrode 1a is formed on the semiconductor element 1. In the semiconductor device of this embodiment, the surface electrode 1a is a laminate of an Al alloy layer and a Ni layer, and the Ni layer is present on the outermost surface of the surface electrode 1a. By forming the outermost surface of the surface electrode 1a as a Ni layer, the strength of the surface electrode 1a can be increased, and even if thermal stress is repeatedly applied, the surface electrode 1a is less likely to crack, thereby improving the reliability of the wire bonded portion. The thickness of the Ni layer can be appropriately set according to the strength of the Ni layer, and by setting it to, for example, 1 to 20 μm, the reliability of the wire bonded portion is improved. The Ni layer is a metal layer containing Ni as a main component, and there is no problem even if it contains an additive element.

[0033] The semiconductor device in this embodiment solves the following problems. In order to explain the problems, a semiconductor device 90 of Study Example 1 studied by the present inventor will be described. The semiconductor device 90 of Study Example 1 has a plurality of semiconductor elements 1, surface electrodes 1a of the semiconductor elements 1, wires 6, and a first resin 31, similar to the semiconductor device 10 in this embodiment.

[0034] FIG. 9 is a schematic diagram of a joint between the surface electrode 1a of the semiconductor element 1 and the wire 6 in the study example 1. The first problem is caused by the high strength of the wire 6. If the strength of the wire 6 is high (for example, the tensile strength exceeds 80 MPa), the wire 6 is less likely to deform when the wire 6 is joined by ultrasonic bonding, for example. In this case, in order to join the wire 6 with a joint strength that does not damage the surface electrode 1a, for example, as shown in FIG. 9, the length L2 of the wire joint needs to be smaller than 85% of the diameter ratio L1 of the wire 6. In this case, as shown in FIG. 9, there is a space surrounded by the wire 6 and the surface electrode 1a (hereinafter, referred to as the space 91 of the wire joint) that cannot be confirmed from the top surface of the joint. This space 91 of the wire joint has a problem that a void 92 occurs in the first resin 31 because the resin solvent containing the first resin does not flow sufficiently into the wire joint when the wire joint is covered with the first resin 31. FIG. 10 is a schematic diagram of a void 92 that exists in the first resin 31 of the wire joint in the study example 1.

[0035] The second problem is caused by the high elastic modulus of the first resin 31. When the elastic modulus of the first resin 31 is high, the viscosity of the resin solution containing the first resin is often also high, which makes it difficult for the resin solution to flow into the space 91 in the wire bonding portion described above, which also causes a problem that voids are likely to occur in the first resin 31 that covers the wire bonding portion.

[0036] The present invention is based on the discovery that even when the tensile strength of the wire 6 is 80 MPa or more and the elastic modulus of the first resin layer 31 is 5 GPa or more, the reliability of the wire bonding portion can be improved compared to the conventional art by making the outermost surface of the surface electrode 1a of the semiconductor element 1 Ni and further by covering the space of the wire bonding portion with the first resin 31 without leaving voids using the manufacturing method described below.

[0037] <Method of Manufacturing Semiconductor Device according to Example 1> The method for manufacturing the semiconductor device of this embodiment will be described with reference to the drawings. Fig. 16 is a flow diagram showing a representative method for manufacturing the semiconductor device according to the first embodiment. As shown in Fig. 16, the method for manufacturing the semiconductor device of this embodiment includes a semiconductor element mounting step S1, a wire bonding step S2, a plasma treatment step S3, a first resin application step S4, and a first resin hardening step S5. The method for manufacturing the semiconductor device of this embodiment may also include a second resin application step S6 and a second resin hardening step S7.

[0038] <Semiconductor element mounting process S1> The semiconductor element mounting process S1 is a process of bonding a semiconductor element 1 to a wiring board 3 using a bonding material 2. The outermost surface of the surface electrode 1a of the semiconductor element 1 is Ni, which can be formed by a method such as electrolytic plating, electroless plating, or vapor deposition. The bonding material 2 can be, for example, solder or sintered metal.

[0039] <Wire bonding process S2> The wire bonding step S2 is performed after the semiconductor element mounting step S1. The wire bonding step S2 is a step of bonding the surface electrodes 1a of the semiconductor element 1 to the wiring patterns 3aa, 3ac on the upper surface 3a of the wiring board 3 with wires 6. For example, ultrasonic bonding can be used as a bonding method.

[0040] <Plasma treatment step S3> The plasma treatment step S3 is carried out after the wire bonding step S2. The plasma treatment step S3 is a step in which the object is subjected to plasma treatment to remove contamination and oxidation on the object surface, thereby increasing the wettability of the resin solvent to the object. For the plasma treatment, various plasma treatments such as vacuum plasma and atmospheric pressure plasma can be used. For example, nitrogen, argon, oxygen, hydrogen, or a mixture of these gases can be used as the gas used for the treatment. The plasma output and treatment time can be appropriately set according to the presence of contamination, oxidation, etc. on the object surface.

[0041] The plasma treatment step S3 can be performed between the first resin application step S4 and the wire bonding step S2, which will be described later. By irradiating the wire bonding portion with plasma, the wettability of the resin solvent to the front electrode 1a and the wire 6 can be increased, so that the first resin 31 can be applied to the wire bonding portion without voids.

[0042] If the wire 6 blocks the plasma and the plasma cannot be sufficiently irradiated to the wire bonded portion, the object may be set at an appropriate inclination with respect to the plasma irradiation direction. By tilting the object with respect to the plasma irradiation direction, the wire 6 is prevented from being blocked in the plasma irradiation direction, and the plasma can be irradiated to the wire bonded portion.

[0043] To enhance the effect of the plasma treatment, a plasma treatment may additionally be performed on the front surface electrode 1a of the semiconductor element 1 before the wire bonding step S2. That is, a plasma treatment may additionally be performed before the wire bonding step S2 and after the semiconductor element mounting step S1. By adding a plasma treatment before the wire bonding step S2, the plasma is irradiated onto the front surface electrode 1a of the semiconductor element 1 without being blocked by the wire 6, so that the wettability of the resin solution can be further improved.

[0044] <First resin coating step S4> The first resin application step S4 is performed after the plasma treatment step S3. The first resin application step S4 is a step of applying a resin solution in which the first resin 31 is dissolved to the wire bonding portion. The resin solution can be applied to the wire bonding portion using, for example, a dispenser. At this time, if the solid content concentration of the first resin 31 is high, the viscosity of the resin solution is high and the resin solution does not flow into the space of the wire bonding portion, causing voids to occur in the first resin 31. In order to prevent voids from occurring in the wire bonding portion, it is necessary to reduce the solid content concentration of the resin solution to 0.70 wt% or less after the above-mentioned plasma treatment step S3.

[0045] When the solid content concentration of the resin solvent is low, it is necessary to increase the amount of resin solution applied in order to ensure the thickness of the first resin 31 at the wire bonding portion. On the other hand, when the amount of resin solution applied is large, the resin solution overflows from the semiconductor element 1 or is absorbed into the loop portion (not shown) of the wire 6, so that the desired amount of the first resin 31 cannot be applied to the wire bonding portion. In this way, when the first resin 31 of the required thickness cannot be formed by one application, the number of applications can be appropriately increased. In addition, when applying multiple times, the application process can be completed in a shorter time by providing drying of the solvent between the applications. The drying conditions of the solvent are not particularly limited, and for example, the drying temperature can be appropriately set within a temperature range from room temperature to about 100°C. By drying the solvent, it is possible to prevent the resin solution from overflowing from the semiconductor element 1 or being absorbed into the loop portion of the wire 6 even if the application is repeated, and the desired amount of resin cannot be applied to the wire bonding portion.

[0046] When the resin solution is applied multiple times, the solid content concentration of the resin solution from the second application onward can be higher than that of the first application. In the first application, the solid content ratio needs to be lowered to, for example, 0.70 wt% in order to allow the resin solution to flow into the space of the wire bonding portion. However, in the second and subsequent applications, the resin solution applied in the first application covers the wire bonding portion, and the resin solvent has good wettability, so that the first resin 31 can cover the wire bonding portion without voids even if the solid content ratio is higher than that of the first application. The solid content concentration of the resin solution used in the second and subsequent applications may be higher than the solid content concentration of the resin solvent used in the first application, and can be, for example, 0.70 wt% in the first application and 7.0 wt% in the second application. This allows the first resin 31 to cover the wire bonding portion with the desired thickness in a shorter time.

[0047] The elastic modulus of the resin in the resin solution applied after the second application may be lower than the elastic modulus of the resin in the resin solution used in the first application. The resin solution of the resin with high elasticity exceeding 5 GPa used in the first application has high viscosity and is costly to dilute. After the resin with high elasticity exceeding 5 GPa is coated, for example, 10 μm, in the first application, a resin with an elastic modulus of 2 GPa can be additionally coated, for example, in the second or subsequent application. This can further improve the reliability of the joint while keeping costs down.

[0048] In this case, the amount of metal ion impurities in the resin applied the second time or later may be higher than that in the first time. Since the resin applied the second time or later does not directly contact the electrodes of the semiconductor element, the breakdown voltage is less likely to decrease due to the inclusion of metal ions. Since refining the metal ion impurities is unnecessary or can be simplified, costs can be reduced.

[0049] <First resin curing step S5> The first resin curing step S5 is carried out after the first resin application step S4. The first resin curing step S5 is a step of evaporating the solvent of the first resin solution applied to the wire bonding portion and curing the resin. The curing temperature and curing time can be appropriately set according to the solvent of the resin solution. When NMP (N-methyl-2-pyrrolidone) is used as the solvent, the curing temperature can be set to 200°C, for example.

[0050] When the second resin 32 is not used, the representative manufacturing method of the semiconductor device of the embodiment ends with the first resin curing step S5. On the other hand, when the second resin 32 is used, a second resin applying step S6 and a second resin curing step S7 are additionally performed after the first resin curing step S5.

[0051] <Second resin coating step S6> The second resin application step S6 is performed after the first resin curing step S5. The second resin application step S6 is a step of applying a resin solution in which the second resin 32 is dissolved to the wire bonding portion. The resin solution can be applied to the wire bonding portion using, for example, a dispenser. The second resin application step S6 may be performed after the first resin application step S4, and may be performed before or after the first resin curing step S5. By performing the second resin application step S6 before the first resin curing step S5, the first resin curing step S5 can also serve as the second resin curing step S7, and the manufacturing process can be shortened, thereby reducing costs.

[0052] <Second resin curing step S7> The second resin curing step S7 is performed after the second resin application step S6. The second resin curing step S7 is a step of evaporating the solvent of the second resin solution applied to the wire bonding portion and curing the resin. The curing temperature and curing time can be appropriately set according to the solvent of the resin solution. When NMP is used as the solvent, the curing temperature can be set to 200°C, for example. When the second resin application step S6 is before the first resin curing step S5, the first resin curing step S5 can also serve as the second resin curing step S7. This shortens the manufacturing process, thereby reducing costs.

[0053] <Modification of the manufacturing method of the first embodiment> 17 is a diagram for explaining a manufacturing method of a semiconductor device of Example 1 according to a modified example. The manufacturing method of FIG. 17 shows a manufacturing method configured such that the second resin application step S6 is performed before the first resin curing step S5, and the first resin curing step S5 also serves as the second resin curing step S7. By performing the second resin application step S6 before the first resin curing step S5, the first resin curing step S5 can also serve as the second resin curing step S7, and the manufacturing process of the semiconductor device can be shortened, thereby reducing the manufacturing cost of the semiconductor device. The plasma treatment step S3 may be performed between the semiconductor element mounting step S1 and the wire bonding step S2.

[0054] <Effects of the present invention> The effects of the manufacturing method of the semiconductor device in this embodiment are described below. Fig. 13 is a diagram of Table 1 showing the relationship between the presence or absence of a plasma treatment step, the solids concentration of the first resin solution in the first resin application step, and the presence or absence of voids in the wire bonding portion. Fig. 14 is a diagram of Table 2 showing the power cycle life when the tensile strength of the surface electrode, the wire, and the elastic modulus of the first resin are changed. Fig. 15 is a diagram of Table 3 showing the power cycle life when the thickness of the first resin layer is changed.

[0055] Table 1 in Figure 13 shows the relationship between the presence or absence of plasma treatment step S3 and the solids concentration of the first resin solution in the first resin application step S4, and the presence or absence of voids in the wire bonded portion. The resin contained in the resin solution is a polyamide-imide resin with an average molecular weight of 30,000 and an elastic modulus of 5 GPa, and the solvent is NMP. As shown in Table 1, in order to prevent the occurrence of voids in the wire bonded portion, the solids concentration of the resin solution needs to be 0.70 wt% or less after the aforementioned plasma treatment step S3. The viscosity of the resin solution at this time is 0.013 Pa s or less.

[0056] The effects of the semiconductor device in this embodiment are as follows.

[0057] Table 2 shown in FIG. 14 shows the power cycle life when the tensile strength of the surface electrode 1a, the wire 6, and the elastic modulus of the first resin 31 are changed. The power cycle life is the life of the semiconductor device when a temperature load is applied in which the temperature of the semiconductor element 1 rises from 50°C to 175°C and then falls back to 50°C repeatedly. In Table 2, the condition in which the surface electrode is described as Ni is a condition in which an electroless Ni plating of 3 μm is laminated on an electrode layer of an Al alloy. The thicknesses t1 and t2 of the first resin layer are both 20 μm. Comparing Configuration 3 and Configuration 6, it can be seen that when the tensile strength of the wire 6 is 80 MPa and the elastic modulus of the first resin 31 is 5 GPa, the life is increased by about four times by making the surface electrode 1a a Ni layer compared to when the surface electrode is an Al alloy.

[0058] Table 3 shown in FIG. 15 shows the power cycle life when the thicknesses t1 and t2 of the first resin layer 31 are changed. The power cycle life is the life of the semiconductor device when a temperature load is applied in which the temperature of the semiconductor element 1 rises from 50° C. to 175° C. and then falls back to 50° C. repeatedly. The surface electrode 1a of the semiconductor element 1 is made of Ni, and the wire tensile strength is 80 MPa. When the thicknesses t1 and t2 of the first resin layer are both 10 μm, the life is increased by 1.12 times compared to the conventional structure in which the elastic modulus of the resin is low (3 GPa). Furthermore, when t1 is 20 μm and t2 is 10 μm, the life is increased by 1.37 times, and when t1 and t2 are both 20 μm, the life is increased by 1.43 times. Even if t1 exceeds 20 μm, when the film thickness of t1 is zero, that is, when voids exist, the life remains at 0.56 compared to the conventional structure, and reliability is reduced. EXAMPLES

[0059] Next, a second embodiment of the present invention will be described with reference to FIGS.

[0060] 11 is a schematic cross-sectional view showing the structure of a semiconductor device 20 in this embodiment. In this embodiment, the first resin layer 31, the semiconductor element 1, the bonding material 2, the wiring board 3, and the wiring patterns 3aa, 3ab, and 3ac on the upper surface 3a of the wiring board 3 are covered with a third resin layer 33, which is a difference from the first embodiment. The other components have the same functions as the components with the same reference numerals shown in Figs. 1 to 8 already described, and therefore the description thereof will be omitted.

[0061] Since a high voltage of several hundred to 10 kV is applied to the semiconductor device, discharge may occur starting from a point where the electric field is concentrated, such as the end of the semiconductor element 1 or the end of the wiring patterns 3aa, 3ab, and 3ac. In order to suppress discharge, the end of the semiconductor element 1 or the end of the wiring patterns 3aa, 3ab, and 3ac may be covered with a resin layer having a high dielectric constant to reduce the electric field. On the other hand, if the wettability of the resin solution to the covered part is poor, there may be a part that is not covered with the resin or a void in the resin occurs, resulting in a problem that the discharge suppression effect cannot be sufficiently obtained.

[0062] In this embodiment, a plasma treatment process is performed before applying the third resin 33, thereby removing contamination and oxidation of the semiconductor element 1, the wiring board 3, and the wiring patterns 3aa, 3ab, and 3ac, and improving the wettability of the resin solvent. For example, polyimide resin or polyamide-imide resin can be used as the resin used for the third resin 33. The thickness of the third resin 33 can be appropriately set according to the rated voltage of the semiconductor device, but by setting the thickness to, for example, 5 to 100 μm, the insulation reliability is improved. This not only improves the reliability of the wire bonding portion covered by the first resin 31, but also improves the insulation reliability by covering the end of the semiconductor element 1 and the end of the wiring patterns 3aa, 3ab, and 3ac with the third resin layer 33. In addition, since the effect of the third resin 33 is electric field relaxation, the elastic modulus of the resin is not particularly limited, and a resin having an elastic modulus lower than that of the first resin layer, such as 1 to 3 GPa, can be used.

[0063] 12 is a schematic cross-sectional view showing a structure when the portion coated with the third resin is changed in the semiconductor device of this embodiment. The portions to which the third resin solution is applied can be the semiconductor element 1, the bonding material 2, the wiring board 3, and the wiring patterns 3aa, 3ab, and 3ac on the upper surface 3a of the wiring board 3, excluding the first resin 31 that covers the wire bonding portion, or excluding the second resin 32. When the reliability of the wire bonding portion can be ensured by the first resin 31, the amount of the third resin layer used can be reduced, and costs can be reduced by omitting to coat the wire bonding portion with the third resin 33.

[0064] The coating area of ​​the third resin layer may include at least one of the semiconductor element 1, the bonding material 2, the wiring board 3, and the wiring patterns 3aa, 3ab, and 3ac on the upper surface 3a of the wiring board 3. By appropriately selecting the coating area according to the location where the electric field is concentrated, it is possible to ensure insulation reliability while suppressing the amount of resin used.

[0065] <Method of Manufacturing a Semiconductor Device according to the Second Embodiment> The manufacturing method of the semiconductor device of this embodiment will be described with reference to the drawings. Fig. 18 is a flow diagram showing a representative manufacturing method of a semiconductor device according to embodiment 2. The manufacturing method of the semiconductor device of this embodiment shown in Fig. 18 includes a third resin applying step S8 and a third resin curing step S9 in addition to the manufacturing steps (S1 to S7) described in embodiment 1 of Fig. 16. The other steps (S1 to S7) and the order of the steps are the same as those described in embodiment 1, so their description will be omitted.

[0066] <Third resin application process S8> When the second resin 32 is not used, the representative method for manufacturing the semiconductor device of this embodiment performs a third resin application step S8 after the first resin hardening step S5. On the other hand, when the second resin 32 is used, as shown in FIG. 18, a third resin application step S8 is performed after the second resin hardening step S7.

[0067] The third resin application step S8 is a step of applying a resin solution having the third resin 33 dissolved therein to the wire bonding portion. For example, the resin solution can be applied to the first resin layer 31, the semiconductor element 1, the bonding material 2, the wiring board 3, and the wiring patterns 3aa, 3ab, and 3ac on the upper surface 3a of the wiring board 3 using a dispenser or the like.

[0068] The solids concentration and viscosity of the third resin solution are not particularly limited, but in order to prevent the resin solution from wetting and spreading to unintended areas, it is advisable to set the solids concentration to about 3.0 to 14.0 wt% and the viscosity to about 0.1 to 3.0 Pa s, for example.

[0069] The third resin application step S8 may be performed after the plasma treatment step S3, and may be performed before or after the first resin application step S4. By performing the third resin application step S8 before the first resin curing step S5, the first resin curing step S5 can also serve as the third resin curing step S9 described below, and the manufacturing process can be shortened, thereby reducing costs.

[0070] <Third resin curing step S9> The third resin curing step S9 is a step of evaporating the solvent of the third resin solution applied to the wire bonding portion and curing the resin. The curing temperature and curing time can be appropriately set according to the solvent of the resin solution. When NMP is used as the solvent, the curing temperature can be set to 200°C, for example. When the third resin application step S8 is performed before the first resin curing step S5, the first resin curing step S5 can also serve as the third resin curing step S9. This shortens the manufacturing process, thereby reducing costs.

[0071] <Modification of the manufacturing method of the second embodiment> FIG. 19 is a diagram for explaining a manufacturing method of a semiconductor device of Example 2 according to a modified example. The manufacturing method of FIG. 19 shows a manufacturing method in which the third resin application step S8 is performed after the first resin application step S4 and the second resin application step S6 and before the first resin hardening step S5, and the first resin hardening step S5 serves both as the second resin hardening step S7 and the third resin hardening step S9. By performing the third resin application step S8 before the first resin hardening step S5, the first resin hardening step S5 can serve both as the second resin hardening step S7 and the third resin hardening step S9, and the manufacturing process of the semiconductor device can be shortened, thereby reducing the manufacturing cost of the semiconductor device. The plasma treatment step S3 may be performed between the semiconductor element mounting step S1 and the wire bonding step S2.

[0072] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0073] 1: Semiconductor elements 1a: Surface electrode 2: Bonding material 3: Wiring board 3a: Top surface of wiring board 3b: Bottom surface of wiring board 3aa, 3ab, 3ac, 3ba: Wiring patterns 4: Base plate 5: Bonding material 6: Wire 7: Terminal 8: Case 9: Sealing resin 10: Semiconductor device of Example 1 20: Semiconductor device of Example 2 31: First resin 32: Second resin 33: Third resin 90: Semiconductor device of study example 1 91: Wire joint space 92: Void

Claims

1. A semiconductor element; a surface electrode formed on the semiconductor element; a wire bonded to the surface electrode; a first resin that covers the surface electrode and the bonded portion of the wire; The surface of the surface electrode is a Ni layer, A second resin having a lower elastic modulus than the first resin is included, the first resin is coated with the second resin, A wiring board supporting the semiconductor element; A wiring pattern formed on an upper surface of the wiring substrate; a bonding material for bonding the wiring board and the semiconductor element; a third resin that covers at least one of the bonding portion between the surface electrode and the wire, the semiconductor element, the bonding material, the wiring pattern, and the wiring substrate, The elastic modulus of the third resin is configured to be lower than the elastic modulus of the first resin, The semiconductor device includes: a base plate to which the wiring board is attached; a case attached to the base plate and covering the semiconductor element, the wires, and the wiring board; a sealing resin for sealing an upper surface of the base plate and an area surrounded by the case.

2. 2. The semiconductor device according to claim 1, The wire has a tensile strength of 80 MPa or more, The first resin has an elastic modulus of 5 GPa or more.

3. 2. The semiconductor device according to claim 1, a thickness of the first resin covering the wire in the longitudinal direction at the joint between the surface electrode and the wire is 10 μm or more;

4. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the thickness of the first resin covering the wire in a diameter direction at the joint between the surface electrode and the wire is 10 μm or more.

5. irradiating at least one of a surface electrode of a semiconductor element and a bonding portion between the surface electrode and a wire with plasma; bonding a surface electrode of the semiconductor element to a wire; applying a solution in which a first resin is dissolved to a joint portion between the wire and the surface electrode; Before the step of applying the solution in which the first resin is dissolved, and exposing the plasma to the 5. The method for manufacturing a semiconductor device, wherein in the step of applying a solution in which the first resin is dissolved, the solution has a solid content of 0.70 wt % or less.

6. 6. The method for manufacturing a semiconductor device according to claim 5, applying a solution in which a third resin is dissolved to at least one of the semiconductor element, the wiring board supporting the semiconductor element, the wiring pattern formed on the upper surface of the wiring board, and a bonding material bonding the wiring board and the semiconductor element; A method for manufacturing a semiconductor device, comprising the steps of: applying a solution in which the third resin is dissolved; and applying the solution after the step of irradiating with plasma.

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