A differential mixed-signal multiplier with three capacitors.

Abstract

A differential mixed-signal logic processor is provided, comprising a plurality of mixed-signal multiplier branches for multiplying an analog value A by an N-bit digital value B. Each of the plurality of mixed-signal multiplier branches comprises a first capacitor connected between a second capacitor and a third capacitor to provide a differential output between the second and third capacitors, the capacitance of the first capacitor being equal to half the capacitances of the second and third capacitors.

Description

[Technical field]

[0001] The present invention relates generally to electronic circuits, and more particularly to a differential mixed-signal multiplier having three capacitors. [Background technology]

[0002] The emergence of sensor-rich platforms, such as the Internet of Things (IoT), healthcare, and autonomous driving, often requires local decision capabilities using machine learning (ML) algorithms. Although these applications require ultra-low power operation in battery-powered platforms, most of them require expensive analog-to-digital conversion (ADC) since the sampled data is in the analog domain. Sensor applications, as well as in-memory computing, neuromorphic computing (e.g., computing based on resistive random access memory (ReRAM)), etc., often generate intermediate results in the analog domain.

[0003] Therefore, analog and digital mixed-signal processing is a good option to avoid the high cost of ADCs. While analog processing suffers from non-idealities in the low-power regime, machine learning algorithms typically have a high inherent noise immunity, which makes approximate computing such as low-power mixed-signal processing more attractive. The primary computing kernel of most machine learning algorithms is multiplication. Naturally, mixed-signal multiplication between analog values ​​(from sensors or neuromorphic computing blocks) and digital values ​​(from memory) is an essential computing building block. Summary of the Invention

[0004] According to an aspect of the present invention, a differential mixed-signal logic processor is provided, the differential mixed-signal logic processor including a plurality of mixed-signal multiplier branches for multiplication of an analog value A and an N-bit digital value B. Each of the plurality of mixed-signal multiplier branches includes a first capacitor connected across a second capacitor and a third capacitor to provide a differential output between the second capacitor and the third capacitor. The capacitance of the first capacitor is equal to half the capacitance of the second and third capacitors.

[0005] According to another aspect of the invention, there is provided a method of forming a differential mixed signal processor, the method including configuring each of a plurality of mixed signal multiplier branches for multiplication of an analog value A and an N-bit digital value B to include a first capacitor connected between a second capacitor and a third capacitor to provide a differential output between the second capacitor and the third capacitor, the capacitance of the first capacitor being equal to half the capacitances of the second and third capacitors.

[0006] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief description of the drawings]

[0007] The following description provides details of the preferred embodiments in conjunction with the following drawings:

[0008] [Figure 1] 1 is a block diagram illustrating an exemplary processing system, in accordance with one embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram illustrating an exemplary mixed-signal dot product computation circuit, in accordance with one embodiment of the present invention. [Diagram 3] FIG. 2 is a block diagram illustrating an exemplary differential mixed signal multiplier having three capacitors, in accordance with one embodiment of the present invention. [Figure 4]FIG. 4 is a flow diagram illustrating an exemplary dot product calculation method according to one embodiment of the present invention. [Diagram 5] FIG. 2 is a block diagram illustrating an exemplary multiplier and accumulator (MAC) arithmetic configuration, in accordance with one embodiment of the present invention. [Figure 6] 1 is a flow diagram illustrating an exemplary method for forming a mixed signal logic processor in accordance with one embodiment of the present invention. [Figure 7] FIG. 2 is a block diagram illustrating exemplary bit precision requirements across layers of a deep neural network, according to one embodiment of the present invention. [Figure 8] FIG. 8 illustrates an exemplary initial design 800 from which the design of FIG. 3 was derived, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment of the present invention is directed to a differential mixed-signal multiplier having three capacitors.

[0010] One or more embodiments of the present invention may be directed to dot products having differential signed numeric representations, however, it should be appreciated that other or the same embodiments may also be directed to other numeric and logical functions, including mixed (analog and digital) signals.

[0011] One or more embodiments of the present invention utilize three capacitors for any bit precision of a value B, where B is:

number

[0012] In one or more embodiments of the invention, each mixed signal multiplier branch includes a first capacitor connected between the second capacitor and the third capacitor to provide a differential output between the second capacitor and the third capacitor.

[0013] In one or more embodiments of the invention, the capacitance of the first capacitor is equal to half the capacitance of the second and third capacitors.

[0014] Thus, for an 8-bit digital value, the proposed multiplier embodiment requires approximately >100x smaller capacitor area and lower energy consumption to charge the capacitors, i.e., for any bit precision requirement, the proposed multiplier uses only three capacitors of the size described herein, resulting in significant savings in area and energy costs.

[0015] One or more embodiments of the proposed multiplier further cover signed representations for both operands in the multiplication.

[0016] One or more embodiments of the proposed multiplier use differential inputs for higher signal integrity.

[0017] One or more embodiments of the proposed multiplier further calculate a dot product, which is a sum over many multiplication results.

[0018] FIG. 1 is a block diagram illustrating an exemplary processing system 100, according to an embodiment of the present invention. The processing system 100 includes a set of processing units (e.g., CPUs) 101, a set of GPUs 102, a set of memory devices 103, a set of communication devices 104, and a set of peripheral devices 105. The CPUs 101 can be single or multi-core CPUs. The GPUs 102 can be single or multi-core GPUs. At least one of the CPUs 101 or GPUs 102 or both includes a differential mixed signal processor with three capacitors per multiplier to perform logic functions such as dot products. The one or more memory devices 103 can include caches, RAMs, ROMs, or other memory (flash, optical, magnetic, etc.). The communication devices 104 can include wireless or wired or both communication devices (e.g., network (e.g., WIFI, etc.) adapters, etc.). The peripheral devices 105 can include display devices, user input devices, printers, imaging devices, etc. The elements of the processing system 100 are connected by one or more buses or networks (collectively designated in the drawings by the reference numeral 100).

[0019] In one embodiment, the memory device 103 can store specially programmed software modules for transforming the computer processing system into a special purpose computer configured to implement various aspects of the present invention. In one embodiment, special purpose hardware (e.g., application specific integrated circuits, field programmable gate arrays (FPGAs), etc.) can be used to implement various aspects of the present invention.

[0020] Of course, processing system 100 can also include other elements (not shown) or omit certain elements, as would be readily contemplated by one of ordinary skill in the art. For example, various other input or output devices, or both, can be included in processing system 100 depending on their particular implementation, as would be readily appreciated by one of ordinary skill in the art. For example, various types of wireless and / or wired input and / or output devices can be used. Furthermore, additional processors, controllers, memories, etc. in various configurations can also be utilized. These and other variations of processing system 100 can be readily contemplated by one of ordinary skill in the art given the teachings of the invention provided herein.

[0021] Additionally, it should be appreciated that various figures are described below with reference to various elements and steps associated with the present invention that may be performed, in whole or in part, by one or more elements of system 100.

[0022] As employed herein, the term "hardware processor subsystem" or "hardware processor" may refer to a processor, memory, software, or a combination thereof working together to perform one or more specific tasks. In useful embodiments, the hardware processor subsystem may include one or more data processing elements (e.g., logic circuits, processing circuits, instruction execution devices, etc.). The one or more data processing elements may be included in a central processing unit, a graphics processing unit, and / or a separate processor or computing element based controller (e.g., logic gates, etc.). The hardware processor subsystem may include one or more on-board memories (e.g., caches, dedicated memory arrays, read-only memories, etc.). In some embodiments, the hardware processor subsystem may include one or more memories (e.g., ROMs, RAMs, basic input / output system (BIOS), etc.), which may be on-board or off-board or may be dedicated for use by the hardware processor subsystem.

[0023] In some embodiments, the hardware processor subsystem may include and execute one or more software elements, which may include an operating system, one or more applications, and / or specific code for achieving a particular result.

[0024] In other embodiments, the hardware processor subsystem may include specific dedicated circuitry to perform one or more electronic processing functions to achieve a particular result. Such circuitry may include one or more application specific integrated circuits (ASICs), FPGAs, and / or PLAs.

[0025] These and other variations of hardware processor subsystems are also contemplated in accordance with embodiments of the present invention.

[0026] FIG. 2 is a block diagram illustrating an exemplary mixed signal dot product calculation circuit 200, in accordance with one embodiment of the present invention.

[0027] The mixed signal dot product computation circuit 200 includes an array of sensor nodes 210, a set of amplifiers 220, a memory 230, and a set of mixing multiplier branches (or simply "mixing multipliers") 240. For purposes of illustration, the number of mixing multipliers 240 has been arbitrarily selected to be four, although other numbers of mixing multipliers may be used in other embodiments.

[0028] A pair of mixing multipliers 240 outputs a differential output OUT(OUT + and OUT - ) is provided.

[0029] The memory 230 stores the digital value w 1-4 to provide.

[0030] FIG. 3 is a block diagram illustrating an exemplary differential mixed-signal multiplier 300 having three capacitors, in accordance with one embodiment of the present invention.

[0031] In one embodiment, the differential mixed signal multiplier 300 may be one of the mixing multipliers 240 in the mixed signal dot product computation circuit 200 of FIG.

[0032] The differential mixed signal multiplier 300 has a differential input v A+ and v A- Includes.

[0033] The differential mixed signal multiplier 300 has a differential output v out Includes.

[0034] The differential mixed signal multiplier 300 includes a capacitor c 1 301, Capacitor C 2p 302, capacitor c 2n 303, Switch 1 304, another switch 1 305, Switch S0 306, another switch 0 307, Switch

number

[0035] Capacitor C 1 One end of 301 is the node sp + is coupled to a capacitor c 1 The other end of 301 is the node sp - is combined with

[0036] Node sp + In addition, switch s 0 One side of 306, switch s 0 One side of the bar 308 and the switch s 1 304. 0 The other side of 306 is the input v A+ The switch s 0 The other side of the bar 308 is connected to the input v A- The switch s 1 The other side of 304 is the capacitor c 2p 302 is coupled to one side of the capacitor c 2p The other side of 302 is grounded.

[0037] Node sp - In addition, switch s 0 One side of 307, switch s 0 One side of the bar 309 and the switch s 1 305 is coupled to one side of the switch s 0 The other side of 307 is the input v A- The switch s 0 The other side of bar 309 is the input v A+ The switch s 1 The other side of 305 is the capacitor c 2n303 is coupled to one side of the capacitor c 2n The other side of 303 is grounded.

[0038] In the differential version,

number

[0039] In the reset phase, v A+ =v A- =v cm is

[0040] Table 1 shows signals for different processing phases of a differential mixed signal multiplier with three capacitors according to one embodiment of the present invention. [Table 1]

[0041] The sizing of the capacitor, according to one embodiment of the present invention, will now be described.

[0042] In one embodiment, the capacitor c 1 301=c / 2.

[0043] In one embodiment, the capacitor c 2p 302=c.

[0044] In one embodiment, the capacitor c 2n 303=c.

[0045] FIG. 4 is a flow diagram illustrating an exemplary dot product calculation method 400, according to one embodiment of the present invention.

[0046] In block 405, the capacitors are reset by discharging them (e.g., by grounding them) to v sp+ =v sp- =v cmIn another embodiment, the capacitors can be discharged by connecting them to a discharge potential.

[0047] At block 410, we perform B evaluation phases, each of which includes a sample stage, a blend stage, and an accumulation stage. Thus, for an nth evaluation phase (for an N-bit value, this stage is repeated N times), the following holds:

[0048] (a) Sample: For the nth bit, sample node sp + is the voltage v cm +b n v A and sample node sp - is the voltage v cm -b n v A has.

[0049] (b) Accumulation: Node sp + and v out+ Similarly, sp - and v out- is charge-shared. Therefore,

number

[0050] At block 415, the output v out ∝Bv A It is.

[0051] A description will now be given of the operation of a multiplier and accumulator (MAC) according to one embodiment of the present invention.

[0052] In many signal processing and machine learning applications, the results of multiplications are to be summed (in a so-called MAC operation).

[0053] Here, the positive and negative ports of the multiplier can be separately connected to the positive and negative rails, respectively, by a charge sharing operation.

[0054] FIG. 5 is a block diagram illustrating an exemplary multiplier and accumulator (MAC) arithmetic configuration 500, in accordance with one embodiment of the present invention.

[0055] As shown in the figure, the multiplier outputs out of multipliers 1 to M + is the voltage v MAC+ , and the multiplier outputs out- of multipliers 1 to M are connected to the positive rail 511 at MAC- 512 to the negative rail 512.

[0056] For a MAC operation the following applies:

number

[0057] FIG. 6 is a flow diagram illustrating an exemplary method 600 for forming a mixed signal logic processor, according to one embodiment of the present invention.

[0058] In block 605, a plurality of mixed signal multiplier branches are configured to have three dedicated capacitors including a first, a second, and a third capacitor, a positive supply node connected to a first end of the first capacitor, and a negative supply node connected to a second end of the first capacitor. In one embodiment, the first capacitor is connected between the second and third capacitors and has half the capacitance of the second and third capacitors. In one embodiment, a differential output is provided between the second and third capacitors.

[0059] At block 610, a first end of a first set of switches including a first, second, and third switch is connected to a positive supply node.

[0060] At block 615, a first end of a second set of switches including a fourth, fifth, and sixth switch is connected to the negative supply node.

[0061] In block 620, the second ends of the first and fourth switches are connected to the positive input voltage.

[0062] In block 625, the second ends of the second and fifth switches are connected to the negative input voltage.

[0063] In block 630, the second end of the third switch is connected to the first end of the second capacitor and to the positive output node of the mixed signal processor.

[0064] In block 635, the second end of the sixth switch is connected to the first end of the third capacitor and to the negative output node of the mixed signal processor.

[0065] At block 640, different settings of the first and second sets of switches enable different modes of the mixed signal logic processor.

[0066] FIG. 7 is a block diagram illustrating example bit precision requirements 700 across layers of a deep neural network, according to one embodiment of the present invention.

[0067] As can be seen, the bit precision requirements 700 include 8-bit, 6-bit, 4-bit, 5-bit, and 3-bit precision depending on the layer involved. In particular, the input layer 701 requires 8-bit precision, the first layer 711, the second layer 712, and the third hidden layer 713 require 6-bit, 4-bit, and 5-bit precision, respectively, and the output layer 721 requires 3-bit precision.

[0068] 8 is a diagram illustrating an example initial design 800 from which the design of FIG. 3 was derived, according to one embodiment of the present invention. The initial design 800 includes a total of four capacitors, and the design of FIG. 3 includes the capacitors c 1p and c 1n 3 to form a single capacitor c 1Thus, design 800 requires four capacitors of size C, whereas the design of FIG. 3 requires only three capacitors of values ​​C, C, and C / 2, thus saving space and cost. 1p and c 1n C total teeth, 1 / (1 / c 1p +1 / c 1n )=C / 2 Therefore, the design of FIG. 3 uses the capacitor c 1p and c 1n This provides an opportunity to save the capacitor area in half.

[0069] The differential mixed signal multiplier 800 has a differential input v A+ and v A- Includes.

[0070] The differential mixed signal multiplier 800 has a differential output v out Includes.

[0071] The differential mixed signal multiplier 800 includes a capacitor c 1p 801, Capacitor C 1n 810, Capacitor C 2p 802, capacitor c 2n 803, Switch 1 804, another switch 1 805, Switch s 0 806, another switch 0 807, Switch 0 bar 808, and another switch s 0 Includes bar 809.

[0072] Capacitor C 1p One end of 801 is the node sp + is coupled to a capacitor c 1n One end of 810 is the node sp - is connected to the capacitor c 1p 801 and capacitor c 1n The other end of 810 is V cm is connected to.

[0073] Node sp + In addition, switch s 0 One side of 806, switch s 0 One side of the bar 808 and the switch s 1 804. 0 The other side of the 806 is the input v A+ The switch s 0 The other side of the bar 808 is connected to the input v A- The switch s 1 The other side of 804 is connected to a capacitor c 2p 802 is coupled to one side of the capacitor c 2p The other side of 802 is grounded.

[0074] Node sp - In addition, switch s 0 One side of the 807, switch s 0 One side of the bar 809 and the switch s 1 805. 0 The other side of the 807 is the input v A- The switch s 0 The other side of the bar 809 is the input v A+ The switch s 1 The other side of 805 is the capacitor c 2n 803 is coupled to one side of the capacitor c 2n The other side of 803 is grounded.

[0075] Various advantages offered by embodiments of the present invention will now be described.

[0076] One or more embodiments of the present invention provide a multiplier that uses only three capacitors for any bit precision requirement, resulting in significant savings in area and energy costs.

[0077] One or more embodiments of the present invention cover signed representations for both operands in a multiplication.

[0078] One or more embodiments of the present invention use differential inputs for higher signal integrity.

[0079] One or more embodiments of the present invention calculate a dot product that is a sum over many multiplication results.

[0080] One or more embodiments of the present invention perform mixed signal multiplication without an offset.

[0081] These and countless other attendant advantages of embodiments of the present invention may be readily determined by one of ordinary skill in the art given the teachings of the present invention provided herein.

[0082] The present invention may be a system, method, or computer program product, or both, at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium or media having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0083] A computer readable storage medium may be any tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, punch cards or mechanically encoded devices such as raised structures in grooves having instructions recorded thereon, and any suitable combination thereof. Computer-readable storage media, as used herein, should not be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves traveling through a waveguide or other transmission medium (e.g., light pulses through a fiber optic cable), or electrical signals through electrical wires.

[0084] The computer readable program instructions described herein can be downloaded from a computer readable storage medium to each computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or both. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or both. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and transfers the computer readable program instructions to a computer readable storage medium within the respective computing / processing device for storage.

[0085] The computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk, C++, and the like, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server, as a stand-alone software package. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions using state information of the computer readable program instructions to personalize the electronic circuitry to perform aspects of the invention.

[0086] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0087] These computer readable program instructions are provided to a processor of a computer or other programmable data processing apparatus to produce a machine such that the instructions are executed via the computer or other programmable data processing apparatus to produce means for performing the functions / acts specified in the block(s) of the flowcharts or block diagrams or both. These computer readable program instructions may also be stored in a computer readable storage medium that can instruct a computer, programmable data processing apparatus or other device or both in a particular manner, such that a computer readable storage medium having instructions stored therein comprises a product containing instructions that implement aspects of the functions / acts specified in the block(s) of the flowcharts or block diagrams or both.

[0088] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable data processing apparatus, or other device to perform a series of operational steps to create a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device perform the functions / acts specified in the block(s) of the flowcharts or block diagrams or both.

[0089] Reference herein to "one embodiment" or "one embodiment" of the invention, as well as other variations thereof, means that a particular feature, structure, characteristic, etc. described in connection with that embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification, as well as other variations thereof, do not necessarily all refer to the same embodiment. However, it should be recognized that features of one or more embodiments may be combined, given the teachings of the invention provided herein.

[0090] For example, " / ", "and / or" and "at least one" in "A / B", "A and / or B" and "at least one of A and B" are intended to encompass the selection of only the first listed alternative (A), the selection of only the second listed alternative (B), or the selection of both alternatives (A and B). As yet another example, in "A, B, and / or C" and "at least one of A, B, and C", such phrases are intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first and second listed alternatives (A, B), or the selection of only the first and third listed alternatives (A, C), or the selection of only the second and third listed alternatives (B, C), or the selection of all three alternatives (A and B and C). This can be extended to any number of listed items.

[0091] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur in a different order than that shown in the figures. For example, two blocks shown in succession may in fact be performed simultaneously, substantially simultaneously, partially or fully in a time-overlapping manner, or the blocks may sometimes be performed in reverse order, depending on the functionality involved. Furthermore, it should be noted that each block of the block diagrams or flowchart illustrations or both, and combinations of blocks in the block diagrams or flowchart illustrations or both, may be implemented by a dedicated hardware-based system that performs the specified functions or acts or performs or executes a combination of dedicated hardware and computer instructions.

[0092] Having described preferred embodiments of the system and method (intended to be illustrative and not limiting), it is noted that modifications and variations can be made by those skilled in the art in view of the above teachings. It is therefore understood that variations can be made to the particular embodiments disclosed which fall within the scope of the invention as outlined by the appended claims. Thus, having described aspects of the invention with the detail and particularity required by the patent laws, it is in the appended claims that it is desired to claim and protect by Letters Patent.

Claims

1. a plurality of mixed-signal multiplier branches for multiplying an analog value A by an N-bit digital value B; Each of the plurality of mixed signal multiplier branches comprises: a first capacitor having a first end connected to the second capacitor via a positive supply node and a switch, and a second end connected to the third capacitor via a negative supply node and another switch different from the switch, to provide a differential output between the second capacitor and a third capacitor; the capacitance of the first capacitor is equal to half the capacitance of the second and third capacitors; A differential mixed-signal logic processor.

2. a first set of switches including first, second, and third switches, each having a first end coupled to the positive supply node; a second set of switches including fourth, fifth, and sixth switches each having a first end coupled to the negative supply node; 2. The differential mixed signal logic processor of claim 1, further comprising: said third switch being said one switch and said sixth switch being said other switch.

3. 3. The differential mixed signal logic processor of claim 2, wherein second ends of the first and fourth switches are connected to a positive input voltage, second ends of the second and fifth switches are connected to a negative input voltage, a second end of the third switch is connected to a first end of the second capacitor and a positive output node, and a second end of the sixth switch is connected to a first end of the third capacitor and a negative output node.

4. The differential mixed-signal logic processor of claim 3 , wherein second ends of the second and third capacitors are connected to ground.

5. 3. The differential mixed signal logic processor of claim 2, wherein the first and second switches provide complementary inputs to the positive supply node and the fourth and fifth switches provide complementary inputs to the negative supply node.

6. The differential mixed-signal logic processor of claim 3 , wherein the differential mixed-signal logic processor is configured to calculate a dot product between a vector of analog values ​​and a vector of digital values.

7. 7. The differential mixed-signal logic processor of claim 6, wherein the differential mixed-signal logic processor is included in a system having at least one sensor and a memory device, and the vector of analog values ​​is received from the at least one sensor and the digital values ​​are received from the memory device.

8. 7. The differential mixed-signal logic processor of claim 6, wherein a sample mode samples the vector of analog values ​​and stores sample values ​​using a capacitor dedicated to a single branch in each of the plurality of mixed-signal multiplier branches.

9. 4. The differential mixed-signal logic processor of claim 3, wherein with respect to capacitors, each of the plurality of mixed-signal multiplier branches includes only three dedicated capacitors.

10. 4. The differential mixed signal logic processor of claim 3, wherein the various modes of the differential mixed signal logic processor include a reset mode, a sample mode, and an accumulate mode.

11. 4. The differential mixed signal logic processor of claim 3, wherein the positive supply node and the positive output node share charge and the negative supply node and the negative output node share charge during an accumulation mode of the differential mixed signal logic processor.

12. 4. The differential mixed signal logic processor of claim 3, wherein during a reset mode of the differential mixed signal logic processor, the positive supply node and the negative supply node have the same potential.

13. 4. The differential mixed signal logic processor of claim 3, wherein the first and second switches form a first switch pair and the fourth and fifth switches form a second switch pair, the switches in each of the first and second switch pairs being complementary to each other in providing either a positive input voltage or a negative input voltage at a given time.

14. a positive supply rail connected to the positive output node; a negative supply rail connected to the negative output node; Further comprising: The positive and negative supply rails are provided for multiplier and accumulator operations.

4. The differential mixed signal logic processor of claim 3.

15. 15. The differential mixed signal logic processor of claim 14, wherein a charge sharing operation is performed connecting the positive supply rail to the positive output node and the negative supply rail to the negative output node.

16. In the multiplication of the analog value A and the N-bit digital value B, the N-bit digital value B is [0010] and b ｎ 2. The differential mixed signal logic processor of claim 1, wherein: n is the binary value at the nth bit position.

17. each of a plurality of mixed signal multiplier branches for multiplying an analog value A and an N-bit digital value B includes a first capacitor having a first end connected to the second capacitor via a positive supply node and a switch, and a second end connected to the third capacitor via a negative supply node and another switch different from the switch, to provide a differential output between a second capacitor and a third capacitor; the capacitance of the first capacitor is equal to half the capacitance of the second and third capacitors; A method for forming a differential mixed signal processor.

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