Filtering methods and filters

Abstract

The present disclosure relates to a filtering method and a filter. The method comprises integrating the values ​​of an input signal (x[k]) by an integrator (2) comprising a storage device (22); storing the integrated value (y[k]) in the storage device; periodically resetting the storage device after integrating a first predetermined number (N1) of values ​​of the input signal; and generating an output signal (z[k]) based on the integrated value stored in the storage device in a stable operation mode after each integration of the first predetermined number of values ​​of the input signal. DEC ]); and in an initial operation mode, after integrating a second predetermined number (N2, N3, Nm) of values ​​of the input signal, generating an initial value of the output signal based on the integrated value stored in a storage device, wherein the second predetermined number is less than the first predetermined number.

Description

Technical Field

[0001] The present disclosure generally relates to a signal filtering method and a filter, and more specifically, to a low-pass filtering method and a low-pass filter. Background Art

[0002] Low pass filtering the signal may include calculating an average value of several consecutive signal values ​​of the signal. Calculating the average value may include integrating a predetermined number of consecutive signal values ​​of the input signal and generating an output signal value for each sequence of the predetermined number of consecutive signal values, the output signal value representing the result of the integration. However, in this method, there is a delay in the start of the filtering process because the first output signal value is not generated before the predetermined number of consecutive signal values ​​of the input signal are integrated.

[0003] There is a need for an improved low pass filtering method, particularly a low pass filtering method with reduced delay at the beginning of the filtering process. Summary of the invention

[0004] One example relates to a method. The method includes integrating a value of an input signal by an integrator including a storage device, storing the integrated value in the storage device; and periodically resetting the storage device after integrating a first predetermined number of values ​​of the input signal. The method further includes, in a stable operation mode, generating a value of an output signal based on the integrated value stored in the storage device after each integration of the first predetermined number of values ​​of the input signal; and in an initial operation mode, generating an initial value of the output signal based on the corresponding integrated value stored in the storage device after integrating a second predetermined number of values ​​of the input signal, wherein the second predetermined number is less than the first predetermined number.

[0005] Another example relates to a filter. The filter includes an integrator, a reset circuit, and an output circuit. The integrator includes a storage device, and the integrator is configured to sequentially integrate the value of the input signal and store the integrated value in the storage device. The reset circuit is configured to reset the storage device after integrating a first predetermined number of values ​​of the input signal. The output circuit is coupled to the storage device and is configured to generate a value of the output signal based on the integrated value stored in the storage device after each integration of the first predetermined number of values ​​of the input signal in a stable operation mode; and generate an initial value of the output signal based on the corresponding integrated value stored in the storage device after integrating a second predetermined number of values ​​of the input signal in an initial operation mode, wherein the second predetermined number is less than the first predetermined number. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following examples are described with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles and therefore only show aspects necessary for understanding these principles. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent similar features.

[0007] Figure 1 shows a signal waveform illustrating an example of a conventional method for low-pass filtering a signal;

[0008] Figure 2 A flow chart is shown which illustrates one example of an improved low pass filtering method;

[0009] Figure 3 Shows that it is possible to achieve Figure 2 An example of a filter of the method described in;

[0010] Figure 4 The signal waveform is shown, which illustrates the Figure 3 The function of the integrator and reset circuit in the filter;

[0011] Figure 5 Explained Figure 3 An example of an output circuit of a low pass filter is shown;

[0012] Figure 6 The signal waveform is shown, which illustrates the Figure 5 The output circuit shown here realizes the function of the filter;

[0013] Figure 7 Explained Figure 3 Another example of an output circuit of the filter shown;

[0014] Figure 8 The signal waveform is shown, which illustrates the Figure 7 The output circuit shown here functions as a low pass filter; and

[0015] Fig. 9 Instructions for use Figure 3 A filter of the type described in is used to determine the offset in the current measurement circuit. DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings are part of the specification and for illustrative purposes show examples of how the invention can be used and implemented. It should be understood that the features of the various embodiments described herein can be combined with each other unless otherwise specifically stated.

[0017] Figure 1A signal waveform is shown, which illustrates an example of a conventional method for low-pass filtering a discrete input signal x[k]. The conventional low-pass filtering method includes: for each of a plurality of sequences including a predetermined number of continuous values ​​of the input signal x[k], integrating the values ​​of each sequence to obtain a corresponding integral value. The method further includes generating an output signal y'[k] based on the integral value, so that the integral value obtained based on one sequence constitutes an output value of the output signal y'[k] until a new integral value based on the continuous sequence is obtained. However, the method results in a time delay between a first time instance and a second time instance, receiving a first signal value of the input signal x[k] at the first time instance and providing a first signal value of the output signal y'[k] at the second time instance. This is explained below.

[0018] Reference Figure 1 , the input signal x[k] may start at a first time instance t1, which is a time instance at which the filter ( Figure 1 The first value x[1] of the input signal is received (not shown). After integrating a predetermined number N1 of consecutive values ​​of the input signal x[k], a first value of the output signal y'[k] is output at a second time instance t2. The delay time T between the first time instance t1 and the second time instance t2 DEL Given by the following formula: T DEL =(N1-1)·T CLK =(N1-1) / f CLK , where N1 is a predetermined number, and T CLK =1 / f CLK is the sampling period, i.e. the inverse of the sampling frequency of the input signal x[k].

[0019] depends on the predetermined number N1 of signal values ​​to be integrated and the sampling frequency f of the input signal x[k] CLK , corresponding to the desired performance, the delay time T DEL The sampling frequency may be, for example, between 1 ms and 100 ms. The sampling frequency may be, for example, between 1 kHz and 10 kHz, and the predetermined number N1 may be, for example, selected between 100 and 2000. However, in many applications, delay times within this range are unacceptable. Therefore, a method for low-pass filtering an input signal is needed, the method having a reduced delay between the start of the input signal x[k] and the time instance when the first value of the output signal is provided.

[0020] Figure 2An example block diagram of a method for low pass filtering an input signal and providing a first value of an output signal with a reduced delay time is shown. The method comprises integrating (101) the value of the input signal by an integrator comprising a storage device, and periodically resetting the storage device (102) after a first predetermined number of values ​​of the input signal have been integrated. In the following, the "value of the input signal" is also referred to as the input signal value. Reference Figure 2 , the method further comprises, in a stable operating mode, outputting the value stored in the storage device each time after a first predetermined number of input signal values ​​have been integrated (103). Thus, in the stable operating mode, a new value is output each time a sequence of input signal values ​​comprising a predetermined number of input signal values ​​is integrated. The value stored in the storage device at the end of the integration process may be output once for each sequence of input signal values. According to another example, the same value is output multiple times until the signal values ​​of the next sequence of input signal values ​​have been integrated.

[0021] Reference Figure 2 The method further comprises, in the initial operation mode, outputting the initial value stored in the storage device after the second predetermined number of signal values ​​are integrated and before the first predetermined number of input signal values ​​are integrated (104). This can reduce the delay time between a time instance at which the integrator receives the first value of the input signal and another time instance at which the first value is output. In particular, the delay time is shorter than the first predetermined number minus one (N1-1) multiplied by the sampling frequency f CLK The inverse of T DEL <(N1-1) / f CLK This is explained in further detail below. In the following, the first predetermined number N1 is referred to as the predetermined number.

[0022] Figure 3 Describes the Figure 2 An example of filter 1 of the method shown. Figure 3 The filter 1 comprises an input 11 configured to receive an input signal x[k], and a filter 11 configured to output an output signal z[k] based on a low-pass filtering of the input signal x[k]. DEC ] output 12. As will be explained in further detail below, the output signal z[k DEC ] has a lower sampling frequency than the input signal x[k], so that the input signal x[k] and the output signal z[k DEC ] with different discrete time variables k and k DEC .

[0023] The filter 1 further comprises an integrator 2 connected to the input 11, an output circuit 3 downstream of the integrator 2 and connected to the output 12, and a reset circuit 4 connected to the integrator 2. The integrator 2 comprises a storage device 22, and the integrator is configured to integrate (sum) consecutive values ​​of the input signal x[k] and to store a new integrated value y[k] in the storage device 22 each time a new value of the input signal x[k] is received. The integrated value y[k] is available at the output 24 of the storage device 22, i.e., the output signal of the integrator 2 represents a sequence of integrated values ​​y[k] stored in the storage device 22. In the following, x[k] is used to represent the input signal and the value of the input signal. Equivalently, y[k] is used to represent the output signal y[k] of the integrator 22 and the integrated value.

[0024] It should be noted that Figure 3 The block diagram of the filter 1 shown illustrates the functional blocks of the filter in a specific embodiment. These functional blocks can be implemented in different ways. According to one example, dedicated circuits are used to implement these functional blocks. According to another example, the filter is implemented using hardware and software. For example, the filter includes a microcontroller and software running on the microcontroller. Therefore, the storage device 22 can include any kind of memory configured to store digital values. According to one example, the storage device includes a register. In addition, the output circuit 3 is not necessarily a dedicated electronic circuit, but can be implemented by the circuit of the microcontroller.

[0025] Reference Figure 3 , the adder 21 adds each incoming input signal value x[k] to the integral value currently stored in the storage device 22, wherein the result of this operation is received at the input 23 of the storage device 22 and is used to update the integral value stored in the storage device 22. Therefore, each integral value y[k] stored in the storage device 22 and available at the output of the storage device is given by the following formula:

[0026] y[k]=y[k-1]+x[k] (1),

[0027] That is, each integrated value y[k] is given by the integrated value y[k-1] previously stored in the storage device 22 plus the instantaneous signal value x[k] of the input signal. According to one example, x[1] represents the first signal value received by the filter 1, and before receiving the first signal value x[0], the integrated value (initial value) stored in the storage device 22 is zero. In this case, the first integrated value y[1] is given by the first signal value, y[1]=x[1]. The second integrated value y[2] is given by y[2]=x[2]+y[1]=x[2]+x[1], and so on.

[0028] Reference Figure 3, the reset circuit 4 is connected to the reset input 25 of the storage device 22. The reset circuit 4 is configured to reset the storage device 22 each time a predetermined number N1 of input signal values ​​x[k] are received and integrated (accumulated) by the integrator 2. Resetting the storage device includes setting the value stored in the storage device to a predetermined value, such as zero (0). According to one example, the reset circuit 4 receives a clock signal CLK, which defines the sampling frequency of the input signal x[k], counts a predetermined number N1 of clock cycles, and resets the storage device 22 each time N1 clock cycles pass. According to another example, the reset circuit 4 receives the input signal x[k], counts a predetermined number N1 of signal values ​​x[k] received by the integrator 2, and resets the storage device 22 each time N1 input signal values ​​x[k] are received. In the first case, the reset circuit 4 may additionally receive a start signal from a controller (not shown). The start signal may include information about the start of the input signal x[k], or may be a signal instructing the filter 1 to start operation. The controller may, for example, initiate the generation of the input signal x[k]. In the second case, the reset circuit can obtain information about the start of the input signal x[k] from the input signal itself.

[0029] Whenever the reset circuit 4 resets the storage device 22, a new integration sequence begins, wherein in each integration sequence a predetermined number N1 of input signal values ​​x[k] are integrated. In the following, the sequence of N1 input signal values ​​integrated before the storage device 22 is reset is referred to as an integration sequence.

[0030] The functions of the integrator 2 and the reset circuit 4 are Figure 4 , which illustrates an example of continuous input signal values ​​x[k] and corresponding integral values ​​y[k]. For illustrative purposes only, it is assumed that the input signal x[k] includes the same signal value x[k], so that the signal value of each integral sequence is the same and each time a new input signal value x[k] is received, the integral value y[k] is incremented, wherein the increment is given by the constant input signal value x[k]. Of course, in practice the input signal values ​​x[k] are not the same. In fact the input signal x[k] may include a low-frequency desired signal superimposed by a high-frequency noise signal. The integration performed by the integrator 2 has a low-pass filtering effect, thereby at least partially suppressing the noise signal.

[0031] Reference Figure 4, each time an input signal value x[k] is received, the storage device 22 outputs an integrated value y[k], so that each value of the input signal x[k] has a corresponding integrated value y[k]. Referring to the above, each time the integrator 2 receives a sequence of input signal values ​​x[k] having a predetermined number N1, the storage device 22 is reset by the reset circuit 4. The last integrated value before the storage device 22 is reset represents: the sum of the input signal values ​​x[k] included in the corresponding integrated sequence. These last integrated values ​​are Figure 4 Involving y[N1], y[2·N1], y[3·N1]. In general, the integral value y[k] can be expressed as follows based on the value of the input signal x[k]:

[0032]

[0033] Reference Figure 3 The output circuit 3 receives the integrated values ​​y[k] and generates an output signal z[k] based on these integrated values ​​y[k]. DEC ]. In the following, z[k DEC ] is used to represent the output signal and the signal value of the output signal.

[0034] After receiving a predetermined number N1 of input signal values ​​x[k] after the start of the input signal x[k], i.e. after the first resetting of the storage device 22, the output circuit 3 operates in a stable operation mode. In the stable operation mode, the output circuit outputs the last integrated value (see Figure 4 y[N1], y[2·N1], y[3·N1]), which is an integral value representing the sum of the input signal values ​​x[k] included in each integral sequence. Generally, in the stable operation mode, the output signal value z[k DEC ] is given by:

[0035] z[k DEC ]=y[k DEC ·N1] (3a).

[0036] Equation (3a) represents an ideal situation and does not take into account possible delays between providing the integrated value y[k] in the storage device 22 and generating the output signal z[k DEC ]. More generally,

[0037] z[k DEC ]=y[k DEC ·N1+τ] (3b),

[0038] where τ represents the delay between providing the integrated value y[k] in the storage device 22 and generating the output signal z[k DEC ]. This delay may be caused by processing the integrated value y[k] in the output circuit 3.

[0039] In the initial operation mode, during a first integration sequence of input signal values ​​x[k], the output circuit 3 outputs at least one of the integration values ​​y[1] ... y[N1-1] output by the storage device 22. The "first integration sequence" includes signal values ​​of the input signal immediately after the start of the input signal x[k] or after the filter is enabled to start integrating the input signal x[k]. According to one example, the input signal x[k] starts when a signal value different from a predetermined initial signal value (e.g., zero) occurs after the input signal x[k] has had an initial signal value for more than a predetermined time period. In this case, the filter 1 decides when to start operation, i.e., when to start the first integration sequence, based on the input signal x[k]. According to another example, a controller, such as the controller mentioned above, instructs the filter 1 to start operation. In this case, the controller defines the start of the first integration sequence, wherein already before the start of the first integration sequence, the input signal x[k] may have a signal value different from zero. However, this signal value may not be processed by the filter 1.

[0040] Figure 5 An example of the output circuit 3 configured to operate in the initial operation mode or the stable operation mode is described. Figure 5 The output circuit 3 comprises: a first down-sampling circuit 321 and at least one other down-sampling circuit 322 to 32 m , among which Figure 5 In the example shown, the output circuit 3 includes three further down-sampling circuits 322 to 32 m However, this is only an example. The other down-sampling circuits 322 to 32 m The number of the first down-sampling circuit 321 and the at least one additional down-sampling circuit 322 to 32 m Each of the downsampling circuits 321, 322, 323, 324 receives the integrated value y[k]. m The downsampled signal y is generated by downsampling the sequence of integrated values ​​y[k]. N1 [k N1 ]、y N2 [k N2 ]、y N3 [k N3 ]、y Nm [k Nm ]. In the following, y N1 [k N1 ] to y Nm [k Nm ] is used to represent the downsampling circuit 321 to 32 mIt must be noted that the principle functionality of the proposed filter 1 is also valid if additional downsampling stages are included before / after the filter 1 and / or from the output of the integrator 2 to the input of the output circuit 3.

[0041] Each down-sampling circuit 321 to 32 m The downsampling factor of the first downsampling circuit 321 is equal to the predetermined number N1, and the downsampling factor of the other downsampling circuits 322 to 32 m The downsampling factors N2, N3, Nm are less than the predetermined number N1. Each downsampling circuit 32 i is configured to: sample each Ni-th integrated value of the sequence of integrated values ​​y[k] and output the sampled signal value (where 32 i The downsampling circuit 321 to 32 m Any one of the above, and Ni represents the corresponding downsampling circuit 32 i Downsampling circuit 32 i The output signal y Ni [k Ni ] is less than the sampling frequency of the integrator output signal y[k]. In addition, due to the different downsampling factors N2, N3, and Nm, the downsampling circuit 32 i The output signal y Ni [k Ni ] is sampled at different frequencies (hence using different discrete time variables k N2 , k N3 , k Nm ). Usually, these signals y Ni [k Ni ] is 1 / Ni times the sampling frequency of the input signal x[k], and the downsampling circuit 32 i The output signal value y Ni [k Ni ] is given by:

[0042] y Nt [k Nt ]=y[k Nt ·Ni+τ t ] (4),

[0043] where τ i represents the delay of the i-th down-sampling circuit. The multiplexer 31 receives the delay of each down-sampling circuit 32. i Receive output signal y Ni [k Ni ], and based on these downsampled signals y Ni [k Ni] generates the output signal z[k DEC The multiplexer 31 is controlled by the operation mode controller 33, wherein the operation mode controller 33 is configured to: control the multiplexer 31 so that in the stable operation mode, the output signal y of the first down-sampling circuit 321 is output N1 [k N1 ] as the output signal z[k DEC ]. That is, in the stable operation mode z[k DEC ]=y N1[ k N1 ]. Therefore, in the stable operation mode, the output signal z[k DEC ] is 1 / N1 times the sampling frequency of the input signal x[k].

[0044] In the initial operation mode, the operation mode controller controls the multiplexer 31 so that the additional down-sampling circuits 322 to 32 m A downsampled signal y generated by N2[ k N2 ] to y Nm [k Nm ] as the output signal z[k DEC ]output.

[0045] The operation mode controller 33 operates the output circuit 3 in the stable operation mode or the initial operation mode by appropriately controlling the multiplexer 31. According to one example, the operation mode controller 33 receives a clock signal CLK, which defines the sampling frequency of the input signal x[k] and a start signal START. The start signal either includes information about when the input signal x[k] starts, or is a signal that instructs the output circuit 3 to start operating. After being instructed to start the operation by the start signal START, the operation mode controller 33 counts the clock cycles of the clock signal and operates the output circuit 3 in the stable operation mode or the initial operation mode. More specifically, within a predetermined number N1 of clock cycles after the start, the operation mode controller 33 operates the output circuit 3 in the initial operation mode, and then operates the output circuit in the stable operation mode. Alternatively, the operation mode controller 33 receives the input signal x[k], detects the start of the input signal x[k], counts the signal value of the input signal x[k], and causes the output circuit 3 to operate in the stable operation mode or the initial operation mode.

[0046] After receiving N1 input signal values ​​x[k], the multiplexer 31 outputs the down-sampled signal y of the first down-sampling circuit 321. N1 [k N1 ] as the output signal z[k DEC], the operation mode controller 33 can operate the output circuit in the stable operation mode. Equivalently, when the output circuit 3 is instructed to start operating, or when the filter 1 receives the first signal value of the input signal x[k], and until the predetermined number N1 of signal values ​​are received, the operation mode controller 33 can operate the output circuit 3 in the initial operation mode. In the initial operation mode, operating the output circuit 3 includes: causing the multiplexer 31 to output the additional down-sampling circuit 32 i The output signal y of a down-sampling circuit N2[ k N2 ] to y Nm [k Nm ], as the output signal z[k DEC ].

[0047] Referring to the above, the other down-sampling circuits 322, 323, 32 m The downsampling factors N2, N3, Nm of the first downsampling circuit 321 are smaller than the downsampling factor N1 of the first downsampling circuit 321. Therefore, after the start of the input signal x[k] or after the filter 1 starts to operate, the output signal y of the first downsampling circuit 321 is obtained. N1 [k N1 ] before obtaining the first signal value of each additional downsampling circuit 322 to 32 m The output signal y N2[ k N2 ] to y Nm [k Nm ] corresponding to the first value. Typically, after the filter 1 receives Ni input signal values ​​x[k], where Ni<N1, another downsampling circuit 32 is obtained. i The output signal y of any one of Ni [k Ni ] is the first value. Ni corresponds to the second predetermined number mentioned above. By (Ni-1) / f CLK Given: the start of the input signal x[k], or the start of the operation of filter 1 and the provision of the output signal z[k DEC ], which is shorter than (N1-1) / f in the conventional method. CLK .

[0048] Figure 3 The filter 1 of the described type is particularly suitable for filtering an input signal having a low-frequency signal component and a superimposed high-frequency (noise) signal component. The filter suppresses the high-frequency signal component by integrating the input signal value x[k]. In this case, the larger the predetermined number N1, the better the high-frequency signal component is suppressed, and the output signal z[k DEC] represents the low-frequency signal components more accurately. In the initial operation mode, the integration sequence is shorter than in the stable operation mode, that is, the output signal z[k DEC ] is based only on Ni input signal values ​​x[k] (where i=2…m) instead of N1 input signal values ​​x[k] in the stable operation mode. Therefore, the signal value z[k] of the output signal in the stable operation mode is DEC ] compared to at least one signal value z[k DEC ] may be less accurate. Nevertheless, as the delay time decreases, at least one signal value provided in the initial operating mode provides a good first order approximation.

[0049] According to one example, in the initial operation mode, the operation mode controller 33 controls the multiplexer so that the additional down-sampling circuits 322 to 32 m The output signal y N2[ k N2 ] to y Nm [k Nm ] is used as the output signal z[k DEC In this case, the operation mode controller may select the additional down-sampling circuits 322 to 324 based on predetermined criteria such as the length of an acceptable delay time. m one of the.

[0050] According to another example, in the initial operation mode, the operation mode controller 33 controls the multiplexer so that the additional down-sampling circuits 322 to 32 m The output signal y N2[ k N2 ] to y Nm [k Nm ] are sequentially used as output signals z[k DEC ] output. If, for example, Nm<N3<N2, the operation mode controller can control the multiplexer 31 so that

[0051] (a) After receiving Nm signal values ​​of the input signal x[k], the downsampling circuit 32 m The output signal y Nm [k Nm ] is taken as the output signal z[k DEC ]output;

[0052] (b) After receiving N3 signal values ​​of the input signal x[k], the output signal y of the downsampling circuit 323 N3 [k N3 ] is taken as the output signal z[k DECOutput; and (c) after receiving N2 signal values of the input signal x[k], the output signal y of the decimation circuit 322 N2 [k N2 is output as the output signal z[k DEC .

[0053] In this way, after the filter 1 receives Nm input signal values x[k], the first signal value of the output signal z[k DEC is provided, after the filter 1 receives N3 input signal values x[k], an updated signal value is provided, and after the filter 1 receives N2 input signal values x[k], another updated signal value is provided, where the accuracy increases with each updated signal value because the number of input signal values x[k] on which the corresponding updated signal value is based increases.

[0054] Figure 6 A signal diagram showing an example of the input signal x[k] and the corresponding output signal z[k DEC generated in the above manner is shown. Referring to Figure 6 , the first signal value of the output signal z[k DEC is generated after Nm input signal values x[k]. This first signal value is given by y[Nm], and the associated delay time is Nm / f CLK . An updated signal value y[N3] is generated after N3 input signal values x[k], where the associated delay time is N3 / f CLK , and so on. When N1 input signal values x[k] are received and the output signal y N1 [k N1 is output as the output signal z[k DEC , the filter enters the stable operation mode.

[0055] The first predetermined number N1 and the second predetermined numbers N2 to Nm can be arbitrary. The first predetermined number N1 can be selected such that a satisfactory filtering result is obtained based on the desired frequency of the high-frequency components to be filtered out. The second predetermined numbers N2 to Nm can be appropriately selected to reduce the waiting time until the first output signal value is generated. According to one example, the first predetermined number N1 is a power of 2, so N1 = 2 n , where n is an integer greater than 3. In addition, each of N2, N3, Nm is a power of 2, that is, each of N2, N3, Nm can be expressed as 2 p , where 1 < p < n. For example, N1 = 256 (= 2 8 ), N2 = 128 (= 2 7 ), N3 = 64 (= 2 6) and N2=32(=2 5 ).

[0056] exist Figure 6 In the example described, in the initial operation mode, the output signal value z[k DEC ] simply corresponds to the additional downsampling circuit 32 i The output signal y of a down-sampling circuit Ni[ k Ni ], where i = 2 ... m, wherein the output signal is substantially equal to the sum of the Ni input signal values. i are different, so in the initial operation mode, the output signal z[k DEC ] increases with each update (even when the low-frequency signal components of the input signal x[k] do not change). This may be undesirable and can be prevented by: m , each additional downsampling circuit 322 to 32 m The output signal y N2[ k N2 ] to y Nm [k Nm ] are multiplied by the corresponding scaling factors s2, s3, sm. According to one example, these scaling factors are proportional to the predetermined number N1 and are proportional to the corresponding further downsampling circuits 322 to 32 m According to one example, si=N1 / Ni, where si is any one of the scaling factors s2 to sm, and Ni is the corresponding downsampling circuit 32 i The downsampling factor. Figure 8 Shown by Figure 7 The output signal z[k DEC ] signal diagram.

[0057] The scaling operation performed by the scaling circuit may include a shift or bit drop operation and does not necessarily include a multiplier. For example, assuming the downsampled signal y N2[ k N2 ] to y Nm [k Nm Each signal value of ] is represented by a digital word comprising a number of u bits. Furthermore, it is assumed that the scaling factor denoted si is si=2 v In this case, scaling of the downsampled signal value represented by the u-bit digital word is obtained by discarding the v least significant bits in the case of negative v or adding the v least significant bits in the case of positive v. A similar situation can be achieved by a shift operation in software, so that in the case of positive v, it is a left shift operation and in the case of negative v, it is a right shift operation. In addition, 0 bits are shifted or discarded, that is, si = 2 v=2 0 , is considered to be scaled by a factor of 1 and inherently exists in Figure 7 is within the range of s0, s1, s2, s3 or sm.

[0058] According to one example, Figure 7 As shown in dashed lines in FIG. 3 , the output signal of the first down-sampling circuit 341 is scaled by the first scaling factor s1. In this case, the output signal of the further down-sampling circuits 342 to 34 m The scaling factor s2 to s m Adapted to the first scaling factor s1, so that

[0059] exist Figure 5 and Figure 7 In each of the examples described, the integrated value y[k] may be multiplied by an arbitrary scaling factor s0 (33) by a multiplier, a shift operation, or a bit addition / dropping so that the downsampling circuits 321 to 32 m A scaled version of the integrated value y[k] is received. The scaling factor s0 may be chosen to be equal to 1 / N1, 1 / Ni or any other number so that the corresponding further scaling factors s1 to sm are selected such that the total downsampling path scaling ratio is 1 / N1 for 321, N2 for 322, 1 / N3 for 323, and so on. The scaling factors are selected to achieve greater or lesser downsampling path scaling, e.g. to meet (output) bit width requirements, without violating this principle. The downsampling path starts at the integrator output 24 and ends at the filter output 12.

[0060] Fig. 9 An example of a current measurement circuit is illustrated in which a filter 1 of the type described herein before is implemented. The current measurement circuit comprises an analog current sensor 51 configured to sense a load current I in a conductor LOAD , and generates a representative load current I LOAD The analog current measurement signal s(t) is obtained by the current sensor 51. The current sensor 51 can be any type of analog current sensor, such as a sensor including a shunt resistor, a Hall sensor, etc. The current measurement signal s(t) may include high-frequency noise signals that may be introduced by the sensor. It is therefore desirable to low-pass filter the current measurement signal s(t) and provide a low-pass filtered discrete current measurement signal at the output of the current measurement circuit. To this end, the current measurement circuit includes an analog-to-digital converter (ADC) that receives an analog input signal and provides a discrete (digital) version of the analog current measurement signal s(t). The first low-pass filter 53 receives the discrete current measurement signal s[k] and provides a low-pass filtered current measurement signal s LP_OFF [k] The first filter 53 may be any type of digital low pass filter.

[0061] Inevitably, the ADC introduces an offset, making the discrete current measurement signal s[k] and thus the low-pass filtered current measurement signal s LP_OFF [k] includes an offset. This offset may distort the measurement result, so it is necessary to compensate for the offset. Therefore, the current measurement circuit includes an offset compensation circuit that provides an estimate of the offset and subtracts the output signal s of the first filter 53 from the output signal s of the first filter 53 through a subtractor 57. LP_OFF This estimate is subtracted from [k] to provide a low pass filtered current measurement output signal s LP[ k]. Fig. 9 In the illustrated example, filter 1 is part of an offset compensation circuit, and the output signal z[k DEC ] represents an estimate of the offset.

[0062] Reference Fig. 9 , the offset compensation circuit includes a second low-pass filter receiving the discrete current measurement signal s[k] and an offset estimator 56 downstream of the second low-pass filter. The second filter 54 can be any kind of digital low-pass filter. The offset estimator estimates the offset using a chopping method. In this case, the analog current measurement signal is multiplied by a chopping signal through a first multiplier, and the chopping signal alternates between -1 and +1. The chopping operation introduced by the first multiplier is inverted by a second multiplier 552 connected downstream of the second filter 54. Because the offset signal is introduced after the analog current measurement signal s(t) is multiplied by the chopper signal, the second multiplier 552 inverts the chopping operation, which is performed on the signal component generated by the analog current measurement signal s(t), but not on the offset. Therefore, the output signal of the second multiplier includes a signal component and a second signal component, the signal component is a low-pass filtered version of the analog current measurement signal s(t), and the second signal component corresponds to the offset multiplied by the chopping signal. The offset estimator 56 receives the output signal of the second multiplier 552 and the chopped signal and is configured to provide an estimate of the offset based on these signals. However, the estimate may still contain noise, so further low-pass filtering by the low-pass filter 1 is required.

[0063] Referring to the above, using the second filter and the offset estimator 56 to estimate the offset includes: multiplying the analog input signal s(t) and the output signal of the second filter 54 by the chopped signal. Unless further measures are taken, the chopping operation, in particular the multiplication of the analog input signal s(t) by the chopped signal, will cause the output signal s(t) of the first filter to be LP_OFFInvalid. According to one example, a further multiplier (not shown) equivalent to the second multiplier is connected downstream of the first filter 53. According to another example, the first filter 53 and the offset estimator 56 operate alternately. That is, there are one or more time periods during which the offset estimator 56 is in operation and the chopping signal is in an active state (i.e., alternating between -1 and +1), and there are one or more time periods in which the first filter 53 is in operation and the chopping signal is inactive (having a constant signal level of +1). The output signal z[k DEC ] is stored in a storage device 58 such as a register, making it available at the subtractor during those time periods when the first filter 53 is active.

[0064] Although the present disclosure is not limited in this regard, the following numbered examples illustrate one or more aspects of the present disclosure.

[0065] Example 1. A method, comprising: integrating the value of an input signal through an integrator including a storage device; storing the integrated value in the storage device; periodically resetting the storage device after integrating a first predetermined number of values ​​of the input signal; in a stable operation mode, generating a value of an output signal based on the integrated value stored in the storage device after each integration of the first predetermined number of values ​​of the input signal; and in an initial operation mode, generating an initial value of the output signal based on the integrated value stored in the storage device after integrating a second predetermined number of values ​​of the input signal, wherein the second predetermined number is less than the first predetermined number.

[0066] Example 2. The method of Example 1, wherein generating the initial value of the output signal comprises generating two or more initial values ​​of the output signal.

[0067] Example 3. A method according to Example 2, wherein each of the two or more initial values ​​of the output signal is generated after integrating the second predetermined number of values ​​of the input signal, wherein the second predetermined number is different for each of the two or more initial values ​​of the output signal.

[0068] Example 4. A method according to any of the preceding examples, wherein the first predetermined number is 2 n , where n is an integer greater than 3.

[0069] Example 5. The method of Example 4, wherein n is selected from 4 to 10.

[0070] Example 6. The method of Example 3, wherein the first predetermined number is 2n , wherein n is an integer greater than 3, and wherein the second predetermined number is 2 p , where p is an integer and 1<p<n.

[0071] Example 7. A method according to any one of Examples 1 to 6, wherein generating the initial value of the output signal based on the corresponding integral value stored in the storage device includes: generating the initial value of the output signal so that the initial value is equal to the corresponding integral value stored in the storage device.

[0072] Example 8. A method according to any one of Examples 1 to 6, wherein generating the initial value of the output signal based on the corresponding integral value stored in the storage device includes: generating the initial value of the output signal so that the initial value is equal to the corresponding integral value stored in the storage device multiplied by a corresponding scaling factor.

[0073] Example 9. The method according to any of the preceding examples further comprises: in order to provide a first downsampled signal, downsample the sequence of integrated values ​​provided by the integrator using a first downsampled factor; in order to provide at least one additional downsampled signal, downsample the sequence of integrated values ​​using at least one additional downsampled factor; in the stable operating mode, outputting the first downsampled signal as the output signal; and in the initial operating mode, outputting the at least one additional downsampled signal as the output signal.

[0074] Example 10. The method of Example 9, wherein the first downsampling factor is greater than the at least one additional downsampling factor.

[0075] Example 11. A filter, comprising: an integrator, comprising a storage device, and the integrator is configured to integrate the values ​​of an input signal in sequence and store the integrated values ​​in the storage device; a reset circuit, configured to reset the storage device after integrating a first predetermined number of values ​​of the input signal; and an output circuit, coupled to the storage device, wherein the output circuit is configured to: in a stable operating mode, generate a value of the output signal based on the integrated value stored in the storage device after each integration of the first predetermined number of values ​​of the input signal; and in an initial operating mode, generate an initial value of the output signal based on the integrated value stored in the storage device after integrating a second predetermined number of values ​​of the input signal, wherein the second predetermined number is less than the first predetermined number.

[0076] Example 12. The filter of Example 11, wherein the output circuit is configured to generate two or more initial values ​​of the output signal.

[0077] Example 13. A filter according to Example 12, wherein the output circuit is configured to generate each of the two or more initial values ​​of the output signal after integrating the second predetermined number of values ​​of the input signal, wherein the second predetermined number is different for each of the two or more initial values ​​of the output signal.

[0078] Example 14. The filter according to any one of Examples 11 to 13, wherein the first predetermined number N1 is 2 n , where n is an integer greater than 3.

[0079] Example 15. A filter according to Example 14, wherein n is selected from between 4 and 10.

[0080] Example 16. The filter of Example 13, wherein the first predetermined number (N1) is 2 n , wherein n is an integer greater than 3, and wherein the second predetermined number is 2 m , where m is an integer and 1<m<n.

[0081] Example 17. A filter according to any one of Examples 11 to 16, wherein the output circuit is configured to: generate the initial value of the output signal based on the corresponding integral value stored in the storage device by generating the initial value of the output signal, so that the initial value is equal to the corresponding integral value stored in the storage device.

[0082] Example 18. A filter according to any one of Examples 11 to 16, wherein the output circuit is configured to: generate the initial value of the output signal based on the corresponding integral value stored in the storage device by generating the initial value of the output signal, so that the initial value is equal to the corresponding integral value stored in the storage device multiplied by the corresponding scaling factor.

[0083] Example 19. A filter according to any one of Examples 11 to 18, wherein the output circuit includes a first downsampling circuit and at least one additional downsampling circuit, each downsampling circuit is configured to receive a series of integrated values ​​stored in the storage device, and wherein the output circuit is further configured to: in the stable operating mode, output the output signal of the first downsampling circuit as the output signal; and in the initial operating mode, output the output signal of the at least one additional downsampling circuit as the output signal.

[0084] Example 20. The filter of Example 19, wherein a downsampling factor of the first downsampling circuit is greater than a downsampling factor of the at least one additional downsampling circuit.

[0085] Although the present invention has been described with reference to illustrative examples, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative examples and other examples of the present invention will be apparent to those skilled in the art by reference to the description. It is therefore intended that the appended claims include any such modifications or examples.

Claims

1. A method comprising: integrating the value of the input signal x[k] by means of an integrator (2) including a storage device (22); storing the integrated value y[k] in the storage device (22); periodically resetting the storage device (22) after integrating a first predetermined number N1 of values ​​of the input signal x[k]; In a stable operation mode, after each integration of the first predetermined number N1 of values ​​of the input signal x[k], an output signal z[k] is generated based on the integrated value y[k] stored in the storage device (22). DEC ]; and In an initial operation mode, after integrating a second predetermined number N2, N3, Nm of values ​​of the input signal x[k], the output signal z[k] is generated based on the integrated value y[k] stored in the storage device (22). DEC ] is an initial value of, wherein the second predetermined number N2, N3, Nm is smaller than the first predetermined number N1.

2. The method according to claim 1, wherein: Generate the output signal z[k DEC ] includes generating the output signal z[k DEC ] two or more initial values.

3. The method according to claim 2, in, After integrating the second predetermined number Nm, N3, N2 of values ​​of the input signal x[k], the output signal z[k] is generated. DEC ] each of the two or more initial values, The second predetermined numbers Nm, N3, N2 are related to the output signal z[k DEC ] Each of the two or more initial values ​​is different.

4. The method according to any one of claims 1 to 3, wherein: The first predetermined number N1 is 2 n , where n is an integer greater than 3.

5. The method according to claim 4, wherein: Choose n from 4 to 10.

6. The method according to claim 3, in, The first predetermined number N1 is 2 n , where n is an integer greater than 3, and Wherein, the second predetermined number Nm, N3, N2 is 2 p , where p is an integer and 1<p<n.

7. The method according to any one of claims 1 to 6, wherein: The output signal z[k] is generated based on the corresponding integrated value y[k] stored in the storage device (22) DEC ] includes: Generate the output signal z[k DEC ] so that the initial value is equal to the corresponding integrated value y[k] stored in the storage device (22).

8. The method according to any one of claims 1 to 6, wherein: The output signal z[k] is generated based on the corresponding integrated value y[k] stored in the storage device (22) DEC ] includes: Generate the output signal z[k DEC ] so that the initial value is equal to the corresponding integrated value y[k] stored in the storage device (22) multiplied by the corresponding scaling factors s2, s3, sm.

9. The method according to any one of claims 1 to 8, further comprising: To provide a first downsampled signal y N1 [k N1 ], downsampling the sequence of integrated values ​​y[k] provided by the integrator using a first downsampling factor N1; To provide at least one further downsampled signal y N2 [k N2 ] to y Nm [k Nm ], downsampling said sequence of integrated values ​​y[k] using at least one further downsampling factor N2 to Nm; In the stable operation mode, the first down-sampled signal y is output N1 [k N1 ] as the output signal z[k DEC ];and In the initial operation mode, the at least one further downsampled signal y is output N2 [k N2 ] to y Nm [k Nm ] as the output signal z[k DEC ].

10. The method according to claim 9, wherein: The first downsampling factor N1 is greater than the at least one further downsampling factor N2 to Nm.

11. A filter comprising: An integrator (2) comprising a storage device (22), wherein the integrator is configured to sequentially integrate the values ​​of the input signal x[k] and store the integrated value y[k] in the storage device (22); a reset circuit (4) configured to reset the storage device (22) after integrating a first predetermined number N1 of values ​​of the input signal x[k]; and An output circuit (3) is coupled to the storage device (22), wherein the output circuit (3) is configured to: In a stable operation mode, after each integration of the first predetermined number N1 of values ​​of the input signal x[k], an output signal z[k] is generated based on the integrated value y[k] stored in the storage device (22). DEC ]; and In an initial operation mode, after integrating a second predetermined number N2, N3, Nm of values ​​of the input signal x[k], the output signal z[k] is generated based on the integrated value y[k] stored in the storage device (22). DEC ], wherein the second predetermined number N2, N3, Nm is smaller than the first predetermined number N1.

12. The filter according to claim 11, wherein The output circuit (3) is configured to generate the output signal z[k DEC ] two or more initial values.

13. The filter according to claim 12, in, The output circuit is configured to generate the output signal z[k] after integrating the values ​​of the second predetermined number Nm, N3, N2 of the input signal x[k]. DEC ] each of the two or more initial values, The second predetermined numbers Nm, N3, N2 are related to the output signal z[k DEC ] Each of the two or more initial values ​​is different.

14. The filter according to any one of claims 11 to 13, wherein: The first predetermined number N1 is 2 n , where n is an integer greater than 3.

15. The filter according to claim 14, wherein Choose n from 4 to 10.

16. The filter according to claim 13, in, The first predetermined number N1 is 2 n , where n is an integer greater than 3, and Wherein, the second predetermined number Nm, N3, N2 is 2 m , where m is an integer and 1<m<n.

17. The filter according to any one of claims 11 to 16, in, The output circuit (3) is configured to generate the output signal z[k DEC ], generating the output signal z[k] based on the corresponding integral value y[k] stored in the storage device (22) DEC ] so that the initial value is equal to the corresponding integral value stored in the storage device (22).

18. The filter according to any one of claims 11 to 16, in, The output circuit (3) is configured to generate the output signal z[k DEC ], generating the output signal z[k] based on the corresponding integral value y[k] stored in the storage device (22) DEC ] so that the initial value is equal to the corresponding integral value stored in the storage device (22) multiplied by the corresponding scaling factors s2, s3, sm.

19. The filter according to any one of claims 11 to 18, in, The output circuit (3) comprises a first down-sampling circuit (321) and at least one other down-sampling circuit (322 to 32 m ), each down-sampling circuit is configured to receive a series of integrated values ​​y[k] stored in the storage device (22), and Wherein, the output circuit (3) is further configured as follows: In the stable operation mode, the output signal y of the first down-sampling circuit (321) is output N1 [k N1 ] as the output signal z[k DEC ];and In the initial operation mode, the output of the at least one additional down-sampling circuit (322 to 32 m )’s output signal y N2 [k N2 ] to y Nm [k Nm ] as the output signal z[k DEC ].

20. The filter according to claim 19, wherein The downsampling factor N1 of the first downsampling circuit (321) is greater than that of the at least one other downsampling circuit (322 to 32 m ) downsampling factor N2 to Nm.

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