Storage circuit, data transmission circuit and memory

Abstract

The present disclosure relates to a storage circuit, a data transmission circuit, and a memory. The storage circuit includes at least one storage structure arranged parallel to a data transmission area, and each storage structure includes a first memory array and a second memory array arranged adjacent to each other in a first direction. A distance between the first memory array and the data transmission area is smaller than a distance between the second memory array and the data transmission area, and the first direction is a direction close to the data transmission area. The first memory array includes a read / write module and a transfer module, and the second memory array includes a read / write module, and the first memory array performs data interaction with the data transmission area based on the read / write module in the first memory array. The second memory array performs data interaction with the data transmission area based on the read / write module in the second memory array and the transfer module in the first memory array.

Description

[Technical field]

[0001] This disclosure relates to, but is not limited to, storage circuits, data transmission circuits, and memories.

[0002] Dynamic random access memory (DRAM) has characteristics such as non-volatility of data, low power consumption, small volume, and no mechanical structure, and is suitable as a storage device for mobile devices.

[0003] With the advancement of technology, consumers have higher and higher performance requirements for mobile devices, and the transmission speed of storage devices has become a key parameter for evaluating whether a storage device is superior. Summary of the Invention [Problem to be solved by the invention]

[0004] To overcome the problems existing in the related art, the present disclosure provides a storage circuit, a data transmission circuit and a memory, thereby improving the transmission efficiency of data read and write in the memory and ensuring the accuracy of data transmission.

[0005] In an exemplary embodiment of the present disclosure, a storage circuit is provided, comprising at least one storage structure disposed adjacent to and parallel to a data transmission region, each storage structure including a first memory array and a second memory array disposed adjacent to each other in a first direction. A distance between the first memory array and the data transmission region is smaller than a distance between the second memory array and the data transmission region, and the first direction is a direction adjacent to the data transmission region. The first memory array includes a read / write module and a transfer module, and the second memory array includes a read / write module, and the first memory array performs data interaction with the data transmission region based on the read / write module in the first memory array. The second memory array performs data interaction with the data transmission region based on the read / write module in the second memory array and the transfer module in the first memory array.

[0006] By installing the transfer module, when data is read and written to the second memory array, the data does not pass through the read and write module of the first memory array, so that the data transmission paths of the first memory array and the second memory array are separated, and then the data in the first memory array and the second memory array can be read and written alternately, which further reduces the difference in the read delay of data in different memory arrays, prevents the read data with long delay from blocking the read data with short delay, and improves the data transmission margin. In addition, by separating the data transmission paths of the first memory array and the second memory array, in the process of reading and writing data, the data transmission direction can be confirmed only by determining whether the data belongs to a write process or a read process, and avoids the complicated data path determination process when the same data transmission path is used, thereby achieving a higher data transmission rate and higher data transmission accuracy.

[0007] In one exemplary embodiment, the first memory array and the second memory array include an even number of memory blocks arranged consecutively in a first direction, and every two adjacent non-overlapping memory blocks share one read / write module, and the read / write module is arranged between two corresponding memory blocks.

[0008] In one exemplary embodiment, the memory block further includes a plurality of memory sub-blocks arranged consecutively in a second direction perpendicular to the first direction, and the plurality of memory sub-blocks share the same read / write module.

[0009] In one exemplary embodiment, the read / write module in the first memory array and the read / write module in the second memory array are both arranged along a first direction, and the transfer module is arranged on the opposite side of the read / write module in a second direction perpendicular to the first direction. By regularly arranging the read / write module and the transfer module, the data transmission line between the read / write module and the transfer module can be regularly arranged, and the resistance of the data transmission line can be reduced through the shortest data transmission line, and the rate and accuracy of data transmission can be improved.

[0010] In one exemplary embodiment, a transfer module is provided opposite each read / write module, and the short-distance transmission and multiplexing of data between multiple transfer modules reduces the possibility of errors occurring during the data transmission process.

[0011] In one exemplary embodiment, the data transmission conductors between the read / write module, the transfer module and the data transmission area are disposed between adjacent power conductors, and the power conductors are configured to receive and transmit power signals and provide power signals to the first memory array and the second memory array. Disposing the data transmission conductors between the power conductors does not further increase the layout area occupied by the memory array.

[0012] In one exemplary embodiment, the data transmission conductor includes a lower transmission conductor and an upper data conductor, where the lower transmission conductor is arranged to transmit lower data in the memory array, and the upper transmission conductor is arranged to transmit upper data in the memory array, thereby further improving data transmission efficiency and data transmission accuracy.

[0013] In an exemplary embodiment of the present disclosure, a data transmission circuit is further provided, the data transmission circuit being disposed in a data transmission area, and including at least two data transmission structures, each of which is connected to at least one of the storage circuits provided in the above embodiment, and configured to read and write data from and to the storage circuits. Each data transmission structure includes a storage transmission end, a bus transmission end, and an interactive transmission end, where the storage transmission end is configured to connect the storage circuit, the bus transmission end is configured to connect the data bus, and the interactive transmission end is configured to connect other data transmission structures. Data input from the storage transmission end is output via the bus transmission end or the interactive transmission end, data input from the bus transmission end is output via the storage transmission end or the interactive transmission end, and data input from the interactive transmission end is output via the bus transmission end or the storage transmission end. Here, the data input from the interactive transmission end is data input from the bus transmission end or the storage transmission end in the other data transmission structure. The control module is connected to the data transmission structure, and receives the input control signal and the adjustment control signal provided by the associated memory. The control module is arranged to generate an output control signal corresponding to the input control signal by performing a delayed output on the input control signal based on the adjusted control signal, and the input control signal and the output control signal are arranged to indicate a data transmission path of the data transmission structure.

[0014] In one exemplary embodiment, the data transmission structure includes an input unit configured to receive at least one input data and an input control signal, and output, based on the input control signal, input data corresponding to the input control signal; an output unit configured to receive the input data output from the input unit and at least one output control signal, and output the input data based on an enabled port represented by the output control signal; and a latch unit connected to the output unit and configured to latch the input data output from the output unit.

[0015] In one exemplary embodiment, the input unit includes a plurality of input controllers, each input controller corresponding to a storage transmission end, a bus transmission end or an interactive transmission end, each input controller is arranged to receive input data and an input control signal of a corresponding storage transmission end, a bus transmission end or an interactive transmission end, and the input controller is arranged to be conducted and output the input data according to the input control signal.

[0016] In one exemplary embodiment, the output unit includes a plurality of output controllers, each output controller corresponding to a storage transmission end, a bus transmission end or an interactive transmission end, each output controller is arranged to receive input data and an output control signal output from an input unit of a corresponding storage transmission end, a bus transmission end or an interactive transmission end, and the output controller is arranged to be turned on and output the input data according to the output control signal.

[0017] In one exemplary embodiment, the data transmission structure further includes an input selection unit configured to receive at least one input control signal and generate a strobe pulse corresponding to the input control signal, where the strobe pulse corresponds to a valid port represented by the input control signal and where a selection delay exists between the strobe pulse and the input control signal; and a trigger unit having a clock end connected to the input selection unit, an input end connected to the input unit, and an output end connected to the output unit, where the trigger unit is configured to transmit input data received by the input end to the output end based on the strobe pulse.

[0018] In one exemplary embodiment, the input selection unit includes a trigger subunit configured to receive at least one input control signal and generate an indication signal upon receiving the input control signal, a delay subunit connected to the trigger subunit and configured to delay the indication signal, and a conversion subunit connected to the delay subunit and configured to convert the delayed indication signal into a strobe pulse.

[0019] In some embodiments, the data transmission structure further includes an inversion unit disposed between the trigger unit and the input unit, the inversion unit being configured to output the input data or invert and output the input data based on an inversion control signal.

[0020] In one exemplary embodiment, the inversion unit includes an inversion control subunit configured to receive an inversion control signal and generate a first control signal and a second control signal based on the inversion control signal, a first selection subunit and a second selection subunit connected in parallel, the input end of which is configured to receive input data and the output end of which is connected to the trigger unit, the first selection subunit is turned on based on the first control signal and is configured to invert and output the input data, and the second selection subunit is turned on based on the second control signal and is configured to output the input data.

[0021] In one exemplary embodiment, the memory transmission end includes a first transmission end, a second transmission end, a third transmission end and a fourth transmission end. The bus transmission end includes a fifth transmission end and a sixth transmission end. The interactive transmission end includes a seventh transmission end and an eighth transmission end. The first transmission end, the second transmission end, the third transmission end and the fourth transmission end are respectively connected to the first memory array and the second memory array, and the first transmission end and the third transmission end are arranged to transmit lower bit data, and the second transmission end and the fourth transmission end are arranged to transmit higher bit data. The fifth transmission end and the sixth transmission end are arranged to perform data interaction transmission between the associated data transmission structure and the data bus. The seventh transmission end and the eighth transmission end are arranged to perform data interaction transmission between two data transmission structures.

[0022] In one exemplary embodiment, the fifth transmission end is arranged to perform data interaction transmission between the associated data transmission structure and a data bus, and the sixth transmission end is arranged to perform unidirectional data transmission to the data bus of the associated data transmission structure.

[0023] An exemplary embodiment of the present disclosure further provides a memory, and employs the memory circuit of the above embodiment to configure a memory array, thereby improving the transmission efficiency of data read and write in the memory and ensuring the accuracy of data transmission. [Brief description of the drawings]

[0024] The drawings constituting a part of the present disclosure are used to provide a further understanding of the present disclosure, and the schematic examples of the present disclosure and the description thereof are used to explain the present disclosure, and are not intended to unduly limit the present disclosure. [Figure 1] 1 is a hypothetical schematic diagram of a memory circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic diagram showing a specific configuration of a memory circuit according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is another specific schematic diagram of a memory circuit according to an embodiment of the present disclosure. [Figure 4] FIG. 13 is a schematic diagram illustrating a configuration of a data transmission circuit according to another embodiment of the present disclosure. [Diagram 5] FIG. 13 is a schematic diagram showing a specific configuration of a control module according to another embodiment of the present disclosure. [Figure 6] FIG. 13 is a schematic diagram of a specific connection mode of a data transmission structure according to another embodiment of the present disclosure. [Figure 7] FIG. 13 is a specific configuration schematic diagram of a data transmission structure when reading data according to another embodiment of the present disclosure. [Figure 8] FIG. 13 is a specific configuration schematic diagram of a data transmission structure when writing data according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] In order to clarify the purpose, technical solutions and advantages of the embodiments of the present disclosure, the following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the drawings in the embodiments of the present disclosure, and obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present disclosure. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present disclosure can be arbitrarily combined with each other.

[0026] FIG. 1 is a hypothetical schematic diagram of a memory circuit according to this embodiment, FIG. 2 is a specific schematic diagram of the memory circuit according to this embodiment, and FIG. 3 is another specific schematic diagram of the memory circuit according to this embodiment. The memory circuit according to this embodiment will be described in further detail below with reference to the drawings, and specifically as follows.

[0027] Referring to FIG. 1, the memory circuit is provided adjacent to the data transmission area 100, It includes at least one storage structure 400 arranged parallel to a data transmission area 100, and each storage structure 400 includes a first memory array 401 and a second memory array 402 arranged adjacent to each other in a first direction X, where the first direction X is a direction close to the data transmission area 100, and the distance between the first memory array 401 and the data transmission area 100 is smaller than the distance between the second memory array 402 and the data transmission area 100, that is, in the same storage structure 400, the first memory array 401 is arranged close to the data transmission area 100, and the second memory array 402 is arranged away from the data transmission area 100.

[0028] The first memory array 401 includes a read / write module 410 and a transfer module 420, and the first memory array 401 performs data interaction with the data transmission area based on the read / write module 410 in the first memory array 401. The second memory array 402 includes a read / write module 410, and the second memory array 402 performs data interaction with the data transmission area 100 based on the read / write module 410 in the second memory array 402 and the transfer module 420 in the first memory array 401.

[0029] That is, in the embodiment of the present disclosure, the read / write module 410 is arranged to directly interact with the storage units in the memory array to which it belongs, and during the data read / write process, the input written from the data transmission area 100 is transmitted through the multiple read / write modules 410 in the memory array, thereby realizing writing to different storage units in the memory array. For memory arrays far from the data transmission area 100, a transfer module 420 is provided in the memory array close to the data transmission area 100, thereby realizing fast and accurate transmission of data to the corresponding memory array.

[0030] Specifically, by installing the transfer module 420, data read and write to the second memory array 402 can be prevented from passing through the read and write module 410 of the first memory array 401, thereby separating the data transmission paths of the first memory array 401 and the second memory array 402, and then alternately reading and writing data in the first memory array 401 and the second memory array 402 can be realized, which further reduces the difference in read delay of data of different memory arrays, prevents read data with long delay from blocking read data with short delay, and improves the margin of data transmission. In addition, by separating the data transmission paths of the first memory array 401 and the second memory array 402, in the process of reading and writing data, it is only necessary to determine whether the data belongs to a write process or a read process to confirm the data transmission direction, which avoids the complicated data path determination process when the same data transmission path is used, thereby achieving a higher data transmission rate and higher data transmission accuracy.

[0031] Referring to FIG. 2, in this embodiment, the first memory array 401 and the second memory array include an even number of memory blocks 430 arranged consecutively in a first direction X, and every two adjacent non-overlapping memory blocks share one read / write module 410, and the read / write module 410 is arranged between two corresponding memory blocks 430.

[0032] Specifically, each memory block 430 includes multiple memory units, and the memory block 430 reads and writes data through the adjacent read / write module 410. More specifically, the memory block 430 includes multiple word lines and multiple bit lines, and each memory unit corresponds to one word line and one bit line. By turning on a specific word line and bit line, the target memory unit in the memory block 430 is connected to the read / write module 410, and the read / write module 410 realizes data reading and writing to different memory units in the memory block 430.

[0033] 2 and 3, in some embodiments, the read / write module 410 in the first memory array 401 and the read / write module in the second memory array 402 are both arranged along a first direction X, and the transfer module 420 is arranged on the opposite side of the read / write module 410 in a second direction perpendicular to the first direction X. By regularly arranging the read / write module 410 and the transfer module 420, the data transmission line between the read / write module 410 and the transfer module 420 can be regularly arranged, and the resistance of the data transmission line can be reduced through the shortest data transmission line, thereby improving the rate and accuracy of data transmission.

[0034] Furthermore, in this embodiment, a transfer module 420 is provided on the opposite side of each read / write module 410, and the short-distance transmission and multiplexing of data between the multiple transfer modules 420 reduces the possibility of errors occurring during the data transmission process.

[0035] It should be noted that the provision of a transfer module 420 on the opposite side of each read / write module 410 in the drawings of this embodiment is not a limitation of this embodiment, and in other embodiments, the number of transfer modules can be correspondingly reduced and still achieve the above technical effect.

[0036] In a specific circuit design, the data transmission conductors between the read / write module 410, the transfer module 420 and the data transmission area 100 are arranged between adjacent power conductors, and the power conductors are used to receive and transmit power signals and provide power signals to the first memory array 401 and the second memory array 402.

[0037] Specifically, the data read and write processes of each memory unit in the first memory array 401 and the second memory array 402 both require charging and discharging processes, and the charging of the memory units requires the use of the internal power supply of the memory; that is, in the process of designing the layout of the memory units, a corresponding power supply network needs to be set up to connect the internal power supply, and the power supply network includes power supply conductors extending along different directions, and data transmission conductors are set up between the power supply conductors, and the power supply conductors can be used as shielding wires, which can suppress data interference between adjacent data transmission conductors, and eliminate the need to add other shielding wires and the need to add other layouts.

[0038] Also, in some embodiments, referring to Figures 2 and 3, the data transmission conductors further include lower transmission conductors and upper data conductors, where the lower transmission conductors are used to transmit lower data in the memory array, and the upper transmission conductors are used to transmit upper data in the memory array.

[0039] In one example, when a memory array transmits 16 bits of data at a time, the lower transmission conductor is used to transmit 1-8 bits of data, and the upper data conductor is used to transmit 9-16 bits of data. In some embodiments, when a memory array transmits 8 bits of data at a time, the lower transmission conductor and the upper transmission conductor are used to transmit data stored in different memory arrays, i.e., the lower transmission conductor and the upper transmission conductor perform data transmission as parallel data transmission conductors, thereby further improving data transmission efficiency and data transmission accuracy.

[0040] In some embodiments, referring to FIG. 3 , the memory block 430 further includes a plurality of memory sub-blocks 440 arranged consecutively in a second direction perpendicular to the first direction X, and the plurality of memory sub-blocks 440 share the same read / write module 410, i.e., the plurality of memory sub-blocks 440 belonging to the same memory block 430 arranged in a direction parallel to the data transmission area 100 share adjacent read / write modules 410.

[0041] For illustrative purposes, this embodiment takes as an example that one memory structure 400 includes only a first memory array 401 and a second memory array 402. In practical applications, the memory structure 400 may further include a third memory array, in which case a transfer module 420 corresponding to the first memory array and the second memory array is provided, thereby realizing data reading and writing of the third memory array. Accordingly, a fourth memory array, etc. may be further provided. That is, any specific embodiment of designing different data transmission paths for each memory array should fall within the protection scope of this patent.

[0042] For illustration, the present embodiment has been described with reference to one parallel storage structure 400 as an example, but this is not intended to be limiting. In other embodiments, the first direction X may further include multiple storage structures, and the data transmission method of each storage structure may be the same as the storage structure exemplified above.

[0043] In this embodiment, the installation of the transfer module 420 prevents data from passing through the transfer of the read / write module 410 of the first memory array 401 when reading and writing data to the second memory array 402, thereby separating the data transmission paths of the first memory array 401 and the second memory array 402, and then realizing alternate reading and writing of data in the first memory array 401 and the second memory array 402, thereby reducing the difference in read delay of data of different memory arrays, avoiding the reading data with long delay blocking the reading data with short delay, and improving the margin of data transmission. In addition, by separating the data transmission paths of the first memory array 401 and the second memory array 402, in the process of reading and writing data, the data transmission direction can be confirmed only by determining whether the data belongs to a writing process or a reading process, and avoiding the complicated data path determination process when using the same data transmission path, thereby achieving a higher data transmission rate and higher data transmission accuracy.

[0044] Each unit in this embodiment is a logical unit, and in practical application, one logical unit may be one physical unit, may be a part of one physical unit, or may be realized by a combination of multiple physical units. In addition, in order to highlight the innovative part of this disclosure, units that are not very relevant to solving the technical problem described in this disclosure are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0045] It should be noted that the features disclosed in the storage circuits provided in the above embodiments can be arbitrarily combined if they do not conflict with each other to obtain new embodiments of the storage circuits.

[0046] Another embodiment of the present disclosure provides a data transmission circuit to improve the transmission efficiency of reading and writing data from a memory.

[0047] FIG. 4 is a schematic diagram of the configuration of a data transmission circuit according to this embodiment, FIG. 5 is a specific schematic diagram of the configuration of a control module according to this embodiment, FIG. 6 is a schematic diagram of a specific connection method of the data transmission structure according to this embodiment, FIG. 7 is a specific schematic diagram of the configuration of the data transmission structure when reading data according to this embodiment, and FIG. 8 is a specific schematic diagram of the configuration of the data transmission structure when writing data according to this embodiment. The data transmission circuit according to this embodiment will be described in further detail below with reference to the drawings, and is specifically as follows:

[0048] Referring to FIG. 4, the data transmission circuit is provided in a data transmission area 100, It includes at least two data transmission structures 101, each of which is connected to at least one of the storage circuits provided in the above embodiments, and is used for reading and writing data from and to the storage circuits.

[0049] Each data transmission structure includes a memory transmission end 111, a bus transmission end 112 and an interactive transmission end 113, where the memory transmission end 111 is used to connect the memory area 102, the bus transmission end 112 is used to connect the data bus 103, and the interactive transmission end 113 is used to connect the interactive transmission end 113 of another data transmission structure.

[0050] Here, data input from the memory transmission end 111 is output via the bus transmission end 112 or the interactive transmission end 113, data input from the bus transmission end 112 is output via the memory transmission end 111 or the interactive transmission end 113, data input from the interactive transmission end 113 is output via the bus transmission end 112 or the memory transmission end 111, and data input from the interactive transmission end 113 is data input from the bus transmission end 112 or the memory transmission end 111 in another data transmission structure 101.

[0051] A control module 104 is connected to the data transmission structure 101 to receive input control signals and regulation control signals provided by the associated memory.

[0052] 4 in conjunction with FIG. 5, the control module 104 is configured to generate an output control signal corresponding to the input control signal by performing a delayed output on the input control signal based on the adjusted control signal, and the input control signal and the output control signal are used to indicate the data transmission path of the data transmission structure 101.

[0053] Here, the adjustment control signal is generated based on the memory to which the data transmission circuit belongs, and is used to control the delay between the corresponding input control signal and the output control signal.

[0054] By controlling the data transmission paths of the two data transmission structures 101 by the control module 104, different data transmission structures can transmit data alternately, corresponding to the same data transmission structure 101, and realize data transmission for different storage areas 102. Through the alternating transmission of multi-path data, data transmission becomes more compact, thereby improving the data transmission efficiency of the memory.

[0055] It should be noted that in other embodiments, the number of data transmission structures may be any even number greater than two, and the above-mentioned data transmission circuit is configured between every two data transmission structures, thereby achieving further improvement of the data transmission efficiency of the memory.

[0056] Specifically, the signal delay between the input control signal and the output control signal is controlled by the adjustment control signal, which is favorable to avoid the output side opening early or late with respect to the preset timing, and ensures that the data transmission structure accurately outputs the corresponding input data. In some embodiments, referring to Figures 4 and 6, the memory transmission end 111 includes a first transmission end A, a second transmission end B, a third transmission end C and a fourth transmission end D. The bus transmission end 112 includes a fifth transmission end E and a sixth transmission end F. The interactive transmission end 113 includes a seventh transmission end G and an eighth transmission end H.

[0057] The first transmission end A, the second transmission end B, the third transmission end C, and the fourth transmission end D are connected to different memory areas 102 of the memory to which they belong, and the first transmission end A and the third transmission end C are arranged to transmit lower-order data, and the second transmission end B and the fourth transmission end D are arranged to transmit higher-order data. The fifth transmission end E and the sixth transmission end F are used for data interaction transmission between the data transmission structure 101 to which they belong and the data bus 103. The seventh transmission end G and the eighth transmission end H are used for data interaction transmission between two data transmission structures 101.

[0058] It should be noted that the first transmitting end A and the second transmitting end B may be used to transmit the same upper and lower data, for example, for transmitting 16-bit data, the first transmitting end A is used to transmit the lower 8 bits of data, and the second transmitting end B is used to transmit the upper 8 bits of data. The first transmitting end A and the second transmitting end B may be used to transmit different data, for example, for transmitting 8-bit data, the first transmitting end A and the second transmitting end B are used to transmit different data.

[0059] Furthermore, in some embodiments, the fifth transmission end E is used for data interaction transmission between the associated data transmission structure 101 and the data bus 103, and the sixth transmission end F is used for unidirectional data transmission to the data bus 103 of the associated data transmission structure 101. Due to the special settings of the fifth transmission end E and the sixth transmission end F, when data is input to the data transmission structure 101 via the data bus 103, data can only be input via the fifth transmission end E, and the fifth transmission end E can only be used for data transmission to the data bus 103 of the associated data transmission structure 101. Error Correction Code, ECC ) By providing the module, the on-chip ECC (on-die ECC) detection of data can be completed, and when the above data transmission circuit is used for data transmission, no additional circuit layout is required for ECC detection.

[0060] 5 in conjunction with FIG 6, in some embodiments, the input control signals include Sel A, Sel B, Sel C, Sel D, Sel E, Sel F, Sel G, and Sel H. The output control signals include Drv A, Drv B, Drv C, Drv D, Drv E, Drv F, Drv G, and Drv H.

[0061] Here, the input control signal corresponding to the first transmission end A is Sel A, and the output control signal is Drv A. The input control signal corresponding to the second transmission end B is Sel B, and the output control signal is Drv B. The input control signal corresponding to the third transmission end C is Sel C, and the output control signal is Drv C. The input control signal corresponding to the fourth transmission end D is Sel D, and the output control signal is Drv D. The input control signal corresponding to the fifth transmission end E is Sel E, and the output control signal is Drv E. The input control signal corresponding to the sixth transmission end F is Sel F, and the output control signal is Drv F. The input control signal corresponding to the seventh transmission end G is Sel G, and the output control signal is Drv G. The input control signal corresponding to the eighth transmission end H is Sel H, and the output control signal is Drv H.

[0062] Referring to Figures 4 and 6, data input from the memory transmission end 111 is output via the bus transmission end 112 or via the interactive transmission end 113, that is, data read from the first transmission end A, the second transmission end B, the third transmission end C and the fourth transmission end D is read via the fifth transmission end E and the sixth transmission end F or via the seventh transmission end G and the eighth transmission end H.

[0063] Data input from the bus transmission end 112 is output via the memory transmission end 111 or via the interactive transmission end 113, that is, data written from the fifth transmission end E is written via the first transmission end A, the second transmission end B, the third transmission end C and the fourth transmission end D, or written via the seventh transmission end G and the eighth transmission end H.

[0064] Data input from the interactive transmission end 113 is output via the bus transmission end 112 or via the memory transmission end 111, that is, data input from the seventh transmission end G and the eighth transmission end H is written via the first transmission end A, the second transmission end B, the third transmission end C and the fourth transmission end D, or read out via the fifth transmission end E and the sixth transmission end F.

[0065] 7 and 8, the data transmission structure 101 includes an input unit 201, which is configured to receive at least one input data and an input control signal, and output input data corresponding to the input control signal according to the input control signal; an output unit 203 configured to receive the input data output from the input unit 201 and at least one output control signal, and output the input data based on an enabled port indicated by the output control signal; a latch unit 204 connected to the output unit 203 and arranged to latch the input data output from the output unit 203 .

[0066] The input unit 201 includes a plurality of input controllers 211, each of which corresponds to a memory transmission end 111, a bus transmission end 112 or an interactive transmission end 113. Each input controller 211 is arranged to receive input data and input control signals from the corresponding memory transmission end 111, the bus transmission end 112 or the interactive transmission end 113, and the input controller 211 is arranged to turn on the corresponding port based on the input control signal, thereby outputting the input data of the corresponding port.

[0067] Specifically, for reading data, refer to FIG. 7, the read data may be read from a memory area connected to the data transmission structure 101 via the first transmission end A, the second transmission end B, the third transmission end C or the fourth transmission end D, and may be read from a memory area connected to another data transmission structure 101 via the seventh transmission end G and the eighth transmission end H.

[0068] Here, the input data Data A of the first transmission end A is connected to one input controller 211, which is controlled by the input control signal Sel A, and outputs the input data Data A of the first transmission end A upon receiving the input control signal Sel A. The input data Data B of the second transmission end B is connected to one input controller 211, which is controlled by the input control signal Sel B, and outputs the input data Data B of the second transmission end B upon receiving the input control signal Sel B. The input data Data C of the third transmission end C is connected to one input controller 211, which is controlled by the input control signal Sel C, and outputs the input data Data C of the third transmission end C upon receiving the input control signal Sel C. The input data Data D of the fourth transmission end D is connected to one input controller 211, which is controlled by the input control signal Sel D, and outputs the input data Data D of the fourth transmission end D upon receiving the input control signal Sel D. The input data Data G of the seventh transmission terminal G is connected to one input controller 211, which is controlled by the input control signal Sel G, and outputs the input data Data G of the seventh transmission terminal G upon receiving the input control signal Sel G. The input data Data H of the eighth transmission terminal H is connected to one input controller 211, which is controlled by the input control signal Sel H, and outputs the input data Data H of the eighth transmission terminal H upon receiving the input control signal Sel H.

[0069] Specifically, for writing data, refer to FIG. 8, write data is written into the data transmission structure 101 via the fifth transmission end E, and write data received by other data transmission structures 101 may be written via the seventh transmission end G and the eighth transmission end H.

[0070] Here, the input data Data E of the fifth transmission terminal E is connected to one input controller 211, which is controlled by the input control signal Sel E, and outputs the input data Data E of the fifth transmission terminal E upon receiving the input control signal Sel E. The input data Data G of the seventh transmission terminal G is connected to one input controller 211, which is controlled by the input control signal Sel G, and outputs the input data Data G of the seventh transmission terminal G upon receiving the input control signal Sel G. The input data Data H of the eighth transmission terminal H is connected to one input controller 211, which is controlled by the input control signal Sel H, and outputs the input data Data H of the eighth transmission terminal H upon receiving the input control signal Sel H.

[0071] In some embodiments, the mask unit 202 further includes a mask unit 202 that is configured to mask the input data Data E of the fifth transmission end E according to the input data Data E of the fifth transmission end E. Data Masking It is placed to generate DM, Data Masking The DM inputs data via the input controller 211 corresponding to the fifth transmission end E, thereby realizing the selective input of data on the data bus 103 .

[0072] Specifically, the memory has a data mask function and Data Bus Inversion The function includes a function that, if the data mask is enabled, the corresponding 8 bits of data are not written, and if the written 8 bits of data are majority 1, the written 8 bits of data are inverted if it is more power-efficient for the transmission channel to transmit 0s than 1s. At the same time, the data mask (DM) and Data Bus Inversion When the databus inversion (DBI) function is turned on, the data mask signal and Data Bus Inversion Both signals must use the same data port, so the data mask signal and Data Bus Inversion The present disclosure only allows the user to select and input one of the signals. Data Bus Inversion When you select a signal, that is, when you write data, the input data is Data Bus Inversiontransmitted along with the signal to the data transmission structure, Data Bus Inversion When the signal is valid, the input data Data E representing the synchronous input must be inverted. If the input data Data E is not written, it does not need to be inverted. Therefore, Data Bus Inversion The signal being valid indicates that further input data Data E needs to be written. Data Bus Inversion When the signal is invalid, if the input data is input normally, the input data should contain the majority of 0s, i.e. Data Bus Inversion When the signal is invalid, it is necessary to detect whether the input data is half or more than half filled with zeros. If so, Data Bus Inversion If the input data is normally input without going through the above process, and 0s account for a minority and 1s account for a majority, then the input data represents that the data mask signal is valid, and the corresponding 8 bits of input data are blocked and not stored in the memory array.

[0073] That is, Data Bus Inversion If the signal is valid, the fifth transmission end E receives the 8-bit raw data to be written, and the inversion unit 207 receives the inversion control signal DBI, at this time the inversion control signal DBI is Data Bus Inversion This indicates that the signal is valid, for example, the inversion control signal DBI is 1, and the input unit 201 inverts the input data and outputs it to the output unit 203 . Data Bus Inversion If the signal is invalid, the fifth transmitting end E writes 8-bit raw data or Data Masking Confirm that you want to receive DMs. Data Bus Inversion If the signal is invalid, compile the input / output Data E through the mask unit 202 to determine whether the data mask signal is valid (assuming valid is 1 and invalid is 0), and signal is valid, there is no need to write 8 bits of raw data. At this time, the fifth transmission terminal E Data Masking Receive DM and mask data signalindicates invalid, it indicates that 8 bits of raw data need to be written, and at this time the fifth transmission end E receives the input data Data E.

[0074] It should be noted that when a data transmission structure only inverts the data input through the corresponding fifth transmission end E, that is, when writing data, the inversion control signal DBI received by the inversion control sub-unit 221 is only the inversion control signal corresponding to the input data Data E, but not the inversion control signal corresponding to the input data Data G and Data H. This is because, for the data input through the seventh input end Sel G and the eighth input end Sel H, that is, the data input through the data bus 103 via another data transmission structure, the input data is inverted by the inversion unit 207 of the other data transmission structure as described above. Data Bus Inversion Because the process has been completed.

[0075] The output unit 203 includes a plurality of output controllers 212, each of which corresponds to a memory transmission end 111, a bus transmission end 112 or an interactive transmission end 113, and each of the output controllers 212 is configured to receive input data and output control signals of the corresponding memory transmission end 111, bus transmission end 112 or interactive transmission end 113, and the output controller 212 is configured to be turned on based on the output control signal, thereby outputting the input data.

[0076] Specifically, for reading data, refer to FIG. 7, the read data is read out to the data bus 103 via the fifth transmission end E or the sixth transmission end F, read out to another data transmission structure 101 by the seventh transmission end G and the eighth transmission end H, and finally read out to the corresponding other data bus 103 via the fifth transmission end E or the sixth transmission end F corresponding to the other data transmission structure 101.

[0077] Here, the output controller 212 connected to the fifth transmission end E is controlled by the output control signal Drv E, and outputs data through the fifth transmission end E upon receiving the output control signal Drv E. The output controller 212 connected to the seventh transmission end G is controlled by the output control signal Drv G, and outputs data through the seventh transmission end G upon receiving the output control signal Drv G. The output controller 212 connected to the eighth transmission end H is controlled by the output control signal Drv H, and outputs data through the eighth transmission end H upon receiving the output control signal Drv H.

[0078] Specifically, for writing data, refer to FIG. 8, the write data is written into a memory area connected to the data transmission structure 101 via the first transmission end A, the second transmission end B, the third transmission end C or the fourth transmission end D, and may also be written into a memory area connected to another data transmission structure 101 via the seventh transmission end G and the eighth transmission end H.

[0079] Here, the output controller 212 connected to the first transmission end A is controlled by the output control signal Drv A, and outputs data from the first transmission end A upon receiving the output control signal Drv A. The output controller 212 connected to the second transmission end B is controlled by the output control signal Drv B, and outputs data from the second transmission end B upon receiving the output control signal Drv B. The output controller 212 connected to the third transmission end C is controlled by the output control signal Drv C, and outputs data from the third transmission end C upon receiving the output control signal Drv C. The output controller 212 connected to the fourth transmission end D is controlled by the output control signal Drv D, and outputs data from the fourth transmission end D upon receiving the output control signal Drv D. The output controller 212 connected to the seventh transmission end G is controlled by the output control signal Drv G, and outputs data from the seventh transmission end G upon receiving the output control signal Drv G. The output controller 212 connected to the eighth transmission end H is controlled by the output control signal Drv H, and outputs data through the eighth transmission end H upon receiving the output control signal Drv H.

[0080] In this embodiment, the latch unit 204 includes a first inverter 214 and a second inverter 213 connected end to end, and the input end of the first inverter 214 and the output end of the second inverter 213 are connected in parallel with the output end of the output unit 203, and are connected in parallel with the output end of the output unit 203 through the latch unit 204, thereby realizing the storage of the data output by the output unit 203. It is to be noted that in another embodiment, the latch unit includes a first inverter and a second inverter connected end to end, and the input end of the first inverter and the output end of the second inverter are connected in series with the output port of the input unit, and are connected in series with the output end of the output unit through the latch unit, thereby realizing the inversion latch for the output data of the output unit, and are connected in series with the inverters to store the output data of the output unit.

[0081] In some embodiments, the input of the data is further delayed to further ensure that the data is accurate during the multiplexing process.

[0082] Specifically, the data transmission structure further includes an input selection unit 205 and a trigger unit 206, see FIG.

[0083] Here, the input selection unit 205 receives at least one input control signal, generates a gate pulse corresponding to the input control signal, the gate pulse corresponds to an effective port represented by the input control signal, and has a selection delay between the gate pulse and the input control signal. The trigger unit 206 has a clock end connected to the input selection unit 205, an input end connected to the input unit 201, and an output end connected to the output unit 203, and is configured to transmit the input data received at the input end to the output end according to the gate pulse.

[0084] The input selection unit 205 includes a trigger subunit 215 configured to receive at least one input control signal and generate an indication signal upon receiving the input control signal, a delay subunit 216 connected to the trigger subunit 215 and configured to apply a delay to the indication signal, and a conversion subunit 217 connected to the delay subunit 216 and configured to convert the delayed indication signal into a gate pulse.

[0085] The instruction signal is delayed through the delay sub-unit 216 to ensure that the data transmission structure accurately outputs the corresponding input data. The specific delay parameters of the delay sub-unit 216 are set according to the memory to which the delay sub-unit 216 belongs, and in some embodiments, the specific delay parameters of the delay sub-unit 216 can be adjusted by an operator.

[0086] In this embodiment, the trigger subunit 215 is realized by an OR gate; when reading data, refer to Fig. 7, the input control signal Sel A, Sel B, Sel C, Sel D, Sel G or Sel H is input to the trigger subunit 215, the trigger subunit 215 generates an indication signal according to the valid level of the input control signal Sel A, Sel B, Sel C, Sel D, Sel G or Sel H, the indication signal is delayed by the delay subunit 216 and then converted into a gate pulse by the conversion subunit 217 to drive the trigger unit 206. When writing data, refer to Fig. 5, the input control signal Sel E, Sel G or Sel H is input to the trigger subunit 215, the trigger subunit 215 generates an indication signal according to the valid level of the input control signal Sel E, Sel G or Sel H, the indication signal is delayed by the delay subunit 216 and then converted into a gate pulse by the conversion subunit 217 to drive the trigger unit 206.

[0087] In some embodiments, the trigger unit comprises a D-trigger.

[0088] In some embodiments, the data transmission structure 101 further includes an inversion unit 207 disposed between the trigger unit 206 and the input unit 201 and configured to output the input data or invert and output the input data based on an inversion control signal.

[0089] The inversion control signal is output after quantizing the data, and the data is output directly or inverted and then output via the inversion unit, thereby reducing the data energy consumption of the data transmission structure 101. Specifically, the low-level energy consumption is small when transmitting data, and transmitting data at a low level can save energy consumption; by quantizing the data, when the high-level data in the data is more than the low-level data, the inversion control signal controls the data to be inverted and transmitted, and when the high-level data in the data is less than the low-level data, the inversion control signal controls the data to be directly transmitted.

[0090] 7 and 8, the inversion unit 207 includes an inversion control subunit 221 configured to receive an inversion control signal and generate a first control signal and a second control signal according to the inversion control signal, a first selection subunit 222 and a second selection subunit 223, whose input ends are configured to receive input data and whose output ends are connected to the trigger unit 206 after the first selection subunit 222 and the second selection subunit 223 are connected in parallel, and the first selection subunit 222 is turned on according to the first control signal and configured to invert and output the input data. The second selection subunit 223 is turned on according to the second control signal and configured to directly output the input data.

[0091] It should be noted that the first control signal and the second control signal may drive the first selection subunit 222 and the second selection subunit 223 as two signals, or may drive the first selection subunit 222 and the second selection subunit 223 as high and low levels of the same signal.

[0092] Referring to FIG. 7, in some embodiments, the inversion unit 207 further includes a determining subunit 224 configured to receive input data and generate an inversion control signal based on the input data.

[0093] In this embodiment, the control module 104 controls the data transmission paths of the two data transmission structures 101, so that different data transmission structures transmit data alternately, corresponding to the same data transmission structure 101, and data transmission for different memory areas 102 can be realized. The alternate transmission of multiplexed data makes the data transmission more compact, thereby improving the data transmission efficiency of the memory.

[0094] For clarification, the signal driving method mentioned in this embodiment is described by taking the existence of a signal as an example, and in a specific application, it may be driven based on whether a signal exists or not, or based on the high or low level of the signal, that is, when a signal exists, it is driven based on whether the level of the signal is an effective level or not.

[0095] Each unit in this embodiment is a logical unit, and in practical application, a logical unit may be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this disclosure, units that are not related to solving the technical problem proposed by this disclosure are not introduced in this embodiment, but this does not indicate that there are no other units in this embodiment.

[0096] It should be noted that the features disclosed in the data transmission circuits provided in the above embodiments can be arbitrarily combined in the absence of conflict to obtain new data transmission circuit embodiments.

[0097] Another embodiment of the present disclosure provides a memory, and employs the memory circuit of the above embodiment to configure a memory array, thereby improving the transmission efficiency of data read and write of the memory and ensuring the accuracy of data transmission.

[0098] In some embodiments, the memory is a dynamic random access memory DRAM chip, where the memory of the dynamic random access memory DRAM chip conforms to the DDR 2 memory standard.

[0099] In some embodiments, the memory is a dynamic random access memory DRAM chip, where the memory of the dynamic random access memory DRAM chip conforms to the DDR3 memory standard.

[0100] In some embodiments, the memory is a dynamic random access memory DRAM chip, where the memory of the dynamic random access memory DRAM chip conforms to the DDR4 memory standard.

[0101] In some embodiments, the memory is a dynamic random access memory DRAM chip, where the memory of the dynamic random access memory DRAM chip conforms to the DDR5 memory standard.

[0102] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as a method, an apparatus, or a computer program product. Thus, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product embodied in one or more computer usable storage mediums containing computer usable program code. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (e.g., computer readable instructions, data structures, program modules, or other data), including, but not limited to, any method or technology for storing information. Random Access Memory, RAM ) , Read Only Memory, ROM ) , Electrically Erasable Programmable ROM, EEPROM ) , flash memory or other memory technology; Compact Disc ROM, CD-ROM), Digital Multi-Function Disc ( Digital Video Disk, The present invention includes, but is not limited to, a computer readable medium, such as a DVD (or other optical disk storage), a magnetic box, a magnetic tape, a magnetic disk storage or other magnetic storage device, or any other medium for storing the desired information and accessible by a computer. Additionally, those skilled in the art will appreciate that communication media generally includes computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0103] The present disclosure will be described with reference to flowcharts and / or block diagrams of methods, apparatuses (devices) and computer program products according to embodiments of the present disclosure. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be realized by computer program instructions. By providing these computer program instructions to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to generate an apparatus, the instructions executed by the processor of the computer or other programmable data processing device generate an apparatus for implementing the function specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0104] These computer program instructions may be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture that includes an instruction apparatus, which implements the functions specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0105] These computer program instructions may be loaded into a computer or other programmable data processing device, which causes the computer or other programmable device to execute a series of operational steps to generate a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0106] In this disclosure, the terms "comprise," "include," or any other variation thereof are intended to include a non-exclusive inclusion, such that an article or device that includes a set of elements includes not only those elements, but also other elements not expressly listed, or that are inherent to such article or device. In the absence of further limitations, an element limited by the phrase "comprises" does not exclude the presence of other identical elements in the article or device that includes that element.

[0107] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments upon learning the basic creative concept. Therefore, it is intended that the appended claims be interpreted to include the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0108] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the intention of the present disclosure is to include these modifications and variations. [Industrial Applicability]

[0109] The memory circuit according to the present disclosure can improve the transmission efficiency of data read and write in the memory and ensure the accuracy of data transmission.

[0110] This disclosure is based on and claims priority to a Chinese patent application filed with the China Patent Office on February 24, 2022, bearing application number 202210174060.X and titled "Memory Circuit, Data Transmission Circuit, and Memory," the entire contents of which are hereby incorporated by reference into this disclosure.

Claims

1. A memory circuit provided adjacent to a data transmission area, the memory circuit comprising: at least one memory structure arranged parallel to the data transmission region, each of the memory structures including a first memory array and a second memory array arranged adjacent to each other in a first direction, a distance between the first memory array and the data transmission region being smaller than a distance between the second memory array and the data transmission region, and the first direction being a direction adjacent to the data transmission region; The first memory array includes a read / write module and a transfer module, and the second memory array includes a read / write module, the first memory array performs data interaction with the data transmission area based on the read / write module in the first memory array, the second memory array performs data transmission with the data transmission area based on the read / write module in the second memory array and the transfer module in the first memory array, and during the process of the second memory array performing data transmission with the data transmission area, data is not transferred through the read / write module of the first memory array, The read / write module in the first memory array and the read / write module in the second memory array are both arranged along a first direction, and the transfer module is provided on the opposite side of the read / write module in a second direction perpendicular to the first direction. memory circuit.

2. 2. The memory circuit of claim 1, wherein the first memory array and the second memory array include an even number of memory blocks arranged consecutively in the first direction, and two adjacent non-overlapping memory blocks share one read / write module, and the read / write module is arranged between two corresponding memory blocks.

3. 3. The memory circuit of claim 2, wherein the memory block further includes a plurality of memory sub-blocks arranged consecutively in a second direction perpendicular to the first direction, the plurality of memory sub-blocks sharing the same read / write module.

4. The memory circuit of claim 1 , wherein one of the transfer modules is provided on an opposite side of each of the read / write modules.

5. 2. The memory circuit of claim 1, wherein data transmission conductors between the read / write module, the transfer module and the data transmission area are provided between adjacent power conductors, and the power conductors are configured to receive and transmit power signals, thereby providing the power signals to the first memory array and the second memory array.

6. 6. The memory circuit of claim 5, wherein the data transmission conductors include lower transmission conductors and upper transmission conductors, wherein the lower transmission conductors are arranged to transmit lower data in the memory array and the upper transmission conductors are arranged to transmit upper data in the memory array.

7. A data transmission circuit provided in a data transmission area, at least two data transmission structures and a control module, each of said data transmission structures being connected to a storage circuit according to claim 1 and arranged to be used for reading and writing data from said storage circuit; Each of the data transmission structures includes a memory transmission end, a bus transmission end and an interactive transmission end, wherein the memory transmission end is arranged to be connected to the memory circuit, the bus transmission end is arranged to be connected to a data bus, and the interactive transmission end is arranged to be connected to another of the data transmission structures; The data input from the storage transmission end is output via the bus transmission end or the interactive transmission end; The data input from the bus transmission end is output via the storage transmission end or the interactive transmission end; The data input from the interactive transmission end is output via the bus transmission end or the storage transmission end, where the data input from the interactive transmission end is data input via the bus transmission end or the storage transmission end in another data transmission structure; A data transmission circuit, comprising: a control module connected to the data transmission structure and receiving an input control signal and an adjustment control signal provided from an associated memory; the control module generates an output control signal corresponding to the input control signal by performing a delayed output on the input control signal based on the adjustment control signal; and the input control signal and the output control signal are arranged to indicate a data transmission path of the data transmission structure.

8. The data transmission structure includes: an input unit configured to receive at least one input data and the input control signal, and output, based on the input control signal, the input data corresponding to the input control signal; an output unit configured to receive the input data output from the input unit and at least one of the output control signals, and to output the input data based on a valid port indicated by the output control signal; 8. The data transmission circuit of claim 7, further comprising: a latch unit connected to said output unit and arranged to latch said input data output from said output unit.

9. The input unit includes: A plurality of input controllers are included, each of the input controllers corresponds to the storage transmission end, the bus transmission end or the interactive transmission end; Each of the input controllers is arranged to receive the input data and the input control signal of the corresponding one of the storage transmission ends, the bus transmission ends or the interactive transmission ends; 9. The data transmission circuit of claim 8, wherein the input controller is configured to be turned on based on the input control signal to output the input data.

10. The output unit is A plurality of output controllers are included, each of the output controllers corresponds to the storage transmission end, the bus transmission end or the interactive transmission end; Each of the output controllers is arranged to receive the input data and the output control signal output from the input unit of the corresponding storage transmission end, the bus transmission end or the interactive transmission end; 9. The data transmission circuit of claim 8, wherein the output controller is configured to be turned on based on the output control signal to output the input data.

11. The data transmission structure includes: an input selection unit arranged to receive at least one of said input control signals and generate a gating pulse corresponding to said input control signal, said gating pulse corresponding to a valid port indicated by said input control signal, and having a selection delay between said gating pulse and said input control signal; 9. The data transmission circuit of claim 8, further comprising: a trigger unit having a clock end connected to the input selection unit, an input end connected to the input unit, and an output end connected to the output unit, the trigger unit being configured to transmit the input data received by the input end to the output end based on the gate pulse.

12. The input selection unit is a trigger subunit arranged to receive at least one of said input control signals and to generate an indication signal upon receipt of said input control signal; a delay subunit connected to the trigger subunit and configured to provide a delay to the indication signal; 12. The data transmission circuit of claim 11, further comprising: a conversion subunit connected to said delay subunit and arranged to convert said delayed instruction signal into said gate pulse.

13. 12. The data transmission circuit of claim 11, wherein the data transmission structure further includes an inversion unit, the inversion unit being disposed between the trigger unit and the input unit, and configured to output the input data or invert and output the input data based on an inversion control signal.

14. The inversion unit includes: an inversion control subunit configured to receive the inversion control signal and generate a first control signal and a second control signal based on the inversion control signal; a first selection subunit and a second selection subunit, the input ends of which are arranged to receive the input data after the first selection subunit and the second selection subunit are connected in parallel, and the output ends of which are connected to the trigger unit; the first selection subunit is turned on based on the first control signal, and is arranged to invert and output the input data; The data transmission circuit of claim 13 , wherein the second selection subunit is configured to be turned on based on the second control signal to output the input data.

15. The storage transmission end includes a first transmission end, a second transmission end, a third transmission end and a fourth transmission end, the bus transmission end includes a fifth transmission end and a sixth transmission end, and the interactive transmission end includes a seventh transmission end and an eighth transmission end; 8. The data transmission circuit according to claim 7, wherein the first transmission end, the second transmission end, the third transmission end and the fourth transmission end are respectively connected to a first memory array and a second memory array, and the first transmission end and the third transmission end are arranged to transmit lower-bit data, the second transmission end and the fourth transmission end are arranged to transmit higher-bit data, the fifth transmission end and the sixth transmission end are arranged to be used for data interactive transmission between the data transmission structure to which they belong and the data bus, and the seventh transmission end and the eighth transmission end are arranged to be used for data interactive transmission between two of the data transmission structures.

16. the fifth transmission end is arranged for interactive data transmission between the associated data transmission structure and the data bus; 16. The data transmission circuit according to claim 15, wherein the sixth transmission end is arranged for unidirectional data transmission to the data bus of the associated data transmission structure.

17. A memory employing the memory circuit of claim 1 to configure a memory array.

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