Highly linear multiplier

Abstract

A linear multiplier configured to generate an output current representing the product of a first input voltage and a second input voltage, comprising: a first transconductance stage configured to receive a first input voltage and output a first set of differential currents and having a negative feedback network; at least one second transconductance stage configured to receive a second input voltage and output a predistortion voltage of the second input voltage, each having a negative feedback network; and a pair of third transconductance stages each configured to receive a voltage corresponding to the predistortion voltage of the second input voltage and output a second set of differential currents when a bias current corresponding to one of the first set of differential currents is supplied.

Description

[Technical field]

[0001] The subject matter disclosed in this specification (hereinafter, sometimes referred to as the present disclosure) relates to a highly linear multiplier. More specifically, the present disclosure relates to the design of a multiplier that can generate an output current that represents the product of input voltages with high precision.

[0002] Multipliers are versatile basic functional elements that generate the product of two analog input signals as an output signal, and are used in variable gain amplifiers, mixers, arithmetic circuits, etc. The integrated analog multiplier using bipolar transistors was first presented by Barrie Gilbert in 1968. Since then, analog multipliers using bipolar transistors, also called Gilbert cells, have had a smooth history of development. The accuracy of bipolar multipliers is based on predistortion of the input signal to compensate for the nonlinearity of the bipolar differential stage.

[0003] Since the 1970s, integrated circuits based on MOS and CMOS technologies have become widespread. Their advantages are, among others, energy-efficient digital integration and scalability. High-performance analog circuits can also be integrated using CMOS technology. As analog circuits are increasingly integrated into CMOS, the need for an equivalent to the Gilbert cell known from bipolar technology has arisen. For example, when MOSFETs are operated at very low current densities, i.e. at a threshold voltage V TH A Gilbert cell can be realized in CMOS when operated with gate voltages below 0.01 V. In such a case, the MOSFETs are operated in weak inversion and have an exponential characteristic curve. Such multipliers based on MOSFETs in weak inversion suffer from, at least, low bandwidth, relatively inaccurate, and subject to temperature drift due to threshold voltage variations from device to device. Because MOSFETs do not have a base current like bipolar transistors, the equivalent circuit of a bipolar multiplier cannot be used to pre-distort the input signal to compensate for nonlinearities.

[0004] For this reason, multipliers using the Gilbert principle have not been widely used in applications requiring high accuracy in CMOS technology. This is because, as mentioned above, the CMOS differential stage does not have ideal pre-distortion and does not provide sufficient accuracy. For this reason, CMOS multipliers cannot be used when the MOSFET is in saturation operation (V DS > V GS - V TH ) has a parabolic characteristic (V GS 2 ), and the MOSFET is in the linear region (V DS <V GS - V TH ) for the linear term (V GS ×V DS )

[0005] In the following, we will discuss the problem of nonlinearity in the CMOS differential stage. This problem is important because Gilbert-type multipliers in CMOS technology contain such CMOS differential stages, and the nonlinearity of the CMOS differential stage affects the linearity and therefore the overall accuracy of the multiplier.

[0006] FIG. 1 is an example circuit diagram of a differential stage of CMOS transistors, or a CMOS differential pair.

[0007] In Figure 1, I bias is the bias current (tail current or common current), V xDC is the average common mode voltage, v x indicates the input differential voltage, and the positive input V XinP and negative input V XinN As a load, a dummy voltage source was placed between the drain node of each transistor and the power supply voltage Vdd, which was used to measure the current in the switching simulation.

[0008] Below, v is the operating point. x = 0mV, bias current I bias Consider an example where we assume = 2μA.

[0009] FIG. 2 shows an example of the characteristics of the differential stage shown in FIG. 1, where FIG. 2(a) shows an example of a voltage-current transfer function, and FIG. 2(b) shows an example of a transconductance function.

[0010] As is clear from Fig. 2(a), where the currents in both branches of the differential stage are plotted against the input differential voltage, the differential stage has a small dynamic range and a nonlinear transfer function, i.e., a nonlinear voltage-to-current conversion characteristic. As is clear from Fig. 2(b), the transconductance Gm, which is the derivative of the difference between the currents in both branches of the differential stage, has a peak near the operating point.

[0011] The Gilbert cell circuit is composed of a bipolar differential stage with a constant bias current, and a bipolar differential stage stacked on top of it for each branch. Nonlinearity occurs because the conversion from the input current to the output current of the bipolar differential stage located at the bottom stage becomes nonlinear. As shown by the highly nonlinear transconductance Gm in Figure 2(b), a CMOS differential stage has the same problem.

[0012] In a stacked differential stage, nonlinearity can essentially be caused by two effects: the variation of the input differential voltage when the common current of the stacked differential stage is assumed to be constant (as already shown in Figure 2), and the variation of the common current when the input differential voltage is assumed to be constant. Even if the voltage-current transfer function of a CMOS differential stage could be linearized, the question remains as to whether the current distribution is exactly proportional to the change in the common current when the input differential voltage is constant.

[0013] FIG. 3 shows examples of further characteristics of the differential stage shown in FIG. 1, where FIG. 3(a) shows an example of a current-current transfer function, and FIG. 3(b) shows an example of a function of the derivative of the current difference.

[0014] In Figure 3(a), the current in both branches of the differential stage is plotted against the bias current. This is done by plotting the input differential voltage v x= 100 mV. As is clear from Fig. 2(a) and (b), the voltage-current transfer function is already highly nonlinear. In Fig. 2(a) and (b), the input differential voltage v x By changing I bias = 2μA, whereas in Figure 3(a) the common / tail current I bias It is noteworthy that v in Figure 2(a) x = 100 mV operating point, but in Figure 3(a) it is I bias = 2μA, and the drain current is I(V mulP ) = 1.87 μA,I(V mulN ) = 0.13 μA. From Fig. 3(a) we can see that the currents in the two branches change very linearly. Similar to Fig. 2(b), Fig. 3(b) shows the derivative of the difference between the currents in both branches of the differential stage. With a nominal bias current of 2 μA, an eight-fold change in current between 0.5 μA and 4 μA results in a change in the derivative of only ±5.8% (differential at 0.5 μA: - 0.88, 2.0 μA: - 0.86, 4.0 μA: - 0.83).

[0015] From the above, it can be seen that a CMOS differential stage, and therefore any differential stage in a CMOS-based Gilbert multiplier, suffers from nonlinearities, which are primarily due to the nonlinear voltage-current transfer function, and less due to non-idealities in the proportionality between the output current and the common operating current, i.e., the tail current or bias current.

[0016] Therefore, there is room for improvement in the linearity of multipliers, especially Gilbert-type multipliers in CMOS technology.

[0017] Various embodiments disclosed herein aim to address at least some of the issues and / or problems and drawbacks described above.

[0018] More specifically, an object of the present disclosure is to provide a highly linear multiplier, that is, a multiplier capable of realizing high-precision multiplication, in particular, a Gilbert-type multiplier using CMOS technology.

[0019] Various aspects of the embodiments of the present disclosure are set forth in the following claims.

[0020] According to one exemplary aspect of the present disclosure, there is provided a multiplier configured to generate an output current representative of a product of a first input voltage and a second input voltage, the multiplier comprising: a first transconductance stage configured to receive the first input voltage and output a first set of differential currents when a first fixed bias current is provided thereto, the first transconductance stage having a negative feedback network; at least one second transconductance stage configured to receive the second input voltage and output a predistorted voltage of the second input voltage when a second fixed bias current is provided thereto, each transconductance stage having a negative feedback network; a third pair of transconductance stages each configured to receive a voltage corresponding to the predistortion voltage of the second input voltage and output a second set of differential currents when a bias current corresponding to one of the first set of differential currents is provided; and a combining network configured to generate an output current by combining the second set of differential currents from each of the third pair of transconductance stages; Equipped with.

[0021] This configuration makes it possible to provide a linearized multiplier based on transconductance, specifically, a linearized voltage input unit capable of compensating for the nonlinearity of the transconductance (e.g., a differential stage that constitutes the transconductance).

[0022] In the above configuration, the first transconductance stage may have two current outputs for each of the first set of differential currents;

[0023] The first transconductance stage may be configured such that, for each of the first set of differential currents, one of the two current outputs is subtracted from a first reference current corresponding to an output current at an operating point of the first transconductance stage, the resulting current difference is fed back to an input side of the first transconductance stage via a feedback resistor, and the other of the two current outputs is output from the first transconductance stage.

[0024] With this configuration, it is possible to linearize the voltage input section to which the first voltage is input. More specifically, it is possible to realize negative feedback in the first transconductance stage capable of compensating for nonlinearity of transconductance such as a differential stage constituting a transconductance.

[0025] In any of the above-mentioned configurations, each second transconductance stage may be configured such that each of a pair of currents at the output side of the second transconductance stage is subtracted from a second reference current corresponding to the output current of the second transconductance stage at an operating point, and the resulting current difference is fed back to the input side of the second transconductance stage via a feedback resistor in a feedback path.

[0026] Each of the second transconductance stages may be configured to output, as the predistortion voltage, a potential difference between two of the feedback paths, each of which corresponds to one of a pair of currents at the output side of the second transconductance stage.

[0027] This configuration makes it possible to linearize the voltage input section to which the second voltage is input. More specifically, it is possible to realize negative feedback in the second transconductance stage and generate a predistortion voltage for the second input voltage. This predistortion voltage makes it possible to compensate for the nonlinearity of the transconductance of the third transconductance stage (for example of the differential stage constituting the transconductance).

[0028] In any of the above-described configurations, the second fixed bias current of the second transconductance stage may be set to the middle of a range of bias currents of a third transconductance stage configured to receive a voltage based on the predistortion voltage from the second transconductance stage.

[0029] Additionally or alternatively, the transconductance of the second transconductance stage may be substantially equal to a third transconductance stage configured to receive a voltage based on the predistortion voltage from the second transconductance stage.

[0030] Additionally or alternatively, the transconductance of the second transconductance stage may be equal to that of a third transconductance stage configured to receive a voltage based on the predistortion voltage from the second transconductance stage.

[0031] Additionally or alternatively, the gain of the second transconductance stage may be set such that an input of the predistortion voltage of the second input voltage causes a third transconductance stage configured to receive an input of a voltage based on the predistortion voltage from the second transconductance stage to output the second set of differential currents, where the second set of differential currents is equal to a set of differential currents generated by the transconductance of the second transconductance stage upon input of the second input voltage.

[0032] Using any of these configurations, the second transconductance stage can be designed and / or operated to provide a suitable linearization of the voltage input for inputting the second voltage.

[0033] In any of the above configurations, each third transconductance stage may be configured to receive an input of the predistortion voltage of the second input voltage of the second transconductance stage.

[0034] By using such a configuration, the multiplier can be linearized simply and effectively.

[0035] In any of the above-described configurations, the multiplier may include an error compensation circuit configured to generate a compensation voltage to compensate for an error in an output current relative to a precise algebraic product of the first input voltage and the second input voltage.

[0036] Additionally or alternatively, the multiplier may include at least one fourth transconductance stage configured to output a scaled version of the second input voltage when the second input voltage is received and a third fixed bias current is provided; a multiplier-summing network configured to generate a compensation voltage for the second input voltage by multiplying the predistorted voltage of the second input voltage from a second transconductance stage by a first coefficient, multiplying the scaled voltage of the second input voltage from a fourth transconductance stage by a second coefficient, and adding the multiplied predistorted voltage and the multiplied scaled voltage; Further comprising: Each of the third transconductance stages 30 may be configured to receive a compensated voltage of the second input voltage from the multiplier-summing network.

[0037] Such a configuration makes it possible to realize a multiplier with improved error compensation and therefore improved linearization.

[0038] In any of the above configurations, each transconductance stage may be comprised of a differential pair of CMOS transistors with the bias current as the tail current.

[0039] Additionally or alternatively, the multiplier may be integrated in CMOS technology.

[0040] Additionally or alternatively, the first transconductance stage may be constructed with NMOS transistors, and the second transconductance stage and the third transconductance stage may both be constructed with PMOS transistors.

[0041] This configuration allows the implementation and integration of multipliers based on CMOS technology.

[0042] In any of the above configurations, the first input voltage and the second input voltage may be or represent analog signals;

[0043] At least one of the first input voltage and the second input voltage may be or represent a signal resulting from pulse width modulation of an analog signal;

[0044] One of the first input voltage and the second input voltage may be or represent a signal representing a reference signal of a digital-to-analog converter, and the other of the first input voltage and the second input voltage may be or represent a signal representing a digital input of a digital-to-analog converter.

[0045] That is, the multiplier may be an analog multiplier, ie, a multiplier based on an analog structure, implementation or mode (wherein the first input voltage and the second input voltage are or represent analog signals).

[0046] Alternatively, the multiplier may be a (partially or fully) digital-to-analog multiplier, i.e. a multiplier based on a (partially or fully) digital configuration, realization or mode (wherein at least one of the first input voltage and the second input voltage is or represents a signal resulting from pulse width modulation of an analog signal).

[0047] Or the multiplier may be a (partially or fully) digital-analog multiplier, i.e. a (partially or fully) multiplier based on a digital configuration, realization or mode (wherein one of the first input voltage and the second input voltage is or represents a signal representative of a reference signal of a digital-to-analog converter, and the other of the first input voltage and the second input voltage is or represents a signal representative of a digital input of a digital-to-analog converter).

[0048] Any such configuration may be used to adapt the multiplier to its intended use and the underlying application or usage environment or circumstances, thereby enhancing the applicability of the multiplier.

[0049] Hereafter, further developments and / or modifications of the aforementioned exemplary embodiments are also disclosed. [Brief description of the drawings]

[0050] The disclosure of the present application will now be explained in more detail, by way of non-limiting examples, with reference to the accompanying drawings, in which: [Figure 1] 1 is an example of a circuit diagram of a differential stage of CMOS transistors, i.e. a CMOS differential pair. [Diagram 2] 2A and 2B are diagrams showing example characteristics of the differential stage shown in FIG. 1, where FIG. 2A shows an example of a voltage-current transfer function and FIG. 2B shows an example of a transconductance function. [Diagram 3]3A and 3B are diagrams showing examples of further characteristics of the differential stage shown in FIG. 1, where FIG. 3(a) shows an example of a current-current transfer function and FIG. 3(b) shows an example of a function of the derivative of the current difference. [Figure 4] FIG. 2 illustrates an example circuit diagram of a multiplier according to an embodiment. [Diagram 5] 1 is an example of a circuit diagram of a voltage input unit applied to a multiplier according to an embodiment. [Figure 6] 13 is an example of a circuit diagram of another voltage input unit applied to a multiplier according to an embodiment. [Figure 7] FIG. 2 illustrates another example of a circuit diagram of a multiplier according to an embodiment. [Figure 8] FIG. 8 is a diagram showing an example of modulation characteristics of an embodiment of a multiplier according to the circuit diagram of FIG. 7. [Figure 9] 8 illustrates an example of an operation process or signal flow according to an embodiment of a multiplier according to the circuit diagram of FIG. 7. [Figure 10] 3A-3C illustrate example transistor circuits for various portions of a multiplier according to an embodiment. [Figure 11] FIG. 11 illustrates an example of a modulation characteristic of a multiplier according to the transistor circuit of FIG. 10 in accordance with an embodiment. [Figure 12] FIG. 11 illustrates an example of linear characteristics of a multiplier according to the transistor circuit of FIG. 10 in accordance with an embodiment. [Figure 13] 8 illustrates an example of an error characteristic for a first input voltage of a multiplier according to the circuit diagram of FIG. 7 in accordance with an embodiment. [Figure 14] 8 illustrates an example of an error characteristic for a second input voltage of a multiplier according to the circuit diagram of FIG. 7 in accordance with an embodiment. [Figure 15] FIG. 2 illustrates yet another example of a circuit diagram of a multiplier in accordance with an embodiment. [Figure 16] 16 illustrates an example of an error characteristic for a first input voltage of a multiplier according to the circuit diagram of FIG. 15 in accordance with an embodiment. [Figure 17] 16 illustrates an example of an error characteristic for a second input voltage of a multiplier according to the circuit diagram of FIG. 15 in accordance with an embodiment. [Figure 18]16 illustrates an example of an operation process or signal flow of a multiplier according to the circuit diagram of FIG. 15 according to an embodiment. Detailed explanation

[0051] The disclosure of the present application will now be described with reference to certain non-limiting examples of currently contemplated embodiments, but those skilled in the art will appreciate that the disclosure is in no way limited to these examples and embodiments, but may be more broadly applicable.

[0052] Please note that the following description mainly focuses on the specifications used as non-limiting examples and embodiments of certain exemplary circuit structures, implementations, and techniques. Such descriptions are only used in the context of the disclosed non-limiting examples and embodiments, and are not intended to limit the disclosure of this specification in any way. Rather, any other circuit structures, implementations, and techniques may be used as well, so long as the contents described herein and / or the embodiments described herein are applicable.

[0053] Various examples and embodiments of some aspects disclosed in the present application are described below with some variations and / or alternatives. In general, it should be noted that all of the various forms and / or alternatives described may be provided alone or in any possible combination (including combinations of individual features of the various forms and / or alternatives) according to specific needs and constraints. In this specification, the words "comprise", "have", and "include" should be understood not to limit the described examples and embodiments to only the mentioned features. Such examples and embodiments may also include structures, units, modules, networks, etc. that are not mentioned.

[0054] It should be noted that in the drawings, lines and arrows interconnecting individual blocks or entities are generally meant to illustrate an operational coupling therebetween, which may be a physical and / or logical coupling, on the one hand, that is independent of the implementation, and on the other hand, that may consist of any number of intermediate functional blocks or entities not shown.

[0055] According to the embodiments of the present disclosure, in general terms, a multiplier having high linearity, that is, a multiplier capable of realizing high-precision multiplication, and in particular a Gilbert-type multiplier in CMOS technology, is provided.

[0056] Hereinafter, when referring to transconductance, this can mean transconductance as an electrical property relating the current through the output of a device, unit or element to the voltage at the input of said device, unit or element (i.e. the reciprocal of resistance), or it can mean a transconductance element as a structural means (e.g. device, unit or element) exhibiting a transconductance property (i.e. a transconductance related transfer function).Also, a transconductance stage refers to a structural means containing a transconductance, i.e. a structural means containing a transconductance property or element, such that a voltage at its input is converted into a current at its output.

[0057] 4 is a diagram showing an example of a circuit diagram of a multiplier according to an embodiment. The multiplier shown in FIG. 4 is an analog multiplier based on transconductance, or in other words, an analog multiplier based on the Gilbert principle (i.e., a Gilbert-type multiplier).

[0058] As shown in FIG. 4, multiplier 1A is an analog multiplier that receives a first input voltage v x and the second input voltage v y The input is configured to generate an output current i0 that represents the product of

[0059] According to the Gilbert principle, the multiplier 1A can be generally described as follows: In the first unit, the first input voltage v x is converted to a current change i1 by the transconductance G11. Here, the transconductance G11 is a constant bias current I bias1 This current change is countered by a constant bias current Ibias2B is added and supplied to the transconductances G2B and G2B' as a bias current. G2B is the positive part of the current change i1 (i.e., the output current of the positive or plus output part, for example, I(V mulP ) in FIG. 2(a), and G2B' receives the negative part of the current change i1 (i.e., the output current of the negative or minus output section, e.g., I(V mulN ) corresponding to the second input voltage v y is applied in both polarities to a second unit having transconductances G2A / G2A', which are connected to a constant bias current I bias2A The second input voltage v y The voltage v is the predistortion voltage of d is converted to a current change i2 by the transconductance G2B / G2B'. The transconductances G2B / G2B' operate with bias currents corresponding to their respective portions of the current change i1, i2. The output current changes i2 (each of which is a pair of differential currents like i1) of the transconductances G2B and G2B' are subtractively combined, resulting in a current change of the input voltage v x and v y forms a current i0 proportional to the product of

[0060] As shown in FIG. 4, the multiplier 1A includes a first transconductance stage 10 (having a transconductance G11). The first transconductance stage 10 is coupled to a first input voltage v x is input, and the first fixed bias current I bias1 The multiplier 1A is configured to output a pair of first differential currents i1 when a second input voltage v is applied to the first transconductance stage 10. The first transconductance stage 10 has a negative feedback network (denoted FB). The multiplier 1A further comprises a pair of second transconductance stages 20 (having a transconductance G2A or G2A'). Each of these stages receives a second input voltage v y is input, and a second fixed bias current I bias2A is supplied, the second input voltage v y Predistortion voltage v dEach of the second transconductance stages 20 has a negative feedback network (denoted FB). The multiplier 1A further comprises a pair of third transconductance stages 30 (having a transconductance G2B or G2B'). Each of these stages is configured to output a predistortion voltage v d (In the example of Figure 4, the predistortion voltage v d The multiplier 1A is configured to output a pair of second differential currents i2 when a bias current corresponding to one of the pair of first differential currents i1 is provided and the multiplier 1A further comprises a combining network (40) configured to generate an output current i0 by combining the pair of second differential currents i2 from each of the pairs of the third transconductance stage 30.

[0061] The above-mentioned transconductance G11, G2A and G2A', G2B and G2B', that is, the internal transconductance characteristics of the transconductance elements of the transconductance stage, basically correspond to Gm in FIG. 2(b).

[0062] The exemplary circuit configuration of FIG. 4 includes a pair of second transconductance stages 20, the output of which corresponds to a voltage, i.e., a predistortion voltage v d are applied to the two transconductance stages 30 with corresponding signs or polarities, then only one second transconductance stage is sufficient.

[0063] In the exemplary circuit configuration of Fig. 4, each transconductance stage can be configured with a differential pair, such as a differential pair of CMOS transistors with their respective bias currents as common / tail currents. Thus, each of the transconductance stages 10, 20, 30, i.e., each of the transconductances G11, G2A / G2A', G2B / G2B', can be realized according to the circuit configuration of Fig. 1.

[0064] As is clear from FIG. 4, the multiplier 1A is a first input voltage vx This corresponds to the first transconductance stage 10. The multiplier 1A also comprises a linear voltage input unit for inputting a second input voltage v y This corresponds to a combination of at least one second transconductance stage 20 and each third transconductance stage 30. That is, although the overall transfer function of the voltage input units is linearized, their internal transconductance characteristics (i.e., transconductances G11, G2A / G2A', G2B / G2B') are highly non-linear, as is evident from FIG. 2(b).

[0065] In the following, the linearization of a voltage input unit according to the present disclosure, i.e. its overall transfer function or transconductance characteristics, is described.

[0066] 5 is an example of a circuit diagram of a voltage input unit applied to a multiplier according to an embodiment. The voltage input unit 15 shown in FIG. 5 represents a transconductance stage with a negative feedback network, and can be used as the first transconductance stage 10 in the multiplier of FIG. 4.

[0067] As shown in Figure 5, the transconductance G11 has parallel outputs at the positive and negative outputs, and outputs the same current, i.e. +i1 or -i1. A circuit that outputs the same positive and negative currents is similar to a current conveyor. These same currents can be realized, for example, by a current mirror using CMOS technology. The output currents, i.e. +i1 and -i1, are subtracted from each other to obtain the reference current I bias1o It is compared with the reference current I bias1o is the same as the current i1 at the operating point, for example when the input differential voltage is zero.

[0068] When an input differential voltage v1 is applied, the output of the transconductance G11 has two inputs i1 and I bias1o This causes a voltage swing due to the feedback resistor R fbCurrent flows through the input resistance R in Together this produces negative feedback.

[0069] The output voltage of the transconductance G11 is of no importance to the first order, since the current of a second identical output is evaluated. However, the transconductance G11 can be considered as an inverting voltage amplifier. To calculate the transconductance of the inverting circuit, I bias1o The current difference caused by -i1 is fed back to the feedback resistor R fb and the input resistance R in The direct input differential voltage at the transconductance G11, i.e., the voltage v d is adjusted to a small value by negative feedback, so the input resistance R in determines the overall transconductance. Due to the negative feedback, the resulting overall transconductance is almost independent of the transconductance of the differential pair (corresponding to Gm in Figure 2(b)) of the transconductance stage. Therefore, the nonlinearity caused by the voltage control of the differential stage due to the highly nonlinear Gm is eliminated or at least greatly mitigated by the negative feedback.

[0070] Therefore, the unit 15 and its overall transfer function or transconductance characteristics, i.e., current-voltage transfer function (i.e., v1 or v x The conversion from i to i1 can be linearized with the exemplary circuit configuration of FIG.

[0071] 6 is an example of a circuit diagram of another voltage input unit applied to a multiplier according to an embodiment. The voltage input unit 25 shown in FIG. 6 represents a combination of a transconductance stage with a negative feedback network and a subsequent transconductance stage (without a negative feedback network), and can be used as a combination of the second and third transconductance stages 20, 30 in the multiplier of FIG. 4.

[0072] As shown in Fig. 6, two transconductance stages are connected and used. These transconductances G2A and G2B are characterized by having the same characteristics. Having the same characteristics means that the transconductance of the preceding transconductance stage is at least substantially equal to the transconductance of the succeeding transconductance stage, or may include such a configuration. Here, the succeeding transconductance stage is configured to receive a voltage based on the (pre-distorted) voltage from the preceding transconductance stage.

[0073] Additionally or alternatively, having the same characteristics may mean or include matching a preceding transconductance stage with a following transconductance stage configured to receive a voltage based on the (pre-distorted) voltage from the preceding transconductance stage. Such equivalence of characteristics may be achieved by placing the two inputs or stages G2A and G2B side-by-side in the physical layout, or even by placing the transistors together in a so-called quad or inter-digitated layout.

[0074] As in Figure 5, the output current of transconductance G2A, i.e. +i 2A or -i 2A Let I be the reference current. bias2o The reference current I bias2o is the same as the current i2A at the operating point, for example when the input differential voltage is 0. The input differential voltage v in2 When is applied, the output of transconductance G2A has i2 and I bias2o This causes a voltage swing due to the feedback resistor R fb Current flows through the input resistance R in Together this produces negative feedback.

[0075] The transconductance G2A is a constant bias current I bias2A (i.e., a constant bias current I bias2A The bias current I bias2A is preferably the bias current of the subsequent transconductance G2B, i.e., the variable signal input current i in2 The bias current I bias2A is the signal input i in2 can be chosen to minimize the nonlinearity of , which is already low when coming from a linear transconductance stage such as that shown in Figure 5.

[0076] At the same time, the gain of the transconductance G2A is preferably chosen to be significantly less than ∞, because the feedback around the transconductance G2A at its direct input reduces the voltage v d is set to generate the same current in transconductance G2B as in transconductance G2A. That is, the voltage v d In a normal op-amp circuit, the gain, or more precisely, the Gm of the input differential stage, is set as high as possible, and the voltage gain is ideally set to ∞, so that v d To obtain the best linearity, we minimize the input differential voltage V in2 To obtain sufficient linearity at an input level of v dIt is sufficient to select a gain of a magnitude that minimizes the above. Referring to FIG. 6, it can be said that the transconductance G2A of the second transconductance stage and the transconductance G2B of the third transconductance stage should be selected not too high but sufficiently low to enable mutual matching between the second and third transconductance stages. More specifically, the Gm of the input differential stage of the second and third transconductance stages should be selected such that the Vgs-Vth of the transistors is not too small. That is, the Vgs-Vth should be selected such that the mismatch of Vth between the transistors of the two transconductance stages does not affect (at least not excessively or excessively) the mutual matching between the second and third transconductance stages.

[0077] Thus, transconductance G2B represents a transconductance stage that is linearized by predistortion through negative feedback of the preceding transconductance G2A.

[0078] Therefore, the transconductance G2A is v in2 I bias2A It can be considered as a multiplier that multiplies the input signal by the output signal. (It can also be considered as an amplifier with adjustable gain.) bias2A is constant, and v in2 Only the feedback resistor R fb and the input resistance R in Linearization is achieved by negative feedback through v d is distorted accordingly. Then, the variable current i in2 The predistorted voltage v d Thus, the nonlinearity caused by the voltage control of the differential stage due to the highly nonlinear Gm can be eliminated or at least significantly reduced by the predistortion of the preceding differential stage and its negative feedback.

[0079] Therefore, the unit 25 and its overall transfer function or transconductance characteristics, i.e., the current-voltage transfer function (i.e., v in2 or v y The conversion from i to i can be linearized with the exemplary circuit configuration of Figure 6. That is, the transconductance stage of transconductance G, which is stacked on top of the transconductance stage of transconductance G, can be linearized in that it is driven with a (pre-)distortion voltage that compensates for the nonlinearity of the voltage drive.

[0080] 7 is a diagram showing another example of a circuit diagram of a multiplier according to an embodiment. Similar to the multiplier shown in FIG. 4, the multiplier shown in FIG. 7 is a transconductance-based analog multiplier, or in other words, an analog multiplier based on the Gilbert principle (i.e., a Gilbert-type multiplier), and is configured to receive a first input voltage v x and the second input voltage v y is an analog multiplier configured to generate an output current i0 that represents the product of

[0081] As shown in Fig. 7, the multiplier 1B has the same basic configuration as the multiplier 1A in Fig. 4. That is, the multiplier 1B includes a first transconductance stage 10, a pair of second transconductance stages 20, a pair of third transconductance stages 30, and a coupling network 40, which have the same or equivalent functions and configurations as those described in relation to Fig. 4. Therefore, detailed description thereof will be omitted.

[0082] More specifically, the multiplier 1B adopts a linearized voltage input unit 15 as shown in FIG. 5 in the first transconductance stage 10, and a linearized voltage input unit 25 as shown in FIG. 6 in both the second transconductance stage 20 and the third transconductance stage 30. In other words, the linearized transconductance of FIG. 5 for the first stage (previous stage) of the stacked (or cascaded) transconductance is connected to the second stage (next stage) of the stacked (or cascaded) transconductance driven by a variable current, such as the linearized transconductance unit of FIG. 6. Therefore, in addition to the description of FIG. 4, the description of FIG. 5 and FIG. 6 can be referred to for detailed description.

[0083] The function of multiplier 1B can be briefly explained as follows. Multiplier 1B multiplies two input voltages, namely v x and v y The input voltage v x is the current i x and, as the second factor in the product formation, is supplied as bias currents with opposite signs (i.e., positive and negative) to the transconductances G2B and G2B', respectively. For operating point adjustment, the current I bias2B is the variable current i x The multiplication stages G2B and G2B' are controlled by the predistortion stages G2A and G2A', which apply a voltage v d , and supplies the linearized v y The v at the input of the transconductance stages G2B and G2B' is d are the same, the transconductance stage G2A' can be omitted and the voltage v generated by the transconductance stage G2A can be d may be supplied not only to the transconductance stage G2B but also to the transconductance stage G2B'.

[0084] 8 is a diagram illustrating an example of the modulation characteristic (i.e., signal change) of a multiplier according to the circuit diagram of FIG.

[0085] The y-axis values ​​are the currents at the positive and negative outputs of the transconductance stages G2B and G2B'. The second input voltage v y on the x-axis and v x = 0 and v y The operation point is marked on the bisector of the angle when > 0.

[0086] The first quadrant is the current component where y+ > 0, and the fourth quadrant is the current component where y- < 0. x > 0, the operation line of the transconductance stage G2B' becomes larger in absolute value (i x+y+ , i x+y- ), the operating line of the transconductance stage G2B becomes smaller in absolute value (i x-y+ , i x-y- To calculate the product, the current i x+y+ i x-y- and current i x-y+ i x+y- and subtract each other.

[0087] Thus, the combining network 40 can be configured to generate an output current (representing the product of the first input voltage and the second input voltage) by appropriately combining the respective currents (or differential currents). That is, by appropriately connecting the signal lines carrying the respective currents, these currents are (implicitly) added or subtracted. Also, when combining the differential currents, if it is desired to generate a unipolar output current as the output, a differential-to-unipolar conversion is performed by the combining network 40. Thus, the combining network 40 can generate an output current by a subtraction operation (AB). The subtraction value (B) here is obtained by the combination of the positive-going part (i.e. the output current of the positive output part or + output part) of the output current of the third transconductance stage (which however operates and is supplied with the negative-going part (i.e. the output current of the negative output part or - output part) of the output signal of the first transconductance stage) with the negative-going part (i.e. the output current of the negative output part or - output part) of the output current of the third transconductance stage (which however operates and is supplied with the positive-going part (i.e. the output current of the positive output part or + output part) of the output signal of the first transconductance stage). Furthermore, the value (A) subtracted is obtained by combining the negative-going portion of the output current (i.e. the output current of the negative output section or -output section) of the third transconductance stage (which however operates and is supplied with the negative-going portion of the output signal of the first transconductance stage (i.e. the output current of the negative output section or -output section)) with the positive-going portion of the output current (i.e. the output current of the positive output section or +output section) of the third transconductance stage (which however operates and is supplied with the positive-going portion of the output signal of the first transconductance stage (i.e. the output current of the positive output section or +output section).

[0088] Fig. 9 illustrates an example of an operation process or signal flow according to an embodiment of a multiplier according to the circuit diagram of Fig. 7. That is, Fig. 9 illustrates an operation process or signal flow of a linearized multiplier according to an embodiment.

[0089] The schematic diagram shown in Figure 9 illustrates the operation of a multiplier according to the circuit diagram of Figure 7, i.e., its operating process (i.e., how the multiplier operates) or signal flow. The illustrated operation is merely illustrative of what has been previously described regarding how the multiplier and its elements operate, so the contents of Figure 9 will be obvious to those skilled in the art without further elaboration when referring to the above description together with Figure 7 (as well as Figures 4-6).

[0090] As an example, referring to FIG. 7, stage 10 converts a first input voltage to a current using a linearized transconductance, and stage 20 converts a second input voltage to a predistorted voltage using a linearized transconductance, respectively. The current from stage 10 is subtracted from the bias current of the first transconductance of the upper stage 30. The upper stage 30 also uses the predistorted voltage from the upper stage 20 as an input voltage. The current from stage 10 is added to the bias current of the second transconductance of the lower stage 30. The lower stage 30 also uses the predistorted voltage from the lower stage 20 as an input voltage. And a combining network 40 combines the outputs from the first and second transconductances, i.e., the output from the upper stage 30 and the output from the lower stage 30.

[0091] 10 is a diagram illustrating example transistor circuits for various portions of a multiplier according to an embodiment. Any of the transistor circuits shown in FIG. 10 may be implemented or manufactured separately or may be implemented in a multiplier such as any of the example multipliers 1A, 1B, or 1C illustrated herein.

[0092] As shown in FIG. 10, each part of the multiplier can be realized with CMOS transistors. In FIG. 10, the same reference numerals as in FIG. 7 are used, but they indicate the elements which function as corresponding stages or units of the multiplier. The relationship or connection between the individual elements when incorporated into a multiplier such as that shown in FIG. 7 will be clearly understood from the designation of the corresponding signals. For example, the current I(V) of element 10 which functions as the first transconductance stage is MxP ) and I(V MxN ) is supplied as a current to element 30, which functions as a third transconductance stage, and the voltage V and V YinNG2 are each input as a voltage to element 30 which functions as a third transconductance stage.

[0093] In order for the multiplier (consisting of a combination of elements as shown in FIG. 10) to operate at low supply voltages, the first transconductance stage 10, i.e. the differential pair of transconductance G11, is constructed with NMOS transistors, i.e. the NMOS input stage or input part, and the second and third transconductance stages 20 and 30, i.e. the differential pairs of transconductances G2A, G2A', G2B and G2B', respectively, are constructed with PMOS transistors, i.e. the PMOS input stage or input part. The current mirrors and the loads are not realized here at the transistor level, but with dummy voltage sources with a voltage of 0V. These dummy voltage sources are V M ...The dummy voltage source is a current-controlled current source I(V M ...) are used to measure the currents that control the V MxP and V MxN measures the currents in the first transconductance G11. These currents are calculated by the I(V MxN ) and transconductance G2B' I(V MxP At the transistor level, this function can be realized with a current mirror.

[0094] In the first transconductance stage 10, the first transconductance G11 is connected to the first input voltage v x Processing voltage v x V XinP and V XinN The current generated by the first transconductance G11 is applied to the input of the transconductance G11 as a bias current source I to realize negative feedback. bias ×I gain It is compared with / 2. Coefficient I gain is used to adjust the gain of the first transconductance G11, and therefore the level of negative feedback, and controls the level of linearization of the first transconductance G11.

[0095] In the second and third transconductance stages 20 and 30, the gate nodes V YinNG and V YinPG are connected to each other via the labels on the wires. The gate nodes V of the transconductances G2A and G2B YinNG2 and V YinPG2 The transconductances G2A' and G2A generate a voltage at the input node of the differential stage through a negative feedback network, which in turn feeds the matched transconductances G2B' and G2B to a second input voltage v y The operating current of the transconductances G2B', G2B, controlled by the first transconductance stage 10, is proportional to the first input voltage v x Since it is proportional to the input voltage v x , v yThen, in the combining network 40, the differential current results of the transconductances G2B' and G2B are combined with the correct sign using the current controlled voltage sources CCVS1-CCVS4 to obtain the multiplication result VOUT.

[0096] FIG. 11 is a diagram showing an example of modulation characteristics of a multiplier according to the transistor circuit of FIG. 10, ie, a result of a transistor simulation, according to an embodiment.

[0097] As shown in Figure 11, the second input voltage v y On the x-axis, the first input voltage v x is changed in 100mV increments as a parameter. y = ±400 mV, demonstrating the precision of the multiplier in the implementation shown in FIG.

[0098] Multiplication of small numbers, i.e., currents on the order of μA, produces small numbers on the order of nV in the model of the multiplier with a current-controlled voltage source, as shown in Figure 10, but produces much larger voltage levels in the actual transistor circuit.

[0099] FIG. 12 is a diagram showing an example of linear characteristics of a multiplier according to the transistor circuit of FIG. 10, ie, a result of a transistor simulation, according to an embodiment.

[0100] The linearity of the multiplier in the configuration shown in Figure 10 can be seen from the plot derivation of the characteristic curve, as shown in Figure 12. At 0.5μ the derivatives are exactly equidistant, and v y = 270mV,v x Even at the = 400mV level (i.e., the upper marker), the deviation of the derivative from the nominal value of 2.00μ is less than 0.5%, i.e., 1.991μ. y = 300mV, v x At the level of = 100mV (i.e. the lower marker), the derivative does not show any deviation and is located at the nominal value of 500n, at which point there is no error.

[0101] As described above, a multiplier with improved linearity, particularly a Gilbert-type multiplier using CMOS technology, can be realized with the circuit configuration of Figure 4, Figure 7, or Figure 9. However, as will be described below, it is possible to further improve the linearity.

[0102] When the transconductances G2B and G2B' are linearized by the transconductances G2A and G2A', i.e., when a voltage input unit 25 is provided as shown in FIG. 6 and FIG. 7, the voltage v formed by the transconductances G2A / G2A' is d is the voltage at its input, v d current i x-y+ and i x-y+ However, this assumption is incorrect because the transconductance characteristic Gm of the transconductance element G2B is exactly the inverse function of the bias current I bias2B -i x is precisely proportional to the bias current I bias2B +i x This is only true if the inverse function is exactly proportional to G2A / G2A. The finite amplification of the transconductance G2A / G2A may result in deviation from the desired inverse function.

[0103] Fig. 13 shows an example of an error characteristic with respect to a first input voltage of a multiplier according to the circuit diagram of Fig. 7 according to an embodiment, and Fig. 14 shows an example of an error characteristic with respect to a second input voltage of a multiplier according to the circuit diagram of Fig. 7 according to an embodiment. That is, Fig. 13 and Fig. 14 show the results of a simulation based on the circuit diagram of Fig. 7. The simulation involves the implementation of an element or unit according to any of the transistor circuits as shown in Fig. 10.

[0104] As shown in Figure 13, the first input voltage v x The second input voltage v can be varied from -1V to +1V. yis a parameter that can be increased from 0 V to 1 V in steps of 0.1 V. The graphs in Fig. 13, from top to bottom, show the product in Fig. 13(a), the absolute error in Fig. 13(b), and the relative error in Fig. 13(c).

[0105] In FIG. 14, the second input voltage v y is varied from -1V to +1V, and the second input voltage v x is a parameter that is increased from 0 V to 1 V in steps of 0.1 V. The individual graphs in Fig. 14, from top to bottom, show the product in Fig. 14(a), the absolute error in Fig. 14(b), and the relative error in Fig. 14(c).

[0106] As a basis for error calculation, v x = 0.1V and v y = 0.1 V. From Fig. 13(c) we can see that: y If is large, the error is v x It is almost independent of v and has a maximum of 1%, which corresponds to 10×10-3 = 10mV. y = 100mV, the error calculation is normalized to 100mV, so the relative error is v x = 100 mV, the relative error curves in Figure 13(c) are not equidistant. This fact is due to the fact that y By continuously changing v x This is reflected in the approximate parabolic shape of the relative error when the parameter is changed stepwise from 0 V to 1 V. Such an error curve is shown in Fig. 14(c).

[0107] In light of this discovery, the linearization of the transconductances G2B and G2B' by the transconductances G2A and G2A' can be further improved.

[0108] In some embodiments, the multiplier comprises an error compensation circuit configured to generate a compensation voltage to compensate for an error in the output current relative to a precise algebraic product of the first input voltage and the second input voltage.

[0109] FIG. 15 is a diagram showing yet another example of a circuit diagram of a multiplier according to an embodiment. Similar to the multipliers shown in FIG. 4 and FIG. 7, the multiplier shown in FIG. 15 is an analog multiplier based on transconductance, or in other words, an analog multiplier based on the Gilbert principle (i.e., a Gilbert-type multiplier), and has a first input voltage v x and the second input voltage v y is an analog multiplier configured to generate an output current i0 that represents the product of

[0110] As shown in FIG. 15, the multiplier 1C has the same basic configuration as the multiplier 1B in FIG. 7. That is, the multiplier 1C includes a first transconductance stage 10, a second transconductance stage 20, a pair of third transconductance stages 30, and a coupling network 40. These have the same or equivalent functions and configurations as those described in relation to FIG. 4 and FIG. 7. Therefore, detailed description thereof will be omitted. In the circuit configuration of FIG. 15, a single second transconductance stage 20 is used to provide a pre-distortion voltage for the second input voltage, and a voltage based on this pre-distortion voltage (i.e., a compensation voltage v Ycomp ) are input to both of the third transconductance stages 30 pair, respectively.

[0111] Compared to the circuit configuration of FIG. 7, the multiplier 1C of FIG. 15 is expanded by a compensation circuit. This compensation circuit is configured to reduce the error. This error reduction can be about 10 times, as shown below in FIGS. 16 and 17 by simulation. In some embodiments, the compensation circuit is realized by a combination of a second transconductance stage 20, a fourth transconductance stage 50 and a multiply-add network 60, which in the circuit configuration of FIG. 15 replaces the second transconductance stage 20 in the circuit configuration of FIG. 7.

[0112] As shown in FIG. 15, the compensation circuit of the multiplier 1C is a compensation voltage v Ycomp That is, the transconductance stage 20 generates the predistortion voltage v dGA2 and the transconductance stage 50 (without providing gain or negative feedback) generates a scaled voltage v G3 Next, the predistortion voltage v dGA2 is multiplied by the coefficient ky to obtain the scaled voltage v G3 is multiplied by the coefficient (1-ky) and the resulting multiplied voltage is added (by an adder or summing circuit) to obtain the compensation voltage v Ycomp , i.e. v Ycomp = v dGA2 ×ky + v G3 × (1-ky). The compensation voltage v Ycomp are input to a third transconductance stage 30, ie, transconductances G2B and G2B', respectively.

[0113] Note that the multiplication of ky by (1-ky) can be accomplished with a multiplier, but does not require a multiplier. Rather, since the multiplication is by a constant, such multiplication can be accomplished with a voltage divider or potentiometer.

[0114] When ky = 1, the output voltage of the transconductance G3 (v G3 ) is v G3 is multiplied by 0, so it has no effect on the correction voltage, and the output voltage of transconductance G2A (v dGA2 ) is v dGA2 is multiplied by 1, so it is used as the correction voltage as is. Therefore, the circuit configuration in FIG. 15 has the same function as the circuit configuration in FIG.

[0115] As explained above, the coefficient ky for error compensation can be selected between 0 and 1. In that case, the voltage v dGA2 and v G3is multiplied by ky and (1-ky). The sum of the coefficients ky and (1-ky) is equal to 1. In the illustrated example which produced the simulation results of Figures 13 and 14, ky may be preferably set to 0.45 to obtain optimal error compensation (i.e., error compensation by a factor of 10).

[0116] However, the coefficient k for error compensation can be chosen to be greater than 1, for example 10. In that case, the voltage v dGA2 and v G3 is multiplied by ky and 1 / ky, where the product of the coefficients ky and 1 / ky is equal to 1. Also preferably, a normalization by the coefficient ky may be applied subsequently, i.e., such normalization may be applied before the adder / summer.

[0117] The coefficient k for error compensation may be selected manually or automatically. For example, the coefficient k may be set by a user, operator, designer, etc., taking into account the results of a simulation and / or test. Or, the coefficient k may be set by a control circuit (not shown) to minimize an error value based on a simulation and / or test. For example, the coefficient k may be set by the control circuit by feedback control in response to an error value obtained in a simulation or test.

[0118] Without additional error compensation, the voltage V generated by the second transconductance stage 20 dG2A will be fed directly to the voltage inputs of the transconductances G2B and G2B'.

[0119] As shown in Fig. 7, the transconductance G2A', i.e. an additional second transconductance stage, is not necessary, because the transconductances G2A and G2A' generate the same voltage, and therefore the transconductance G2A' is redundant as shown above. In any case, the multiplier 1C can be constructed from two compensation circuits (each equivalent to the compensation circuit shown in Fig. 15), with the compensated voltage of one compensation circuit (corresponding to the transconductance G2A) being fed to the voltage input of the transconductance G2B, and the compensated voltage of the other compensation circuit (corresponding to the transconductance G2A') being fed to the voltage input of the transconductance G2B'.

[0120] According to the embodiment of Fig. 15, the multiplier 1C comprises at least one fourth transconductance stage 50, which has a transconductance G3. The fourth transconductance stage 50 is configured to receive a second input voltage and output a scaled voltage of the second input voltage when a third fixed bias current is provided. The multiplier 1C also comprises at least one multiplier-summing network 60. The multiplier-summing network 60 is configured to generate a compensation voltage of the second input voltage by multiplying a predistortion voltage of the second input voltage from the second transconductance stage by a first coefficient, multiplying a scaled voltage of the second input voltage from the fourth transconductance stage by a second coefficient, and adding the multiplied predistortion voltage and the multiplied scaled voltage. Each of the third transconductance stages 30 is configured to receive a compensated voltage of the second input voltage from the multiplier-summing network 60.

[0121] Fig. 16 shows an example of an error characteristic with respect to a first input voltage of a multiplier according to the circuit diagram of Fig. 15 according to an embodiment, and Fig. 17 shows an example of an error characteristic with respect to a second input voltage of a multiplier according to the circuit diagram of Fig. 15 according to an embodiment. That is, Fig. 16 and Fig. 17 show the results of a simulation based on the circuit diagram of Fig. 15. The simulation involves the implementation of an element or unit according to any of the transistor circuits as shown in Fig. 10.

[0122] The graphs in Figures 16 and 17 are equivalent to the graphs in Figures 13 and 14, so please refer to the explanations in those graphs for details. Repetition of the explanation will be omitted here. As mentioned above, the graphs in Figures 16 and 17 are the results of a simulation based on the circuit diagram in Figure 15, with a coefficient ky of 0.45 applied.

[0123] Comparing Figures 16 and 17 with Figures 13 and 14, it can be seen that a factor of 10 error correction is possible. x0 = 0.1V and v y0 = 0.1V, all relative errors are less than 0.1%.

[0124] Figure 18 illustrates an example of an operation process or signal flow of a multiplier according to the circuit diagram of Figure 15 in accordance with an embodiment. That is, Figure 18 illustrates an operation process or signal flow of a linearized and error-compensated multiplier in accordance with an embodiment.

[0125] The schematic diagram shown in Figure 18 illustrates the operation of a multiplier according to the circuit diagram of Figure 15, i.e., its operating process (i.e., how the multiplier operates) or signal flow. The illustrated operation is merely illustrative of what has been previously described regarding how the multiplier and its elements operate, so the contents of Figure 15 will be obvious to those skilled in the art without further elaboration when referring to the above description together with Figure 15 (as well as Figures 4-7).

[0126] As an example, referring to FIG. 15, stage 10 converts a first input voltage to a current using a linearized transconductance, and stage 20 converts a second input voltage to a predistorted voltage using a linearized transconductance and converts the second input voltage to a voltage using a gain (transconductance). Stage 60 combines the outputs from stage 20 and stage 50 to generate a compensated voltage. The current from stage 10 is subtracted from the bias current of the first transconductance of the upper stage 30, which uses the compensation voltage from stage 60 as its input voltage. The current from stage 10 is also added to the bias current of the second transconductance of the lower stage 30, which uses the compensation voltage from stage 60 as its input voltage. The combining network 40 then combines the outputs from the first and second transconductances, i.e., the output from the upper stage 30 and the output from the lower stage 30.

[0127] As described above, the circuit configuration of FIG. 15 makes it possible to realize a multiplier with further improved linearity, in particular a Gilbert-type multiplier using CMOS technology.

[0128] Various examples and embodiments have been disclosed above for realizing a multiplier having high linearity, that is, a multiplier capable of realizing high-precision multiplication, particularly a Gilbert-type multiplier using CMOS technology.

[0129] The examples and embodiments thus disclosed are for illustrative purposes and are not intended to limit the present disclosure. For example, analog multipliers have been illustrated, i.e., configurations in which an analog input signal (e.g., a voltage) is multiplied to generate an analog output signal (e.g., a current). However, the present disclosure is not limited to such (fully) analog configurations, but equally encompasses fully or partially digital configurations, e.g., multipliers that combine analog and digital designs. In such (designs of) analog-digital multipliers, an analog signal may be pulse-width modulated (PWM), and the PWM signal may be used as the input signal; and / or a reference signal of a digital-to-analog converter (DAC) may be used as one analog input signal and a digital input of the DAC as the other analog input signal, for example.

[0130] Although a multiplier has been described so far, the circuit configuration disclosed in this application may be generally applied to any kind of electric circuit, unit or device. For example, the illustrated multiplier may be applied to a digital-to-analog converter (DAC) or any other element that may be considered as (part of) a multiplier, at least under certain conditions and / or assumptions. Furthermore, the illustrated multiplier may be applied to any kind of analog computing circuit or device, and may also be applied to a computer for (implementing or realizing) artificial intelligence, a computer for (performing) neural signal processing, a circuit or device for (implementing or realizing) any kind of neural network, etc. Thus, the present disclosure enables the construction of an analog computing circuit or device or an analog computer based on CMOS technology that is suitable and competitive in the field of neural signal processing and neural networks as well as artificial intelligence.

[0131] Furthermore, it should be noted that all illustrated elements, stages, units, etc. can be implemented and used alone or in any conceivable combination, and the illustrated circuit configurations and configurations merely represent non-limiting examples, for example, the units of Figures 5 and 6, respectively, can be applied / used in any kind of electrical circuit, unit, or device (even other than a multiplier).

[0132] As further supplements / additions, the following descriptions are provided, which are applicable to the present disclosure and therefore constitute a part of the present disclosure:

[0133] A highly linear multiplier is provided having at least some of the following characteristics:

[0134] Multiple transconductance stages connected in series (differential stages) can be used.

[0135] The transconductance stage (differential stage) at the input of the input voltage is linearized by negative feedback.

[0136] The transconductance stage (differential stage) can be realized with MOS or CMOS transistors as the transconductance.

[0137] A first signal input is converted to a current by a linearized transconductance stage or a transconductance and fed as a differential current to a second transconductance stage (differential stage).

[0138] A second transconductance is connected to the second signal input and is linearized using a third transconductance with negative feedback to convert the second signal input to a differential signal for the second transconductance. The second transconductance does not require negative feedback.

[0139] The second transconductance can be implemented twice. One of the transconductances is fed with a positive current from the first transconductance. The other of the transconductances is fed with a negative current from the first transconductance. The currents from these two transconductances are combined with the correct sign to produce an output signal equivalent to a four-quadrant multiplier.

[0140] The high linearity multiplier is based on the following considerations.

[0141] Nonlinearities in a differential MOS or CMOS stage are due to the inherently nonlinear current-to-voltage conversion, and are reduced by the non-proportional sharing of the common currents of the differential stages for a fixed input voltage.

[0142] A transconductance stage (differential stage) fed by current from the first transconductance is driven with a voltage that is predistorted with respect to the original second input voltage such that the change in differential current is proportional to the original second input voltage.

[0143] Predistortion is achieved by adding to the transconductance to be linearized an equal or (substantially) identical transconductance with negative feedback, such that the signal for driving the transconductance to be linearized is generated at the transistor input of this negative feedback transconductance.

[0144] It is possible to realize a cascade of transconductances, which is useful for realizing the function of a four-quadrant multiplier, in which a first transconductance has at least two identical current outputs, one of which is used for negative feedback and the other current output is used to supply the operating current of a subsequent or cascaded transconductance.

[0145] In addition to applying the second signal input to a linearized transconductance (with negative feedback) for predistortion, the error of the multiplier can be further reduced by using a non-predistorted second signal input that is simply scaled, for example with a gain smaller than 1. Two transconductances are then fed to the voltage input that add the scaled second input signal and a scaled portion of the predistorted second input signal, treating the predistorted second input signal as a voltage and the first input signal as a current.

[0146] Additionally, the present disclosure is directed to all possible combinations of the above described components or functional elements so long as the concepts of the above described methods and configurations are applicable.

[0147] In view of the above, there is provided a linear multiplier configured to generate an output current representative of the product of a first input voltage and a second input voltage, the multiplier comprising: a first transconductance stage configured to receive a first input voltage and output a first set of differential currents, the first transconductance stage having a negative feedback network; at least one second transconductance stage configured to receive a second input voltage and output a predistorted voltage of the second input voltage, each transconductance stage having a negative feedback network; a third pair of transconductance stages each configured to receive a voltage corresponding to the predistortion voltage of the second input voltage and output a second set of differential currents when a bias current corresponding to one of the first set of differential currents is provided; Equipped with.

[0148] Although the present disclosure has been described with reference to the embodiments illustrated in the accompanying drawings, the present disclosure is not limited to these embodiments, and it will be apparent to those skilled in the art that the disclosed embodiments can be modified in many ways without departing from the inventive concept disclosed.

Claims

1. a multiplier configured to generate an output current representative of a product of a first input voltage and a second input voltage, a first transconductance stage configured to convert the first input voltage into a first current change when provided with a first fixed bias current and to output a positive going portion of the first current change and a negative going portion of the first current change, the first transconductance stage having a negative feedback network; at least one second transconductance stage configured to receive the second input voltage and output a predistorted voltage of the second input voltage when a second fixed bias current is provided thereto, each transconductance stage having a negative feedback network; a first third transconductance stage configured to receive a voltage corresponding to the predistortion voltage of the second input voltage and output a first second current change when a bias current corresponding to the positive going portion is provided; a second third transconductance stage configured to receive a voltage corresponding to the predistortion voltage of the second input voltage and output a second second current change when a bias current corresponding to the negative going portion is provided; a combining network configured to subtractively combine the first second current change and the second second current change to generate an output current; The multiplier comprises:

2. the first transconductance stage having two current outputs for the first current change; the first transconductance stage is configured such that, for the first current change, one of the two current outputs is subtracted from a first reference current corresponding to an output current at an operating point of the first transconductance stage, the resulting current difference is fed back to an input side of the first transconductance stage via a feedback resistor, and the other of the two current outputs is output from the first transconductance stage. The multiplier of claim 1 .

3. each of the second transconductance stages is configured such that a pair of currents at the output side of the second transconductance stage is subtracted from a second reference current corresponding to the output current of the second transconductance stage at an operating point, and the resulting current difference is fed back to the input side of the second transconductance stage via a feedback resistor of a feedback path; each of the second transconductance stages is configured to output a potential difference across the feedback path as the predistortion voltage; 3. A multiplier according to claim 1 or 2.

4. 4. The multiplier according to claim 1, wherein the second fixed bias current of the second transconductance stage is set to the middle of a range of bias currents of the first or second third transconductance stage configured to receive a voltage based on the predistortion voltage from the second transconductance stage.

5. A multiplier as described in any one of claims 1 to 4, wherein the transconductance of the second transconductance stage is substantially equal to that of the first or second third transconductance stage configured to input a voltage based on the pre-distortion voltage from the second transconductance stage.

6. A multiplier as described in any one of claims 1 to 5, wherein the internal transconductance characteristics of the transconductance of the second transconductance stage and the internal transconductance characteristics of the transconductance of the first or second third transconductance stage configured to input a voltage based on the pre-distortion voltage from the second transconductance stage are equivalent to each other.

7. A multiplier as claimed in any one of claims 1 to 6, wherein a gain of the second transconductance stage is set to output a corresponding one of the first and second second current changes to the first or second third transconductance stage configured to receive a voltage based on the predistortion voltage from the second transconductance stage upon input of the second input voltage, wherein the first and second second current changes are equal to a current change produced by a transconductance of the second transconductance stage upon input of the second input voltage.

8. A multiplier as described in any one of claims 1 to 7, wherein the first or second third transconductance stage is configured to receive an input of the pre-distortion voltage of the second input voltage of the second transconductance stage.

9. 9. The multiplier of claim 1, comprising an error compensation circuit configured to generate a compensation voltage to compensate for an error in an output current for a precise algebraic product of the first input voltage and the second input voltage.

10. at least one fourth transconductance stage configured to output a scaled version of the second input voltage when the second input voltage is received and a third fixed bias current is provided; a multiplier-summing network configured to generate a compensation voltage for the second input voltage by multiplying the predistorted voltage of the second input voltage from a second transconductance stage by a first coefficient, multiplying the scaled voltage of the second input voltage from a fourth transconductance stage by a second coefficient, and adding the multiplied predistorted voltage and the multiplied scaled voltage; Further comprising: the first or second third transconductance stage is configured to receive the compensated voltage of the second input voltage from a multiplier-summing network; The multiplier of claim 9.

11. A multiplier according to any one of claims 1 to 10, Each transconductance stage is a multiplier consisting of a differential pair of CMOS transistors with the bias current as the tail current.

12. A multiplier according to any one of claims 1 to 11, integrated in CMOS technology.

13. 13. The multiplier according to claim 11, wherein the first transconductance stage is composed of NMOS transistors, and the second transconductance stage and the first and second third transconductance stages are all composed of PMOS transistors.

14. the first input voltage and the second input voltage are or represent analog signals; at least one of the first input voltage and the second input voltage is or represents a signal resulting from pulse width modulation of an analog signal; one of the first input voltage and the second input voltage is or represents a signal representative of a reference signal of a digital-to-analog converter, and the other of the first input voltage and the second input voltage is or represents a signal representative of a digital input of a digital-to-analog converter; A multiplier according to any preceding claim.

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