How passive elements work

Abstract

To provide a wiring structure and the like that can suppress an increase in a resistance value of a wiring layer due to miniaturization.SOLUTION: In a method of operating a passive element for operating a passive element electrically connected to a wiring structure 1, the wiring structure 1 includes a wiring layer 10 mainly composed of metal and extending in one direction, a metal layer 20 facing the wiring layer 10, and a solid electrolyte layer 30 that is located between the wiring layer 10 and the metal layer 20 and is formed to surround the wiring layer 10 in a cross-sectional view taken along a plane perpendicular to one direction, the wiring layer 10 and the metal layer 20 are electrically insulated via the solid electrolyte layer 30, the passive element is electrically connected to the wiring layer 10, and in a state in which a voltage is applied to the solid electrolyte layer 30, an electric signal is transmitted from the passive element to the wiring layer 10, or an electric signal is transmitted from the wiring layer 10 to the passive element.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present disclosure relates to a wiring structure, a semiconductor device, a method of operating an active element, a method of manufacturing a wiring structure, a method of using a wiring structure, and a method of manufacturing a wiring resistor of a wiring structure. [Background technology]

[0002] Patent Document 1 discloses a method for forming a cobalt wiring made of cobalt (Co). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2016 / 0309596 Summary of the Invention [Problem to be solved by the invention]

[0004] In semiconductor devices such as semiconductor integrated circuit devices, active elements such as transistors and diodes as well as passive elements such as capacitors and resistors are formed as circuit elements by semiconductor microfabrication. Furthermore, in the semiconductor device, wiring for connecting these circuit elements to each other is also formed by semiconductor microfabrication.

[0005] In recent years, as semiconductor devices have become finer, there has been a demand for finer wiring. However, there is a problem in that finer wiring increases the resistance of the wiring.

[0006] An object of the present disclosure is to provide a wiring structure and a semiconductor device that can suppress an increase in the resistance value of a wiring layer that accompanies miniaturization. [Means for solving the problem]

[0007] One aspect of the method for operating a passive element according to the present disclosure is a method for operating a passive element electrically connected to a wiring structure, the wiring structure comprising: a wiring layer having a metal as a main component and extending in one direction; a metal layer facing the wiring layer; and a solid electrolyte layer located between the wiring layer and the metal layer in a cross-sectional view when cut along a plane perpendicular to the one direction and formed to encase the wiring layer, the wiring layer and the metal layer being electrically insulated via the solid electrolyte layer, the passive element being electrically connected to the wiring layer, and when a voltage is applied to the solid electrolyte layer, an electrical signal is transmitted from the passive element to the wiring layer or an electrical signal is transmitted from the wiring layer to the passive element.

[0008] Another aspect of the method for operating a passive element according to the present disclosure is a method for operating a passive element electrically connected to a wiring structure, the wiring structure comprising: a wiring layer containing metal as a main component and extending in one direction; a metal layer facing the wiring layer; and a solid electrolyte layer located between the wiring layer and the metal layer and in contact with each of the wiring layer and the metal layer in a cross-sectional view when cut along a plane perpendicular to the one direction, a side of the wiring layer and a side of the solid electrolyte layer are in surface-to-surface contact, a side of the solid electrolyte layer and a side of the metal layer are in surface-to-surface contact, the wiring layer and the metal layer are electrically insulated via the solid electrolyte layer, the passive element is electrically connected to the wiring layer, and when a voltage is applied to the solid electrolyte layer, an electrical signal is transmitted from the passive element to the wiring layer or an electrical signal is transmitted from the wiring layer to the passive element. Effect of the Invention

[0009] According to the present disclosure, it is possible to realize a wiring structure etc. capable of suppressing an increase in the resistance value of a wiring layer that accompanies miniaturization. [Brief description of the drawings]

[0010] [Figure 1A] 1 is a diagram illustrating a schematic configuration of a wiring structure according to a first aspect of the first embodiment. [Figure 1B]Cross-sectional view of the wiring structure according to the first aspect of Embodiment 1. [Figure 1C] Cross-sectional view of the wiring structure according to the first aspect of Embodiment 1 taken along line 1C-1C of FIG. 1B. [Figure 2A] Schematic diagram showing the state inside the solid electrolyte layer when a voltage is applied with V1 < V2 in a wiring structure having a cation-conductive solid electrolyte layer. [Figure 2B] Schematic diagram showing the state inside the solid electrolyte layer when a voltage is applied with V1 < V2 in a wiring structure having an anion-conductive solid electrolyte layer. [Diagram 3] Diagram showing the configuration of the wiring structure and the semiconductor device according to the second aspect of Embodiment 1. [Figure 4] Diagram showing the configuration of the first semiconductor device according to the second aspect of Embodiment 1. [Diagram 5] Diagram showing the configuration of the second semiconductor device according to the second aspect of Embodiment 1. [Figure 6] Diagram showing the configuration of the third semiconductor device according to the second aspect of Embodiment 1. [Figure 7] Cross-sectional view showing the configuration of the wiring structure and the semiconductor device according to the third aspect of Embodiment 1. [Figure 8A] Cross-sectional view of the wiring structure according to the example. [Figure 8B] Cross-sectional view of the wiring structure according to the example taken along line 8B-8B of FIG. 8A. [Figure 9A] Cross-sectional view of the wiring structure of the comparative example. [Figure 9B] Cross-sectional view of the wiring structure of the comparative example taken along line 9B-9B of FIG. 9A. [Figure 10] Diagram showing the relationship between the line width and the resistance value in the wiring structure according to the example. [Figure 11A] Cross-sectional view showing the first interlayer insulation layer formation step in the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 11B]1 is a perspective view showing a first interlayer insulating layer forming step in the method for manufacturing a semiconductor device according to the first embodiment. FIG. [Figure 11C] 5 is a cross-sectional view showing a recess forming step in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 11D] 10 is a perspective view showing a recess forming step in the manufacturing method for the semiconductor device according to the first embodiment. FIG. [Figure 11E] 5 is a cross-sectional view showing a first metal layer forming step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11F] 5 is a cross-sectional view showing a first solid electrolyte layer forming step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11G] 5 is a cross-sectional view showing a wiring layer forming step in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 11H] 5 is a cross-sectional view showing a first resist formation step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11I] 5 is a cross-sectional view showing a wiring layer patterning step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11J] 5A to 5C are cross-sectional views showing a first resist removal step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11K] 5 is a cross-sectional view showing a second resist formation step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11L] 5 is a cross-sectional view showing a first solid electrolyte layer patterning step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11M] 5 is a cross-sectional view showing a second resist removal step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11N] 5A to 5C are cross-sectional views showing a third resist formation step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11O] 5 is a cross-sectional view showing a first metal layer patterning step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11P]5A to 5C are cross-sectional views showing a third resist removal step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11Q] 5 is a cross-sectional view showing a second solid electrolyte layer forming step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11R] 5A to 5C are cross-sectional views showing a fourth resist formation step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11S] 5 is a cross-sectional view showing a second solid electrolyte layer patterning step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11T] 5A to 5C are cross-sectional views showing a fourth resist removal step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11U] 5 is a cross-sectional view showing a second metal layer forming step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11V] 5A to 5C are cross-sectional views showing a fifth resist formation step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11W] 5A to 5C are cross-sectional views showing a second metal layer patterning step in the method for manufacturing the semiconductor device according to the first embodiment. [Fig. 11X] 5A to 5C are cross-sectional views showing a fifth resist removal step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11Y] 5 is a cross-sectional view showing a second interlayer insulating layer forming step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 12] FIG. 1 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 13A] 11 is a cross-sectional view showing a step of embedding a first metal layer, a first solid electrolyte layer, and a wiring layer in a recess in a first interlayer insulating layer in a manufacturing method of a semiconductor device according to a first modification of the first embodiment. FIG. [Figure 13B] 10 is a cross-sectional view showing a polishing step in a method for manufacturing a semiconductor device according to Modification 1 of the first embodiment. [Figure 13C] 11 is a cross-sectional view showing a step of forming a second interlayer insulating layer having a recess on an underlying wiring structure in a manufacturing method of a semiconductor device according to Modification 1 of the first embodiment. FIG. [Figure 13D] 13 is a cross-sectional view showing a step of embedding a second wiring path in a recess in a second interlayer insulating layer in a manufacturing method of a semiconductor device according to Modification 1 of the first embodiment. FIG. [Figure 14] FIG. 11 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 15] FIG. 11 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment. [Figure 16] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 17] FIG. 11 is a cross-sectional view of a semiconductor device according to a fifth modification of the first embodiment. [Figure 18A] FIG. 2 is a plan view of a wiring structure used in an experiment. [Figure 18B] 18B is a cross-sectional view of the wiring structure taken along line 18B-18B in FIG. 18A. [Figure 19] FIG. 13 is a diagram showing the relationship between the resistance value and the applied voltage of a first electrode layer in a wiring structure according to an experimental example. [Figure 20A] FIG. 13 is a diagram showing a change in potential difference over time. [Figure 20B] FIG. 13 shows the change in resistance over time. [Figure 20C] FIG. 13 is a diagram showing a change in current over time. [Figure 21A] 10 is a diagram illustrating a schematic configuration of a wiring structure according to a first aspect of the second embodiment. FIG. [Figure 21B] 11 is a cross-sectional view of a wiring structure according to a first aspect of the second embodiment. FIG. [Figure 21C] 21C is a cross-sectional view of the wiring structure according to the first aspect of the second embodiment taken along line 21C-21C in FIG. 21B. [Figure 22] 13 is a diagram showing configurations of a wiring structure and a semiconductor device according to a second aspect of the second embodiment. FIG. [Figure 23] FIG. 13 is a diagram showing a configuration of a semiconductor device according to a second aspect of the second embodiment. [Figure 24] 11 is a cross-sectional view showing a configuration of a wiring structure and a semiconductor device according to a third aspect of the second embodiment. FIG. [Figure 25A]11 is a cross-sectional view showing a first interlayer insulating layer forming step in a manufacturing method for a semiconductor device according to a second embodiment. FIG. [Figure 25B] 11 is a cross-sectional view showing a recess forming step in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 25C] 11 is a cross-sectional view showing a first metal layer forming step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Figure 25D] 11 is a cross-sectional view showing a first solid electrolyte layer forming step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Figure 25E] 11 is a cross-sectional view showing a first insulating layer forming step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Figure 25F] 11 is a cross-sectional view showing a wiring layer forming step in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 25G] 11 is a cross-sectional view showing a first resist formation step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Fig. 25H] 11 is a cross-sectional view showing a wiring layer patterning step in a manufacturing method of a semiconductor device according to a second embodiment. FIG. [Figure 25I] 11 is a cross-sectional view showing a first resist removal step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Figure 25J] 11 is a cross-sectional view showing a second insulating layer forming step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Figure 25K] 11 is a cross-sectional view showing a second resist forming step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Figure 25L] 11 is a cross-sectional view showing a first solid electrolyte layer patterning step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Figure 25M] 11 is a cross-sectional view showing a second resist removal step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Figure 25N] 11 is a cross-sectional view showing a third resist formation step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Figure 25O]11 is a cross-sectional view showing a first metal layer patterning step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Figure 25P] 11 is a cross-sectional view showing a third resist removal step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Figure 25Q] 11 is a cross-sectional view showing a second solid electrolyte layer forming step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Figure 25R] 10 is a cross-sectional view showing a fourth resist formation step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Figure 25S] 11 is a cross-sectional view showing a second solid electrolyte layer patterning step in a method for manufacturing a semiconductor device according to a second embodiment. FIG. [Figure 25T] 10 is a cross-sectional view showing a fourth resist removal step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Fig. 25U] 11 is a cross-sectional view showing a second metal layer forming step in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 25V] 10 is a cross-sectional view showing a fifth resist formation step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Fig. 25W] 11 is a cross-sectional view showing a second metal layer patterning step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Fig. 25X] 10 is a cross-sectional view showing a fifth resist removal step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Figure 25Y] 11 is a cross-sectional view showing a second interlayer insulating layer forming step in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 26A] 13 is a diagram illustrating a schematic configuration of a wiring structure according to a first aspect of the third embodiment. FIG. [Figure 26B] 11 is a cross-sectional view of a wiring structure according to a first aspect of the third embodiment. FIG. [Figure 26C] 26C is a cross-sectional view of the wiring structure according to the first aspect of the third embodiment taken along line 26C-26C in FIG. 26B. [Figure 27] 13 is a diagram showing configurations of a wiring structure and a semiconductor device according to a second aspect of the third embodiment. FIG. [Figure 28] FIG. 13 is a diagram showing a configuration of a semiconductor device according to a second aspect of the third embodiment. [Figure 29] 13 is a cross-sectional view showing configurations of a wiring structure and a semiconductor device according to a third aspect of the third embodiment. FIG. [Figure 30A] 13 is a cross-sectional view showing a first interlayer insulating layer forming step in a manufacturing method for a semiconductor device according to a third embodiment. [Figure 30B] 13A to 13C are cross-sectional views showing a recess forming step in a manufacturing method for a semiconductor device according to a third embodiment. [Figure 30C] 13A to 13C are cross-sectional views showing a first metal layer forming step in a method for manufacturing a semiconductor device according to a third embodiment. [Figure 30D] 13A to 13C are cross-sectional views showing a first insulating layer forming step in a manufacturing method for a semiconductor device according to a third embodiment. [Figure 30E] 11 is a cross-sectional view showing a first solid electrolyte layer forming step in a manufacturing method for a semiconductor device according to a third embodiment. FIG. [Figure 30F] 13A to 13C are cross-sectional views showing a wiring layer forming step in a manufacturing method for a semiconductor device according to a third embodiment. [Figure 30G] 13A to 13C are cross-sectional views showing a first resist formation step in a method for manufacturing a semiconductor device according to a third embodiment. [Figure 30H] 13A to 13C are cross-sectional views showing a wiring layer patterning step in a manufacturing method for a semiconductor device according to a third embodiment. [Figure 30I] 13A to 13C are cross-sectional views showing a first resist removal step in the method for manufacturing a semiconductor device according to the third embodiment. [Figure 30J] 13A to 13C are cross-sectional views showing a second resist formation step in the method for manufacturing a semiconductor device according to the third embodiment. [Figure 30K] 13 is a cross-sectional view showing a first solid electrolyte layer patterning step in a manufacturing method for a semiconductor device according to a third embodiment. FIG. [Figure 30L] 13A to 13C are cross-sectional views showing a second resist removal step in the method for manufacturing a semiconductor device according to the third embodiment. [Figure 30M]13A to 13C are cross-sectional views showing a third resist formation step in the method for manufacturing a semiconductor device according to the third embodiment. [Figure 30N] 13 is a cross-sectional view showing a first metal layer patterning step in a manufacturing method for a semiconductor device according to a third embodiment. FIG. [Figure 30O] 13A to 13C are cross-sectional views showing a third resist removal step in the method for manufacturing a semiconductor device according to the third embodiment. [Figure 30P] 11 is a cross-sectional view showing a second solid electrolyte layer forming step in a manufacturing method for a semiconductor device according to a third embodiment. FIG. [Figure 30Q] 13 is a cross-sectional view showing a fourth resist formation step in the method for manufacturing a semiconductor device according to the third embodiment. FIG. [Figure 30R] 13 is a cross-sectional view showing a second solid electrolyte layer patterning step in a method for manufacturing a semiconductor device according to a third embodiment. FIG. [Figure 30S] 13A to 13C are cross-sectional views showing a fourth resist removal step in the method for manufacturing a semiconductor device according to the third embodiment. [Figure 30T] 13 is a cross-sectional view showing a second insulating layer forming step in a manufacturing method for a semiconductor device according to a third embodiment. [Fig. 30U] 13 is a cross-sectional view showing a second metal layer forming step in a method for manufacturing a semiconductor device according to a third embodiment. [Figure 30V] 13 is a cross-sectional view showing a fifth resist formation step in the method for manufacturing a semiconductor device according to the third embodiment. FIG. [Fig. 30W] 13 is a cross-sectional view showing a second metal layer patterning step in the method for manufacturing a semiconductor device according to the third embodiment. FIG. [Fig. 30X] 13A to 13C are cross-sectional views showing a fifth resist removal step in the method for manufacturing a semiconductor device according to the third embodiment. [Figure 30Y] 13 is a cross-sectional view showing a second interlayer insulating layer forming step in a manufacturing method for a semiconductor device according to a third embodiment. [Figure 31A] FIG. 13 is a diagram illustrating a schematic configuration of a wiring structure according to a first aspect of the fourth embodiment. [Figure 31B] 13 is a cross-sectional view of a wiring structure according to a first aspect of the fourth embodiment. FIG. [Figure 31C] 31C is a cross-sectional view of the wiring structure according to the first aspect of the fourth embodiment taken along line 31C-31C in FIG. 31B. [Diagram 32] 13 is a diagram showing configurations of a wiring structure and a semiconductor device according to a second aspect of the fourth embodiment. FIG. [Diagram 33] FIG. 13 is a diagram showing a configuration of a semiconductor device according to a second aspect of the fourth embodiment. [Diagram 34] 13 is a cross-sectional view showing a configuration of a wiring structure and a semiconductor device according to a third aspect of the fourth embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] One aspect of a wiring structure according to the present disclosure comprises a wiring layer containing a metal element as a main component and extending in one direction, a metal layer opposite the wiring layer, and a solid electrolyte layer located between the wiring layer and the metal layer and formed so as to encase the wiring layer in a cross-sectional view when cut along a plane perpendicular to at least the one direction, wherein the wiring layer and the metal layer are electrically insulated via the solid electrolyte layer.

[0012] With this configuration, when a voltage is applied to the solid electrolyte layer, ions move inside the solid electrolyte layer, increasing the electron concentration of the wiring layer. This reduces the resistance of the wiring layer, making it possible to suppress an increase in the resistance of the wiring layer due to thinning. Moreover, the resistance can be reduced compared to a wiring structure of the same line width that does not have a solid electrolyte layer.

[0013] In addition, in one aspect of the wiring structure according to the present disclosure, in the cross-sectional view, the wiring layer has a pair of opposing side surfaces and a bottom surface, and the metal layer and the solid electrolyte may both face each of the pair of side surfaces and the bottom surface.

[0014] This configuration makes it possible to easily realize a wiring structure having a wiring layer whose cross-sectional shape is made up of straight sides, such as a rectangular shape.

[0015] Alternatively, in one aspect of the wiring structure according to the present disclosure, the wiring layer may be circular or elliptical in the cross-sectional view.

[0016] This configuration makes it possible to easily realize a wiring structure having a wiring layer with a circular or elliptical cross-sectional shape.

[0017] In this case, the wiring layer may be a columnar contact plug.

[0018] With this configuration, the wiring structure can be used as a contact plug for use in an interlayer insulating layer of a semiconductor device.

[0019] In addition, in one aspect of the wiring structure according to the present disclosure, in the cross-sectional view, the entire outer periphery of the wiring layer is covered by the solid electrolyte layer, and in the cross-sectional view, the entire outer periphery of the solid electrolyte layer is covered by the metal layer.

[0020] This configuration can improve the effect of reducing the resistance value of the wiring layer by the solid electrolyte layer, and can further suppress an increase in the resistance value of the wiring layer due to thinning.

[0021] In addition, in one aspect of the wiring structure according to the present disclosure, in the cross-sectional view, the entire outer periphery of the wiring layer is covered by a first insulating layer, in the cross-sectional view, the entire outer periphery of the first insulating layer is covered by the solid electrolyte layer, and in the cross-sectional view, the entire outer periphery of the solid electrolyte layer is covered by the metal layer.

[0022] This configuration makes it possible to suppress electron leakage from the wiring layer. In particular, when the wiring layer has a narrow line width, electron leakage from the wiring layer is likely to occur, but by providing the first insulating layer, electron leakage can be effectively suppressed.

[0023] Alternatively, in one aspect of the wiring structure according to the present disclosure, in the cross-sectional view, the entire outer periphery of the wiring layer is covered by the solid electrolyte layer, in the cross-sectional view, the entire outer periphery of the solid electrolyte layer is covered by the second insulating layer, and in the cross-sectional view, the entire outer periphery of the second insulating layer is covered by the metal layer.

[0024] This configuration makes it possible to suppress electron leakage from the wiring layer. In particular, when the wiring layer has a narrow line width, electron leakage from the wiring layer is likely to occur, but by providing the second insulating layer, electron leakage can be effectively suppressed.

[0025] Alternatively, in one aspect of the wiring structure according to the present disclosure, in the cross-sectional view, the entire outer periphery of the wiring layer is covered by a first insulating layer, in the cross-sectional view, the entire outer periphery of the first insulating layer is covered by the solid electrolyte layer, in the cross-sectional view, the entire outer periphery of the solid electrolyte layer is covered by a second insulating layer, and in the cross-sectional view, the entire outer periphery of the second insulating layer is covered by the metal layer.

[0026] This configuration can effectively suppress electron leakage from the wiring layer. In particular, when the wiring layer has a narrow line width, electron leakage from the wiring layer is likely to occur, but by providing the first insulating layer and the second insulating layer, electron leakage can be more effectively suppressed than when only one of the first insulating layer and the second insulating layer is provided.

[0027] In one aspect of the wiring structure according to the present disclosure, an insulating layer may be further provided covering an outer periphery of the metal layer.

[0028] This configuration makes it possible to realize a wiring structure in which a wiring path made up of a wiring layer, a metal layer, and a solid electrolyte layer is embedded in an insulating layer.

[0029] In one aspect of the wiring structure according to the present disclosure, in the cross-sectional view, a ratio of a thickness of the solid electrolyte layer to a thickness of the wiring layer may be greater than 1 / 4.

[0030] Furthermore, in one aspect of the wiring structure according to the present disclosure, in the cross-sectional view, the sum of a thickness of the solid electrolyte layer and a thickness of the wiring layer may be 20 nm or less.

[0031] Furthermore, in one aspect of the wiring structure according to the present disclosure, the width of the wiring layer in the cross-sectional view may be 10 nm or less.

[0032] These configurations can further improve the effect of reducing the resistance of the wiring layer by the solid electrolyte layer, and can further suppress an increase in the resistance of the wiring layer due to thinning.

[0033] In one aspect of the wiring structure according to the present disclosure, the solid electrolyte layer may have a thickness of 5 nm or more in the cross-sectional view.

[0034] This configuration makes it possible to suppress the occurrence of electronic leakage.

[0035] In one aspect of the wiring structure according to the present disclosure, when a voltage is applied to the solid electrolyte layer, ions moving inside the solid electrolyte layer are proton ions, silver ions, copper ions, and the like. The ion may be at least one selected from the group consisting of lithium ions, nickel ions, magnesium ions, iron ions, cobalt ions and manganese ions.

[0036] With this configuration, when a voltage is applied to the solid electrolyte layer, cations move inside the solid electrolyte layer, increasing the electron concentration in the wiring layer, thereby reducing the resistance of the wiring layer and suppressing the increase in resistance of the wiring layer due to thinning.

[0037] Alternatively, in one aspect of the wiring structure according to the present disclosure, when a voltage is applied to the solid electrolyte layer, ions that migrate within the solid electrolyte layer may be at least one selected from the group consisting of hydride ions, hydroxide ions, fluoride ions, chloride ions, bromide ions, iodide ions, and oxygen ions.

[0038] With this configuration, when a voltage is applied to the solid electrolyte layer, anions move inside the solid electrolyte layer, increasing the electron concentration of the wiring layer, thereby reducing the resistance of the wiring layer and suppressing an increase in the resistance of the wiring layer due to thinning.

[0039] In one aspect of the wiring structure according to the present disclosure, the solid electrolyte layer may be made of at least one material selected from the group consisting of lithium oxynitride phosphate and magnesium oxynitride phosphate.

[0040] With this configuration, the solid electrolyte layer can be easily formed by atomic layer deposition, and the solid electrolyte layer can be formed with a uniform thickness. This further improves the effect of reducing the resistance of the wiring layer by the solid electrolyte layer, and further suppresses the increase in the resistance of the wiring layer due to thinning.

[0041] Furthermore, in one aspect of the wiring structure according to the present disclosure, the wiring layer may be made of a material containing cobalt, and the solid electrolyte layer may be made of a material containing lithium oxynitride.

[0042] This configuration ensures that the effect of reducing the resistance value of the wiring layer due to the solid electrolyte layer can be achieved.

[0043] Moreover, one aspect of a semiconductor device according to the present disclosure includes a substrate, a transistor formed on the substrate, and any one of the wiring structures described above formed on the substrate.

[0044] With this configuration, it is possible to realize a semiconductor device including a wiring structure having a wiring layer whose resistance value decreases during operation.

[0045] In addition, in one aspect of the semiconductor device according to the present disclosure, the semiconductor device includes an interlayer insulating layer formed on the wiring structure, and a second wiring layer formed in the interlayer insulating layer, having a larger line width than the wiring layer of the wiring structure, and made of a different material than the first wiring layer.

[0046] This configuration makes it possible to realize a semiconductor device including a wiring layer having a low resistance due to the presence of a solid electrolyte layer and a second wiring layer having a low resistance without a solid electrolyte layer.

[0047] One aspect of a method for operating an active element according to the present disclosure is a method for operating an active element electrically connected to a wiring structure, the wiring structure comprising: a wiring layer containing metal as a main component and extending in one direction; a metal layer facing the wiring layer; and a solid electrolyte layer positioned between the wiring layer and the metal layer in a cross-sectional view taken along a plane perpendicular to the one direction and formed so as to encase the wiring layer, the wiring layer and the metal layer being mutually bonded to each other. The active element is electrically insulated via the solid electrolyte layer, the active element is electrically connected to the wiring layer, and when a voltage is applied to the solid electrolyte layer, an electrical signal is transmitted from the active element to the wiring layer, or an electrical signal is transmitted from the wiring layer to the active element.

[0048] With this configuration, the resistance of the wiring layer of the wiring structure can be reduced, and electrical signals can be transmitted without delay through the wiring layer with reduced resistance.

[0049] In one aspect of the method for operating an active element according to the present disclosure, a first voltage may be applied to the wiring layer, and a second voltage higher than the first voltage may be applied to the metal layer.

[0050] With this configuration, cations can be moved to the wiring layer side of the solid electrolyte layer, thereby reducing the resistance value of the wiring layer.

[0051] Furthermore, one aspect of a method for manufacturing a wiring structure according to the present disclosure includes the steps of forming a metal layer along an inner surface of a recess extending in one direction formed in an insulating layer, forming a solid electrolyte layer to cover the metal layer but not fill the recess, and forming a wiring layer to be enveloped by the solid electrolyte layer and to fill the recess, wherein the wiring layer and the metal layer are electrically insulated via the solid electrolyte layer.

[0052] This makes it possible to obtain a wiring structure in which a wiring path having a configuration in which a solid electrolyte layer is disposed between a wiring layer and a metal layer extending in one direction is embedded in a recess in the insulating layer.

[0053] In one aspect of the method for manufacturing a wiring structure according to the present disclosure, in the step of forming the solid electrolyte layer, the solid electrolyte layer may be formed using an atomic layer deposition method.

[0054] This makes it possible to easily form a solid electrolyte layer with a uniform thickness even if the base on which the solid electrolyte layer is formed has an uneven structure.

[0055] In addition, one aspect of a method for manufacturing a wiring structure according to the present disclosure may include a step of forming an interlayer insulating layer on the wiring structure, and a step of forming a second wiring layer on the interlayer insulating layer, the second wiring layer having a larger line width than the wiring layer of the wiring structure and made of a different material than the first wiring layer.

[0056] This makes it possible to form an interlayer insulating layer on the wiring structure, the interlayer insulating layer having a second wiring layer with a lower resistance than the wiring layer of the wiring structure.

[0057] Moreover, one aspect of the method for manufacturing a wiring structure according to the present disclosure may include the steps of forming a contact hole in the insulating layer, and forming a columnar contact plug in the contact hole.

[0058] In this way, a wiring structure having pillar-shaped contact holes formed therein can be manufactured.

[0059] The present disclosure can also be used as a method for using a wiring structure. Specifically, one aspect of the method for using a wiring structure according to the present disclosure is a method for using any of the wiring structures described above, in which an electrical signal is transmitted to the wiring layer while a voltage is applied to the solid electrolyte layer.

[0060] The present disclosure can also be used as a method for controlling the wiring resistance of a wiring structure. Specifically, the method for controlling the wiring resistance of a wiring structure according to the present disclosure is a method for controlling the wiring resistance of any of the wiring structures described above, in which a voltage applied to the solid electrolyte layer is changed to change the resistance value of the wiring layer.

[0061] (Embodiment) Hereinafter, the embodiments of the present disclosure will be described with reference to the drawings. Note that the embodiments described below all show a comprehensive or specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, the arrangement and connection forms of the components, as well as the steps and the order of the steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept of the present disclosure will be described as optional components.

[0062] In addition, each drawing is a schematic diagram and is not necessarily a precise illustration. Therefore, the scale and the like are not necessarily the same in each drawing. In addition, in each drawing, the same reference numerals are given to substantially the same configurations, and duplicated explanations are omitted or simplified.

[0063] In this specification and the drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a three-dimensional Cartesian coordinate system. The X-axis and Y-axis are mutually orthogonal and are both orthogonal to the Z-axis. In this embodiment, one direction in which the wiring structure and the wiring layer extend is defined as the X-axis direction.

[0064] (Embodiment 1) [Configuration of Wiring Structure and Semiconductor Device] First, the configuration of wiring structure 1 according to a first aspect of embodiment 1 will be described with reference to Figures 1A to 1C. Figure 1A is a diagram illustrating a schematic configuration of wiring structure 1 according to the first aspect of embodiment 1. Figure 1B is a cross-sectional view of wiring structure 1. Figure 1C is a cross-sectional view of wiring structure 1 taken along line 1C-1C in Figure 1B.

[0065] The wiring structure 1 in this embodiment is used in a semiconductor device such as a semiconductor integrated circuit device. Specifically, the wiring structure 1 includes wiring paths 100 for electrically connecting circuit elements to each other in the semiconductor device. Therefore, the wiring paths 100 of the wiring structure 1 propagate electrical signals.

[0066] As shown in FIGS. 1A to 1C, the wiring path 100 of the wiring structure 1 is formed in a linear shape extending in one direction (the X-axis direction in this embodiment). In this case, the wiring path 100 is, for example, a straight path formed in a straight line, but the wiring path 100 is not limited to this as long as it includes a straight portion extending in one direction, and may be partially bent. The shape of the wiring path 100 can be a known shape (wiring pattern) of a wiring path used in a semiconductor integrated circuit device. The wiring path 100 may also include a curved portion.

[0067] 1A to 1C, wiring structure 1 includes wiring layer 10, metal layer 20 facing wiring layer 10, and solid electrolyte layer 30 located between wiring layer 10 and metal layer 20. Wiring path 100 is composed of wiring layer 10, metal layer 20, and solid electrolyte layer 30. In the present embodiment, wiring structure 1 is wiring path 100 itself.

[0068] The wiring layer 10 functions as a signal line for mainly transmitting an electric signal in the wiring path 100. The wiring layer 10 is a wiring mainly composed of a metal element. The metal element constituting the wiring layer 10 is at least one selected from the group consisting of cobalt (Co), tungsten (W), copper (Cu), and ruthenium (Ru). In the present embodiment, the wiring layer 10 is made of a metal material containing cobalt.

[0069] Moreover, the wiring layer 10 is elongated and extends in one direction (the X-axis direction in this embodiment). The wiring layer 10 is a part that forms the main shape of the wiring structure 1. Therefore, the wiring layer 10 is linear, for example, but may be partially bent as long as it includes a linear portion extending in one direction.

[0070] The metal layer 20 is made of a material mainly composed of a metal element. Specifically, the metal layer 20 is made of at least one selected from the group consisting of titanium nitride (TiN), lithium cobalt oxide (LiCoO3), lithium manganese oxide (LiMn2O4), lithium chromate (LiCrO2), silver tungstate (Ag2WO4), copper tungstate (CuWO4), and lithium tungstate (Li2WO4). In this embodiment, the metal layer 20 is made of titanium nitride (TiN). The metal layer 20 is not limited to these materials, and may be made of a material mainly composed of any of platinum, gold, iridium, tungsten, ruthenium, palladium, and rhodium.

[0071] The shape of the metal layer 20 is not particularly limited as long as the metal layer 20 faces the wiring layer 10. In the present embodiment, the metal layer 20 extends in one direction (the X-axis direction in the present embodiment) similarly to the wiring layer 10.

[0072] Moreover, the metal layer 20 is formed so as to encase the wiring layer 10 and the solid electrolyte layer 30 in a cross-sectional view when cut at least along a plane perpendicular to one direction in which the wiring layer 10 extends (this is a YZ cross-section in this embodiment, and hereinafter this plane will be referred to as a YZ cross-section). Specifically, the metal layer 20 is formed so as to cover the entire wiring layer 10 and the solid electrolyte layer 30 in a cross-sectional view when cut along the YZ cross-section. Note that, although the metal layer 20 constitutes the outermost periphery of the wiring path 100 in this embodiment, this is not limited thereto.

[0073] The solid electrolyte layer 30 is made of at least one material selected from the group consisting of lithium nitrile phosphate (LiPON) and magnesium nitrile phosphate (MgPON). In this embodiment, the solid electrolyte layer 30 is made of a material containing lithium nitrile phosphate (LiPON). Specifically, the solid electrolyte layer 30 is made of only lithium nitrile phosphate (LiPON). Lithium nitrile phosphate (LiPON) has an amorphous structure rather than a crystalline structure.

[0074] Furthermore, the material of the solid electrolyte layer 30 is not limited to these. For example, the solid electrolyte layer 30 may be made of a material including at least one material selected from the group consisting of polyethylene glycol, polyethylene oxide, polyvinylpyrrolidone, polyacrylonitrile, polyvinylidene fluoride, and polymethyl methacrylate.

[0075] Alternatively, the solid electrolyte layer 30 may be composed of a polymer electrolyte made of a polymer containing a metal salt. In this case, the metal salt is a silver electrolyte salt, a copper electrolyte salt, a nickel electrolyte salt, a magnesium electrolyte salt, an iron electrolyte salt, a cobalt electrolyte salt, or a manganese electrolyte salt, and the polymer is composed of polyethylene glycol, polyethylene oxide, polyvinylpyrrolidone, polyacrylonitrile, polyvinylidene fluoride, or polymethyl methacrylate.

[0076] The solid electrolyte layer 30 may be formed of silver iodide (AgI), copper iodide (CuI), lithium iodide (LiI), silver bromide (AgBr), copper bromide (CuBr), lithium bromide (LiBr), or rubidium silver iodide (RbAg4I5).

[0077] The solid electrolyte layer 30 may also be formed of germanium sulfide (GeS), silver sulfide (AgS), copper sulfide (CuS), germanium selenide (GeSe), silver selenide (AgSe), copper selenide (CuSe), germanium telluride (GeTe), antimony telluride (SbTe), or antimony germanium telluride (GeSbTe).

[0078] Alternatively, the solid electrolyte layer 30 may be formed from a crystal. In this case, the crystal may be a silicon oxide (SiO2) crystal, an aluminum oxide (Al2O3) crystal, an yttrium oxide (Y2O3) crystal, a lanthanum oxide (La2O3), a tantalum oxide (Ta2O5) crystal, a tungsten oxide (WO3) crystal, a hafnium oxide (HfO2) crystal, a titanium oxide (TiO2) crystal, a vanadium oxide (VO5) crystal, a zirconium oxide (ZrO2) crystal, or a strontium titanate (SrTiO3) crystal.

[0079] When a voltage is applied to the solid electrolyte layer 30, ions of the material contained in the solid electrolyte layer 30 move inside the solid electrolyte layer 30. Specifically, when the solid electrolyte layer 30 is of a cation conductive type, the ions that move inside the solid electrolyte layer 30 when a voltage is applied to the solid electrolyte layer 30 are cations, and are, for example, at least one selected from the group consisting of proton ions, silver ions, copper ions, lithium ions, nickel ions, magnesium ions, iron ions, cobalt ions, and manganese ions. An example of a cation conductive material is LiPON (Li + Conduction), MgPON(Mg 2+ Conduction), AgI (Ag + Conduction), or CuI (Cu +On the other hand, when the solid electrolyte layer 30 is an anion conductive type, the ions that move inside the solid electrolyte layer 30 when a voltage is applied to the solid electrolyte layer 30 are anions, such as oxygen ions. An example of an anion conductive material is ZrO2 (O 2- Conductive) and Y2O3(O 2- conduction).

[0080] The solid electrolyte layer 30 is formed so as to surround the wiring layer 10 in at least a cross-sectional view when cut along the YZ cross section. In the present embodiment, the solid electrolyte layer 30 is formed so as to cover the entire wiring layer 10 in a cross-sectional view when cut along the YZ cross section.

[0081] Moreover, the solid electrolyte layer 30 extends in one direction (the X-axis direction in this embodiment) similar to the wiring layer 10 and the metal layer 20. That is, the wiring layer 10, the metal layer 20, and the solid electrolyte layer 30 extend in the same direction.

[0082] In the present embodiment, the solid electrolyte layer 30 is in contact with the wiring layer 10. Specifically, a side surface of the solid electrolyte layer 30 and a side surface of the wiring layer 10 are in surface contact. Furthermore, the solid electrolyte layer 30 is in contact with the metal layer 20. Specifically, a side surface of the solid electrolyte layer 30 and a side surface of the metal layer 20 are in surface contact.

[0083] Thus, in the wiring structure 1, the solid electrolyte layer 30 is provided between the wiring layer 10 and the metal layer 20, and the wiring layer 10 and the metal layer 20 are electrically insulated via the solid electrolyte layer 30. In addition, in the present embodiment, in a cross-sectional view taken along the YZ cross section, the entire outer periphery of the wiring layer 10 is covered with the solid electrolyte layer 30. In addition, the entire outer periphery of the solid electrolyte layer 30 is covered with the metal layer 20. In other words, the wiring structure 1 has a triple structure with the wiring layer 10 as a core wire.

[0084] Note that the wiring structure 1 (wiring path 100) shown in FIGS. 1A to 1C is in the shape of a long cylinder. Also, the wiring layer 10 is in the shape of a long cylinder. Therefore, in a cross-sectional view when cut along the YZ plane, the wiring structure 1 and the wiring layer 10 are circular or elliptical. Specifically, the shapes of the wiring structure 1 and the wiring layer 10 in the YZ cross-section are circular. Therefore, the side surface of the wiring layer 10 is a curved surface. In this case, the solid electrolyte layer 30 covering the wiring layer 10 is in a thin cylindrical shape, and the metal layer 20 covering the solid electrolyte layer 30 is also in a thin cylindrical shape.

[0085] The wiring structure 1 configured as described above is used with a voltage applied to the solid electrolyte layer 30. Specifically, by applying a voltage to the wiring layer 10 and the metal layer 20 to set the wiring layer 10 and the metal layer 20 at a predetermined potential, a predetermined voltage can be applied to the solid electrolyte layer 30. That is, the wiring layer 10 functions as a first electrode layer, and the metal layer 20 functions as a second electrode layer. For example, as shown in FIG. 1A, a first voltage V1 is applied to the wiring layer 10, and a second voltage V2 different from the first voltage V1 is applied to the metal layer 20.

[0086] Note that the metal layer 20 covering the wiring layer 10 and the solid electrolyte layer 30 also functions as a barrier film that prevents the materials contained in the wiring layer 10 and the solid electrolyte layer 30 from coming out of the wiring path 100.

[0087] Here, the state inside the solid electrolyte layer 30 when a voltage is applied to the solid electrolyte layer 30 will be described with reference to FIGS. 2A and 2B.

[0088] FIG. 2A shows the state inside the solid electrolyte layer 30p when the first voltage V1 applied to the wiring layer 10 of the wiring structure 1 is lower than the second voltage V2 applied to the metal layer 20 (V1 < V2) when a cation-conductive (p-type) solid electrolyte layer 30p is used as the solid electrolyte layer 30.

[0089] In this case, inside the solid electrolyte layer 30p, positively charged cations (here, lithium ions (Li +)(())) moves to the side of the wiring layer 10 with a lower potential. As a result, the electron concentration of the wiring layer 10 increases, and the resistance value of the wiring layer 10 decreases. That is, the resistance value of the wiring structure 1 decreases. Incidentally, when cations (lithium ions) move in the solid electrolyte layer 30p, cations are depleted and negative charges are generated, but they accumulate in the region near the metal layer 20.

[0090] On the other hand, FIG. 2B shows the state inside the solid electrolyte layer 30n when the first voltage V1 applied to the wiring layer 10 of the wiring structure 1 is lower than the second voltage V2 applied to the metal layer 20 (V1 <V2) when an anion-conducting (n-type) solid electrolyte layer 30n is used as the solid electrolyte layer 30.

[0091] In this case, inside the solid electrolyte layer 30n, negatively charged anions such as oxygen ions (O 2- )) move to the side of the metal layer 20 in the direction of higher potential. As a result, positive charges generated by the depletion of anions accumulate in the region of the solid electrolyte layer 30 near the wiring layer 10. As a result, the electron concentration of the wiring layer 10 increases, and the resistance value of the wiring layer 10 decreases. That is, the resistance value of the wiring structure 1 decreases.

[0092] Whether the solid electrolyte layer 30 is anion-conducting or cation-conducting can be determined by the material contained in the solid electrolyte layer 30. Also, the voltage (potential difference) applied to the solid electrolyte layer 30 is, for example, 3V, but it is not limited to this.

[0093] Next, the wiring structure 1A according to the second aspect of Embodiment 1 will be described with reference to FIG. 3. FIG. 3 is a diagram showing the configuration of the wiring structure 1A according to the second aspect of Embodiment 1 and the configuration of the semiconductor device 2 in which this wiring structure 1A is used.

[0094] As shown in FIG. 3, the wiring structure 1A further includes an insulating layer 40 in addition to the wiring layer 10, the metal layer 20, and the solid electrolyte layer 30. The wiring layer 10, the metal layer 20, and the solid electrolyte layer 30 constitute a wiring path 100A in the same manner as in FIGS. 1A to 1C.

[0095] A recess 40a is formed in the insulating layer 40. The recess 40a is a groove extending in the same direction as the wiring path 100A. The wiring path 100A is embedded in the recess 40a. Therefore, the insulating layer 40 covers the outer periphery of the metal layer 20 of the wiring path 100A. That is, the metal layer 20 is formed on the insulating layer 40. In FIG. 3, the metal layer 20 is formed along the inner surface of the recess 40a. The insulating layer 40 is an insulating film made of an insulating material such as silicon dioxide or silicon carbide (SiOC). The insulating layer 40 is formed on a substrate 50.

[0096] 1A to 1C is cylindrical in shape, the wiring path 100A shown in Fig. 3 is rectangular in shape. Specifically, in a cross-sectional view of the wiring path 100A cut along the YZ cross section, the wiring layer 10 is rectangular and has a pair of opposing side surfaces 10a and a bottom surface 10b. The metal layer 20 and the solid electrolyte layer 30 each face the pair of side surfaces 10a and the bottom surface 10b of the wiring layer 10.

[0097] 1A, in the wiring path 100A shown in Fig. 3, the solid electrolyte layer 30 is formed to surround the wiring layer 10. In addition, the metal layer 20 is formed to surround the wiring layer 10 and the solid electrolyte layer 30.

[0098] However, in the wiring path 100A shown in FIG. 3, the solid electrolyte layer 30 does not cover the entire outer periphery of the wiring layer 10, and the metal layer 20 does not cover the entire outer periphery of the wiring layer 10 and the solid electrolyte layer 30. Specifically, the metal layer 20 and the solid electrolyte layer 30 cover each of a pair of side surfaces 10a and a bottom surface 10b of the wiring layer 10, but do not cover the upper surface of the wiring layer 10. In this embodiment, the metal layer 20 and the solid electrolyte layer 30 in the wiring path 100A have a U-shaped cross section and have a pair of sidewall portions and a bottom surface portion. The solid electrolyte layer 30 contacts each of the pair of side surfaces 10a and the bottom surface 10b of the metal layer 20.

[0099] As shown in FIG. 3, semiconductor device 2 includes substrate 50 and wiring structure 1A formed on substrate 50. As shown in FIG.

[0100] The substrate 50 may be a semiconductor substrate such as a silicon substrate or a GaN substrate, or an insulating substrate made of an insulating material such as a glass substrate or a resin substrate. The substrate 50 may be a rigid substrate that does not have flexibility, or a flexible substrate that has flexibility.

[0101] The number of wiring paths 100A included in wiring structure 1A formed on substrate 50 is not limited to one. Specifically, as in semiconductor device 3 shown in Fig. 4, wiring structure 1A on substrate 50 may include multiple wiring paths 100A. In this case, multiple recesses 40a are formed in insulating layer 40, and wiring paths 100A are embedded in each recess 40a.

[0102] 5, the semiconductor device 4 may further include a substrate 50, a wiring structure 1A formed on the substrate 50, and a transistor 60 formed on the substrate 50. A wiring path 100A of the wiring structure 1A is electrically connected to the source / drain of the transistor 60. The transistor 60 is an example of an active element, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

[0103] In addition, in semiconductor device 4, other circuit elements such as active elements such as diodes and passive elements such as capacitors and resistors may be formed in addition to transistor 60. Wiring path 100A of wiring structure 1A functions as wiring for electrically connecting these circuit elements to each other.

[0104] By using the semiconductor device 4 configured in this manner, it is possible to realize a method for operating an active element for operating the transistor 60, which is an active element. In this case, with a voltage applied to the solid electrolyte layer 30 of the wiring structure 1A, an electric signal is transmitted from the transistor 60 to the wiring layer 10, or an electric signal is transmitted from the wiring layer 10 to the transistor 60. That is, in the wiring structure 1A, it is sufficient that a voltage is applied to the solid electrolyte layer 30 so that an electric signal is transmitted from the transistor 60 to the wiring layer 10. Alternatively, it is sufficient that a voltage is applied to the solid electrolyte layer 30 so that an electric signal is transmitted from the wiring layer 10 to the transistor 60.

[0105] 2A, when a cation-conducting solid electrolyte layer is used as the solid electrolyte layer 30, a first voltage V1 is applied to the wiring layer 10, and a second voltage V2 higher than the first voltage V1 is applied to the metal layer 20. This causes cations to move in the solid electrolyte layer 30 to the vicinity of the wiring layer 10, and the electron concentration of the wiring layer 10 increases, thereby decreasing the resistance value of the wiring layer 10.

[0106] 2B, when an anion conductive solid electrolyte layer is used as the solid electrolyte layer 30, a first voltage V1 is applied to the wiring layer 10, and a second voltage V2 higher than the first voltage V1 is applied to the metal layer 20. This causes anions to move within the solid electrolyte layer 30, increasing the electron concentration in the vicinity of the solid electrolyte layer side of the wiring layer 10, thereby making it possible to reduce the resistance value of the wiring layer 10.

[0107] Such a configuration of semiconductor device 4 makes it possible to reduce the resistance of wiring path 100A (wiring layer 10) of wiring structure 1A, and to transmit electrical signals without delay via wiring path 100A with reduced resistance.

[0108] Furthermore, such a method of using wiring structure 1A and semiconductor device 4 makes it possible to transmit an electrical signal to wiring layer 10 of wiring structure 1A. That is, by using wiring structure 1A and semiconductor device 4 with a voltage applied to solid electrolyte layer 30, an electrical signal is transmitted to wiring layer 10 of wiring structure 1A.

[0109] Here, a specific example of a semiconductor device including a transistor 60 will be described with reference to Fig. 6. Fig. 6 shows a specific cross-sectional view of a semiconductor device 5 including a transistor 60. The semiconductor device 5 shown in Fig. 6 has a multi-layer wiring structure. Examples of the semiconductor device 5 having such a structure include a semiconductor integrated circuit device of a solid-state imaging device or a TFT substrate of a display device.

[0110] As shown in FIG. 6, semiconductor device 5 comprises a substrate 50, a first interlayer insulating layer 41 formed on substrate 50, a second interlayer insulating layer 42 formed on first interlayer insulating layer 41, and a third interlayer insulating layer 43 formed on second interlayer insulating layer 42.

[0111] The semiconductor device 5 also includes a first wiring 100a embedded in a first interlayer insulating layer 41, a second wiring 100b embedded in a second interlayer insulating layer 42, and a third wiring 100c embedded in a third interlayer insulating layer 43.

[0112] The semiconductor device 5 includes a first transistor 61 and a second transistor 62 as the transistor 60. Furthermore, the semiconductor device 5 includes a contact plug 100p that connects the first transistor 61 and the first wiring 100a.

[0113] 6, the substrate 50 is a semiconductor substrate. In the substrate 50, an impurity diffusion region constituting a drain region 60d of the first transistor 61 and the second transistor 62, and an impurity region constituting a source region 60s of the first transistor 61 and the second transistor 62 are formed. In addition, in the first interlayer insulating layer 41, a gate electrode 60g of the first transistor 61 and the second transistor 62 is formed.

[0114] The contact plug 100p is embedded in the first interlayer insulating layer 41, and connects the drain region 60d of the first transistor 61 and the first wiring 100a.

[0115] 3 to 5 is used in semiconductor device 5. In this case, wiring path 100A of wiring structure 1A is used for at least one of first wiring 100a, second wiring 100b, third wiring 100c, and contact plug 100p.

[0116] When the wiring path 100A is applied to the first wiring 100a, the second wiring 100b, or the third wiring 100c, one direction in which the wiring path 100A and the wiring layer 10 extend (the X-axis direction in this embodiment) is perpendicular to the paper. When the wiring path 100A is applied to the contact plug 100p, one direction in which the wiring path 100A and the wiring layer 10 extend is the up-down direction of the paper.

[0117] Next, another aspect of the wiring structure according to the first embodiment will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view showing the configuration of wiring structure 1B according to a third aspect of the first embodiment and the configuration of semiconductor device 6 in which wiring structure 1B is used.

[0118] A semiconductor device 6 shown in FIG. 7 includes a substrate 50 and a wiring structure 1B formed on the substrate 50. The wiring structure 1B includes a substrate 50 and a wiring structure 1B formed on the substrate 50.

[0119] Wiring structure 1B includes three wiring paths, ie, first wiring path 101, second wiring path 102, and third wiring path 103, and two insulating layers, ie, first interlayer insulating layer 41 and second interlayer insulating layer .

[0120] The first wiring path 101, the second wiring path 102 and the third wiring path 103 are each composed of a wiring layer 10B, a metal layer 20B and a solid electrolyte layer 30B, similar to the wiring path 100 of the wiring structure 1 and the wiring path 100A of the wiring structure 1A described above.

[0121] In the present embodiment, the wiring layer 10B is composed of a first wiring layer 11 and a second wiring layer 12. The metal layer 20B is composed of a first metal layer 21 and a second metal layer 22, and the solid electrolyte layer 30B is composed of a first solid electrolyte layer 31 and a second solid electrolyte layer 32.

[0122] The first wiring layer 11 is a lower wiring layer embedded in the recess 41a. Specifically, the first wiring layer 11 is embedded in a groove-shaped first solid electrolyte layer 31 formed in the recess 41a. The second wiring layer 12 is an upper wiring layer located on the first wiring layer 11, and is formed on the surface of the first solid electrolyte layer 31 located other than in the recess 41a.

[0123] The first metal layer 21 is a lower metal layer formed along the inner surface of the recess 41a. The first metal layer 21 is formed along a pair of side surfaces and a bottom surface of the recess 41a. The second metal layer 22 is an upper metal layer located on the first metal layer 21 and is an upper metal layer covering the second solid electrolyte layer 32.

[0124] The first solid electrolyte layer 31 is a lower solid electrolyte layer located between the first metal layer 21 and the wiring layer 10B. The second solid electrolyte layer 32 is an upper solid electrolyte layer located on the first solid electrolyte layer 31, and is located between the wiring layer 10B and the second metal layer 22.

[0125] In the wiring structure 1B, the first wiring path 101 and the second wiring path 102 have a wiring layer 10B consisting of a first wiring layer 11 and a second wiring layer 12, a metal layer 20B consisting of a first metal layer 21 and a second metal layer 22, and a solid electrolyte layer 30B consisting of a first solid electrolyte layer 31 and a second solid electrolyte layer 32.

[0126] On the other hand, the third wiring path 103 has a wiring layer 10B consisting only of the first wiring layer 11, a metal layer 20B consisting of the first metal layer 21 and the second metal layer 22, and a solid electrolyte layer 30B consisting of the first solid electrolyte layer 31 and the second solid electrolyte layer 32. In other words, unlike the first wiring path 101 and the second wiring path 102, the third wiring path 103 does not have a second wiring layer 12.

[0127] In addition, the second wiring path 102 and the third wiring path 103 share the first metal layer 21 and the second metal layer 22 in common, and also share the first solid electrolyte layer 31 and the second solid electrolyte layer 32 in common.

[0128] The first interlayer insulating layer 41 is formed on the substrate 50. The first interlayer insulating layer 41 is the bottom insulating layer. A plurality of recesses 41a are formed in the first interlayer insulating layer 41. Parts of the first wiring path 101, the second wiring path 102, and the third wiring path 103 are embedded in the recesses 41a.

[0129] The second interlayer insulating layer 42 is formed above the first interlayer insulating layer 41 so as to cover the first wiring path 101, the second wiring path 102, and the third wiring path 103. In other words, the first wiring path 101, the second wiring path 102, and the third wiring path 103 are embedded between the first interlayer insulating layer 41 and the second interlayer insulating layer 42.

[0130] Other than these, the configuration of the wiring structure 1B shown in FIG. 7 is basically the same as that of the wiring path 100A of the wiring structure 1A described above. The materials of the first wiring layer 11 and the second wiring layer 12 can be the same as that of the wiring layer 10 of the wiring path 100A described above. Similarly, the materials of the first metal layer 21 and the second metal layer 22 and the materials of the first solid electrolyte layer 31 and the second solid electrolyte layer 32 can be the same as that of the metal layer 20 and the solid electrolyte layer 30 in the wiring path 100A described above. Also, the materials of the first interlayer insulating layer 41 and the second interlayer insulating layer 42 can be the same as that of the insulating layer 40 in the wiring path 100A described above.

[0131] [Effect of wiring structure] Next, the effects of the wiring structure according to the present embodiment will be described in comparison with a wiring structure of a comparative example.

[0132] Assuming that the wiring structure according to the present embodiment is used for contact plug 100p of semiconductor device 5 in Fig. 6, wiring structure 7 shown in Fig. 8A and Fig. 8B was used. Fig. 8A is a cross-sectional view of wiring structure 7 according to the embodiment, and Fig. 8B is a cross-sectional view taken along line 8B-8B in Fig. 8A. In Fig. 8A, one direction in which wiring path 100 and wiring layer 10 extend (the X-axis direction in this embodiment) is taken as the up-down direction on the paper.

[0133] 8A and 8B includes a wiring layer 10, a metal layer 20, and a solid electrolyte layer 30. A wiring path 100 constituted by the wiring layer 10, the metal layer 20, and the solid electrolyte layer 30 is cylindrical.

[0134] As shown in FIGS. 8A and 8B, in the cross-sectional view of the wiring structure 7 according to the embodiment when cut along the YZ cross section, the height (wiring length) of the wiring structure 7 is L, and the radius of the wiring layer 10 is r M The thickness of the solid electrolyte layer 30 is r SE The wiring layer 10 and the solid electrolyte layer 30 are The radius of the semiconductor wiring portion SCL is defined as r. The thickness r of the semiconductor wiring portion SCL is the radius r of the wiring layer 10. M and the thickness r of the solid electrolyte layer 30 SE Since it is the sum of r and r, r = r M +r SE It becomes.

[0135] On the other hand, the wiring structure according to the comparative example was wiring structure 7X shown in Figures 9A and 9B. Figure 9A is a cross-sectional view of wiring structure 7X according to the comparative example, and Figure 9B is a cross-sectional view taken along line 9B-9B in Figure 9A.

[0136] 9A and 9B includes a wiring layer 10X and a metal layer 20X. That is, the wiring structure 7X of the comparative example does not include a solid electrolyte layer 30. Furthermore, a wiring path 100X formed of the wiring layer 10X and the metal layer 20X has a cylindrical shape.

[0137] As shown in FIGS. 9A and 9B, in a cross-sectional view of a wiring structure 7X according to a comparative example, the height (wiring length) of the wiring structure 7X is L, and the radius of the wiring layer 10X is r M (=r).

[0138] In the wiring structure 7 according to the embodiment and the wiring structure 7X according to the comparative example, the materials of the wiring layer 10 and the wiring layer 10X are the same, both of which are cobalt (Co). The materials of the metal layer 20 and the metal layer 20X are also the same, both of which are titanium nitride (TiN). The material of the solid electrolyte layer 30 in the wiring structure 7 according to the embodiment is lithium phosphate-oxygen (LiPON). The overall shapes of the wiring path 100 of the wiring structure 7 according to the embodiment and the wiring path 100X of the wiring structure 7X according to the comparative example are the same, and the portion not having the solid electrolyte layer 30 in the wiring structure 1 according to the comparative example is the wiring layer 10X.

[0139] First, the resistance reducing effect of wiring structure 7X according to the embodiment will be estimated based on the following document 1. In document 1, gold (Au) is used for the electrode portion.

[0140] [Reference 1] D. Daghero et al., “Large Conductance Modulation of Gold Thin Films by Huge Charge Injection via Electrochemical Gating”, PHYSICAL REVIEW LETTERS, PRL 108, 066807 (2012).

[0141] In the sample used in the experiment in Reference 1, the electrode part made of Au covered with the solid electrolyte layer has a surface area S of S = 1.2 × 10 -4 (cm 2 ) and the film thickness d is d = 41 × 10 -7 (cm). The resistivity ρ of gold is ρ = 2.2 × 10 -6 (Ωcm). The carrier density of gold is 1.85×10 15 (e / cm 2 ).

[0142] In this case, from Fig. 4 of Reference 1, ΔR / R(300k) = 0.2 / 4.4, so the two-dimensional carrier density n Au2D (t=41nm) is nAu2D (t=41nm)=1.85×10 15 / (0.2 / 4.4)=4.07×10 16 (e / cm 2 )

[0143] Therefore, the three-dimensional carrier density in gold, n Au3D Considering the thickness of 41 nm, n Au3D =(4.07×10 16 ) / (41×10 -7 )=1×10 22 (e / cm 3 )

[0144] From the calculation results, the effect of cobalt (Co) constituting the wiring layer 10 is estimated. Specifically, the resistance value per unit length of the wiring layer 10 whose side surfaces are covered with the solid electrolyte layer 30 is calculated. In addition, the solid electrolyte layer 30 covering the side surfaces of the wiring layer 10 is covered with a metal layer 20 made of titanium nitride (TiN).

[0145] As described above, the thickness r of the semiconductor wiring portion SCL composed of the wiring layer 10 and the solid electrolyte layer 30 is expressed as follows: M +r SE It is.

[0146] Here, the radius r of the wiring layer 10 M The ratio x of the radius r of the semiconductor wiring part SCL to x = r / r M Then, the resistance value R of the semiconductor wiring portion SCL can be expressed by the following formula (1).

[0147] R = (1 / R Co +1 / R SE ) -1 ...Equation (1)

[0148] In addition, in (Equation 1), R Co represents the resistance value of the wiring layer 10 made of cobalt (Co), and R SErepresents the resistance value at the interface between the wiring layer 10 made of cobalt (Co) and lithium phosphate-oxynitride (LiPON) that changes when a voltage is applied to the lithium phosphate-oxynitride (LiPON).

[0149] When the voltage Vg applied to the solid electrolyte layer 30 is set to Vg=0 V, the resistance value R(V0) of the semiconductor wiring portion SCL can be expressed by the following (Equation 2).

[0150] R(V0)=1 / (e×μ)×(nCo3D×π×(1 / 4)×(2×r / x)2)-1...(Formula 2)

[0151] Furthermore, when the voltage Vg applied to the solid electrolyte layer 30 is set to Vg≠0 V, the resistance value R(Vg) of the semiconductor wiring portion SCL can be expressed by the following (Equation 3).

[0152] R(Vg) = 1 / (e × μ) × (n Co3D ×π×(1 / 4)×(2×r / x) 2 +n Au1D ) -1 ...(Formula 3)

[0153] In (Equation 2) and (Equation 3), μ represents the carrier mobility, n Co3D represents the carrier volume density of cobalt. Au1D represents the one-dimensional carrier density of Au.

[0154] Here, when the voltage Vg applied to the solid electrolyte layer 30 is Vg=5V, the length L of the semiconductor wiring portion SCL is L=1×10 -4 cm, the resistivity ρ of cobalt is ρ = 5.81 × 10 -6 Since the carrier volume density of cobalt is Ωcm, n Co3D Calculating, n Co3D =(2.2 / 5.8)×1×10 22 (e / cm 3 )=3.8×10 21 (e / cm 3 )

[0155] Therefore, in (Equation 1) and (Equation 2), "1 / (μ×e×n Co3D ) is 1 / (μ×e×n Co3D )=283(cm 2 / (V×sec)).

[0156] The carrier density injected by the solid electrolyte layer 30 is the carrier density n Au1D is the same as n Au1D =n Au2D ×2×π×r M It becomes.

[0157] From the above, the radius r M r M = r / 4, and the remaining 3 / 4 × r is the thickness r of the solid electrolyte layer 30. SE When a voltage of Vg=5V was applied to the solid electrolyte layer 30, all the parameters were substituted into (Equation 3) to obtain R(Vg). Then, this R(Vg) was taken as the resistance value R of the wiring structure 7 according to the example shown in FIGS. 8A and 8B, and its dependency on the line width 2×r is shown in FIG.

[0158] On the other hand, in the case of a wiring structure in which the wiring layer is not covered with a solid electrolyte layer, in FIG. 8A and FIG. 8B, the radius r M =r, and R(V0) was calculated by substituting related parameters into (Equation 2) for the case where no voltage is applied to solid electrolyte layer 30. This R(V0) is taken as the resistance value of wiring structure 7X of the comparative example shown in Figures 9A and 9B, and its dependency on line width 2 × r is shown in Figure 10.

[0159] 10, the resistance value increases as the line width decreases in both the wiring structure 7 according to the embodiment and the wiring structure 7X according to the comparative example, but it can be seen that the wiring structure 7 according to the embodiment is able to suppress the increase in the resistance value of the wiring layer associated with thinning, compared to the wiring structure 7X according to the comparative example. In other words, for the same line width, the wiring structure 7 according to the embodiment can obtain a resistance reducing effect that can reduce the resistance value of the wiring layer 10, compared to the wiring structure 7X according to the comparative example.

[0160] Furthermore, when compared at the same line width, the percentage by which the resistance value of wiring structure 7 according to the embodiment can be reduced (resistance reduction rate) relative to wiring structure 7X of the comparative example was as shown in Table 1 below.

[0161] [Table 1]

[0162] As shown in Table 1, it can be seen that the resistance reduction rate of the wiring structure 7 according to the embodiment increases as the line width decreases. In other words, according to the wiring structure 7 according to the embodiment, the smaller the line width, the greater the resistance reduction effect can be obtained.

[0163] In the wiring structure 7 according to the embodiment, the radius r M and the thickness r of the solid electrolyte layer 30 SE The ratio of M :r SE When r=1:3, the effect of reducing resistance in the wiring structure 7 according to the embodiment can be obtained with r=57.2 nm or less, that is, with a line width (2×r) of 114.4 nm or less. In other words, the ratio of the thickness of the solid electrolyte layer 30 to the thickness of the wiring layer 10 is desirably greater than 1 / 4.

[0164] Moreover, the resistance reducing effect in the wiring structure 7 according to the embodiment is greater as the valence of the conductive ions moving in the solid electrolyte layer 30 is greater. For example, when magnesium nitrile phosphate (MgPON) is used as the material of the solid electrolyte layer 30, the conductive ions moving in the solid electrolyte layer 30 are Mg ions, which are divalent cations. On the other hand, when lithium nitrile phosphate (LiPON) is used as the material of the solid electrolyte layer 30, the conductive ions moving in the solid electrolyte layer 30 are Li ions, which are monovalent cations. Therefore, the use of magnesium nitrile phosphate (MgPON) as the material of the solid electrolyte layer 30 can obtain twice the resistance reducing effect as compared to the use of lithium nitrile phosphate (LiPON).

[0165] From the viewpoint of obtaining a low resistance effect, the cross section of the solid-state The sum of the thickness of the electrolyte layer 30 and the thickness of the wiring layer 10 is preferably 20 nm or less, and the width of the wiring layer 10 is preferably 10 nm or less.

[0166] Moreover, in the cross-sectional view when cut in the YZ cross section, the thickness of the solid electrolyte layer 30 is preferably 5 nm or more, because if the thickness is smaller than this, electron leakage is thought to occur.

[0167] The effect of the wiring structure 7 according to the above embodiment can be obtained not only in the cylindrical wiring structure 1 shown in Figs. 1A to 1C, but also in a wiring structure having a solid electrolyte layer 30 disposed between the wiring layer 10 and the metal layer 20 and a semiconductor device including the wiring structure. Specifically, the effect of suppressing an increase in the resistance value of the wiring layer due to thinning can be obtained for all of the semiconductor device 2 shown in Fig. 3, the semiconductor device 3 shown in Fig. 4, the semiconductor device 4 shown in Fig. 5, the semiconductor device 5 shown in Fig. 6, and the semiconductor device 6 shown in Fig. 7. In addition, a resistance reduction effect that can reduce the resistance value of the wiring layer can be obtained as compared with a wiring structure of the same line width that does not have the solid electrolyte layer 30.

[0168] [Method of manufacturing wiring structure and semiconductor device] Next, a method for manufacturing the wiring structure and semiconductor device according to the first embodiment will be described with reference to Figures 11A to 11Y. Figures 11A to 11Y are views for explaining a method for manufacturing semiconductor device 6 shown in Figure 7.

[0169] First, as shown in FIGS. 11A and 11B, a substrate 50 is prepared, and a first interlayer insulating layer 41 is formed on the substrate 50. A semiconductor substrate or an insulating substrate can be used as the substrate 50. In the present embodiment, a semiconductor substrate is used as the substrate 50. Also, as a material for the first interlayer insulating layer 41, for example, silicon dioxide or silicon oxide carbide (SiOC) can be used. The first interlayer insulating layer 41 can be formed by, for example, a chemical vapor deposition (CVD) method.

[0170] Next, as shown in Fig. 11C and Fig. 11D, recesses 41a for forming the wiring paths 100 are formed in the first interlayer insulating layer 41. The recesses 41a are formed to extend in one direction (the X-axis direction in this embodiment). For example, the recesses 41a that become trenches by etching are formed in the first interlayer insulating layer 41. In this embodiment, a plurality of recesses 41a are formed.

[0171] In this embodiment, three wiring paths, a first wiring path 101, a second wiring path 102, and a third wiring path 103, are formed as the wiring path 100. Therefore, in FIG. 11C, three recesses 41a are shown corresponding to these three wiring paths. Specifically, in FIG. 11C, the recess 41a on the right side corresponds to the first wiring path 101, the recess 41a on the left side corresponds to the second wiring path 102, and the recess 41a in the center corresponds to the third wiring path 103. In the following steps, the first wiring path 101, the second wiring path 102, and the third wiring path 103 will be described in this correspondence.

[0172] 11E, a first metal layer 21f is formed along the inner surface of a recess 41a extending in one direction formed in the first interlayer insulating layer 41. Specifically, the first metal layer 21f is formed so as to cover the surface of the first interlayer insulating layer 41 and the inner side and bottom surface of the recess 41a, thereby covering the entire first interlayer insulating layer 41. In this embodiment, a titanium nitride film made of titanium nitride is formed as the first metal layer 21f by a sputtering method.

[0173] Next, as shown in FIG. 11F, a first solid electrolyte layer 31f is formed so as to cover the first metal layer 21f and not fill the recess 41a. Specifically, the first solid electrolyte layer 31f is formed so as to cover the entire surface of the first metal layer 21f. At this time, the first solid electrolyte layer 31f The first solid electrolyte layer 31f is formed so as to cover the surface of the first metal layer 21f that is not formed in the recess 41a and the inner side and bottom surface of the first metal layer 21f that is formed in the recess 41a. The first solid electrolyte layer 31f can be formed by, for example, a sputtering method or an atomic layer deposition (ALD) method.

[0174] In this case, it is better to form the first solid electrolyte layer 31f by the ALD method, not by the sputtering method. By forming the first solid electrolyte layer 31f by the ALD method, even if the base on which the first solid electrolyte layer 31 is formed has an uneven structure, the first solid electrolyte layer 31f can be easily formed as a continuous film of uniform thickness along the uneven surface. That is, not only can the first solid electrolyte layer 31f be formed with a uniform thickness on the surface of the first metal layer 21f that is not formed in the recess 41a, but also the first solid electrolyte layer 31f can be formed with a uniform thickness on the inner side and bottom surface of the recessed first metal layer 21f formed along the inner surface shape of the recess 41a. In this embodiment, lithium phosphate nitride (LiPON) is formed as the first solid electrolyte layer 31f by the ALD method. Details of the formation of lithium phosphate nitride (LiPON) are described in, for example, U.S. Pat. No. 9,809,490.

[0175] Next, as shown in FIG. 11G, the wiring layer 10f is formed so as to be surrounded by the first solid electrolyte layer 31f and to fill the recess 41a. Specifically, the wiring layer 10f is formed so as to fill the trench of the first solid electrolyte layer 31f. At this time, the wiring layer 10f is formed so as to cover the surface of the first solid electrolyte layer 31f that is not formed in the recess 41a and the inner side and bottom surface of the first solid electrolyte layer 31f formed in the recess 41a. In this embodiment, a cobalt film is formed as the wiring layer 10f by a CVD method. Thereafter, the cobalt film is heat-treated.

[0176] Next, as shown in Fig. 11H, in order to pattern the wiring layer 10f, a first resist 71 having a predetermined shape is formed on the wiring layer 10f. For example, the first resist 71 having a predetermined shape can be formed by forming a film of a photosensitive resin material on the entire surface above the substrate 50, exposing it to light, and developing it. Note that in Fig. 11H, the first resist 71 is formed on the first wiring path 101 and the second wiring path 102, but the first resist 71 is not formed on the third wiring path 103.

[0177] Next, as shown in FIG. 11I, the wiring layer 10f is etched using the first resist 71 as a mask, thereby patterning the wiring layer 10f. At this time, the wiring layer 10f is removed until the first solid electrolyte layer 31f directly below the wiring layer 10f is exposed. As a result, the wiring layer 10f is partially removed and separated, and a wiring layer 10B having a predetermined shape can be formed. Specifically, the wiring layer 10f below the first resist 71 remains without being etched, and becomes the wiring layer 10B consisting of the first wiring layer 11 and the second wiring layer 12. In addition, the wiring layer 10f in the portion where the first resist 71 is not formed is etched away from the first solid electrolyte layer 31f, and becomes the wiring layer 10B consisting only of the first wiring layer 11. At this time, the first solid electrolyte layer 31f in the portion where the first resist 71 is not formed is exposed.

[0178] 11J, the first resist 71 is removed, thereby exposing the wiring layer 10B.

[0179] Next, as shown in FIG. 11K, in order to pattern the first solid electrolyte layer 31f, a second resist 72 having a predetermined shape is formed on the first solid electrolyte layer 31f so as to cover the wiring layer 10B. For example, the second resist 72 having a predetermined shape can be formed by forming a film of a photosensitive resin material on the entire surface above the substrate 50, exposing it to light, and developing it. In FIG. 11K, the second resist 72 is formed on the first wiring path 101 and is also formed so as to straddle the second wiring path 102 and the third wiring path 103, and the second resist 72 is not formed between the first wiring path 101 and the third wiring path 103.

[0180] Next, as shown in FIG. 11L, the first solid electrolyte layer 31f is etched using the second resist 72 as a mask, thereby patterning the first solid electrolyte layer 31f. At this time, the first solid electrolyte layer 31f is removed until the first metal layer 21f directly below the first solid electrolyte layer 31f is exposed. As a result, the first solid electrolyte layer 31f is partially removed and separated, and the first solid electrolyte layer 31 having a predetermined shape can be formed. Specifically, the first solid electrolyte layer 31f under the second resist 72 remains without being etched, and becomes the first solid electrolyte layer 31. Also, the first solid electrolyte layer 31f in the portion where the second resist 72 is not formed is removed by etching.

[0181] 11M, the second resist 72 is removed, thereby exposing the wiring layer 10B and the first solid electrolyte layer 31.

[0182] Next, as shown in FIG. 11N, in order to pattern the first metal layer 21f, a third resist 73 having a predetermined shape is formed on the first metal layer 21f so as to cover the wiring layer 10B and the first solid electrolyte layer 31. For example, the third resist 73 having a predetermined shape can be formed by forming a film of a photosensitive resin material on the entire surface above the substrate 50, exposing it to light, and developing it. In FIG. 11N, the third resist 73 is formed on the first wiring path 101 and is also formed so as to straddle the second wiring path 102 and the third wiring path 103, and the third resist 73 is not formed between the first wiring path 101 and the third wiring path 103.

[0183] Next, as shown in FIG. 11O, the first metal layer 21f is etched using the third resist 73 as a mask, thereby patterning the first metal layer 21f. At this time, the first metal layer 21f is removed until the first interlayer insulating layer 41 directly below the first metal layer 21f is exposed. As a result, the first metal layer 21f is partially removed and separated, and the first metal layer 21 having a predetermined shape can be formed. Specifically, the first metal layer 21f below the third resist 73 remains without being etched, and becomes the first metal layer 21. Also, the first metal layer 21f in the portion where the third resist 73 is not formed is removed by etching.

[0184] 11P, the third resist 73 is removed, thereby exposing the wiring layer 10B, the first solid electrolyte layer 31, and the first metal layer 21.

[0185] Next, as shown in FIG. 11Q, the second solid electrolyte layer 32f is formed so as to cover the wiring layer 10B, the first solid electrolyte layer 31, and the first metal layer 21. Specifically, the second solid electrolyte layer 32f is formed on the entire surface above the substrate 50. The second solid electrolyte layer 32f can be formed by, for example, a sputtering method or an atomic layer deposition method. The material of the second solid electrolyte layer 32f is preferably the same as the material of the first solid electrolyte layer 31f. In this embodiment, lithium phosphate nitride (LiPON) is formed as the second solid electrolyte layer 32f by an ALD method.

[0186] Next, as shown in FIG. 11R, in order to pattern the second solid electrolyte layer 32f, a fourth resist 74 having a predetermined shape is formed on the second solid electrolyte layer 32f. For example, a photosensitive resin material is formed on the entire surface of the second solid electrolyte layer 32f, and then exposed and developed to form the fourth resist 74 having a predetermined shape. In FIG. 11R, the fourth resist 74 is formed on the first wiring path 101, but is not formed so as to straddle the second wiring path 102 and the third wiring path 103. In addition, the third resist 73 is not formed on the first metal layer 21 exposed from the first solid electrolyte layer 31 between the first wiring path 101 and the third wiring path 103.

[0187] Next, as shown in FIG. 11S, the second solid electrolyte layer 32f is etched using the fourth resist 74 as a mask, thereby patterning the second solid electrolyte layer 32f. The second solid electrolyte layer 32f is removed until the first metal layer 21 is exposed. As a result, the second solid electrolyte layer 32f is partially removed and separated, and the second solid electrolyte layer 32 having a predetermined shape can be formed. Specifically, the second solid electrolyte layer 32f below the fourth resist 74 remains without being etched, and becomes the second solid electrolyte layer 32. Moreover, the second solid electrolyte layer 32f in the portion where the fourth resist 74 is not formed is removed by etching.

[0188] 11T, the fourth resist 74 is removed, thereby exposing the ends of the second solid electrolyte layer 32 and the first metal layer 21.

[0189] Next, as shown in Fig. 11U, a second metal layer 22f is formed so as to cover the ends of the second solid electrolyte layer 32 and the first metal layer 21. Specifically, the second metal layer 22f is formed on the entire surface above the substrate 50 so as to fill the gaps between the second solid electrolyte layers 32. The material of the second metal layer 22f is preferably the same as the material of the first metal layer 21f. In this embodiment, a titanium nitride film made of titanium nitride is formed as the second metal layer 22f by a sputtering method.

[0190] Next, as shown in FIG. 11V, in order to pattern the second metal layer 22f, a fifth resist 75 having a predetermined shape is formed on the second metal layer 22f. For example, a photosensitive resin material is formed on the entire surface of the second metal layer 22f, and then exposed and developed to form the fifth resist 75 having a predetermined shape. In FIG. 11V, the fifth resist 75 is formed on the first wiring path 101 and is also formed so as to straddle the second wiring path 102 and the third wiring path 103, and the fifth resist 75 is not formed between the first wiring path 101 and the third wiring path 103.

[0191] Next, as shown in FIG. 11W, the second metal layer 22f is etched using the fifth resist 75 as a mask, thereby patterning the second metal layer 22f. At this time, the second metal layer 22f is removed until the second solid electrolyte layer 32 is exposed. As a result, the second metal layer 22f is partially removed and separated, and the second metal layer 22 having a predetermined shape can be formed. Specifically, the second metal layer 22f under the fifth resist 75 remains without being etched, and becomes the second metal layer 22. In addition, the second metal layer 22f in the portion where the fifth resist 75 is not formed is removed by etching. As a result, the metal layer 20B consisting of the first metal layer 21 and the second metal layer 22 is formed.

[0192] 11X, the fifth resist 75 is removed, thereby exposing the second metal layer 22.

[0193] 11Y, a second interlayer insulating layer 42 is formed so as to cover the second metal layer 22. As the material of the second interlayer insulating layer 42, for example, a silicon dioxide or silicon carbide oxide film can be used, similar to the first interlayer insulating layer 41. The second interlayer insulating layer 42 can be formed by, for example, a sputtering method or a CVD method.

[0194] In this manner, it is possible to fabricate a semiconductor device 6 including a wiring structure 1B including the first wiring path 101, the second wiring path 102, and the third wiring path 103. That is, it is possible to fabricate a semiconductor device 6 shown in FIG.

[0195] Semiconductor devices and wiring structures other than the semiconductor device 6 shown in FIG. 7 can also be fabricated in accordance with the manufacturing method shown in FIGS. 11A to 11Y.

[0196] (First Modification of First Embodiment) Next, a semiconductor device 8 according to a first modification of the first embodiment will be described with reference to Fig. 12. Fig. 12 is a cross-sectional view of the semiconductor device 8 according to the first modification of the first embodiment.

[0197] As shown in FIG. 12, semiconductor device 8 of this modified example includes substrate 50, wiring structure 1A (first wiring structure) formed on substrate 50, and second wiring structure 1M formed on wiring structure 1A.

[0198] Wiring structure 1A in this modification has the same configuration as wiring structure 1A shown in Fig. 3. However, insulating layer 40 of wiring structure 1A is formed as first interlayer insulating layer 41. Specifically, first interlayer insulating layer 41 is formed on substrate 50.

[0199] The second wiring structure 1M includes a second interlayer insulating layer formed on a first interlayer insulating layer 41, and a second wiring path 100M formed in the second interlayer insulating layer .

[0200] The material of second interlayer insulating layer 42 may be the same as or different from the material of first interlayer insulating layer 41 (insulating layer 40) of wiring structure 1A. In this modification, second interlayer insulating layer 42 is made of a low dielectric material such as fluorosilicate glass (FSG).

[0201] Second wiring path 100M includes second wiring layer 10M and second metal layer 20M. Second wiring path 100M is a wiring for electrically connecting circuit elements to each other in semiconductor device 8, similar to wiring path 100A (first wiring path) of wiring structure 1A.

[0202] The second wiring layer 10M functions as a signal line for mainly transmitting an electric signal in the second wiring path 100M. In this modification, the second wiring layer 10M is elongated and extends in one direction (the X-axis direction in this embodiment) like the wiring layer 10 (first wiring layer) of the wiring path 100A.

[0203] Moreover, the second wiring layer 10M is a wiring whose main component is a metal element. The material of the second wiring layer 10M may be the same as or different from the material of the wiring layer 10 (first wiring layer) of the wiring path 100A. In this modification, the second wiring layer 10M is made of a material different from the first wiring layer (wiring layer 10). Specifically, the second wiring layer 10M is made of copper (Cu).

[0204] The second metal layer 20M faces the second wiring layer 10M. In this modification, the second metal layer 20M extends in the same direction as the second wiring layer 10M. The second metal layer 20M is formed so as to surround the second wiring layer 10M. Specifically, the second metal layer 20M covers a pair of side surfaces and a bottom surface of the second wiring layer 10M.

[0205] The second metal layer 20M is made of a material mainly composed of a metal element. The material of the second metal layer 20M may be the same as or different from the material of the metal layer 20 (first metal layer) of the wiring path 100A. In this modification, the second metal layer 20M is made of tantalum nitride (TaN). The second metal layer 20M functions as a barrier film that prevents the material (Cu in this modification) contained in the second wiring layer 10M from leaking to the outside of the second wiring path 100M.

[0206] In this modification, second wiring layer 10M of second wiring structure 1M has a larger line width than wiring layer 10 of wiring structure 1A. Therefore, the resistance value of second wiring layer 10M of second wiring structure 1M is smaller than the resistance value of wiring layer 10 of wiring structure 1A. As a result, the wiring resistance of second wiring path 100M of second wiring structure 1M is smaller than the wiring resistance of wiring layer 10 of wiring structure 1. As an example, the line width of second wiring layer 10M of second wiring structure 1M is 20 nm.

[0207] Thus, according to the semiconductor device 8 of this modification, since it has the wiring structure 1A of the above-mentioned embodiment 1, it has the same effects as the above-mentioned embodiment 1. That is, it is possible to suppress an increase in the resistance value of the wiring layer 10 due to thinning. Also, it is possible to reduce the resistance value of the wiring layer 10 compared to a wiring structure of the same line width that does not have the solid electrolyte layer 30.

[0208] Furthermore, semiconductor device 8 in this modification includes second wiring structure 1M having second wiring layer 10M with a line width larger than that of wiring layer 10 of wiring structure 1A. This makes it possible to realize semiconductor device 8 of a hybrid structure including wiring layer 10 having low resistance due to having solid electrolyte layer 30 and second wiring layer 10M having low resistance even without a solid electrolyte layer.

[0209] Next, a method for manufacturing semiconductor device 8 according to this modification will be described with reference to Figures 13A to 13D. Figures 13A to 13D are views for explaining the method for manufacturing semiconductor device 8 according to Modification 1 of the first embodiment.

[0210] As shown in FIG. 13A, first, a first metal layer 21f, a first solid electrolyte layer 31f and a wiring layer 10f are embedded in recess 41a of first interlayer insulating layer 41 formed on substrate 50 by the same steps as those shown in FIGS. 11A to 11G above.

[0211] 13B, for example, by chemical mechanical polishing (CMP), the wiring layer 10f, the first solid electrolyte layer 31f, and the first metal layer 21f are polished to remove the portions above the first interlayer insulating layer 41 until the surface of the first interlayer insulating layer 41 is exposed. This makes it possible to form a wiring structure 1A having a wiring path 100A embedded in the first interlayer insulating layer 41 on the substrate 50. In this modification, a wiring structure 1A having a plurality of wiring paths 100A is formed.

[0212] Next, as shown in Fig. 13C, a second interlayer insulating layer 42 having a recess 42a is formed on the wiring structure 1A. Specifically, first, the second interlayer insulating layer 42 is formed by a CVD method, and the recess 42a for forming the second wiring path 100M is formed in the second interlayer insulating layer 42 by etching. At this time, the width of the recess 42a is made larger than the width of the recess 41a formed in the first interlayer insulating layer 41 of the wiring structure 1A. The width of the recess 42a is, for example, 20 nm.

[0213] Next, as shown in FIG. 13D, a second wiring path 100M is formed embedded in the recess 42a of the second interlayer insulating layer 42. Specifically, first, a second metal layer 20M made of tantalum nitride is formed along the inner surface of the recess 42a by a sputtering method, and then a thin copper film is formed on the second metal layer 20M made of tantalum nitride by a sputtering method, and the second wiring layer 10M is deposited by plating using the thin copper film as a seed layer so that the recess 42a is filled. For example, copper (Cu) can be used as a material for the second wiring layer 10M. The second wiring layer 10M protruding from the recess 42a is removed by polishing using CMP until the second interlayer insulating layer 42 is exposed.

[0214] In the manner described above, a wiring path 100A having a wiring layer 10 made of cobalt and a solid electrolyte layer 30 is embedded in the bottom first interlayer insulating layer 41, and a semiconductor device 8 is fabricated in which a second wiring path 100M having a second wiring layer 10M made of copper is embedded in the second interlayer insulating layer 42, which is the layer above the first interlayer insulating layer 41.

[0215] Furthermore, by repeatedly forming at least one of the first interlayer insulating layer 41 in which the wiring path 100A is embedded and the second interlayer insulating layer 42 in which the second wiring path 100M is embedded, it is possible to form, for example, a semiconductor device 5 having a multilayer wiring structure as shown in Figure 6 above.

[0216] (Modification 2 of the First Embodiment) Next, a semiconductor device 6C according to a second modification of the first embodiment will be described with reference to Fig. 14. Fig. 14 is a cross-sectional view of the semiconductor device 6C according to the second modification of the first embodiment.

[0217] As shown in FIG. 14, a semiconductor device 6C according to this modification differs from the semiconductor device 6 shown in FIG. 7 in the structure between first wiring path 101 and third wiring path 103 in wiring structure 1C.

[0218] 7, the second solid electrolyte layer 32 is formed up to the second metal layer 22 of the metal layer 20B between the first wiring path 101 and the third wiring path 103. In contrast, as shown in FIG. 14, in the semiconductor device 6C according to this modification, the second solid electrolyte layer 32 is not formed up to the second metal layer 22 of the metal layer 20B between the first wiring path 101 and the third wiring path 103, and the second solid electrolyte layer 32 between the first wiring path 101 and the third wiring path 103 is formed only up to the first metal layer 21 of the metal layer 20B. Therefore, the second interlayer insulating layer 42C is embedded in the side of the second metal layer 22 between the first wiring path 101 and the third wiring path 103.

[0219] 7, the semiconductor device 6C according to this modification also includes a wiring structure 1C having a solid electrolyte layer 30B disposed between the wiring layer 10B and the metal layer 20B, and thus has the same effects as the semiconductor device 6 in the above-described first embodiment. That is, it has an effect of suppressing an increase in the resistance value of the wiring layer due to thinning.

[0220] (Third Modification of First Embodiment) Next, a semiconductor device 6D according to a third modification of the first embodiment will be described with reference to Fig. 15. Fig. 15 is a cross-sectional view of the semiconductor device 6D according to the third modification of the first embodiment.

[0221] As shown in FIG. 15, a semiconductor device 6D according to this modification differs from the semiconductor device 6C shown in FIG. 14 in the structure of the metal layer 20D in the first wiring path 101D, the second wiring path 102D, and the third wiring path 103D.

[0222] 14, in a wiring structure 1C of a semiconductor device 6C, metal layers 20B of a first wiring path 101, a second wiring path 102, and a third wiring path 103 cover a solid electrolyte layer 30B. Specifically, second metal layer 22 of metal layer 20B is formed up to above solid electrolyte layer 30B.

[0223] 15, in a wiring structure 1D of a semiconductor device 6D according to this modification, metal layers 20D of a first wiring path 101D, a second wiring path 102D, and a third wiring path 103D do not cover a solid electrolyte layer 30B. Specifically, a second metal layer 22D of the metal layer 20D is not formed above the solid electrolyte layer 30B.

[0224] 14, the semiconductor device 6D according to this modification also has a wiring structure 1D having a solid electrolyte layer 30B disposed between the wiring layer 10B and the metal layer 20D, and thus has the same effect as the semiconductor device 6C according to the modification 2. That is, it has an effect such as being able to suppress an increase in the resistance value of the wiring layer 10B due to thinning.

[0225] (Fourth Modification of the First Embodiment) Next, a semiconductor device 6E according to a fourth modification of the first embodiment will be described with reference to Fig. 16. Fig. 16 is a cross-sectional view of the semiconductor device 6E according to the fourth modification of the first embodiment.

[0226] As shown in FIG. 16, a semiconductor device 6E according to this modification differs from the semiconductor device 6 shown in FIG. 7 in the structures of the metal layer 20E and the solid electrolyte layer 30E in the first wiring path 101D, the second wiring path 102D, and the third wiring path 103D.

[0227] Specifically, as shown in FIG. 7, in the wiring structure 1B in the semiconductor device 6, the first solid electrolyte layer 31 of the solid electrolyte layer 30B is separated by the first wiring path 101 and the third wiring path 103, and the solid electrolyte layer 30B of the third wiring path 103 is covered with the metal layer 20B.

[0228] In contrast, as shown in FIG. 16, in the wiring structure 1E in the semiconductor device 6E according to this modification, the first solid electrolyte layer 31 of the solid electrolyte layer 30E is not separated between the first wiring path 101E and the third wiring path 103E, and the first solid electrolyte layer 31 is common to the first wiring path 101E, the second wiring path 102E, and the third wiring path 103E. Therefore, the first metal layer 21 of the metal layer 20E is formed only up to the surface of the first interlayer insulating layer 41. In addition, in this modification, the metal layer 20E of the third wiring path 103E does not cover the solid electrolyte layer 30E. Specifically, the second metal layer 22 of the metal layer 20E is formed only in the recess of the first interlayer insulating layer 41, and faces the first solid electrolyte layer 31 formed in the recess of the first interlayer insulating layer 41.

[0229] In each of the first wiring path 101E, the second wiring path 102,E, and the third wiring path 103E, the first metal layer 21 and the second metal layer 22 are connected at a portion not shown.

[0230] As described above, the semiconductor device 6E according to this modification also has a wiring structure 1E having a solid electrolyte layer 30E disposed between the wiring layer 10B and the metal layer 20E, similar to the semiconductor device 6 shown in Fig. 7, and therefore has the same effect as the semiconductor device 6 shown in Fig. 7. That is, it has an effect such as being able to suppress an increase in the resistance value of the wiring layer due to thinning.

[0231] (Fifth Modification of the First Embodiment) Next, a semiconductor device 3F according to a fifth modification of the first embodiment will be described with reference to Fig. 17. Fig. 17 is a cross-sectional view of a semiconductor device 3F according to a fifth modification of the first embodiment.

[0232] As shown in FIG. 17, a semiconductor device 3F according to this modification differs from the semiconductor device 3 shown in FIG. 4 in the structures of a metal layer 20F and a solid electrolyte layer 30F in a wiring path 100F.

[0233] Specifically, as shown in FIG. 4, in wiring structure 1A in semiconductor device 3, metal layer 20 and solid electrolyte layer 30 in wiring path 100A cover not only a pair of side surfaces of wiring layer 10 but also the bottom surface.

[0234] In contrast, as shown in FIG. 17, in a wiring structure 1F in a semiconductor device 3F according to this modified example, a metal layer 20F and a solid electrolyte layer 30F in a wiring path 100F cover only a pair of side surfaces of the wiring layer 10, and do not cover a bottom surface of the wiring layer 10.

[0235] As described above, the semiconductor device 3F according to this modification also has a wiring structure 1F having a solid electrolyte layer 30F disposed between the wiring layer 10 and the metal layer 20F, similarly to the semiconductor device 3 shown in Fig. 4, and therefore has the same effect as the semiconductor device 3 shown in Fig. 4. That is, it has an effect such as being able to suppress an increase in the resistance value of the wiring layer 10 due to thinning.

[0236] [experiment] Next, the results of an experiment conducted by the inventors of the present application will be described. Specifically, an experiment was conducted to confirm the effects of the wiring structure according to the first embodiment, and the results of the experiment will be described.

[0237] First, an outline of the experiment will be described with reference to Figures 18A and 18B. Figure 18A is a plan view of wiring structure 1Y used in the experiment, and Figure 18B is a cross-sectional view taken along line 18B-18B in Figure 18A.

[0238] The wiring structure 1Y shown in Figures 18A and 18B comprises a substrate 50Y, an insulating layer 40Y formed on the substrate 50Y, a first electrode layer 10Y (corresponding to a "wiring layer") formed on the insulating layer 40Y, a solid electrolyte layer 30Y formed on the insulating layer 40Y so as to cover the first electrode layer 10Y, and a second electrode layer 20Y (corresponding to a "metal layer") formed on the solid electrolyte layer 30Y.

[0239] Specifically, first, a first electrode layer 10Y made of a cobalt film was formed on a substrate 50Y by evaporating cobalt (Co). A silicon substrate on which a thermally oxidized film made of silicon dioxide (SiO2) having a thickness of 2400 nm was formed was used as the substrate 50Y. The first electrode layer 10Y was formed to have a fine line shape with a width of 5 μm, a length of 9 mm, and a target film thickness of 40 nm.

[0240] Next, a 1 μm-thick film of lithium phosphate nitride (LiPON) was formed using a mask sputtering device to form a solid electrolyte layer 30Y so as to cover the first electrode layer 10Y. For contact purposes, masks were used to prevent the solid electrolyte layer 30Y from being formed on both ends of the first electrode layer 10Y by 2 mm.

[0241] Next, gold was evaporated to a thickness of 100 nm over an 8 mm-long region where the first electrode layer 10Y and the solid electrolyte layer 30Y were laminated, thereby forming a second electrode layer 20Y made of a gold film on the solid electrolyte layer 30Y.

[0242] Although not shown, a silver paste was applied to both ends in the longitudinal direction of the first electrode layer 10Y to form contact portions. The distance between the ends to which the silver paste was applied was set to 8 mm.

[0243] Next, for wiring structure 1Y fabricated in this manner, resistance value R of first electrode layer 10Y was determined when voltage Vg applied to second electrode layer 20Y was changed.

[0244] Specifically, first, for the wiring structure 1Y, 4 V was applied to one end of the first electrode layer 10Y to which the silver paste was applied, and the opposite end was fixed to the ground voltage. Next, Vg=0.8 V was applied to the second electrode layer 20Y, and the current value I SD The voltage Vg applied to the second electrode layer 20Y was then decreased by 0.1 V from 0.8 V, and the current value I was measured for each voltage Vg within the voltage range from 0 V to 0.8 V. SD The measurements were repeated. Then, the voltage Vg and current I SDBased on the measurement results, the resistance value R of the first electrode layer 10Y was calculated. The results are shown in Table 2 below and FIG. 19. The current value I SD The measurement was carried out using a digital source meter (KEITHLEY 2400 series (manufactured by Tektronix)).

[0245] [Table 2]

[0246] As shown in Table 2 and FIG. 19, the actual resistance value R (measured value) of the first electrode layer 10Y when the voltage Vg is not applied is about 1.98×10 4 It turned out to be Ω.

[0247] On the other hand, the resistivity of cobalt constituting the first electrode layer 10Y is set to 5.81×10 -6 When the resistance of the first electrode layer 10Y in a region of 8 mm length in which the first electrode layer 10Y having a width of 5 μm and a target thickness of 40 nm and the solid electrolyte layer 30Y are laminated is calculated as Ωcm, the resistance R (theoretical value) of the first electrode layer 10Y is 2.32×10 3 It becomes Ω.

[0248] Therefore, the resistance value R (actual value) of the first electrode layer 10Y obtained by experiment is 1.75×10 smaller than the resistance value R (theoretical value) of the first electrode layer 10Y calculated by calculation. 4 The difference in resistance value is larger by Ω. Possible reasons for this difference in resistance value include the formation of an oxide film on the surface of first electrode layer 10Y and low crystallinity of first electrode layer 10Y.

[0249] 19, the resistance value of wiring structure 1Y in a state where it is operated by applying voltage Vg of 0.8 V is reduced compared to the resistance value of wiring structure 1Y in a state where it is not operated with voltage Vg set to 0 V. That is, it is found that the resistance value is reduced by applying a voltage to solid electrolyte layer 30Y.

[0250] From the above results, in the wiring structure 1Y according to this experimental example, when cobalt is used as the material of the first electrode layer 10Y corresponding to the wiring layer of the wiring structure according to the first embodiment, it was found that the resistance value of the wiring structure can be reduced by 0.8% (= 100×(19801 - 19641) / 19801). This is presumably because ions moved within the solid electrolyte layer 30Y when a voltage was applied.

[0251] (Application Example Using the Wiring Structure) A method for controlling electrical resistance will be described with reference to FIGS. 20A to 20C using the "wiring structure" described so far.

[0252] FIG. 20A is a diagram showing the change in the potential difference ΔV with respect to time t. The horizontal axis t represents time, and the vertical axis represents the potential difference ΔV.

[0253] FIG. 20B is a diagram showing the change in resistance R with respect to time t. The horizontal axis t is the same as in FIG. 20A and represents time, and the vertical axis represents the resistance R.

[0254] FIG. 20C is a diagram showing the change in current I with respect to time t. The horizontal axis t is the same as in FIG. 20A and represents time, and the vertical axis represents the current I.

[0255] A voltage V1 is applied to the wiring layer 10 of the "wiring structure" shown in FIGS. 1A to 1C, a voltage V2 (V1 < V2) is applied to the metal layer 20, and the potential difference ΔV1 (V2 - V1) is applied to the solid electrolyte layer 30. The timing of applying the voltages V1 and V2 is as shown in FIG. 20A. Up to t1, the potential difference ΔV1 is applied, from t1 to t2, ΔV is zero (no potential difference), and from t2 to t3, the voltage of ΔV1 is applied.

[0256] As a result, as shown in FIG. 20B, since there is a potential difference ΔV1 in the wiring layer 10 up to t1, the resistance is in the RL (low resistance state), and from t1 to t2, ΔV is zero ( By applying a voltage of ΔV1 from t2 to t3, the resistance changes to RL (low resistance state).

[0257] In this manner, the resistance (resistance value) of the wiring layer 10 can be changed by changing the voltage applied to the wiring layer 10 and the metal layer 20 over time. In other words, by changing the voltage applied to the solid electrolyte layer 30, the resistance of the wiring layer 10 can be controlled.

[0258] 20C, the wiring layer 10 has a low resistance until t1, so the current is IH (high current), and from t1 to t2, the resistance becomes RH (high resistance state) and the current becomes IL (low current). Similarly, from t2 to t3, the resistance changes to RL (low resistance state), so the current becomes high current IH.

[0259] In this manner, the value of the current flowing through the wiring layer 10 can be changed by changing the voltage applied to the wiring layer 10 and the metal layer 20 over time. In other words, by changing the voltage applied to the solid electrolyte layer 30, the value of the current flowing through the wiring layer 10 can be controlled.

[0260] (Embodiment 2) Next, a second embodiment will be described. First, a configuration of wiring structure 2001 according to a first aspect of the second embodiment will be described with reference to Figs. 21A to 21C. Fig. 21A is a schematic diagram showing a configuration of wiring structure 2001 according to the first aspect of the second embodiment. Fig. 21B is a cross-sectional view of wiring structure 2001. Fig. 21C is a cross-sectional view of wiring structure 2001 taken along line 21C-21C in Fig. 21B.

[0261] Wiring structure 2001 in this embodiment is used in a semiconductor device such as a semiconductor integrated circuit device, similarly to the above-described embodiment 1. In the semiconductor device, wiring structure 2001 includes wiring path 200 for electrically connecting circuit elements to each other.

[0262] 21A to 21C, the wiring path 200 in the present embodiment is configured such that the wiring path 100 in the above-mentioned first embodiment further includes an insulating layer 80. Other than that, the wiring path 200 has the same configuration as the wiring path 100 in the above-mentioned first embodiment.

[0263] Specifically, wiring structure 2001 includes wiring layer 10, metal layer 20, solid electrolyte layer 30, and insulating layer 80.

[0264] Insulating layer 80 is a first insulating layer in wiring structure 2001, and is located between wiring layer 10 and solid electrolyte layer 30. Thus, in wiring structure 2001, wiring layer 10, insulating layer 80, solid electrolyte layer 30, and metal layer 20 are formed in this order from the inside to the outside, and metal layer 20 is formed so as to enclose not only wiring layer 10 and solid electrolyte layer 30 but also insulating layer 80.

[0265] Specifically, in cross-sectional view when cut along the YZ cross section, the entire outer periphery of the wiring layer 10 is covered by the insulating layer 80, the entire outer periphery of the insulating layer 80 is covered by the solid electrolyte layer 30, and the entire outer periphery of the solid electrolyte layer 30 is covered by the metal layer 20.

[0266] The insulating layer 80 is an insulating film made of an insulating material. For example, an alumina film (Al2O3 film) made of Al2O3 (aluminum oxide), a silicon oxynitride film (SiON film) made of SiON, or a silicon nitride film (Si3N4 film) made of Si3N4 can be used as the insulating layer 80.

[0267] Next, wiring structure 2001A according to a second aspect of embodiment 2 will be described with reference to Fig. 22. Fig. 22 is a diagram showing the configuration of wiring structure 2001A according to the second aspect of embodiment 2 and the configuration of semiconductor device 2002 in which wiring structure 2001A is used.

[0268] 22, wiring structure 2001A includes insulating layer 40 in addition to wiring layer 10, metal layer 20, solid electrolyte layer 30, and insulating layer 80. Wiring layer 10, metal layer 20, solid electrolyte layer 30, and insulating layer 80 form wiring path 200A, similar to wiring path 200 shown in FIGS. 21A to 21C. Also, as shown in FIG. 22, semiconductor device 2002 includes substrate 50 and wiring structure 2001A formed on substrate 50.

[0269] The number of wiring paths 200A included in wiring structure 2001A formed on substrate 50 is not limited to one. Specifically, as in semiconductor device 2003 shown in Fig. 23, wiring structure 2001A on substrate 50 may include multiple wiring paths 200A. In this case, multiple recesses 40a are formed in insulating layer 40, and wiring paths 200A are embedded in each recess 40a.

[0270] The semiconductor device in this embodiment may also include a transistor 60, like the semiconductor device 4 shown in FIG. 5, or may have a multi-layer wiring structure, like the semiconductor device 5 shown in FIG. 6.

[0271] Next, another aspect of the wiring structure according to the second embodiment will be described with reference to Fig. 24. Fig. 24 is a cross-sectional view showing the configuration of wiring structure 2001B according to a third aspect of the second embodiment and the configuration of semiconductor device 2006 in which wiring structure 2001B is used.

[0272] 24 includes a substrate 50 and a wiring structure 2001B formed on the substrate 50. The wiring structure 2001B includes three wiring paths, namely, a first wiring path 201, a second wiring path 202, and a third wiring path 203, and two interlayer insulating layers, namely, a first interlayer insulating layer 41 and a second interlayer insulating layer 42.

[0273] First wiring path 201, second wiring path 202, and third wiring path 203 have a configuration similar to first wiring path 101, second wiring path 102, and third wiring path 103 of wiring structure 1B in the above-mentioned embodiment 1, further including insulating layer 80B.

[0274] In this embodiment, the insulating layer 80B is also located between the wiring layer 10B and the solid electrolyte layer 30B. Specifically, in cross-sectional view taken along the YZ cross section, the entire outer periphery of the wiring layer 10B is covered with the insulating layer 80B.

[0275] The insulating layer 80B is composed of a first insulating layer 81 and a second insulating layer 82. The first insulating layer 81 is a lower insulating film at least partially embedded in the recess 41a, and is located between the first wiring layer 11 and the first solid electrolyte layer 31. The second insulating layer 82 is an upper insulating film located on the first insulating layer 81, and is located between the second wiring layer 12 and the second solid electrolyte layer 32. The first insulating layer 81 and the second insulating layer 82 are insulating films made of an insulating material, such as an alumina film, a silicon oxynitride film, or a silicon nitride film.

[0276] In this manner, wiring structures 2001, 2001A and 2001B according to the present embodiment have a configuration similar to that of wiring structure 1 according to the above-mentioned embodiment 1, and therefore when a voltage is applied to solid electrolyte layers 30, 30B, ions move within solid electrolyte layers 30, 30B, thereby suppressing an increase in the resistance value of wiring layers 10, 10B due to thinning of the wiring layers, thereby achieving a resistance reduction effect.

[0277] Furthermore, since the wiring structures 2001, 2001A, and 2001B in the present embodiment include the insulating layers 80 and 80B, it is possible to suppress electronic leakage from the wiring layers 10 and 10B. In particular, when the wiring layers 10 and 10B have a narrow line width, electronic leakage from the wiring layers 10 and 10B is likely to occur, but by providing the insulating layers 80 and 80B, it is possible to effectively suppress electronic leakage.

[0278] Next, a method for manufacturing the wiring structure and semiconductor device according to the second embodiment will be described with reference to Figures 25A to 25Y. Figures 25A to 25Y are views for explaining a method for manufacturing semiconductor device 2006 shown in Figure 24.

[0279] The steps of FIGS. 25A to 25D can be performed in the same manner as the steps of FIGS. 11A to 11F.

[0280] Specifically, as shown in FIG. 25A, a substrate 50 is prepared, and a first interlayer insulating layer 41 is formed on the substrate 50. Next, as shown in FIG. 25B, a recess 41a for forming a wiring path 200 is formed in the first interlayer insulating layer 41. Next, as shown in FIG. 25C, a first metal layer 21f is formed along the inner surface of the recess 41a extending in one direction formed in the first interlayer insulating layer 41. Next, as shown in FIG. 25D, a first solid electrolyte layer 31f is formed so as to cover the first metal layer 21f and not to fill the recess 41a. In this embodiment, as shown in FIG. 25B, three wiring paths, a first wiring path 201, a second wiring path 202, and a third wiring path 203, are formed as the wiring path 200. Therefore, as shown in FIG. 25B to FIG. 25D, three recesses 41a are shown corresponding to the three wiring paths.

[0281] Next, as shown in FIG. 25E, a first insulating layer 81f is formed so as to cover the first solid electrolyte layer 31f and not fill the recess 41a. Specifically, the first insulating layer 81f is formed so as to cover the entire surface of the first solid electrolyte layer 31f. At this time, the first insulating layer 81f is formed so as to cover the surface of the first solid electrolyte layer 31f that is not formed in the recess 41a and the inner side and bottom surface of the first solid electrolyte layer 31f formed in the recess 41a. The first insulating layer 81f can be formed by, for example, a CVD method.

[0282] Next, as shown in Fig. 25F, the wiring layer 10f is formed so as to be surrounded by the first solid electrolyte layer 31f and the first insulating layer 81f and to fill the recess 41a. Specifically, the wiring layer 10f is formed so as to fill the trenches of the first solid electrolyte layer 31f and the first insulating layer 81f. The process of Fig. 25F can be performed in the same manner as the process of Fig. 11G.

[0283] Next, the steps of FIGS. 25G to 25I are performed, and the steps of FIGS. 25G to 25I can be performed in the same manner as the steps of FIGS. 11H to 11J.

[0284] Specifically, as shown in FIG. 25G, a first resist 71 having a predetermined shape is formed on the wiring layer 10f. Next, as shown in FIG. 25H, the wiring layer 10f is etched using the first resist 71 as a mask, thereby patterning the wiring layer 10f. As a result, the wiring layer 10f is partially removed and separated, and the wiring layer 10B having a predetermined shape can be formed. At this time, the first insulating layer 81f is exposed in the portion where the first resist 71 is not formed. Next, as shown in FIG. 25I, the first resist 71 is removed. As a result, the wiring layer 10B is exposed.

[0285] 25J, a second insulating layer 82f is formed to cover the wiring layer 10B. Specifically, the second insulating layer 82f is formed to cover the entire surface of the wiring layer 10B and the entire surface of the exposed first insulating layer 81f. The second insulating layer 82f can be formed by, for example, a CVD method.

[0286] Thereafter, the steps of FIGS. 25K to 25Y are performed, and the steps of FIGS. 25K to 25Y can be performed in the same manner as the steps of FIGS. 11K to 11Y.

[0287] Specifically, as shown in FIG. 25K, a second resist 72 having a predetermined shape is formed on the second insulating layer 82f so as to cover the wiring layer 10B. Next, as shown in FIG. 25L, the first solid electrolyte layer 31f is etched using the second resist 72 as a mask, thereby patterning the first solid electrolyte layer 31f. At this time, the first insulating layer 81f and the second insulating layer 82f may also be etched using the second resist 72 as a mask. As a result, the first insulating layer 81f and the second insulating layer 82f are partially removed, and an insulating layer 80B consisting of the first insulating layer 81 and the second insulating layer 82 is formed. Next, as shown in FIG. 25M, the second resist 72 is removed.

[0288] Next, as shown in FIG. 25N, a third resist 73 having a predetermined shape is formed on the first metal layer 21f so as to cover the wiring layer 10B, the first solid electrolyte layer 31, and the second insulating layer 82. Next, as shown in FIG. 25O, the first metal layer 21f is etched using the third resist 73 as a mask, thereby patterning the first metal layer 21f. Next, as shown in FIG. 25P, the third resist 73 is removed. Next, as shown in FIG. 25Q, a second solid electrolyte layer 32f is formed so as to cover the wiring layer 10B, the first solid electrolyte layer 31, the first metal layer 21, and the second insulating layer 82.

[0289] Next, as shown in FIG. 25R, a fourth resist 74 having a predetermined shape is formed on the second solid electrolyte layer 32f. Next, as shown in FIG. 25S, the second solid electrolyte layer 32f is etched using the fourth resist 74 as a mask, thereby patterning the second solid electrolyte layer 32f. Next, as shown in FIG. 25T, the fourth resist 74 is removed. This exposes the ends of the second solid electrolyte layer 32 and the first metal layer 21. Next, as shown in FIG. 25U, a second metal layer 22f is formed so as to cover the ends of the second solid electrolyte layer 32 and the first metal layer 21. Next, as shown in FIG. 25V, a fifth resist 75 having a predetermined shape is formed on the second metal layer 22f. Next, as shown in FIG. 25W, the second metal layer 22f is etched using the fifth resist 75 as a mask, thereby patterning the second metal layer 22f. Next, as shown in FIG. 25X, the fifth resist 75 is removed. This exposes the second metal layer 22. Next, as shown in FIG. 25Y, a second interlayer insulating layer 42 is formed to cover the second metal layer 22.

[0290] In this manner, it is possible to fabricate a semiconductor device 2006 including a wiring structure 2001B including a first wiring path 201, a second wiring path 202, and a third wiring path 203. That is, as shown in Fig. 24, it is possible to fabricate a semiconductor device 2006 including an insulating layer 80 consisting of a first insulating layer 81 and a second insulating layer 82.

[0291] The modifications of the first embodiment shown in Figures 12 to 17 can also be applied to this embodiment. Semiconductor devices and wiring structures other than the semiconductor device 2006 shown in Figure 24 can be manufactured in accordance with the manufacturing method shown in Figures 25A to 25Y.

[0292] (Embodiment 3) Next, a third embodiment will be described. First, a configuration of wiring structure 3001 according to a first aspect of the third embodiment will be described with reference to Figs. 26A to 26C. Fig. 26A is a diagram showing a schematic configuration of wiring structure 3001 according to the first aspect of the third embodiment. Fig. 26B is a cross-sectional view of wiring structure 3001. Fig. 26C is a cross-sectional view of wiring structure 3001 taken along line 26C-26C in Fig. 26B.

[0293] Wiring structure 3001 in this embodiment is used in a semiconductor device such as a semiconductor integrated circuit device, similarly to the above-described embodiment 1. In the semiconductor device, wiring structure 3001 includes wiring paths 300 for electrically connecting circuit elements to each other.

[0294] 26A to 26C, the wiring path 300 in the present embodiment is configured such that the wiring path 100 in the above-mentioned first embodiment further includes an insulating layer 90. Other than that, the wiring path 300 has the same configuration as the wiring path 100 in the above-mentioned first embodiment.

[0295] Specifically, wiring structure 3001 includes wiring layer 10, metal layer 20, solid electrolyte layer 30, and insulating layer 90.

[0296] Insulating layer 90 is a second insulating layer different from insulating layer 80 (first insulating layer) of wiring structure 2001 in the above-described second embodiment, and is located between solid electrolyte layer 30 and metal layer 20. Thus, in wiring structure 3001, wiring layer 10, solid electrolyte layer 30, insulating layer 90, and metal layer 20 are formed in this order from the inside to the outside, and metal layer 20 is formed so as to enclose not only wiring layer 10 and solid electrolyte layer 30 but also insulating layer 90.

[0297] Specifically, in cross-sectional view when cut along the YZ cross section, the entire outer periphery of the wiring layer 10 is covered by the solid electrolyte layer 30, the entire outer periphery of the solid electrolyte layer 30 is covered by the insulating layer 90, and the entire outer periphery of the insulating layer 90 is covered by the metal layer 20.

[0298] The insulating layer 90 is an insulating film made of an insulating material, and may be, for example, an alumina film, a silicon oxynitride film, or a silicon nitride film.

[0299] Next, wiring structure 3001A according to a second aspect of embodiment 3 will be described with reference to Fig. 27. Fig. 27 is a diagram showing the configuration of wiring structure 3001A according to the second aspect of embodiment 3 and the configuration of semiconductor device 3002 in which wiring structure 3001A is used.

[0300] 27, wiring structure 3001A includes an insulating layer 40 in addition to wiring layer 10, metal layer 20, solid electrolyte layer 30, and insulating layer 90. Wiring layer 10, metal layer 20, solid electrolyte layer 30, and insulating layer 90 form wiring path 300A, similar to wiring path 300 shown in FIGS. 26A to 26C. Also, as shown in FIG. 27, semiconductor device 3002 includes substrate 50 and wiring structure 3001A formed on substrate 50.

[0301] The number of wiring paths 300A included in wiring structure 3001A formed on substrate 50 is not limited to one. Specifically, as in semiconductor device 3003 shown in Fig. 28, wiring structure 3001A on substrate 50 may include multiple wiring paths 300A. In this case, multiple recesses 40a are formed in insulating layer 40, and wiring paths 300A are embedded in each recess 40a.

[0302] The semiconductor device in this embodiment may also include a transistor 60, like the semiconductor device 4 shown in FIG. 5, or may have a multi-layer wiring structure, like the semiconductor device 5 shown in FIG. 6.

[0303] Next, another aspect of the wiring structure according to the third embodiment will be described with reference to Fig. 29. Fig. 29 is a cross-sectional view showing the configuration of wiring structure 3001B according to a third aspect of the third embodiment and the configuration of semiconductor device 3006 in which wiring structure 3001B is used.

[0304] 29 includes a substrate 50 and a wiring structure 3001B formed on the substrate 50. The wiring structure 3001B includes three wiring paths, namely, a first wiring path 301, a second wiring path 302, and a third wiring path 303, and two interlayer insulating layers, namely, a first interlayer insulating layer 41 and a second interlayer insulating layer 42.

[0305] First wiring path 301, second wiring path 302, and third wiring path 303 have a configuration similar to first wiring path 101, second wiring path 102, and third wiring path 103 of wiring structure 1B in the above-mentioned embodiment 1, further including insulating layer 90B.

[0306] In this embodiment, the insulating layer 90B is also located between the solid electrolyte layer 30B and the metal layer 20B. Specifically, in cross-sectional view taken along the YZ cross section, the entire outer periphery of the solid electrolyte layer 30B is covered by the insulating layer 90B, and the entire outer periphery of the insulating layer 90B is covered by the metal layer 20B.

[0307] The insulating layer 90B is composed of a first insulating layer 91 and a second insulating layer 92. The first insulating layer 91 is a lower insulating film at least partially embedded in the recess 41a, and is located between the first solid electrolyte layer 31 and the first metal layer 21. The second insulating layer 92 is an upper insulating film located on the first insulating layer 91, and is located between the second solid electrolyte layer 32 and the second metal layer 22. The first insulating layer 91 and the second insulating layer 92 are insulating films made of an insulating material, such as an alumina film, a silicon oxynitride film, or a silicon nitride film.

[0308] Thus, since wiring structures 3001, 3001A, and 3001B according to the present embodiment have the same configuration as wiring structure 1 according to the above-mentioned first embodiment, when a voltage is applied to solid electrolyte layers 30, 30B, ions move inside solid electrolyte layers 30, 30B, increasing the electron concentration of wiring layers 10, 10B. This reduces the resistance of wiring layers 10, 10B, and thus makes it possible to suppress an increase in the resistance of wiring layers 10, 10B due to thinning, thereby achieving a resistance reduction effect.

[0309] Furthermore, since the wiring structures 3001, 3001A, and 3001B in the present embodiment include the insulating layers 90 and 90B, it is possible to suppress electronic leakage from the wiring layers 10 and 10B. In particular, when the wiring layers 10 and 10B have a narrow line width, electronic leakage from the wiring layers 10 and 10B is likely to occur, but by providing the insulating layers 90 and 90B, it is possible to effectively suppress electronic leakage.

[0310] Next, a method for manufacturing the wiring structure and semiconductor device according to the third embodiment will be described with reference to Figures 30A to 30Y. Figures 30A to 30Y are views for explaining a method for manufacturing semiconductor device 3006 shown in Figure 29.

[0311] The steps of FIGS. 30A to 30C can be performed in the same manner as the steps of FIGS. 11A to 11E.

[0312] Specifically, as shown in FIG. 30A, a substrate 50 is prepared, and a first interlayer insulating layer 41 is formed on the substrate 50. Next, as shown in FIG. 30B, a recess 41a for forming a wiring path 300 is formed in the first interlayer insulating layer 41. Next, as shown in FIG. 30C, the first interlayer insulating layer 41 is A first metal layer 21f is formed along the inner surface of a recess 41a extending in one direction formed in the edge layer 41. In this embodiment, as shown in Fig. 30B, three wiring paths are formed as the wiring path 300: a first wiring path 301, a second wiring path 302, and a third wiring path 303. Therefore, as shown in Figs. 30B and 30C, three recesses 41a are shown corresponding to the three wiring paths.

[0313] Next, as shown in Fig. 30D, a first insulating layer 91f is formed so as to cover the first metal layer 21f and not fill the recess 41a. Specifically, the first insulating layer 91f is formed so as to cover the entire surface of the first metal layer 21f. At this time, the first insulating layer 91f is formed so as to cover the surface of the first metal layer 21f that is not formed in the recess 41a and the inner side and bottom surface of the first metal layer 21f formed in the recess 41a. The first insulating layer 91f can be formed by, for example, a CVD method.

[0314] Next, as shown in Fig. 30E, first solid electrolyte layer 31f is formed so as to cover first insulating layer 91f and not fill recess 41a. The step of Fig. 30E can be performed in the same manner as the step of Fig. 11E.

[0315] Next, the steps of FIGS. 30F to 30S are performed, and the steps of FIGS. 30F to 30S can be performed in the same manner as the steps of FIGS. 11G to 11T.

[0316] Specifically, as shown in FIG. 30F, the wiring layer 10f is formed so as to be surrounded by the first solid electrolyte layer 31f and to fill the recess 41a. Next, as shown in FIG. 30G, a first resist 71 having a predetermined shape is formed on the wiring layer 10f. Next, as shown in FIG. 30H, the wiring layer 10f is etched using the first resist 71 as a mask, thereby patterning the wiring layer 10f. As a result, the wiring layer 10f is partially removed and separated, and the wiring layer 10B having a predetermined shape can be formed. Next, as shown in FIG. 30I, the first resist 71 is removed. As a result, the wiring layer 10B is exposed.

[0317] Next, as shown in Fig. 30J, a second resist 72 having a predetermined shape is formed on the first solid electrolyte layer 31f so as to cover the wiring layer 10B. Next, as shown in Fig. 30K, the first solid electrolyte layer 31f is etched using the second resist 72 as a mask, thereby patterning the first solid electrolyte layer 31f. Next, as shown in Fig. 30L, the second resist 72 is removed.

[0318] Next, as shown in FIG. 30M, a third resist 73 having a predetermined shape is formed on the first metal layer 21f so as to cover the wiring layer 10B and the first solid electrolyte layer 31. Next, as shown in FIG. 30N, the first metal layer 21f is etched using the third resist 73 as a mask, thereby patterning the first metal layer 21f. At this time, the first insulating layer 91f may also be etched using the third resist 73 as a mask. As a result, the first insulating layer 91 is partially removed, and the first insulating layer 91 is formed. Next, as shown in FIG. 30O, the third resist 73 is removed.

[0319] Next, as shown in FIG. 30P, a second solid electrolyte layer 32f is formed so as to cover the wiring layer 10B, the first solid electrolyte layer 31, and the first metal layer 21. Next, as shown in FIG. 30Q, a fourth resist 74 having a predetermined shape is formed on the second solid electrolyte layer 32f. Next, as shown in FIG. 30R, the second solid electrolyte layer 32f is etched using the fourth resist 74 as a mask, thereby patterning the second solid electrolyte layer 32f. As a result, a solid electrolyte layer 30B consisting of the first solid electrolyte layer 31 and the second solid electrolyte layer 32 is formed. Next, as shown in FIG. 30S, the fourth resist 74 is removed.

[0320] Next, as shown in Fig. 30T, a second insulating layer 92f is formed to cover the solid electrolyte layer 30B. Specifically, the second insulating layer 92f is formed to cover the entire surface of the solid electrolyte layer 30 and the entire surface of the exposed first insulating layer 91f. This allows the insulating layer 90B made up of the first insulating layer 91 and the second insulating layer 92 to be formed. The second insulating layer 92f can be formed by, for example, a CVD method.

[0321] Next, as shown in Figure 30U, a second metal layer 22f is formed so as to cover the second insulating layer 92f. The step of Figure 30U can be performed in the same manner as the step of Figure 11U.

[0322] Thereafter, the steps of FIGS. 30V to 30Y are performed, and the steps of FIGS. 30V to 30Y can be performed in the same manner as the steps of FIGS. 11V to 11Y.

[0323] Specifically, as shown in FIG. 30V, a fifth resist 75 having a predetermined shape is formed on the second metal layer 22f. Next, as shown in FIG. 30W, the second metal layer 22f is etched using the fifth resist 75 as a mask, thereby patterning the second metal layer 22f. Next, as shown in FIG. 30X, the fifth resist 75 is removed. This exposes the second metal layer 22. Next, as shown in FIG. 30Y, a second interlayer insulating layer 42 is formed so as to cover the second metal layer 22.

[0324] In this manner, it is possible to fabricate a semiconductor device 3006 including a wiring structure 3001B including a first wiring path 301, a second wiring path 302, and a third wiring path 303. That is, it is possible to fabricate a semiconductor device 3006 including an insulating layer 90 consisting of a first insulating layer 91 and a second insulating layer 92, as shown in FIG.

[0325] It should be noted that the modifications of the first embodiment shown in Figures 12 to 17 can also be applied to this embodiment. Semiconductor devices and wiring structures other than the semiconductor device 3006 shown in Figure 29 can be fabricated in accordance with the manufacturing method shown in Figures 30A to 30Y.

[0326] (Embodiment 4) Next, a fourth embodiment will be described. First, the configuration of wiring structure 4001 according to a first aspect of the fourth embodiment will be described with reference to Figs. 31A to 31C. Fig. 31A is a schematic diagram showing the configuration of wiring structure 4001 according to the first aspect of the fourth embodiment. Fig. 31B is a cross-sectional view of wiring structure 4001. Fig. 31C is a cross-sectional view of wiring structure 4001 taken along line 31C-31C in Fig. 31B.

[0327] Wiring structure 4001 in this embodiment is used in a semiconductor device such as a semiconductor integrated circuit device, similarly to the above-described embodiment 1. In the semiconductor device, wiring structure 4001 includes wiring path 400 for electrically connecting circuit elements to each other.

[0328] 31A to 31C, wiring path 400 in the present embodiment is configured such that wiring path 100 in the above-mentioned embodiment 1 further includes insulating layer 80, which is a first insulating layer, and insulating layer 90, which is a second insulating layer. Other than that, the configuration is the same as wiring path 100 in the above-mentioned embodiment 1.

[0329] Specifically, wiring structure 4001 includes wiring layer 10, metal layer 20, solid electrolyte layer 30, and insulating layers 80 and 90. As shown in FIG.

[0330] The insulating layer 80 is located between the wiring layer 10 and the solid electrolyte layer 30. The insulating layer 90 is located between the solid electrolyte layer 30 and the metal layer 20. Thus, in the wiring structure 4001, the wiring layer 10, the insulating layer 80, the solid electrolyte layer 30, the insulating layer 90, and the metal layer 20 are formed in this order from the inside to the outside, and the metal layer 20 is formed so as to enclose not only the wiring layer 10 and the solid electrolyte layer 30 but also the insulating layers 80 and 90.

[0331] Specifically, in cross-sectional view when cut along the YZ cross section, the entire outer periphery of wiring layer 10 is covered by insulating layer 80, which is a first insulating layer, the entire outer periphery of insulating layer 80 is covered by solid electrolyte layer 30, the entire outer periphery of solid electrolyte layer 30 is covered by insulating layer 90, which is a second insulating layer, and the entire outer periphery of insulating layer 90 is covered by metal layer 20.

[0332] The insulating layers 80 and 90 are insulating films made of an insulating material. For example, an alumina film, a silicon oxynitride film, or a silicon nitride film can be used as the insulating layers 80 and 90. The insulating layers 80 and 90 may be made of the same material or different materials.

[0333] Next, wiring structure 4001A according to a second aspect of embodiment 4 will be described with reference to Fig. 32. Fig. 32 is a diagram showing the configuration of wiring structure 4001A according to the second aspect of embodiment 4 and the configuration of semiconductor device 4002 in which wiring structure 4001A is used.

[0334] 32, wiring structure 4001A includes wiring layer 10, metal layer 20, solid electrolyte layer 30, insulating layer 80 as a first insulating layer, insulating layer 90 as a second insulating layer, and further includes insulating layer 40 as a third insulating layer. Wiring layer 10, metal layer 20, solid electrolyte layer 30, insulating layer 80, and insulating layer 90 form wiring path 400A, similar to wiring path 400 shown in FIGS. 31A to 31C. Also, as shown in FIG. 32, semiconductor device 4002 includes substrate 50 and wiring structure 4001A formed on substrate 50.

[0335] The number of wiring paths 400A included in wiring structure 4001A formed on substrate 50 is not limited to one. Specifically, as in semiconductor device 4003 shown in Fig. 33, wiring structure 3001A on substrate 50 may include multiple wiring paths 400A. In this case, multiple recesses 40a are formed in insulating layer 40, and wiring paths 400A are embedded in each recess 40a.

[0336] The semiconductor device in this embodiment may also include a transistor 60, like the semiconductor device 4 shown in FIG. 5, or may have a multi-layer wiring structure, like the semiconductor device 5 shown in FIG. 6.

[0337] Next, another aspect of the wiring structure according to the fourth embodiment will be described with reference to Fig. 34. Fig. 34 is a cross-sectional view showing the configuration of wiring structure 4001B according to a third aspect of the fourth embodiment and the configuration of semiconductor device 4006 in which wiring structure 4001B is used.

[0338] 34 includes a substrate 50 and a wiring structure 4001B formed on the substrate 50. The wiring structure 4001B includes three wiring paths, namely, a first wiring path 401, a second wiring path 402, and a third wiring path 403, and two interlayer insulating layers, namely, a first interlayer insulating layer 41 and a second interlayer insulating layer 42.

[0339] The first wiring path 401, the second wiring path 402, and the third wiring path 403 are configured as the first wiring path 101, the second wiring path 102, and the third wiring path 103 of the wiring structure 1B in the above-mentioned embodiment 1, further including an insulating layer 80B and an insulating layer 90B.

[0340] In this embodiment, the insulating layer 80B is also located between the wiring layer 10B and the solid electrolyte layer 30B. The insulating layer 90B is also located between the solid electrolyte layer 30B and the metal layer 20B. Specifically, in a cross-sectional view taken along the YZ cross section, the entire outer periphery of the wiring layer 10B is covered by the insulating layer 80B, the entire outer periphery of the solid electrolyte layer 30B is covered by the insulating layer 90B, and the entire outer periphery of the insulating layer 90B is covered by the metal layer 20B.

[0341] Insulating layer 80B is the same as insulating layer 80B in the above-mentioned embodiment 2, and is composed of a first insulating layer 81 and a second insulating layer 82. Insulating layer 90B is the same as insulating layer 90B in the above-mentioned embodiment 3, and is composed of a first insulating layer 91 and a second insulating layer 92.

[0342] The semiconductor device 4006 shown in FIG. 34 can be fabricated in accordance with the manufacturing method of the semiconductor devices 2006 and 3006 in the second and third embodiments.

[0343] Thus, since wiring structures 4001, 4001A, and 4001B according to the present embodiment have the same configuration as wiring structure 1 according to the above-mentioned first embodiment, when a voltage is applied to solid electrolyte layers 30, 30B, ions move inside solid electrolyte layers 30, 30B, increasing the electron concentration of wiring layers 10, 10B. This reduces the resistance of wiring layers 10, 10B, and thus makes it possible to suppress an increase in the resistance of wiring layers 10, 10B due to thinning, thereby achieving a resistance reduction effect.

[0344] Furthermore, the wiring structures 4001, 4001A, and 4001B in the present embodiment include insulating layers 80 and 80B and insulating layers 90 and 90B. This makes it possible to effectively suppress electronic leakage from the wiring layers 10 and 10B. In particular, when the wiring layers 10 and 10B have a narrow line width, electronic leakage from the wiring layers 10 and 10B is likely to occur. However, by providing two insulating layers, the insulating layers 80 and 80B and the insulating layers 90 and 90B, electronic leakage can be effectively suppressed compared to the case where only one of the insulating layers 80 and 80B and the insulating layers 90 and 90B is provided.

[0345] 12 to 17 can also be applied to this embodiment. In this case, the semiconductor device and wiring structure in this embodiment can be manufactured in accordance with the manufacturing methods of the semiconductor device and wiring structure in the above-mentioned embodiments 1 to 3.

[0346] (Other variations) While the wiring structure and semiconductor device according to the present disclosure have been described above based on the embodiments and modifications, the present disclosure is not limited to the above-described embodiments and modifications.

[0347] For example, in the above embodiment, one direction in which the wiring layer of the wiring structure extends is a straight line, but the invention is not limited to this and may be a curved line.

[0348] In the above embodiment, the first resist 71, the second resist 72, the third resist 73, the fourth resist 74, and the fifth resist 75 are made of an organic material, but the present invention is not limited to this. For example, the first resist 71, the second resist 72, the third resist 73, the fourth resist 74, and the fifth resist 75 may be made of an inorganic material.

[0349] In addition, the present disclosure also includes forms obtained by applying various modifications to the embodiments and modifications that would come to mind by a person skilled in the art, as well as forms realized by arbitrarily combining the components and functions of the embodiments and modifications without departing from the spirit of the present disclosure. [Industrial Applicability]

[0350] The present disclosure can be used in various devices having wiring structures, including semiconductor devices such as semiconductor integrated circuit devices. [Explanation of symbols]

[0351] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1Y, 7, 2001, 2001A, 2001B, 3001, 3001A, 3001B, 4001, 4001A, 4001B Wiring structure 1M 2nd wiring structure 2, 3, 3F, 4, 5, 6, 6C, 6D, 6E, 8, 2002, 2003, 2006, 3002, 3003, 3006, 4002, 4003, 4006 Semiconductor device 10, 10B, 10f wiring layer 10M 2nd wiring layer 10a Side 10b Bottom 10Y 1st electrode layer 11 1st wiring layer 12 2nd wiring layer 20, 20B, 20D, 20E, 20F metal layer 20M, 22, 22D, 22f 2nd metal layer 20Y 2nd electrode layer 21, 21f 1st metal layer 30, 30p, 30n, 30B, 30E, 30F, 30Y solid electrolyte layer 31, 31f 1st solid electrolyte layer 32, 32f 2nd solid electrolyte layer 40, 40Y, 80, 80B, 90, 90B Insulation layer 40a, 41a, 42a Recess 41 First interlayer insulating layer 42, 42C Second interlayer insulating layer 43 3rd interlayer insulation layer 50, 50Y board 60 Transistor 60g Gate electrode 60s Source Area 60d Drain region 61 First transistor 62 Second transistor 71 First Resist 72 Second Resist 73 3rd Resist 74 4th Resist 75 5th Resist 81, 81f, 91, 91f First insulating layer 82, 82f, 92, 92f Second insulating layer 100, 100A, 100F, 200, 200A, 300, 300A, 400, 400A Wiring Run 100M 2nd wireway 100a 1st Wiring 100b Second wiring 100c 3rd wiring 100p contact plug 101, 101D, 101E, 201, 301, 401 1st wiring path 102, 102D, 102E, 202, 302, 402 Second wiring path 103, 103D, 103E, 203, 303, 403 3rd wiring path

Claims

1. 1. A method for operating a passive element electrically connected to a wiring structure, comprising: The wiring structure includes a wiring layer that is mainly made of metal and extends in one direction; a metal layer facing the wiring layer; and a solid electrolyte layer located between the wiring layer and the metal layer in a cross-sectional view taken along a plane perpendicular to the one direction and formed so as to enclose the wiring layer, the wiring layer and the metal layer are electrically insulated via the solid electrolyte layer, the passive element is electrically connected to the wiring layer; With a voltage applied to the solid electrolyte layer, An electrical signal is transmitted from the passive element to the wiring layer, or an electrical signal is transmitted from the wiring layer to the passive element. How passive elements work.

2. 1. A method for operating a passive element electrically connected to a wiring structure, comprising: The wiring structure includes: A wiring layer mainly made of metal and extending in one direction; a metal layer facing the wiring layer; a solid electrolyte layer located between the wiring layer and the metal layer and in contact with each of the wiring layer and the metal layer in a cross-sectional view taken along a plane perpendicular to the one direction; a side surface of the wiring layer and a side surface of the solid electrolyte layer are in surface contact with each other, a side surface of the solid electrolyte layer and a side surface of the metal layer are in surface contact with each other, the wiring layer and the metal layer are electrically insulated via the solid electrolyte layer, the passive element is electrically connected to the wiring layer; With a voltage applied to the solid electrolyte layer, An electrical signal is transmitted from the passive element to the wiring layer, or an electrical signal is transmitted from the wiring layer to the passive element. How passive elements work.

3. A method for operating a passive element according to claim 1 or 2, comprising the steps of: applying a first voltage to the wiring layer and a second voltage higher than the first voltage to the metal layer; How passive elements work.

4. A method for operating a passive element according to claim 1 or 2, comprising the steps of: The passive element is a capacitor or a resistor. How passive elements work.

Images