Semiconductor Device

Abstract

To provide a semiconductor device capable of increasing the bonding strength with a mounting substrate.SOLUTION: A semiconductor device 100 that is covered with a sealing resin 50 in a rectangular parallelepiped shape, and in which a plurality of lead portions 11 are partially exposed from a side surface 100c and a bottom surface 100a includes a notch portion 100b provided in the sealing resin 50 along the side formed by the side surface 100c and the bottom surface 100a, and the lead portion 11 includes a first exposed surface 11bb that is flush with the side surface 100c and exposed from the side surface 100c, and a second exposed surface 11ba which is a surface adjacent to both sides of the first exposed surface 11bb and is exposed from the notch portion 100b.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A known method for post-processing of semiconductor devices is called Mold Array Package (MAP), in which a plurality of device regions are collectively covered with a sealing resin and the sealing resin is cut into individual pieces according to product size.

[0003] As an example of the MAP method, a technology has been disclosed in which a lead frame is molded in such a way that adjacent device regions are connected by connecting parts, and then a laser is irradiated along grooves formed in the connecting parts to separate the lead frame (see Patent Document 1). As another example of the MAP method, a technology has been disclosed in which a laser is irradiated into the surrounding sealing body that seals a semiconductor chip to form grooves around the leads exposed from the bottom surface of the sealing body, thereby exposing the side surfaces of the leads, thereby improving the mounting strength of a semiconductor device (see Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 8,017,447 [Patent Document 2] JP 2013-143445 A Summary of the Invention [Problem to be solved by the invention]

[0005] In a product form called a "leadless package" manufactured using this type of MAP method, if the lead frame is thin, the area of ​​the lead side, which is the cut surface when separated into individual pieces, is small, making it difficult for a fillet to form on the lead side, and the adhesive strength with the mounting board may be low.

[0006] SUMMARY OF THE PRESENT DISCLOSURE In one aspect, the present invention provides a semiconductor device that can improve the adhesive strength to a mounting board. [Means for solving the problem]

[0007] The semiconductor device according to an embodiment of the present invention comprises: A semiconductor device having a rectangular parallelepiped shape, covered with sealing resin, and a plurality of lead portions partially exposed from the side and bottom surfaces, a notch portion is provided in the sealing resin along an edge formed by the side surface and the bottom surface; The lead portion is a first exposed surface that is flush with the side surface and is exposed from the side surface; a second exposed surface that is adjacent to both sides of the first exposed surface and is exposed through the cutout portion; Equipped with. Effect of the Invention

[0008] According to one aspect of the present invention, it is possible to provide a semiconductor device that can improve the adhesive strength with respect to a mounting board. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view showing the structure of a mounting surface side of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged perspective view showing the structure of a lead portion of the semiconductor device in the first embodiment. [Diagram 3] FIG. 3 is a schematic cross-sectional view taken along line II shown in FIG. [Figure 4] FIG. 4 is a partial perspective view showing a state before the semiconductor device according to the first embodiment is mounted on a substrate. [Diagram 5] FIG. 5 is a partial perspective view showing a state after the semiconductor device according to the first embodiment has been mounted on a substrate. [Figure 6] FIG. 6 is an explanatory diagram showing a cross section taken along line II shown in FIG. 1 after the semiconductor device according to the first embodiment is mounted on a substrate. [Figure 7A] FIG. 7A is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7B] FIG. 7B is an explanatory diagram showing the method for manufacturing the semiconductor device in the first embodiment. [Figure 7C] FIG. 7C is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7D] FIG. 7D is an explanatory diagram showing the method for manufacturing the semiconductor device in the first embodiment. [Figure 7E] FIG. 7E is an explanatory diagram showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7F] FIG. 7F is an explanatory diagram showing the method for manufacturing the semiconductor device in the first embodiment. [Figure 7G] FIG. 7G is an explanatory diagram showing a method for manufacturing the semiconductor device in the first embodiment. [Figure 8] FIG. 8 is a perspective view showing a structure of a mounting surface side of a semiconductor device in a modified example of the first embodiment. [Figure 9] FIG. 9 is an explanatory diagram showing a method for manufacturing a semiconductor device according to a modification of the first embodiment. [Figure 10] FIG. 10 is a perspective view showing the structure of the mounting surface side of the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a perspective view showing a structure of a mounting surface side of a semiconductor device in a modified example of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated explanations may be omitted. In the drawings, the X, Y, and Z directions are perpendicular to each other. The direction including the X direction and the opposite direction of the X direction (-X direction) is called the "X-axis direction", the direction including the Y direction and the opposite direction of the Y direction (-Y direction) is called the "Y-axis direction", and the direction including the Z direction and the opposite direction of the Z direction (-Z direction) is called the "Z-axis direction" (height direction, thickness direction). In this regard, in the following embodiments, the surface on the mounting surface side relative to the mounting board may be called the "bottom surface", and the normal direction of the bottom surface is called the Z-axis direction. The drawings are schematic, and the ratios of width, length, depth, etc. are not as shown in the drawings.

[0011] <Semiconductor device> FIG. 1 is a perspective view showing the structure of a mounting surface side of a semiconductor device according to a first embodiment. As shown in FIG. 1, the semiconductor device 100 is manufactured by the MAP method, and has a 6-pin DFN (Dual-Flat No-leads) leadless package structure. Specifically, the semiconductor device 100 is covered with sealing resin 50 in a rectangular parallelepiped shape, and has a step 100b, which is a notch provided by laser processing in the sealing resin 50 along an edge formed by a bottom surface 100a and a side surface 100c. In this semiconductor device 100, a plurality of lead portions 11 are partially exposed from the bottom surface 100a, the step 100b, and the side surface 100c.

[0012] The lead frame 10 includes six lead portions 11 and a die pad 12 .

[0013] The six lead portions 11 are exposed from the bottom surface 100a of the semiconductor device 100, and when the bottom surface 100a is viewed in plan, three lead portions 11 are arranged along each of the two long sides of the die pad 12 disposed near the center of the bottom surface 100a. The lead portion 11 has a structure in which the rectangular portion 11a and the tip portion 11b are integrated and have the same height.

[0014] The rectangular portion 11a has a rectangular shape when the bottom surface 100a of the semiconductor device 100 is viewed in plan, and only the bottom surface of the rectangular portion 11a is exposed from the sealing resin 50. The rectangular portions 11a are arranged on the die pad 12 side.

[0015] The tip portion 11b is disposed on the opposite side of the rectangular portion 11a to the side of the die pad 12. The tip portion 11b has a trapezoidal shape when the bottom surface 100a is viewed in plan, and the lower base of the trapezoid, which is longer than the upper base, contacts the rectangular portion 11a. The first exposed surface 11ba, which is the surface of the tip portion 11b on the side surface 100c of the semiconductor device 100, is flush with the side surface 100c of the semiconductor device 100 and is exposed from the side surface 100c. The first exposed surface 11ba also extends to the side surface 100c where the step 100b is not provided, and is entirely exposed from the side surface 100c. In addition, the second exposed surfaces 11bb, which are surfaces adjacent to both sides of the first exposed surface 11ba, are exposed from the step 100b including the curved surface and along this curved surface.

[0016] The die pad 12 is disposed near the center of the bottom surface 100a of the semiconductor device 100, and the bottom surface of the die pad 12 is exposed. This allows the die pad 12 to dissipate heat from the semiconductor chip 20 mounted on its upper surface through the bottom surface.

[0017] FIG. 2 is an enlarged perspective view showing the structure of a lead portion of the semiconductor device in the first embodiment. As shown in FIG. 2, in the X direction, the width L1 of the rectangular portion 11a, the widest width L2 of the portion where the tip portion 11b is exposed from the sealing resin 50, and the width L3 of the first exposed surface 11ba narrow in this order (L1>L2>L3).

[0018] The angle between the first exposed surface 11ba and the second exposed surface 11bb can be selected as appropriate without any particular limitation, but from the viewpoint of improving the visibility of the solder joint, it is preferable that it be an obtuse angle as in this embodiment. The height (width in the Z direction) of the step 100b can be appropriately selected without any particular limitation, but is preferably equal to or less than the height of the first exposed surface 11ba.

[0019] Fig. 3 is a schematic cross-sectional view taken along line II in Fig. 1. Line II in Fig. 1 is a straight line that does not pass through first exposed surface 11ba but passes through second exposed surface 11bb. As shown in FIG. 3, the lead frame 10 is disposed on the bottom surface 100a side of the semiconductor device 100. The leads 11 are arranged along the side surfaces 100c of the semiconductor device 100. The leads 11 are provided on the side surfaces of the die pad 12 with notches to prevent the leads 11 from falling off. The die pad 12 is disposed so as to be sandwiched between the lead portions 11. A notch is provided on the side surface of the die pad 12 facing the lead portions 11 to prevent the die pad 12 from falling off. The material of the lead frame 10 is not particularly limited and can be appropriately selected, and examples thereof include a Cu alloy and an Fe-Ni alloy.

[0020] The bottom surface and the second exposed surface 11bb of the lead portion 11 are covered with a metal film 60 having solder wettability. Of these, it is particularly preferable for the second exposed surface 11bb to be covered with the metal film 60, since this makes it easier for the solder to creep up. The metal film 60 is, for example, a plating film of Sn, Pb--Sn, Sn--Bi, Sn--Ag--Cu, or the like. The first exposed surface 11ba is not covered with the metal film 60.

[0021] The semiconductor chip 20 is fixed to the upper surface of the die pad 12 with a die bond material 30 . The semiconductor chip 20 can be appropriately selected without any particular limitation, and examples thereof include a silicon device, a SiC device, and a compound device.

[0022] The die bond material 30 can be appropriately selected without any particular limitation, and examples thereof include Ag paste, high melting point solder, sintered metal, insulating paste, DAF (Die Attach Film), etc. The die bond material is also sometimes called a die attach material.

[0023] The wires 40 electrically connect the bonding pads provided on the upper surface of the semiconductor chip 20 to the leads 11. The wires are also sometimes called conductive members or wiring materials. The material of the wire 40 is not particularly limited and can be appropriately selected, and examples thereof include Au, Cu, Al, Ag, and alloys thereof. In this embodiment, the wires 40 are used to electrically connect the semiconductor chip 20 and the leads 11, but the present invention is not limited to this. For example, flip-chip mounting using bumps may be used.

[0024] The sealing resin 50 protects a part of the lead frame 10 , the semiconductor chip 20 , the die bond material 30 and the wires 40 , and also forms the outer shape of the semiconductor device 100 . The sealing resin 50 can be appropriately selected without any particular limitation, and examples thereof include thermosetting epoxy resins.

[0025] Fig. 4 is a partial perspective view showing a state before the semiconductor device in the first embodiment is mounted on a substrate. Fig. 5 is a partial perspective view showing a state after the semiconductor device in the first embodiment is mounted on a substrate. Fig. 6 is an explanatory diagram showing a cross section of the semiconductor device in the first embodiment after it is mounted on a substrate.

[0026] When the lead portion 11 of the semiconductor device 100 is soldered to the conductor pattern P arranged on the mounting board B made of glass epoxy as shown in Fig. 4, the semiconductor device 100 is mounted in the positional relationship as shown in Fig. 5 and Fig. 6. That is, when the lead portion 11 is connected to the conductor pattern P with solder S, the solder S creeps up to the first exposed surface 11ba and the second exposed surface 11bb shown in Fig. 2, and a fillet with a good shape is formed whose base spreads out from above the first exposed surface 11ba. This makes the semiconductor device 100 firmly bonded to the mounting board B, and improves the fixing strength to the mounting board B.

[0027] In this embodiment, since the surface of the second exposed surface 11bb is covered with the metal film 60 having good solder wettability, even if the first exposed surface 11ba is not covered with this metal film, a fillet with a better shape can be formed. Even if the width of the conductor pattern P is a rectangle having almost the same width as the width L1 of the rectangular portion 11a, the solder S can creep up the second exposed surface 11bb to form a good fillet. Furthermore, with such a shape of the tip 11b of the lead portion 11, visual inspection of the joint with the mounting board B can be easily performed even in a semiconductor device in which the lead portions 11 are narrow and have a large number of lead portions 11.

[0028] (Method of manufacturing a semiconductor device) 7A to 7G are explanatory views showing a method for manufacturing the semiconductor device in the first embodiment.

[0029] <1. Lead frame preparation> First, as shown in FIG. 7A, the lead frame 10 prepared first has two regions: a device region A1 in which the semiconductor device 100 is formed, and a dicing region A2 which is removed by dicing when singulating. The device region A1 includes a die pad 12 which is a chip mounting portion capable of supporting a semiconductor chip 20, and a plurality of lead portions 11 arranged around the die pad 12. The lead portions 11 in the device region A1 are the rectangular portion 11a and the tip portion 11b described above. The lead portions 11 in the dicing region A2 are connection portions 11c which become cut margins when dicing into individual pieces, and which hold the plurality of semiconductor devices 100 as a whole until they are diced into individual pieces.

[0030] <2. Semiconductor chip mounting process> 7B, the semiconductor chip 20 is mounted on the upper surface of the die pad 12. The semiconductor chip 20 is fixed to the die pad 12 by a die bond material 30.

[0031] <3. Wire bonding process> Next, as shown in FIG. 7C, the bonding pads provided on the upper surface of the semiconductor chip 20 and the rectangular portions 11a of the leads 11 are electrically connected by wires 40.

[0032] <4. Resin molding process> 7D, the entire surface of the lead frame 10 is covered with the sealing resin 50. That is, the sealing resin 50 is filled in the gap between the lead portion 11 and the die pad 12. On the other hand, the bottom surface of the lead frame 10 is not covered with the sealing resin 50.

[0033] <5.Resin removal process> Next, as shown in Fig. 7E, the sealing resin 50 near the connection portion 11c is removed while scanning the laser L in the X direction while irradiating it in the +Z direction, to expose the second exposed surface 11bb. The intensity of the laser L is such that the sealing resin 50 can be removed, but the lead portion 11 cannot be removed even if irradiated with the laser L. In this way, the sealing resin 50 is removed using the laser L so that L2>L3, and the step 100b shown in Fig. 2 is provided as shown in Fig. 7F.

[0034] The scanning path of the laser L may be a path for repeatedly irradiating in one direction, or a path for irradiating while going back and forth. The range of the sealing resin 50 to be removed by the laser L is limited to the vicinity of both ends of the connection portion 11c, and it is not necessary to remove the portions that will become cut margins in dicing. The angle at which the laser L is irradiated may be normal to the surface of the lead frame 10, or the angle may be adjusted slightly from the normal to adjust the range of the exposed region of the second exposed surface 11bb. The exposed area of ​​the second exposed surface 11bb may be adjusted by adjusting the intensity of the laser L.

[0035] After the resin is removed by irradiation with the laser L, it is preferable to remove the residual resin, which is the remainder of the sealing resin that has not been completely removed. As a method for removing the residual resin, water jet treatment and liquid honing treatment are preferred since they can be easily carried out in existing processes. In the case of water jet treatment, liquid is sprayed from a nozzle to remove the residual resin, while in the case of liquid honing treatment, slurry is sprayed from a spray gun onto the adhering residual resin to remove the residual resin. The remaining resin may be removed only to the extent that it remains within the effective dimensions that contribute to soldering during mounting.

[0036] <6.Metal film formation process> Next, a metal film 60 having good solder wettability is formed by plating or the like on the lead portion 11 and the bottom surface of the die pad 12, and on the part of the lead portion 11 exposed by removing the resin. This metal film forming step does not have to be performed if the lead portion 11 itself has good solder wettability.

[0037] <7.Singulation process> Next, as shown in Fig. 7G, the connection portions 11c are cut and separated by a dicing saw D to obtain the semiconductor device 100 having the lead portions 11 as shown in Fig. 2. Therefore, the first exposed surface 11ba is a surface cut by the dicing saw D and is not covered with the metal film 60. By carrying out the above steps, the semiconductor device 100 can be manufactured.

[0038] In this manner, the semiconductor device 100 is covered with the sealing resin 50 in a rectangular parallelepiped shape, and a plurality of lead portions 11 are partially exposed from the side surface 100c and the bottom surface 100a. That is, the semiconductor device 100 has a step 100b provided in the sealing resin 50 along an edge formed by the side surface 100c and the bottom surface 100a, and the lead portion 11 includes a first exposed surface 11ba that is flush with the side surface 100c and exposed from the side surface 100c, and a second exposed surface 11bb that is adjacent to both sides of the first exposed surface 11ba and exposed from the step 100b. This allows the semiconductor device 100 to have an increased adhesive strength with the mounting board.

[0039] (Modification of the first embodiment) FIG. 8 is a perspective view showing a structure of a mounting surface side of a semiconductor device in a modified example of the first embodiment. As shown in FIG. 8, the semiconductor device 100 of the modified example of the first embodiment is similar to the semiconductor device 100 of the first embodiment, except that the side surface 11ab of the rectangular portion 11a in the semiconductor device 100 of the first embodiment is exposed. As a result, in the semiconductor device 100 according to the modification of the first embodiment, the area in the lead portion 11 where the solder S is bonded is increased, so that the bonding strength with the mounting board B can be further increased.

[0040] A manufacturing method of the semiconductor device 100 of the modified example of the first embodiment is similar to the manufacturing method of the semiconductor device 100 of the first embodiment, except that in the resin removal step of the first embodiment, the width of the step 100b is increased to remove the sealing resin 50 to expose the side surface 11ab of the rectangular portion 11a, and a metal film 60 is also formed on the side surface 11ab in the metal film formation step, as shown in FIG. 9.

[0041] Second embodiment FIG. 10 is a perspective view showing the structure of the mounting surface side of the semiconductor device according to the second embodiment. As shown in FIG. 10, the semiconductor device 100 of the second embodiment is similar to the semiconductor device 100 of the first embodiment, except that a reinforcing structure 11bd is provided on the upper surface side of the lead portion 11 in the first embodiment. In this manner, the semiconductor device 100 of the second embodiment is provided with the reinforcing structure 11bd, thereby making it possible to improve the mechanical strength of the lead portion 11.

[0042] Furthermore, as a modified example of the second embodiment, as shown in FIG. 11, the sealing resin 50 is deeply removed to the point where the reinforcement structure 11bd is exposed, and a fillet is formed in the exposed reinforcement structure 11bd, thereby increasing the bonding strength.

[0043] The present invention has been specifically described above based on an embodiment of the present invention, but it goes without saying that the present invention is not limited to the embodiment described above, and various modifications are possible without departing from the spirit of the present invention.

[0044] For example, in each of the above-described embodiments, a 6-pin DFN is used as an example of a leadless type semiconductor device, but the present invention is not limited to this, and may be, for example, a QFN (Quad-Flat Non-leaded). In addition, in each of the above-described embodiments, the die pad is exposed from the bottom surface of the semiconductor device, but the die pad may not be exposed from the bottom surface of the semiconductor device. Furthermore, in each of the above-described embodiments, the shape of the lead portion is a shape that is an integral combination of a rectangular portion and a trapezoidal tip portion when the bottom surface of the semiconductor device is viewed in a plane, but this is not limited to this and any shape that can have a first exposed surface and a second exposed surface may be used. Furthermore, in each of the above-described embodiments, the cutout portion has a curved shape as the step 100b, but this is not limited thereto, and any cutout shape that can provide a first exposed surface and a second exposed surface may be used. [Explanation of symbols]

[0045] 10 Lead frame 11 Lead section 11a Rectangular part 11b Tip 11ba First exposed surface 11bb Second exposed surface 11bd Reinforcement structure part 11c Connection 12 Die pad (chip mounting area) 20. Semiconductor Chips 30 Die bond material 40 Wire 50 Sealing resin 100 Semiconductor device 100a Bottom surface of semiconductor device 100b Step (notch) 100c Side of semiconductor device A1 Device Area A2 Dicing area B. Mounting board D Dicing Saw L Laser P Conductor Pattern S solder

Claims

1. A semiconductor device having a rectangular parallelepiped shape, covered with sealing resin, and a plurality of lead portions partially exposed from the side and bottom surfaces, a notch portion is provided in the sealing resin along an edge formed by the side surface and the bottom surface; The lead portion is a first exposed surface that is flush with the side surface and is exposed from the side surface; a second exposed surface that is adjacent to both sides of the first exposed surface and is exposed through the cutout portion; a reinforcing structure portion including a third exposed surface provided on the upper surface and extending in an in-plane direction thereof and exposed from the side surface; Equipped with 2. A semiconductor device comprising: a first exposed surface and a second exposed surface, the first exposed surface and the second exposed surface forming an obtuse angle.

2. The semiconductor device according to claim 1 , wherein the second exposed surface is covered with a metal film having solder wettability.

3. A semiconductor device as described in claim 1 or 2, wherein the height of the cutout portion on the side is less than or equal to the height of the first exposed surface.

4. A semiconductor device described in any one of claims 1 to 3, wherein the cutout portion is a step having a plane parallel to the bottom surface.

5. The reinforcing structure includes a fourth exposed surface on which a bottom surface of the reinforcing structure is exposed, The semiconductor device according to claim 1 , wherein the second exposed surface and the fourth exposed surface are covered with a metal film having solder wettability.

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