Power Conversion Equipment

Abstract

To suppress DC bias magnetism of an inductance element with a simple and low-cost configuration in a DAB type power conversion device.SOLUTION: By sampling an output signal of a current detector at a sampling period, detection values of a primary side AC current IL1 and a secondary side AC current IL2 are acquired. Using the detection values of the AC currents IL1, IL2, a DC component included in an AC current running through an inductance element is computed. On the basis of the computed DC component, a primary duty command value for controlling a primary bridge circuit and a secondary duty command value for controlling a secondary bridge circuit are formed. According to a phase difference command value, the primary duty command value and the secondary duty command value, switching operations of the primary bridge circuit and the secondary bridge circuit are controlled. The sampling period is set to be longer than the switching period of a semiconductor switching element in the switching operation.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] DC / DC converters capable of bidirectionally transferring DC power are widely used in solar power generation systems, power storage systems, etc. One type of bidirectional DC / DC converter is a DAB (Dual Active Bridge) DC / DC converter (see, for example, International Publication No. WO 2019 / 167271 (Patent Document 1)).

[0003] DAB DC / DC converters have a circuit configuration in which two full-bridge circuits are connected via inductance elements such as reactors or transformers. Due to the symmetry of this circuit configuration, DAB DC / DC converters have the advantage that the characteristics are equal in both directions for power transmission, making them suitable for high-power applications.

[0004] However, when the AC voltage applied to the inductance elements from each bridge circuit contains a DC component, a problem occurs in that DC bias magnetism occurs in the inductance elements, which may cause an overcurrent to flow and damage the DC / DC converter.

[0005] To solve such problems, in Patent Document 1, a controller that controls the operation of each bridge circuit is configured to sample the AC current flowing through the inductance element twice during one switching period in the switching operation of the two bridge circuits, and detect the DC component contained in the AC current based on the sampled value. In the above configuration, the controller changes the duty of the AC voltage applied to the inductance element so as to cancel out the detected DC component. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2019 / 167271 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the technology described in Patent Document 1, since the AC current is sampled twice during one switching period, a controller having a sampling period shorter than the switching period is required. Therefore, there is a concern that the switching period may be limited by the sampling period. In order to achieve a desired switching period, a high-speed sampling rate is required, and there is a concern that the controller will become complicated and expensive.

[0008] The present disclosure has been made to solve such problems, and has an object to suppress DC bias magnetism of inductance elements in a DAB type power conversion device with a simple and inexpensive configuration. [Means for solving the problem]

[0009] In one aspect of the present disclosure, a power converter includes a power converter that performs bidirectional DC / DC conversion between a primary side DC terminal and a secondary side DC terminal, and a control device that controls the operation of the power converter. The power converter includes a primary side bridge circuit, a secondary side bridge circuit, and an inductance element. The primary side bridge circuit includes a semiconductor switching element and performs bidirectional DC / AC power conversion between the primary side DC terminal and the primary side AC terminal. The secondary side bridge circuit includes a semiconductor switching element and performs bidirectional DC / AC power conversion between the secondary side DC terminal and the secondary side AC terminal. The inductance element is connected between the primary side AC terminal and the secondary side AC terminal. The power converter further includes a voltage detector that detects a primary side DC voltage of the primary side DC terminal and a secondary side DC voltage of the secondary side DC terminal, and a current detector that detects a primary side AC current flowing in the primary side AC terminal and a secondary side AC current flowing in the secondary side AC terminal. The control device includes a voltage control unit, a current detection unit, a DC component calculation unit, a current control unit, and a control signal generation unit. The voltage control unit generates a phase difference command value between the primary side AC voltage at the primary side AC terminal and the secondary side AC voltage at the secondary side AC terminal, using the detection value of the primary side DC voltage and the detection value of the secondary side DC voltage. The current detection unit obtains the detection value of the primary side AC current and the detection value of the secondary side AC current by sampling the output signal of the current detector at a preset sampling period. The DC component calculation unit calculates the DC component included in the AC current flowing through the inductance element, using the detection value of the primary side AC current and the detection value of the secondary side AC current. The current control unit generates a primary side duty command value for controlling the switching operation of the primary side bridge circuit and a secondary side duty command value for controlling the switching operation of the secondary side bridge circuit, based on the calculated DC component. The control signal generation unit generates a control signal for controlling the switching operation of the primary side bridge circuit and the secondary side bridge circuit, according to the generated phase difference command value, primary side duty command value, and secondary side duty command value. The sampling period is set to be longer than the switching period of the semiconductor switching element in the switching operation. Effect of the Invention

[0010] According to the present disclosure, in a DAB type power conversion device, it is possible to suppress DC bias magnetism of an inductance element with a simple and inexpensive configuration. [Brief description of the drawings]

[0011] [Figure 1] 1 is a main circuit configuration diagram of a power conversion device according to an embodiment; [Diagram 2] 11A and 11B are diagrams illustrating other configuration examples of the inductance element. [Diagram 3] 4 is an example of operational waveforms of a DC / DC converter. [Figure 4] 2 is a block diagram illustrating a control configuration of a control device for a power conversion device according to an embodiment. FIG. [Diagram 5] 5 is an operational waveform diagram of the gate signal generating unit shown in FIG. 4. [Figure 6] 5 is a block diagram showing an example of the configuration of a voltage control unit shown in FIG. 4. [Figure 7] 5 is a block diagram showing an example of the configuration of a DC component calculation unit shown in FIG. 4. [Figure 8] 5 is a block diagram showing an example of the configuration of a current control unit shown in FIG. 4. [Figure 9] 9 is a block diagram showing an example of the configuration of a passing current DC component comparison unit and an excitation current DC component comparison unit shown in FIG. 8. [Figure 10] 11 is an operational waveform diagram illustrating sampling timing of an AC current according to a comparative example. FIG. [Figure 11] 5 is an operational waveform diagram illustrating sampling timing of an AC current according to the present embodiment. FIG. [Figure 12] 11 is an operational waveform diagram showing a change over time in the DC component of the passing current when the load suddenly changes. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference characters, and the description thereof will not be repeated in principle.

[0013] Embodiment 1 FIG. 1 is a main circuit configuration diagram of a power conversion device 100 according to this embodiment.

[0014] 1, a power conversion device 100 according to this embodiment includes primary side DC terminals 102a and 102b, a DC / DC converter 102, secondary side DC terminals 102c and 102d, a control device 103, voltage detectors 119 and 120, and current detectors 121 and 122. The DC / DC converter 102 performs power conversion (DC / DC conversion) between a primary side DC voltage Vdc1 between the primary side DC terminals 102a and 102b and a secondary side DC voltage Vdc2 between the secondary side DC terminals 102c and 102d.

[0015] The DC / DC converter 102 is a DC / DC converter of a DAB configuration, and includes smoothing capacitors 104 and 118 , a primary-side bridge circuit 123 , a secondary-side bridge circuit 124 , and an inductance element 111 .

[0016] The primary side bridge circuit 123 forms a single-phase full bridge. Specifically, the primary side bridge circuit 123 has semiconductor switching elements SW1 to SW4 connected between a high potential side power supply wiring PL1 and a low potential side power supply wiring NL1. The power supply wiring PL1 and the power supply wiring NL1 are connected to primary side DC terminals 102a and 102b, respectively. A smoothing capacitor 104 for stabilizing a primary side DC voltage Vdc1 is connected between the power supply wiring PL1 and the power supply wiring NL1.

[0017] The semiconductor switching elements SW1 and SW2 are connected in series between the power supply wiring PL1 and the power supply wiring NL1 via a node N1a connected to the AC terminal 123a to form a first leg 107. Similarly, the semiconductor switching elements SW3 and SW4 are connected in series between the power supply wiring PL1 and the power supply wiring NL1 via a node N1b connected to the AC terminal 123b to form a second leg 110.

[0018] Similarly, the secondary bridge circuit 124 configures a single-phase full bridge. Specifically, the secondary bridge circuit 124 has semiconductor switching elements SW5 to SW8 connected between a high-potential side power supply wiring PL2 and a low-potential side power supply wiring NL2. The power supply wiring PL2 and the power supply wiring NL2 are connected to secondary side DC terminals 102c and 102d, respectively. A smoothing capacitor 118 for stabilizing the secondary side DC voltage Vdc2 is connected between the power supply wiring PL2 and the power supply wiring NL2.

[0019] The semiconductor switching elements SW5 and SW6 are connected in series between the power supply wiring PL2 and the power supply wiring NL2 via a node N2a connected to the AC terminal 124a to form a third leg 114. Similarly, the semiconductor switching elements SW7 and SW8 are connected in series between the power supply wiring PL2 and the power supply wiring NL2 via a node N2b connected to the AC terminal 124b to form a fourth leg 117. In the first to fourth legs 107, 110, 114, and 117, the semiconductor switching elements SW1, SW3, SW5, and SW7 form an "upper arm," and the semiconductor switching elements SW2, SW4, SW6, and SW8 form a "lower arm." Hereinafter, the semiconductor switching elements SW1 to SW8 are collectively referred to as semiconductor switching elements SW.

[0020] The semiconductor switching element SW has a self-extinguishing switching element and a diode. The switching element can be configured by any self-extinguishing element such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a GCT (Gate Commutated Turn-off) thyristor. The diode is connected in inverse parallel to the switching element to configure a free wheeling diode (FWD).

[0021] The inductance element 111 has primary side AC terminals 111a and 111b connected to the AC terminals 123a and 123b, respectively, of the primary side bridge circuit 123, and secondary side AC terminals 111c and 111d connected to the AC terminals 124a and 124b, respectively, of the secondary side bridge circuit 124. In the example of Fig. 1, the inductance element 111 is configured by a transformer 11 having a primary winding 11a connected between the primary side AC terminals 111a and 111b, and a secondary winding 11b connected between the secondary side AC terminals 111c and 111d.

[0022] Fig. 2 shows another example of the configuration of the inductance element 111. As shown in Fig. 2, the inductance element 111 can be configured by a reactor 11c connected between the primary side AC terminal 111a and the secondary side AC terminal 111c, and a reactor 11d connected between the primary side AC terminal 111b and the secondary side AC terminal 111d. Alternatively, the inductance element 111 can be configured by only one of the reactors 11c and 11d.

[0023] 1, the voltage detector 119 detects the terminal voltage of the smoothing capacitor 104, i.e., the primary side DC voltage Vdc1, and outputs a signal indicating the detected value to the control device 103. The voltage detector 120 detects the terminal voltage of the smoothing capacitor 118, i.e., the secondary side DC voltage Vdc2, and outputs a signal indicating the detected value to the control device 103.

[0024] The current detector 121 detects an AC current IL1 (hereinafter also referred to as the “primary side AC current”) flowing between the AC terminal 123a of the primary side bridge circuit 123 and the primary side AC terminal 111a of the inductance element 111, and outputs a signal indicating the detected value to the control device 103.

[0025] The current detector 122 detects an AC current IL2 (hereinafter also referred to as the “secondary side AC current”) flowing between the AC terminal 124a of the secondary side bridge circuit 124 and the secondary side AC terminal 111c of the inductance element 111, and outputs a signal indicating the detected value to the control device 103.

[0026] In the following description, the direction of the primary side AC current IL1 flowing from the primary side bridge circuit 123 to the inductance element 111 is regarded as the positive direction. Also, the direction of the secondary side AC current IL2 flowing from the secondary side bridge circuit 124 to the inductance element 111 is regarded as the positive direction.

[0027] The control device 103 controls the power conversion in the DC / DC converter 102. Specifically, the control device 103 generates control signals (gate signals) GP1 to GP8 for controlling the on / off of the semiconductor switching elements SW1 to SW8 based on a command from a higher-level controller (not shown) and output signals from voltage detectors 119 and 120 and current detectors 121 and 122.

[0028] For example, the control device 103 can be configured by a microprocessor including a CPU (Central Processing Unit) 103a, a memory 103b, and an input / output (I / O) circuit 103c. The input / output circuit 103a receives detection values ​​from sensors disposed in the DC / DC converter 102, and outputs control signals to the components of the DC / DC converter 102. The control signals include the above-mentioned gate signals GP1 to GP8.

[0029] The control device 103 can realize the control functions described below by software processing in which the CPU 103a executes arithmetic processing according to a program stored in the memory 103b. Alternatively, the control device 103 can realize some or all of the control functions by hardware processing using dedicated electronic circuits.

[0030] The DC / DC converter 102 converts DC power input from the primary side DC terminal 102a into AC power (single-phase AC power in the example of FIG. 1) by the primary side bridge circuit 123, and the AC power is transmitted to the secondary side bridge circuit 124 via the inductance element 111. The secondary side bridge circuit 124 converts the AC power back into DC power and transmits it to the secondary side DC terminals 102c, 102d. In this case, power is transmitted from the primary side DC terminals 102a, 102b to the secondary side DC terminals 102c, 102d.

[0031] Alternatively, the DC / DC converter 102 can transmit power from the secondary side DC terminals 102c, 102d to the primary side DC terminals 102a, 102b due to the symmetry of the circuit. In this case, the DC power input to the secondary side DC terminal 102c is converted to AC power (single-phase AC power in the example of FIG. 1) by the secondary side bridge circuit 124, and the AC power is transmitted to the primary side bridge circuit 123 via the inductance element 111. The primary side bridge circuit 123 converts the AC power back to DC power and transmits it to the primary side DC terminals 102a, 102b. In this way, the power conversion device 100 can perform DC voltage conversion between the primary side and the secondary side, and can control the power transmission direction to either power transmission from the primary side to the secondary side or power transmission from the secondary side to the primary side.

[0032] Next, the operation of the power conversion device 100 according to the first embodiment will be described. Fig. 3 shows an example of operational waveforms of the DC / DC converter 102. Fig. 3 shows the operation when a transformer 11 is applied as the inductance element 111. The horizontal axis of Fig. 3 shows the switching phase when the switching period Tsw of each semiconductor switching element SW is 360 deg.

[0033] 3, in the primary-side bridge circuit 123, the semiconductor switching elements SW1 and SW2 constituting the same leg are turned on and off in a complementary manner, and similarly the semiconductor switching elements SW3 and SW4 are turned on and off in a complementary manner. Furthermore, the semiconductor switching elements SW1 and SW4 are turned on and off in the same phase, and the semiconductor switching elements SW2 and SW3 are turned on and off in the same phase. As a result, the semiconductor switching elements SW1 to SW4 are switched on and off every 1 / 2 (π) of the switching period Tsw.

[0034] Similarly, in the secondary-side bridge circuit 124, the semiconductor switching elements SW5 and SW6 constituting the same leg are turned on and off in a complementary manner, and similarly the semiconductor switching elements SW7 and SW8 are turned on and off in a complementary manner. Furthermore, the semiconductor switching elements SW5 and SW8 are turned on and off in the same phase, and the semiconductor switching elements SW6 and SW7 are turned on and off in the same phase. As a result, the semiconductor switching elements SW5 to SW8 are switched on and off every 1 / 2 (π) of the switching period Tsw.

[0035] A phase difference δ (0≦δ≦π) is provided between the timing at which the semiconductor switching elements SW1 to SW4 in the primary bridge circuit 123 are switched on and off and the timing at which the semiconductor switching elements SW5 to SW8 in the secondary bridge circuit 124 are switched on and off.

[0036] By such on / off control of the semiconductor switching elements SW1 to SW8 in the primary bridge circuit 123 and the secondary bridge circuit 124, an AC voltage Vtrpri (hereinafter also referred to as "primary AC voltage") is generated between the primary AC terminals 111a and 111b (both ends of the primary winding 11a) of the inductance element 111, and an AC voltage Vtrsec (hereinafter also referred to as "secondary AC voltage") is generated between the secondary AC terminals 111c and 111d (both ends of the secondary winding 11b) of the inductance element 111. Also, a secondary AC current IL2 flows through the secondary winding 11b, and a primary AC current IL1 flows through the primary winding 11a (IL1=-IL2).

[0037] Each of the primary side AC voltage Vtrpri and the secondary side AC voltage Vtrsec is a square wave voltage having a voltage pulse width θ according to the on-period length of the semiconductor switching elements SW1 to SW8 (0≦θ≦π). In this specification, the ratio of the on-period length of the semiconductor switching element SW to the switching cycle Tsw is defined as "duty". Furthermore, the duty of the semiconductor switching elements SW1 to SW4 in the primary side bridge circuit 123 is defined as "primary side duty Dpri", and the duty of the semiconductor switching elements SW5 to SW8 in the secondary side bridge circuit 124 is defined as "secondary side duty Dsec".

[0038] In addition, a phase difference δ occurs between the primary side AC voltage Vtrpri and the secondary side AC voltage Vtrsec. Since the AC currents IL1 and IL2 change according to this phase difference δ, the power transmitted between the primary side and the secondary side also changes. Therefore, by providing a phase difference δ set according to a power command value, the transmission power between the primary side and the secondary side can be controlled according to the power command value.

[0039] For example, the transmission power P is expressed by the following equation (1) using the switching frequency fsw of the semiconductor switching element SW, the inductance component L of the transformer 11, and the phase difference δ. P = Vdc1 Vdc2 / (2π 2 ×fsw×L)·δ·(π-δ) …(1) When equation (1) is solved for the phase difference δ, it is transformed into the following equation (2). δ=(π / 2)±(π / 2)·√(1-(8L·fsw·P) / (Vdc1·Vdc2)) …(2) Since δ≦π / 2, a phase difference command value δref, which is a command value for the phase difference δ, can be calculated from the power command value Pref according to the following equation (3). δref=(π / 2)-(π / 2)·√(1-(8L·fsw·Pref) / (Vdc1·Vdc2)) …(3) As shown in Fig. 3, when the duty Dpri, Dsec = 0.5, the primary side AC voltage Vtrpri and the secondary side AC voltage Vtrsec each have a voltage pulse width θ = 180 deg and are a square wave voltage with symmetrical positive and negative. On the other hand, when the duty Dpri, Dsec deviates from 0.5, the primary side AC voltage Vtrpri and the secondary side AC voltage Vtrsec each have an imbalance between the positive potential period and the negative potential period, and therefore are an asymmetrical square wave voltage with positive and negative. This asymmetrical square wave voltage contains a DC component.

[0040] Even if each of the gate signals GP1 to GP8 has a pulse width of 180 deg, the duty may deviate from 0.5 due to variations in switching characteristics between the semiconductor switching elements SW, or variations in turn-on and turn-off between semiconductor switching elements that are turned on and off in the same phase. Even in this case, the above-mentioned DC component is generated in the AC voltages Vtrpri and Vtrsec.

[0041] When the AC voltages Vtrpri and Vtrsec containing a DC component are applied to the inductance element 111, a DC bias magnetism may occur in the inductance element 111. When a DC bias magnetism occurs in the inductance element 111, the inductance element 111 becomes magnetically saturated, causing a sudden increase in current, which may result in damage to the DC / DC converter 102. Therefore, control is required to suppress the occurrence of a DC component for each of the primary side AC voltage Vtrpri and the secondary side AC voltage Vtrsec.

[0042] Next, the power conversion control by the control device 103 will be described. Fig. 4 is a block diagram for explaining a control configuration by the control device 103 of the power conversion device 100 according to the embodiment. The functions of each block in each block diagram including Fig. 4 described below are realized by at least one of software processing and hardware processing by the control device 103.

[0043] As shown in FIG. 4, the control device 103 includes a voltage detection unit 301, a voltage control unit 302, a current detection unit 303, a DC component calculation unit 304, and a current control unit 305.

[0044] The voltage detection unit 301 receives output signals from the voltage detectors 119, 120 (FIG. 1). The voltage detection unit 301 samples the detection value of the primary side DC voltage Vdc1 by the voltage detector 119 at a predetermined sampling period Tsa, and outputs a primary side DC voltage detection value Vdc1_det based on the sampled value. The voltage detection unit 301 samples the detection value of the secondary side DC voltage Vdc2 by the voltage detector 120 at a sampling period Tsa, and outputs a secondary side DC voltage detection value Vdc2_det based on the sampled value.

[0045] The voltage control unit 302 generates a command value for a phase difference δ (phase difference command value δref) between the primary side bridge circuit 123 and the secondary side bridge circuit 124, based on the primary side DC voltage detection value Vdc1_det and the secondary side DC voltage detection value Vdc2_det provided by the voltage detection unit 301. A method for generating the phase difference command value δref will be described later. The voltage control unit 302 provides the generated phase difference command value δref to the gate signal generation unit 306.

[0046] The current detection unit 303 receives output signals from the current detectors 121 and 122 (FIG. 1). The current detection unit 303 samples the detection value of the AC current IL1 by the current detector 121 at a sampling period Tsa, and outputs an AC current detection value IL1_det based on the sampled value. The current detection unit 303 samples the detection value of the AC current IL2 by the current detector 122 at a sampling period Tsa, and outputs an AC current detection value IL2_det based on the sampled value.

[0047] The DC component calculation unit 304 calculates a DC component (hereinafter also referred to as "passing current DC component") Idcp included in the passing current transmitted from the primary side bridge circuit 123 to the secondary side bridge circuit 124, based on the AC current detection values ​​IL1_det and IL2_det provided by the current detection unit 303. The DC component calculation unit 304 calculates a DC component (hereinafter also referred to as "excitation current DC component") Idce included in the excitation current of the transformer 11 that constitutes the inductance element 111, based on the AC current detection values ​​IL1_det and IL2_det. A method of calculating the passing current DC component Idcp and the excitation current DC component Idce will be described later.

[0048] The current control unit 305 executes a control calculation so that the passing current DC component Idcp and the excitation current DC component Idce calculated by the DC component calculation unit 304 become 0, thereby generating a primary side duty command value Drefpri which is a target value of the primary side duty Dpri, and a secondary side duty command value Drefsec which is a target value of the secondary side duty Dsec. The current control unit 305 provides the generated primary side duty command value Drefpri and secondary side duty command value Drefsec to the gate signal generation unit 306.

[0049] The gate signal generating unit 306 generates gate signals GP1 to GP8 for controlling the on / off of the semiconductor switching elements SW1 to SW8 in accordance with the phase difference command value Δref, the primary side duty command value Drefpri, and the secondary side duty command value Drefsec. The gate signals GP1 to GP8 are input to gate drivers (not shown) of the corresponding semiconductor switching elements SW to control the on / off of the semiconductor switching elements SW1 to SW8.

[0050] When the inductance element 111 is the reactors 11c and 11d (see FIG. 2), it is not necessary to calculate the DC component of the excitation current Idce and to perform control for suppressing the DC component of the excitation current, which will be described later.

[0051] Fig. 5 is an operation waveform diagram of the gate signal generating unit 306 shown in Fig. 4. Fig. 5 shows waveforms of the primary duty command value Drefpri and the secondary duty command value Defsec input to the gate signal generating unit 306, and waveforms of the gate signals GP1 to GP8 generated by the gate signal generating unit 306.

[0052] The gate signal generating unit 306 generates gate signals GP1 to GP4 by comparing the primary duty command value Drefpri and the primary carrier carpri. The gate signal generating unit 306 generates gate signals GP5 to GP8 by comparing the secondary duty command value Drefsec and the secondary carrier carsec.

[0053] The primary carrier carpri and the secondary carrier carsec are generated based on a reference carrier carbase having a predetermined frequency. The reference carrier carbase is, for example, a triangular wave. The reference carrier carbase may also be a sawtooth wave.

[0054] The primary carrier carbase leads the reference carrier carbase in phase by 1 / 2 the phase difference command value δref. The secondary carrier carse lagging the reference carrier carbase in phase by 1 / 2 the phase difference command value δref. In other words, the primary carrier carpri and the secondary carrier carse have a phase difference equal to the phase difference command value δref.

[0055] When the primary duty command value Drefpri is greater than the primary carrier carbase, the gate signal generating unit 306 sets the gate signals GP1 and GP4 to H (logical high) level and the gate signals GP2 and GP3 to L (logical low) level. When the primary duty command value Drefpri is smaller than the primary carrier carpi, the gate signal generating unit 306 sets the gate signals GP1 and GP4 to L level and the gate signals GP2 and GP3 to H level.

[0056] When the secondary duty command value Drefsec is greater than the secondary carrier carsec, the gate signal generating unit 306 sets the gate signals GP5 and GP8 to H level and the gate signals GP6 and GP7 to L level. When the secondary duty command value Drefsec is smaller than the secondary carrier carsec, the gate signal generating unit 306 sets the gate signals GP5 and GP8 to L level and the gate signals GP6 and GP7 to H level.

[0057] In actual operation, it is necessary to provide a dead time for the gate signals GP1 to GP8 to prevent shorting of the legs, but this will be ignored here since its effect on operation is sufficiently small.

[0058] When the duty command values ​​Drefpri and Drefsec are 0.5, the gate signals GP1 to GP8 have a pulse width of 180 deg. In this case, as shown in FIG. 3, each of the AC voltages Vtrpri and Vtrsec is a square wave voltage with symmetrical positive and negative polarities, and is an AC voltage that does not include a DC component.

[0059] On the other hand, when the duty command values ​​Drefpri and Drefsec deviate from 0.5, the pulse widths of the gate signals GP1 to GP8 deviate from 180 deg. In the example of Fig. 5, since the primary duty command value Drefpri is greater than 0.5, the pulse widths of the gate signals GP1 and GP4 are greater than 180 deg, while the pulse widths of the gate signals GP2 and GP3 are smaller than 180 deg. Since the secondary duty command value Drefsec is smaller than 0.5, the pulse widths of the gate signals GP5 and GP8 are smaller than 180 deg, while the pulse widths of the gate signals GP6 and GP7 are greater than 180 deg.

[0060] In the above case, each of the AC voltages Vtrpri and Vtrsec is a square wave voltage with an asymmetric positive and negative polarity, and is an AC voltage containing a DC component. As described above, when an AC voltage containing a DC component is applied to the inductance element 111, an AC current containing a DC component flows in the inductance element 111, which may result in DC bias magnetism of the inductance element 111.

[0061] Therefore, in this embodiment, the DC component calculation unit 304 calculates the passing current DC component Idcp and the excitation current DC component Idce, and the current control unit 305 changes the primary side duty command value Drefpri and the secondary side duty command value Drefsec from 0.5 so as to cancel the calculated passing current DC component Idcp and excitation current DC component Idce. This makes it possible to remove the DC component contained in the AC current flowing through the inductance element 111, thereby making it possible to suppress DC bias magnetism of the inductance element 111.

[0062] Fig. 6 is a block diagram showing a configuration example of the voltage control unit 302 shown in Fig. 4. Fig. 6 shows a configuration example in which the primary side DC voltage Vdc1 is held at a constant value and the secondary side DC voltage Vdc2 is controlled to follow the secondary side DC voltage command value Vdc2_ref.

[0063] As shown in FIG. 6, the voltage control unit 302 includes a subtractor 501 and a phase difference command value generating unit 502.

[0064] A secondary side DC voltage detection value Vdc2_det based on a sampling value in the voltage detection unit 301 and a secondary side DC voltage command value Vdc2_ref are input to the subtractor 501. The subtractor 501 calculates a deviation (Vdc2_ref-Vdc2_det) of the secondary side DC voltage detection value Vdc2_det from the secondary side DC voltage command value Vdc2_ref, and outputs the calculated deviation to a phase difference command value generation unit 502.

[0065] The phase difference command value generating unit 502 generates a phase difference command value δref by executing a control calculation (for example, a proportional-integral control calculation) for making the deviation 0. The generated phase difference command value δref is provided to the gate signal generating unit 306.

[0066] Although not shown, when controlling the primary side DC voltage Vdc1 to follow the primary side DC voltage command value Vdc1_ref, a primary side DC voltage detection value Vdc1_det based on a sampled value in the voltage detection unit 301 and the primary side DC voltage command value Vdc1_ref are input to the subtractor 501. The subtractor 501 calculates a deviation (Vdc1_ref-Vdc1_det) of the primary side DC voltage detection value Vdc1_det from the primary side DC voltage command value Vdc1_ref, and outputs the calculated deviation to the phase difference command value generation unit 502.

[0067] FIG. 7 is a block diagram showing an example of the configuration of the DC component calculation unit 304 shown in FIG. As shown in FIG. 7, DC component calculation section 304 includes a subtractor 601, adders 603, 605, and 606, and multipliers 602, 604, and 607.

[0068] The subtractor 601 receives an AC current detection value IL1_det and an AC current detection value IL2_det based on sampled values ​​in the current detection unit 303. The subtractor 601 subtracts the AC current detection value IL2_det from the AC current detection value IL1_det, and outputs the subtracted value (IL1_det-IL2_det) to the multiplier 602.

[0069] The multiplier 602 multiplies the output of the subtractor 601 by a coefficient 0.5. The multiplied value (IL1_det-IL2_det)×0.5 by the multiplier 602 corresponds to the passing current Ip transmitted from the primary side bridge circuit 123 to the secondary side bridge circuit 124. Note that the passing current Ip_n represents the passing current Ip calculated from the AC current detection values ​​IL1_det, IL2_det based on the sampling values ​​at the current sampling timing in the current detection unit 303.

[0070] The passing current Ip_n at the current sampling timing is input to the adder 603. The passing current Ip_d at the previous sampling timing is also input to the adder 603. This passing current Ip_d represents the passing current Ip calculated from the AC currents IL1_det and IL2_det based on the sampled values ​​at the previous sampling timing in the current detection unit 303.

[0071] The adder 603 adds the passing current Ip_n at the current sampling timing and the passing current Ip_d at the previous sampling timing, and outputs the sum (Ip_n+Ip_d) to the multiplier 604 .

[0072] The multiplier 604 multiplies the output of the adder 603 by a coefficient 0.5. That is, the multiplier 604 calculates the average value of the passing current Ip_n at the current sampling timing and the passing current Ip_d at the previous sampling timing. The calculated average value (Ip_n+Ip_d)×0.5 corresponds to the DC component (passing current DC component) Idcp of the passing current transmitted from the primary side bridge circuit 123 to the secondary side bridge circuit 124. That is, the passing current DC component Idcp is calculated according to the following equation (4). Idcp = (Ip_n + Ip_d) × 0.5 … (4) The adder 605 receives the AC current detection value IL1_det and the AC current detection value IL2_det based on the sampling values ​​in the current detection unit 303. The adder 605 adds the AC current detection value IL1_det and the AC current detection value IL2_det, and outputs the sum (IL1_det+IL2_det) to the adder 606. The sum (IL1_det+IL2_det) by the adder 605 corresponds to the excitation current Ie of the transformer 11 that constitutes the inductance element 111. Note that the excitation current Ie_n represents the excitation current Ie calculated from the AC current detection values ​​IL1_det, IL2_det based on the sampling values ​​at the current sampling timing in the current detection unit 303.

[0073] The adder 606 adds the excitation current Ie_n at the current sampling timing and the excitation current Ie_d at the previous sampling timing, and outputs the sum (Ie_n+Ie_d) to the multiplier 607 .

[0074] Multiplier 607 multiplies the output of adder 606 by a coefficient of 0.5. That is, multiplier 606 calculates the average value of excitation current Ie_n at the current sampling timing and excitation current Ie_d at the previous sampling timing. The calculated average value (Ie_n+Ie_d)×0.5 corresponds to the DC component of the excitation current of transformer 11 (excitation current DC component) Idce. That is, excitation current DC component Idce is calculated according to the following equation (5). Idce = (Ie_n + Ie_d) × 0.5 … (5) FIG. 8 is a block diagram showing an example of the configuration of the current control unit 305 shown in FIG.

[0075] As shown in FIG. 8, the current control unit 305 includes a passing current DC component comparison unit 701, an excitation current DC component comparison unit 706, a passing current DC component suppression duty command value generation unit 703, an excitation current DC component suppression duty command value generation unit 708, subtractors 702, 707, 709, and adders 704, 705, 710.

[0076] The passing current DC component comparator 701 compares the passing current DC component Idcp input from the DC component calculator 304 with a predetermined threshold, and generates the passing current DC component Idcp_th used for suppression control of the passing current DC component based on the comparison result.

[0077] The DC component of the excitation current comparison unit 706 compares the DC component of the excitation current Idce input from the DC component calculation unit 304 with a predetermined threshold value, and generates the DC component of the excitation current Idce_th used for suppression control of the DC component of the excitation current based on the comparison result.

[0078] FIG. 9 is a block diagram showing an example of the configuration of passing current DC component comparing section 701 and exciting current DC component comparing section 706 shown in FIG.

[0079] As shown in FIG. 9, the passing current DC component comparing section 701 includes comparators 801 and 802, a negative AND (NAND) circuit 803, and a multiplier 804.

[0080] The comparator 801 compares the passing current DC component Idcp with a threshold value (upper limit maxdcp) and outputs the comparison result. If maxdcp>Idcp, the comparator 801 outputs a signal with a value of "1", and otherwise (i.e., maxdcp≦Idcp), the comparator 801 outputs a signal with a value of "0".

[0081] The comparator 802 compares the passing current DC component Idcp with a threshold value (lower limit mindcp) and outputs the comparison result. If Idcp>mindcp, the comparator 802 outputs a signal with a logical value of "1", and otherwise (i.e., Idcp≦mindcp), the comparator 802 outputs a signal with a logical value of "0".

[0082] The NAND circuit 803 calculates the negative logical product of the output signal of the comparator 801 and the output signal of the comparator 802. When maxdcp ≦ Idcp or Idcp ≦ mindcp, the NAND circuit 803 outputs a signal with a logical value of "1". When mindcp < Idcp < maxdcp, the NAND circuit 803 outputs a signal with a logical value of "0".

[0083] The multiplier 804 generates the DC component of the passing current Idcp_th by multiplying the DC component of the passing current Idcp and the output of the NAND circuit 803. When the output of the NAND circuit 803 has a logical value of "1", Idcp_th = Idcp, and when the output of the NAND circuit 803 has a logical value of "0", Idcp_th = 0.

[0084] The DC component comparison unit 706 of the exciting current includes the comparators 805, 806, the NAND circuit 807, and the multiplier 808.

[0085] The comparator 805 compares the DC component of the exciting current Idce with the threshold value (upper limit value maxdce) and outputs the comparison result. When maxdce > Idce, the comparator 805 outputs a signal with a value of "1", and in other cases (i.e., maxdce ≦ Idce), the comparator 805 outputs a signal with a value of "0".

[0086] The comparator 806 compares the DC component of the exciting current Idce with the threshold value (lower limit value mindce) and outputs the comparison result. When Idce > mindce, the comparator 806 outputs a signal with a logical value of "1", and in other cases (i.e., Idce ≦ mindce), the comparator 806 outputs a signal with a logical value of "0".

[0087] The NAND circuit 807 calculates the negative logical product of the output signal of the comparator 805 and the output signal of the comparator 806. When maxdce ≦ Idce or Idce ≦ mindce, the NAND circuit 807 outputs a signal with a logical value of "1". When mindce < Idce < maxdce, the NAND circuit 807 outputs a signal with a logical value of "0".

[0088] A multiplier 808 generates a DC component of the excitation current Idce_th by multiplying the DC component of the excitation current Idce by the output of the NAND circuit 807. When the output of the NAND circuit 807 is a logical value "1", Idce_th=Idce, and when the output of the NAND circuit 807 is a logical value "0", Idce_th=0.

[0089] In the configuration example of Fig. 9, each of the passing current DC component comparison unit 701 and the excitation current DC component comparison unit 706 constitutes a dead band circuit. Specifically, when the passing current DC component Idcp is within an allowable range having an upper limit value maxdcp and a lower limit value mindcp, the passing current DC component comparison unit 701 regards the passing current DC component Idcp_th=0 (i.e., the passing current DC component Idcp is not included). On the other hand, when the passing current DC component Idcp is out of the allowable range, the passing current DC component comparison unit 701 regards the passing current DC component Idcp_th=Idcp (i.e., the passing current DC component Idcp is included).

[0090] Similarly, when the excitation current DC component Idce is within an allowable range having an upper limit maxdce and a lower limit mindce, the excitation current DC component comparison unit 706 regards the excitation current DC component Idce_th as 0 (i.e., the excitation current DC component Idce is not included). On the other hand, when the excitation current DC component Idce is outside the allowable range, the excitation current DC component comparison unit 706 regards the excitation current DC component Idce_th as Idce (i.e., the excitation current DC component Idce is included).

[0091] Returning to Figure 8, subtractor 702 calculates the deviation ΔIdcp_th (ΔIdcp_th = -Idcp_th) of the passing current DC component Idcp_th from the target value "0" of the passing current DC component Idcp, and outputs the deviation ΔIdcp_th to a duty command value generating unit 703 for suppressing the passing current DC component (hereinafter simply referred to as the "duty command value generating unit 703").

[0092] The duty command value generating unit 703 generates a duty command value Drefdcp by executing a control calculation (for example, a proportional-integral calculation) for making the deviation ΔIdcp_th 0. The duty command value Drefdcp is a duty command value for suppressing the passing current DC component Idcp, and is also referred to as a "passing current duty command value" in the following description.

[0093] The subtractor 707 calculates the deviation ΔIdce_th (ΔIdce_th=-Idce_th) of the excitation current DC component Idce_th relative to the target value "0" of the excitation current DC component Idce, and outputs the deviation ΔIdce_th to a duty command value generating unit 708 for suppressing the excitation current DC component (hereinafter simply referred to as the "duty command value generating unit 708").

[0094] The duty command value generating unit 708 generates a duty command value Drefdce by executing a control calculation (for example, a proportional-integral calculation) for making the deviation ΔIdce_th 0. The duty command value Drefdce is a duty command value for suppressing the excitation current DC component Idce, and is also referred to as an "excitation current duty command value" in the following description.

[0095] The adder 704 adds the passing current duty command value Drefdcp and the excitation current duty command value Drefdce, and outputs the sum (Drefdcp+Drefdce) to the adder 705.

[0096] The adder 705 generates a primary duty command value Drefpri by adding an additional value (Drefdcp+Drefdce) to the reference value "0.5" of the primary duty Dpri. The primary duty command value Drefpri is calculated according to the following equation (6). Drefpri=0.5+Drefdcp+Drefdce …(6) The subtractor 709 subtracts the passing current duty command value Drefdcp from the excitation current duty command value Drefdce, and outputs the subtracted value (Drefdce−Drefdcp) to the adder 710.

[0097] The adder 710 generates a secondary duty command value Drefsec by adding the subtraction value (Drefdce-Drefpri) to the reference value "0.5" of the secondary duty Dsec. The secondary duty command value Drefsec is calculated according to the following equation (7). Drefsec=0.5+Drefdce-Drefdcp …(7) As described above, the primary side duty command value Drefpri and the secondary side duty command value Drefsec are generated using the passing current duty command value Drefdcp and the excitation current duty command value Drefdce for making the passing current DC component Idcp and the excitation current DC component Idce zero, respectively. By controlling the power conversion in the primary side bridge circuit 123 and the secondary side bridge circuit 124 according to the generated duty command values ​​Drefpri and Drefsec, it is possible to remove the DC components contained in each of the primary side AC voltage Vtrpri and the secondary side AC voltage Vtrsec. As a result, it is possible to suppress the occurrence of DC bias magnetism in the inductance element 111 (transformer 11).

[0098] As described above, the passing current DC component comparator 701 and the excitation current DC component comparator 706 form a dead band circuit, so that when the passing current DC component Idcp is within the allowable range, the passing current duty command value Drefdcp is set to 0, and when the excitation current DC component Idce is within the allowable range, the excitation current duty command value Drefdce is set to 0. According to the equations (6) and (7), the duty command values ​​Drefpri and Drefsec are set to the reference value of 0.5.

[0099] In this configuration in which the duty command values ​​Drefpri, Drefsec are changed according to the passing current DC component Idcp and the excitation current DC component Idce, the duty command values ​​Drefpri, Drefsec are updated even for small DC components that occur due to a deviation in the sampling timing in the current detection unit 303 or the influence of current ripple, which may result in the current ripple increasing.

[0100] This can be achieved by appropriately setting the upper and lower limit values ​​of the allowable range in the above-mentioned dead band circuit (passing current DC component comparison unit 701 and excitation current DC component comparison unit 706), so that the duty command values ​​Drefpri and Drefsec are not changed unnecessarily when the DC component is small. The method of setting the upper and lower limit values ​​of the allowable range will be described in detail in the second to fourth embodiments described later.

[0101] Here, as described above, in order to generate the duty command values ​​Drefpri and Drefsec, it is necessary to detect the DC components Idcp and Idce of the passing current and excitation current flowing through the transformer 11 constituting the inductance element 111. As shown in Fig. 3, the DC component calculation unit 304 is configured to calculate the passing current DC component Idcp and the excitation current DC component Idce based on the AC current detection value IL1_det and the AC current detection value IL2_det based on the sampled values ​​in the current detection unit 303. Therefore, the method of sampling the AC currents IL1 and IL2 in the current detection unit 303 is important.

[0102] The following describes the sampling timing of the AC currents IL1 and IL2 in the current detection unit 303. First, the sampling timing of the AC currents IL1 and IL2 as a comparative example of this embodiment will be described with reference to FIG.

[0103] Fig. 10 is an operational waveform diagram for explaining sampling timings of AC currents IL1 and IL2 according to the comparative example. Fig. 10 shows waveforms of a primary side DC voltage Vdc1, a secondary side DC voltage Vdc2, a primary side AC voltage Vtrpri, a secondary side AC voltage Vtrsec, a primary side AC current IL1, and a secondary side AC current IL2. Fig. 10 further shows waveforms of a primary side DC voltage detection value Vdc1_det and a secondary side DC voltage detection value Vdc2_det based on the sampled values ​​in the voltage detection unit 301, and AC voltage detection values ​​IL1_det and IL2_det based on the sampled values ​​in the current detection unit 303.

[0104] In the following, for convenience of explanation, when the phase difference command value δref=0 and the duty Dpri,Dsec=0.5, the timing at which the primary side AC voltage Vtrpri and the secondary side AC voltage Vtrsec rise is defined as a switching phase "θ0 (reference phase)". Also, the timing at which the AC voltages Vtrpri, Vtrsec fall is defined as "θ0+180deg". Furthermore, the period from θ0 to θ0+360deg (i.e., the next θ0) is defined as a "switching period Tsw".

[0105] In the control device 103, when the phase difference command value δref is given, the gate signal generating unit 306 shifts the phase of the primary side AC voltage Vtrpri by −δref / 2 with respect to θ0 (reference phase). Also, the gate signal generating unit 306 shifts the phase of the secondary side AC voltage Vtrsec by +δref / 2 with respect to θ0. Therefore, in the primary side bridge circuit 123, a switching operation is performed at a timing when the switching phase is θ0−δ / 2, and in the secondary side bridge circuit 124, a switching operation is performed at a timing when the switching phase is θ0+δ / 2.

[0106] In the comparative example, the voltage detection unit 301 samples the DC voltages Vdc1 and Vdc2 when the switching phase is θ0+90deg and θ0+270deg. The current detection unit 303 samples the AC currents IL1_det and IL2_det when the switching phase is θ0+90deg and θ0+270deg. As a result, as shown in Fig. 10, the AC currents IL1_det and IL2_det are sampled during the period when they are positive and the period when they are negative.

[0107] The DC voltages Vdc1 and Vdc2 are DC voltages and are smoothed by the smoothing capacitors 104 and 118, respectively, and are therefore less affected by the sampling timing. On the other hand, for the AC currents IL1 and IL2, sampling at the above timings makes it possible to detect the points where the positive and negative symmetries are formed, and it becomes possible to easily calculate the DC component using the detected values.

[0108] However, in the sampling method according to the comparative example, sampling is required twice during one switching period Tsw, so the sampling period Tsa is 1 / 2 the switching period Tsw, which is shorter than the switching period Tsw. As a result, depending on the controller constituting the control device 103, the switching period Tsw may be limited by the sampling period Tsa. In order to achieve a desired switching period, a high-speed sampling rate is required, and there is a concern that the controller may become complicated and expensive.

[0109] FIG. 11 is an operational waveform diagram illustrating the sampling timing of AC currents IL1 and IL2 according to this embodiment, and is to be compared with FIG.

[0110] 11 shows waveforms of the primary side DC voltage Vdc1, the secondary side DC voltage Vdc2, the primary side AC voltage Vtrpri, the secondary side AC voltage Vtrsec, the primary side AC current IL1, and the secondary side AC current IL2, as in Fig. 10. Fig. 11 further shows waveforms of the primary side DC voltage detection value Vdc1_det and the secondary side DC voltage detection value Vdc2_det based on the sampled values ​​in the voltage detection unit 301, and the AC voltage detection values ​​IL1_det and IL2_det based on the sampled values ​​in the current detection unit 303.

[0111] In this embodiment, the voltage detection unit 301 samples the DC voltages Vdc1 and Vdc2 when the switching phase is θ0+90deg in one switching period Tsw and when it is θ0+270deg in the next switching period Tsw. The current detection unit 303 samples the AC currents IL1 and IL2 when the switching phase is θ0+90deg in one switching period Tsw and when it is θ0+270deg in the next switching period Tsw.

[0112] According to this, the sampling period Tsa is 3 / 2 times the switching period Tsw, and is longer than the switching period Tsw. Also in this embodiment, the AC currents IL1 and IL2 are sampled in the positive and negative periods, respectively, as in the comparative example. Therefore, as in the comparative example, it is possible to detect the points where the positive and negative are symmetrical, and it is therefore possible to easily calculate the DC component using the detection values ​​IL1_det and IL2_det.

[0113] In this way, in the sampling method according to the present embodiment, the sampling period Tsa is longer than the switching period Tsw, so that the switching period Tsw is not limited by the sampling period Tsa as in the comparative example. As a result, it is possible to configure the control device 103 using a simple and inexpensive controller.

[0114] In the example of Fig. 11, the sampling period Tsa is set to 3 / 2 times the switching period Tsw, but this is not limiting and it is sufficient if the AC currents IL1 and IL2 can be sampled at points where the positive and negative are symmetrical. To this end, the sampling period Tsa should be set to (2N+1) / 2 times the switching period Tsw, where N is an integer equal to or greater than 1.

[0115] In addition, in the example of Figure 11, in order to detect a point of positive and negative symmetrical, sampling is performed at timings when the switching phase is θ0 + 90 deg and θ0 + 270 deg, but the switching phase is not limited to this as long as it is a point of positive and negative symmetrical.

[0116] Embodiment 2 In the above-described first embodiment, a configuration has been described in which the sampling period Tsa of the AC currents IL1 and IL2 is made longer than the switching period Tsw in the DC / DC converter 102. According to this configuration, a simple and inexpensive controller can be used for the control device 103.

[0117] On the other hand, in the above configuration, since a positive / negative symmetrical point is detected over two different switching periods Tsw, when the phase difference command value δ varies in response to a sudden change in the load, as described below, the DC component calculated using the AC current detection values ​​IL1_det, IL2_det may not match the DC component actually contained in the AC currents IL1, IL2. In such a case, there is a concern that the current ripple may increase because the duty command values ​​Drefpri, Drefsec are changed unnecessarily.

[0118] In order to eliminate such concerns, in the second embodiment, a method for setting the allowable range of the DC component in passing current DC component comparator 701 and excitation current DC component comparator 706 that constitute the dead band circuit will be described.

[0119] Fig. 12 is an operational waveform diagram showing a time change of the passing current DC component Idcp when the load suddenly changes. Fig. 12 shows the waveforms of the phase difference command value δref, the AC currents IL1, IL2, and the AC current detection values ​​IL1_det, IL2_det. Fig. 12 further shows the waveforms of the passing currents Ip_n, Ip_d, and the passing current DC component Idcp calculated using the AC current detection values ​​IL1_det, IL2_det. Note that the sampling period Tsa is set to 3 / 2 times the switching period Tsw, as in Fig. 11.

[0120] 7, Ip_n represents the passing current calculated from the AC current detection values ​​IL1_det and IL2_det at the current sampling timing. Ip_d represents the passing current calculated from the AC current detection values ​​IL1_det and IL2_det at the previous sampling timing. Idcp represents the passing current DC component obtained by multiplying the sum of the passing current Ip_n at the current sampling timing and the passing current Ip_d at the previous sampling timing by a coefficient of 0.5 (Idcp=(Idcp_n+Idcp_d)×0.5).

[0121] 12, it is assumed that the phase difference command value Δref changes from 0 deg to 90 deg at timing (A). As the phase difference command value Δref increases, the AC currents IL1 and IL2 increase sharply from 0.

[0122] Sampling of the AC currents IL1 and IL2 is performed at a timing (B) when the switching phase becomes θ0 after the timing (A), and at a timing (D) delayed by one sampling period Tsa from the timing (B).

[0123] At timing (A), the AC currents IL1 and IL2 increase from 0, and therefore at timing (B), the AC current detection values ​​IL1_det and IL2_det both increase from 0. As a result, the passing current Ip_n at the current sampling timing also increases from 0.

[0124] Here, assuming that the AC current detection values ​​IL1_det, IL2_det at timing (B) are IL1B, IL2B, respectively, and the passing current Ip_n at the current sampling timing is Ip_nB, Ip_nB is calculated according to the following equation (8). Ip_nB = (IL1B - IL2B) × 0.5 … (8) Also, at timing (B), the passing current Ip_d at the previous sampling timing is 0. Therefore, if the passing current DC component Idcp calculated from the average value of the passing current Ip_n at the current sampling timing and the passing current Ip_d (=0) at the previous sampling timing is IdcpC, IdcpC is calculated according to the following equation (9). IdcpC=(Ip_nB+0)×0.5=Ip_nB×0.5 …(9) At timing (D), which is the sampling timing next to timing (B), IL1_det=IL2B, IL2_det=IL1B, so if the passing current Ip_n at the current sampling timing is Ip_nD, Ip_nD is calculated according to the following equation (10). Ip_nD=(IL2B-IL1B)×0.5=-Ip_nB …(10) At timing (D), the passing current Ip_d at the previous sampling timing (ie, timing (B)) is Ip_d=Ip_nB, so that the passing current DC component Idcp=(-Ip_nB+Ip_nB)×0.5=0.

[0125] According to this, in the period (C) from timing (B) to timing (D), the passing current DC component Idcp temporarily changes from 0 to IdcpC. Therefore, in the period (C), the duty command values ​​Drefpri and Drefsec are generated so that the passing current DC component IdcpC becomes 0.

[0126] When the phase difference command value δref changes abruptly at timing (A) in this way, the passing current Ip_n based on the sampling value after sampling (A) changes abruptly with respect to the passing current Ip_d based on the sampling value before timing (A), and a passing current DC component Idcp is temporarily generated during one sampling period Tsa. In such a case, actually, the AC currents IL1 and IL2 have a positive / negative symmetric waveform and do not contain a DC component, but computationally, the passing DC current is treated as having a current component Idcp. As a result, there is a concern that the duty command values Drefpri and Drefsec will be unnecessarily changed, and consequently, the current ripple will increase.

[0127] Therefore, in Embodiment 2, the upper limit value maxdcp and the lower limit value mindcp in the passing current DC component comparison unit 701 are set so that the passing current duty command value Drefdcp is not generated according to the computationally obtained passing current DC component Idcp (IdcpC in FIG. 12). In the example of FIG. 12, the upper limit value maxdcp and the lower limit value mindcp are set so that the relationship mindcp < IdcpC < maxdcp holds.

[0128] In this way, when the computationally obtained passing current DC component Idcp satisfies mindcp < Idcp < maxdcp, that is, when the computationally obtained passing current DC component Idcp is within the allowable range, the passing current DC component for control Idcp_th = 0 is set, and it is regarded that the passing current DC component Idcp is not included. As a result, since the passing current duty command value Drefdcp = 0 is set, it is possible to suppress the unnecessary change in the duty command values Drefpri and Drefsec.

[0129] In the example of Figure 12, a configuration has been described in which the upper limit value maxdcp and the lower limit value mindcp are set based on the passing current DC component Idcp calculated when the phase difference command value δref changes from 0 deg to 90 deg. However, it is also possible to configure the upper limit value maxdcp and the lower limit value mindcp to be set based on a change in the phase difference command value δref that occurs due to a sudden change in load that is expected in the actual operation of the DC / DC converter 102.

[0130] As for the excitation current DC component Idce, ideally, no DC component is generated in the calculation due to the sudden change in the phase difference command value δref. However, due to the variation in impedance or loss between the primary side bridge circuit 123 and the secondary side bridge circuit 124, or the variation in impedance of the inductance element 111, a DC component may also be generated in the excitation current in response to the sudden change in the phase difference command value δref. To deal with such a case, an upper limit value maxdce and a lower limit value mindce in the excitation current DC component comparison unit 706 may be set in accordance with the DC component generated by the sudden change in the phase difference command value δref.

[0131] Alternatively, the upper limit value maxdce and the lower limit value mindce in the excitation current DC component comparison section 706 may be set to the same values ​​as the upper limit value maxdcp and the lower limit value mindcp in the passing current DC component comparison section 701, respectively.

[0132] As described above, in the second embodiment, the allowable range of the DC component in the passing current DC component comparator 701 and the excitation current DC component comparator 706 constituting the dead band circuit is set so as to include the DC component generated in the calculation due to the fluctuation of the phase difference command value δref caused by a sudden change in the load, thereby making it possible to configure the duty command values ​​Drefpri and Drefsec not to change unnecessarily. This makes it possible to configure the control device 103 using a simple and inexpensive controller while suppressing an increase in the current ripple.

[0133] Embodiment 3 In the above-mentioned second embodiment, a configuration is described in which the allowable range of the DC component in the dead band circuit is set based on the DC component that is generated in the calculation in response to the fluctuation of the phase difference command value Δref. In the third embodiment, a configuration is described in which the allowable range is set based on the rated current of the DC / DC converter 102.

[0134] The upper limit value maxdcp and lower limit value mindcp of the allowable range in passing current DC component comparison section 701 are set based on the rated current In of DC / DC converter 102, as shown in the following expressions (11) and (12). Note that the rated current In corresponds to the DC current when DC / DC converter 102 is outputting the rated power. maxdcp = In × k1 … (11) mindcp = -In × k2 … (12) Here, coefficients k1 and k2 in equations (11) and (12) are arbitrary constants having values ​​between 0 and 1.

[0135] The upper limit maxdce and lower limit mindce of the allowable range in the excitation current DC component comparison unit 706 are also set based on the rated current In of the DC / DC converter 102, as shown in the following expressions (13) and (14). maxdce = In × k3 … (13) mindce = -In × k4 … (14) Here, coefficients k3 and k4 in equations (13) and (14) are arbitrary constants having values ​​between 0 and 1.

[0136] As described above, according to the third embodiment, by setting the allowable range of the DC component in the passing current DC component comparator 701 and the excitation current DC component comparator 706 that constitute the dead band circuit based on the rated current In of the DC / DC converter 102, it is possible to prevent the duty command values ​​Drefpri and Drefsec from being updated for a DC component that is sufficiently small with respect to the rated current In. As a result, it is possible to configure the control device 103 using a simple and inexpensive controller while suppressing an increase in the current ripple.

[0137] Embodiment 4 In the fourth embodiment, a configuration will be described in which an allowable range of a DC component in a dead band circuit is set based on detection errors of current detectors 121 and 122 for detecting AC currents IL1 and IL2.

[0138] 7, in the DC component calculation unit 304, the passing current DC component Idcp is calculated based on the difference between the AC current detection value IL1_det and the AC current detection value IL2_det, and the excitation current DC component Idce is calculated based on the sum of the AC current detection value IL1_det and the AC current detection value IL2_det. Since the AC current detection values ​​IL1_det and IL2_det are acquired by the current detection unit 303 from the output signals of the current detectors 121 and 122, the DC components Idcp and Idce are affected by the detection errors of the current detectors.

[0139] Specifically, when the calculated DC components Idcp and Idce are derived from detection errors of the current detectors 121 and 122, the passing DC is treated as having the current component Idcp in the calculation, even though the AC currents IL1 and IL2 do not actually contain a DC component, as in the second embodiment. As a result, the duty command values ​​Drefpri and Drefsec are unnecessarily changed, which may result in an increase in the current ripple.

[0140] Therefore, in the fourth embodiment, taking into consideration the influence of detection errors of the current detectors 121, 122, the upper limit maxdcp and lower limit mindcp of the allowable range in the passing current DC component comparator 701 are set according to the following equations (15) and (16). maxdcp = 2 × Ierr × k5 … (15) mindcp = -2 × Ierr × k6 … (16) Here, Ierr in equations (15) and (16) indicates the detection error of each of the current detectors 121 and 122. k5 and k6 are arbitrary constants having values ​​of 0 or more and 1 or less.

[0141] Similarly, the upper limit maxdce and lower limit mindce of the allowable range in the excitation current DC component comparison unit 706 are set according to the following equations (17) and (18) based on the detection error Ierr of each current detector. maxdce = 2 × Ierr × k7 … (17) mindce = -2 × Ierr × k8 … (18) Here, k7 and k8 in equations (17) and (18) are arbitrary constants having values ​​between 0 and 1. The detection error Ierr of the current detector is calculated according to the following equation (19). Ierr = Ib × A … (19) Here, Ib is a current that serves as a reference for the detection value by the current detector, and A is the accuracy of the current detector.

[0142] The reference current Ib may be a constant value such as the rated current of the DC / DC converter 102 or a current value based on the offsets of the current detectors 121 and 122. Alternatively, it may be a value that changes actively such as a current value detected by the current detector during operation of the DC / DC converter 102. The accuracy A of the current detector may be a value described in a previously obtained data sheet of the current detector, for example.

[0143] As described above, according to the fourth embodiment, the allowable range of the DC component in the dead band circuit is set so as to include the DC component generated in the calculation due to the detection error of the current detectors 121 and 122 that detect the AC currents IL1 and IL2, thereby making it possible to configure the duty command values ​​Drefpri and Drefsec not to be changed unnecessarily. This makes it possible to configure the control device 103 using a simple and inexpensive controller while suppressing an increase in the current ripple.

[0144] With regard to the multiple embodiments 1 to 4 described above, it is intended from the outset of the application that the configurations described in each embodiment may be appropriately combined, including combinations not mentioned in the specification, to the extent that no inconvenience or contradiction arises.

[0145] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0146] 11 transformer, 11a primary winding, 11b secondary winding, 11c, 11d reactor, 100 power conversion device, 102 DC / DC converter, 103 control device, 104, 118 smoothing capacitor, 107, 110, 114, 117 leg, 111 inductance element, 119, 120 voltage detector, 121, 122 current detector, 123 primary side bridge circuit, 124 secondary side bridge circuit, 301 voltage detection unit, 302 voltage control unit, 303 current detection unit, 304 DC component calculation unit, 305 current control unit, 306 gate signal generation unit, 501, 601, 702, 707, 709 subtractor, 502 phase difference command value generation unit, 602, 604, 607, 804, 808 Multiplier, 603, 605, 606, 704, 705, 710 Adder, 701 Passing current DC component comparison unit, 703 Passing current DC component suppression duty command value generation unit, 706 Excitation current DC component comparison unit, 708 Excitation current DC component suppression duty command value generation unit, 801, 802, 805, 806 Comparator, 803, 807 NAND circuit, Vd1 Primary side DC voltage, Vd2 Secondary side DC voltage, Vdc1_det Primary side DC voltage detection value, Vdc2_det Secondary side DC voltage detection value, Vtrpri Primary side AC voltage, Vtrsec Secondary side AC voltage, IL1 Primary side AC current, IL2 Secondary side AC current, IL1_det Primary side AC current detection value, IL2_det Secondary side AC current detection value, Ip Passing current, Idcp Passing current DC component, Ie excitation current, Idce excitation current DC component, Drefpri primary side duty command value, Drefsec secondary side duty command value, Drefdcp passing current duty command value, Drefdce excitation current duty command value, δ phase difference, δref phase difference command value, GP1 to GP8 gate signals, SW1 to SW8 semiconductor switching elements.

Claims

1. a power converter that performs bidirectional DC / DC conversion between a primary side DC terminal and a secondary side DC terminal; A control device for controlling an operation of the power converter, The power converter includes: a primary-side bridge circuit including semiconductor switching elements that performs bidirectional DC / AC power conversion between the primary-side DC terminal and the primary-side AC terminal; a secondary bridge circuit including a semiconductor switching element that performs bidirectional DC / AC power conversion between the secondary DC terminal and the secondary AC terminal; an inductance element connected between the primary AC terminal and the secondary AC terminal; a voltage detector for detecting a primary side DC voltage at the primary side DC terminal and a secondary side DC voltage at the secondary side DC terminal; a current detector for detecting a primary side AC current flowing through the primary side AC terminal and a secondary side AC current flowing through the secondary side AC terminal, The control device includes: a voltage control unit that generates a phase difference command value between a primary side AC voltage at the primary side AC terminal and a secondary side AC voltage at the secondary side AC terminal, using a detection value of the primary side DC voltage and a detection value of the secondary side DC voltage; a current detection unit that obtains a detection value of the primary side AC current and a detection value of the secondary side AC current by sampling an output signal of the current detector at a preset sampling period; a DC component calculation unit that calculates a DC component included in the AC current flowing through the inductance element using the detected value of the primary AC current and the detected value of the secondary AC current; a current control unit that generates a primary side duty command value for controlling a switching operation of the primary side bridge circuit and a secondary side duty command value for controlling a switching operation of the secondary side bridge circuit based on the calculated DC component; a control signal generating unit that generates a control signal for controlling the switching operations of the primary side bridge circuit and the secondary side bridge circuit in accordance with the generated phase difference command value, the primary side duty command value, and the secondary side duty command value, the sampling period is set to be longer than a switching period of the semiconductor switching element in the switching operation, the DC component calculation unit calculates the DC component by calculating an average value of a first current component calculated using the detection value of the primary side AC current and the detection value of the secondary side AC current acquired by the current detection unit at a current sampling timing, and a second current component calculated using the detection value of the primary side AC current and the detection value of the secondary side AC current acquired by the current detection unit at a previous sampling timing.

2. 2. The power conversion device according to claim 1, wherein the sampling period is set to have a length that is (2N+1) / 2 times the switching period, where N is a positive integer equal to or greater than 1.

3. 2. The power conversion device according to claim 1, wherein the current control unit includes a duty command value generation unit that calculates a duty command value for making the DC component zero in accordance with a control calculation that receives the DC component as an input, and generates the primary side duty command value and the secondary side duty command value using the generated duty command value.

4. the current control unit further includes a comparison unit that compares the DC component calculated by the DC component calculation unit with a predetermined allowable range, 4. The power conversion device according to claim 3, wherein the comparison unit inputs the DC component to the duty command value generation unit when the DC component is outside the allowable range, and inputs a logical value of 0 to the duty command value generation unit when the DC component is within the allowable range.

5. The power conversion device according to claim 4 , wherein the upper limit and the lower limit of the permissible range are set so that the DC component temporarily calculated in response to a fluctuation in the phase difference command value is included in the permissible range.

6. The power conversion device according to claim 4 , wherein the upper and lower limits of the tolerance range are set based on a rated current of the power converter.

7. The power conversion device according to claim 4 , wherein the upper and lower limits of the allowable range are set based on a detection error of the current detector.

8. the inductance element is a transformer having a primary winding connected to the primary AC terminals and a secondary winding connected to the secondary AC terminals, 8. The power conversion device according to claim 1, wherein the DC component calculation unit calculates a DC component of a passing current passing through the transformer and a DC component of an excitation current of the transformer based on the detection value of the primary side AC current and the detection value of the secondary side AC current.

9. the inductance element is a reactor connected between the primary AC terminal and the secondary AC terminal, 8. The power conversion device according to claim 1, wherein the DC component calculation unit calculates a DC component of a passing current passing through the reactor based on the detected value of the primary side AC current and the detected value of the secondary side AC current.

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