Image Sensor

Abstract

To provide an image sensor in which the performance is improved and leakage current and noise are reduced.SOLUTION: An image sensor includes: a substrate including a first surface and a second surface that are opposite to each other; a first transistor including a first gate electrode on the first surface; a photoelectric conversion layer that generates optical charges from incident light that enters in a first direction; a second transistor disposed between the first surface and the photoelectric conversion layer, separated from the photoelectric conversion layer, including a metal oxide semiconductor material, including a transistor structure including a semiconductor layer with a third surface extending in a direction orthogonal to the first direction and a fourth surface opposite to the third surface, having a second gate on the semiconductor layer, and having the semiconductor layer connected to the first gate; and a light-blocking film disposed between the third surface and the photoelectric conversion layer and separated from the photoelectric conversion layer.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor including a light blocking film. [Background technology]

[0002] An image sensor is a semiconductor device that converts optical information into an electrical signal. Such image sensors can include charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors.

[0003] On the other hand, CMOS image sensors are classified into front-illuminated (FSI; Front Side Illumination) CMOS image sensors, in which light is incident on the front side of the substrate, and back-illuminated (BSI; Back Side Illumination) CMOS image sensors, in which light is incident on the back side of the substrate. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide an image sensor having improved performance by reducing leakage current and noise.

[0005] The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] According to some embodiments of the image sensor for achieving the above technical objective, the image sensor includes a substrate including a first surface and a second surface opposite to each other, a first transistor including a first gate electrode on the first surface, a photoelectric conversion layer for generating photocharges from incident light incident in a first direction, and a second transistor between the first surface and the photoelectric conversion layer and separated from the photoelectric conversion layer, the second transistor including a metal oxide semiconductor material and a semiconductor layer including a third surface extending in a direction perpendicular to the first direction and a fourth surface opposite to the third surface, a second gate is disposed on the semiconductor layer, and the semiconductor layer is connected to the first gate electrode, and the second transistor includes a light shielding film separated from the photoelectric conversion layer between the third surface and the photoelectric conversion layer.

[0007] In order to achieve the above technical objective, an image sensor according to some embodiments includes a substrate having a first surface and a second surface opposite to each other, a source follower transistor including a first gate on the first surface of the substrate, a first photoelectric conversion layer separated from the substrate and configured to generate a first photocharge from incident light, a transistor structure disposed adjacent to the first surface of the substrate and including a semiconductor layer including a metal oxide semiconductor material and a second gate on a central region of the semiconductor layer, and a light shielding film disposed between the first photoelectric conversion layer and the transistor structure, separated from the first photoelectric conversion layer and covering at least a portion of the semiconductor layer from the incident light, and a first portion of the semiconductor layer disposed on one side of the central region is connected to the first gate and the first photoelectric conversion layer.

[0008] In order to achieve the above technical problem, an image sensor according to some embodiments includes a substrate having a first surface and a second surface opposite to each other, a first transistor including a first gate on the first surface of the substrate, a photoelectric conversion layer within the substrate for generating photocharges from incident light, a second transistor arranged adjacent to the first surface of the substrate and including a transistor structure including a semiconductor layer including a metal oxide semiconductor material and a second gate on a central region of the semiconductor layer, a light shielding film and a capacitor structure arranged adjacent to the first surface of the substrate, covering at least a portion of the semiconductor layer from the incident light, and a first portion of the semiconductor layer located at an edge portion of the semiconductor layer is connected to the first gate and the capacitor structure.

[0009] Specific details of other embodiments are included in the detailed description and drawings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating an image sensor according to some embodiments. [Diagram 2] 1 is an exemplary circuit diagram of a unit pixel area of ​​an image sensor according to some embodiments. [Diagram 3] 1 is a schematic plan view of an image sensor according to some embodiments. [Figure 4] 1 is a schematic layout diagram illustrating a unit pixel area of ​​an image sensor according to some embodiments. [Diagram 5] FIG. 5 is a cross-sectional view taken along line AA in FIG. [Figure 6a] 6A-6C are diagrams illustrating various embodiments that may be used for the transistor structures and connecting structures in the S1 region of FIG. 5. [Figure 6b] 6A-6C are diagrams illustrating various embodiments that may be used for the transistor structures and connecting structures in the S1 region of FIG. 5. [Figure 6c] 6A-6C are diagrams illustrating various embodiments that may be used for the transistor structures and connecting structures in the S1 region of FIG. 5. [Figure 6d] 6A-6C are diagrams illustrating various embodiments that may be used for the transistor structures and connecting structures in the S1 region of FIG. 5. [Figure 6e] 6A-6C are diagrams illustrating various embodiments that may be used for the transistor structures and connecting structures in the S1 region of FIG. 5. [Figure 7] 1 is an exemplary timing diagram to illustrate the operation of an image sensor according to some embodiments. [Figure 8] 1 is a schematic layout diagram illustrating a unit pixel area of ​​an image sensor according to some embodiments. [Figure 9] FIG. 9 is a cross-sectional view taken along line BB in FIG. 8. [Figure 10a] 10A-10C are various close-up views of respective embodiments of the S2 region of FIG. [Figure 10b] 10A-10C are various close-up views of respective embodiments of the S2 region of FIG. [Figure 10c] 10A-10C are various close-up views of respective embodiments of the S2 region of FIG. [Figure 10d] 10A-10C are various close-up views of respective embodiments of the S2 region of FIG. [Figure 10e] 10A-10C are various close-up views of respective embodiments of the S2 region of FIG. [Figure 11] 1 is a cross-sectional view illustrating an image sensor according to some embodiments. [Figure 12] 12A to 12C are partial perspective views for explaining other embodiment structures of the first light blocking film in FIG. 11. [Figure 13] 12A to 12C are partial perspective views for explaining other embodiment structures of the first light blocking film in FIG. 11. [Figure 14] 1 is an exemplary circuit diagram of a unit pixel area of ​​an image sensor according to some embodiments. [Figure 15] 1A-1D are cross-sectional views illustrating respective image sensors according to some embodiments. [Figure 16]1A-1D are cross-sectional views illustrating respective image sensors according to some embodiments. [Figure 17] 1 is an exemplary circuit diagram of a unit pixel area of ​​an image sensor according to some embodiments. [Figure 18] 1A-1D are cross-sectional views illustrating respective image sensors according to some embodiments. [Figure 19] 1A-1D are cross-sectional views illustrating respective image sensors according to some embodiments. [Figure 20] 1 is an exemplary circuit diagram of a unit pixel area of ​​an image sensor according to some embodiments. [Figure 21] 1 is a schematic layout diagram illustrating a unit pixel area of ​​an image sensor according to some embodiments. [Figure 22] FIG. 22 is a cross-sectional view taken along CC in FIG. 21. [Figure 23a] 23A-23C are various enlarged views of the S3 region of FIG. 22. [Figure 23b] 23A-23C are various enlarged views of the S3 region of FIG. 22. [Figure 23c] 23A-23C are various enlarged views of the S3 region of FIG. 22. [Figure 23d] 23A-23C are various enlarged views of the S3 region of FIG. 22. [Figure 23e] 23A-23C are various enlarged views of the S3 region of FIG. 22. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Image sensors according to some embodiments will now be described with reference to Figures 1 to 23e.

[0012] In this application, when a component of each layer is said to be "on" or "disposed on" or "connected" or "coupled" to another component or layer, it may be directly connected (i.e., there is a direct physical interface) to the other component or layer, or there may be intermediate component(s) or layer(s). When the context refers to a drawing showing a first component or layer "on" a second component or layer, and the associated components and layers being physically interfaced, an embodiment may be provided in which the component or layer associated with the drawing is physically "directly on" the second component or layer, without other intervening components or layers. However, it may be understood that intermediate intervening components or layers are possible in alternative embodiments with respect to the described embodiment.

[0013] In this application, when a gate electrode is said to be "on" a surface or substrate, a gate dielectric layer, such as a gate oxide layer, may be interposed between the gate electrode and the surface or substrate. The combination of the gate electrode and the gate dielectric layer is referred to as the "gate" of a transistor.

[0014] In this application, when a layer is said to contain a particular material, the layer may be composed in part or entirely of that particular material.

[0015] FIG. 1 is a block diagram illustrating an image sensor 5 according to some embodiments.

[0016] The image sensor 5 may include an active pixel sensor array (APS, Active Pixel Sensor array) (10), a row decoder (20), a row driver (30), a column decoder (40), a timing generator (50), a correlated double sampler (CDS, Correlated Double Sampler) (60), an analog to digital converter (ADS, Analog to Digital Converter) (70), and an input / output buffer (80).

[0017] The active pixel sensor array 10 includes a plurality of unit pixel regions PU arranged two-dimensionally, and can convert optical signals into electrical signals. The active pixel sensor array 10 can be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver 30. The electrical signals converted by the active pixel sensor array 10 can be provided to a correlated double sampler 60.

[0018] The row driver 30 can provide a number of driving signals to the active pixel sensor array 10 for driving a number of unit pixel areas PU according to the result of decoding by the row decoder 20. When the unit pixel areas PU are arranged in a matrix form, a driving signal can be provided for each row.

[0019] A timing generator 50 may provide timing and control signals to the row decoder 20 and the column decoder 40 .

[0020] The correlated double sampler (CDS; 60) can receive, hold, and sample the electrical signal generated by the active pixel sensor array 10. The correlated double sampler 60 can double sample a specific noise level and a signal level based on an electrical signal, and output a difference level corresponding to the difference between the noise level and the signal level.

[0021] An analog-to-digital converter (ADC; 70) can convert an analog signal corresponding to the difference level output from the correlated double sampler 60 into a digital signal and output the digital signal.

[0022] The input / output buffer 80 latches digital signals, and outputs the latched signals to an image signal processor (not shown) in sequence according to the results of decoding by the column decoder 40 .

[0023] 2 illustrates an example circuit within a unit pixel area (PU, interchangeably referred to as pixel circuit PU) of image sensor 5. The pixel circuit PU may include a first photoelectric conversion element PD1, a first floating diffusion region FD1, a first reset transistor RG1, a first source follower transistor SF1, and a first select transistor SEL1.

[0024] The first photoelectric conversion element PD1 can absorb light and accumulate charges corresponding to the amount of light. The first photoelectric conversion element PD1 can include, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode, an organic photodiode, a quantum dot, or a combination thereof.

[0025] The electric charge accumulated from the first photoelectric conversion element PD1 is stored in the first floating diffusion region FD1. The first floating diffusion region FD1 is a region that switches the electric charge to a voltage and has a parasitic capacitance, so that the electric charge can be cumulatively stored.

[0026] The first source follower transistor SF1 may function as a source follower buffer amplifier controlled by the first floating diffusion region FD1. The first source follower transistor SF1 may amplify a change in the electrical potential of the first floating diffusion region FD1 and provide it to a first output line OL1. For example, a predetermined electrical potential (e.g., a first V DD 1) may be controlled by a first floating diffusion region FD1 and provided to a first output line OL1.

[0027] The first selection transistor SEL1 can select a unit pixel area to be read out on a row-by-row basis. The first selection transistor SEL1 is driven by a selection line that applies a predetermined bias. For example, when the first selection transistor SEL1 is turned on, a predetermined electrical potential (e.g., an electrical potential provided from the source of the first source follower transistor SF1) provided to the drain of the first selection transistor SEL1 by a signal (SEL) applied to the gate of the first selection transistor SEL1 can be output to the first output line OL1.

[0028] The first reset transistor RG1 can periodically reset the first floating diffusion region FD1. The first reset transistor RG1 can be driven by a reset line that applies a predetermined bias. For example, when the first reset transistor RG1 is turned on, a predetermined electrical potential (e.g., a second V DD 2) can be transferred to the first floating diffusion region FD1.

[0029] Fig. 3 is a schematic plan view of an image sensor 5 according to some embodiments. Fig. 4 is a schematic layout diagram illustrating a unit pixel region of an image sensor according to some embodiments. Referring to Fig. 3, the image sensor 5 may include a sensor array region I and a peripheral circuit region II.

[0030] The sensor array region I may be, for example, a region in which the active pixel sensor array 10 of Fig. 1 is formed. For example, the sensor array region I may include a plurality of unit pixel regions PU.

[0031] The peripheral circuit region II may be, for example, a region in which the correlated double sampler 60, the analog-to-digital converter 70, etc. of FIG. 1 are formed. In FIG. 3, the peripheral circuit region II only surrounds the sensor array region I. In other embodiments, the peripheral circuit region II may overlap the sensor array region I. For example, the peripheral circuit region II may be formed in a lower substrate, and the sensor array region I may be formed in an upper substrate stacked on the lower substrate.

[0032] In the example of the pixel region PU described in FIG. 4, the region in which the transistors (SEL1, SF1, RG1) are arranged will be described. In the example described below, the first source follower transistor SF1 may have a first gate electrode G1, and the first reset transistor RG1 may have a second gate electrode G2. Region 120 is an active region that forms a circuit path between the source and drain of each transistor (SEL1, SF1). Although the embodiment of FIG. 4 shows a case in which only one pixel is formed in the unit pixel region PU, multiple pixels may be formed in the unit pixel region PU in other embodiments.

[0033] Figure 5 is a cross-sectional view taken along line AA in Figure 4. Figures 6a to 6e are views illustrating various embodiments used for the transistor structure and the connecting structure in the S1 region of Figure 5. Referring to Figures 2 to 6a, an embodiment of a pixel unit PU of an image sensor 5 includes a substrate 100, an isolation film 130, a first interlayer insulating film 200, a first gate electrode G1, a first photoelectric conversion layer 320, a first transistor structure TR1, a first light blocking film 250 and a microlens 340.

[0034] Substrate 100 can be, for example, bulk silicon or silicon-on-insulator (SOI). Alternatively, substrate 100 can be a silicon substrate or can include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Substrate 100 can also be an epitaxial layer formed on a base substrate.

[0035] The substrate 100 may include a first surface 100a and a second surface 100b that are opposite to each other. The first surface 100a may be a front side of the substrate 100, and the second surface 100b may be a back side of the substrate 100. For example, the first surface 100a of the substrate 100 may be used to arrange various transistors for processing electrical signals generated from the first photoelectric conversion layer 320. For example, The first source follower transistor SF1 and the first select transistor SEL1 may include active regions (120, doped regions) formed in the substrate 100, and each may include gate, source and drain electrodes formed on the first surface 100a. The first reset transistor RG1 may include a transistor structure TR1 partially supported by a first interlayer insulating film 200 formed on the first surface 100a.

[0036] Incident light IL is incident on a first surface 100a of the substrate 100. For example, the incident light IL may be incident in a first direction from the outside of the image sensor. At this time, the first surface 100a extends (faces) in a direction perpendicular to the first direction.

[0037] The active region 120 is a doped region of the substrate 100 surrounded by the isolation layer 130. The isolation layer 130 may define the active region 120 in the unit pixel region PU. For example, the isolation layer 130 may be formed in the substrate 100 adjacent to the first surface 100a. The isolation layer 130 may be formed by filling an insulating material in a trench formed by patterning the substrate 100. Thus, an edge portion of the isolation layer 130 may define a portion of the unit pixel region PU as the active region 120. Although not specifically described as one plane of the substrate 100, the first surface 100a may extend beyond the isolation layer 130 and be a plane partially defined as the plane of the isolation layer 130 and the substrate 100. Hereinafter, references to the first surface 100a are intended to be general references to any portion of a surface unless otherwise specified by the context.

[0038] The first interlayer insulating film 200 is formed on the first surface 100a. The first interlayer insulating film 200 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide.

[0039] The first gate electrode G1 may be formed on the first surface 100a of the substrate 100 (as described above, a gate insulator such as the first gate insulator 122 may be present between the gate electrode and a plane, and the gate electrode may be said to be disposed "on" the surface). For example, the first gate electrode G1 may be formed in the first interlayer insulating film 200 and implemented as the gate electrode of the first source follower transistor SF1. The first gate electrode G1 may be part of a patterned metal layer that forms other gate electrodes (not shown), such as the gate electrode for the first select transistor SEL1.

[0040] In some embodiments, the first gate electrode G1 may be formed directly on a first gate insulating film 122 formed directly on the active region 120. The first gate electrode G1 and the first gate insulating film 122 may be included in a first gate GT1, which is the gate of the source follower transistor SF1. The first gate GT1 may be disposed on the first surface 100a as shown in FIG.

[0041] The first gate insulating film 122 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and a material having a higher dielectric constant (high-k) than silicon oxide. The first gate electrode G1 may include, for example, a metal material such as tungsten (W), titanium (Ti), titanium nitride (TiN), copper (Cu), aluminum (Al), etc. Alternatively, the second gate electrode G2 may include, for example, a metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semiconductor material such as doped silicon.

[0042] The first photoelectric conversion layer 320 can generate a first photoelectric charge in proportion to the amount of incident light IL incident from the outside. That is, the first photoelectric conversion layer 320 can receive light and convert an optical signal into an electrical signal. For example, the first photoelectric conversion layer 320 corresponds to the first photoelectric conversion element PD1 in FIG. 2.

[0043] 5, the first photoelectric conversion layer 320 may be formed in a state separated from the substrate 100. For example, the first photoelectric conversion layer 320 may be formed on the first interlayer insulating film 200. The first photoelectric conversion layer 320 may be formed on the first surface 100a of the substrate 100 and may be separated from the substrate 100 by the first interlayer insulating film 200.

[0044] The first lower electrode 322 and the first upper electrode 324 adjacent to the first photoelectric conversion layer 320 may be formed on different planes. The first photoelectric conversion layer 320 may be interposed between the first lower electrode 322 and the first upper electrode 324. For example, the first lower electrode 322 may extend along the bottom surface of the first photoelectric conversion layer 320, and the first upper electrode 324 may extend along the top surface of the first photoelectric conversion layer 320. In FIG. 5, the first lower electrode 322 has an edge adjacent to the top of the first interlayer insulating film 200 under the first photoelectric conversion layer 320, but in other embodiments, the first lower electrode may extend completely along the bottom surface of the first photoelectric conversion layer 320.

[0045] Voltages of different levels may be applied to the first lower electrode 322 and the first upper electrode 324. For example, voltages of different levels may be applied to the first lower electrode 322 and the first upper electrode 324 so that an electrical signal generated from the first photoelectric conversion layer 320 is directed to the first lower electrode 322.

[0046] The first lower electrode 322 and the first upper electrode 324 may include a transparent conductive material. For example, the first lower electrode 322 and the first upper electrode 324 may include a transparent conductive material such as indium tin oxide (ITO), zinc oxide (ZnO), tin dioxide (SnO2), antimony-doped tin oxide (ATO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), TiO 2 The first lower electrode 322 and the first upper electrode 324 may include at least one of titanium dioxide (Titanium Dioxide), fluorine-doped tin oxide (FTO), or a combination thereof. The first lower electrode 322 and the first upper electrode 324 may include the same material or different materials.

[0047] The first photoelectric conversion layer 320 may include an organic photoelectric conversion layer.

[0048] The first transistor structure TR1 may be formed adjacent to the first surface 100a of the substrate 100. For example, the first transistor structure TR1 may be formed in the first interlayer insulating film 200. The first transistor structure TR1 may be separated from each of the substrate 100 and the first photoelectric conversion layer 320. The first transistor structure TR1 may be interposed between the substrate 100 and the first photoelectric conversion layer 320, and is closer to the substrate 100 than the first photoelectric conversion layer 320.

[0049] The first transistor structure TR1 may include a first semiconductor layer 242, a second gate dielectric film 244 and a second gate electrode G2.

[0050] The first semiconductor layer 242 may include a semiconductor material. For example, the first semiconductor layer 242 may include a metal oxide semiconductor material such as indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO), an elemental semiconductor material such as polysilicon (poly Si) or amorphous silicon (amorphous Si), an organic semiconductor material, a carbon semiconductor material such as graphene or carbon nanotubes (CNTs), or a combination thereof. Additionally or alternatively, the first semiconductor layer 242 may include a semiconductor material such as CdSe, CdS, ZnO, SnO 2 , MoS 2 , TiO 2 , Fe 2 O 3 , WO 3 , InGaZnO, ZnO-Rh 2 O 3 , In 2 O 3 , ZnInO, InGaO, InZnO, ZnSnO, or a combination thereof.

[0051] When the first semiconductor layer 242 includes IGZO, the leakage current can be effectively reduced.

[0052] 6a is an enlarged view of the S1 region of FIG. 5. In the embodiment of FIG. 6a, the first semiconductor layer 242 may include a third surface 242a and a fourth surface 242b that are opposite to each other. The third surface 242a of the first semiconductor layer 242 may be defined as a surface that extends in a direction perpendicular to the first direction in which the incident light is incident (opposing direction). That is, the incident light IL is incident from the outside of the image sensor toward the third surface 242a of the first semiconductor layer 242.

[0053] The second gate electrode G2 may be formed on the first semiconductor layer 242. The second gate electrode G2 may be formed on the fourth surface 242b. Therefore, the second gate electrode G2 may be interposed between the substrate 100 and the first semiconductor layer 242.

[0054] The second gate electrode G2 may be formed directly below a central region between the first portion SP1 and the second portion SP2 of the first semiconductor layer 242. The first portion SP1 and the second portion SP2 are end regions of the first semiconductor layer 242 that are opposite ends of each other.

[0055] The second gate electrode G2 may include a conductive material. For example, the second gate electrode G2 may include a metal material such as tungsten (W), titanium (Ti), titanium nitride (TiN), copper (Cu), aluminum (Al), etc. Also, for example, the second gate electrode G2 may include a metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semiconductor material such as doped silicon.

[0056] The second gate dielectric film 244 may be interposed between the first semiconductor layer 242 and the second gate electrode G2. For example, the second gate dielectric film 244 may conformally extend along the profile of the fourth surface 242b. The second gate electrode G2 and the second gate insulating film 244 may be included in a second gate GT2 formed on the fourth surface 242b in a central region of the first semiconductor layer 242.

[0057] The second gate dielectric layer 244 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and other high-k materials having a higher dielectric constant than silicon oxide.

[0058] As mentioned above, the first portion SP1 of the first semiconductor layer 242 can form the first floating diffusion region FD1. For example, as shown in FIG. 5, the first portion SP1 can form the source region (interchangeably referred to as "source" or source electrode) of the first reset transistor RG1 and can be electrically connected with the respective first gate electrode G1 and the first photoelectric conversion layer 320 (the second portion SP2 can form the drain of the first reset transistor RG1, or alternatively the first portion SP1 can form the drain and the second portion SP2 can form the source of the first reset transistor RG1). Thus, the first photocharge generated from the first photoelectric conversion layer 320 can be stored in the first portion SP1. Also, the first source follower transistor SF1 including the first gate electrode G1 can amplify the change in the electrical potential of the first portion SP1.

[0059] Since the first floating diffusion region FD1 of the image sensor according to some embodiments does not contact the substrate 100, contact leakage between the first floating diffusion region FD1 and the substrate 100 can be effectively reduced.

[0060] As described above, the first transistor structure TR1 including the first semiconductor layer 242 can form the first reset transistor RG1. For example, the second portion SP2 can be provided with a predetermined electrical potential (e.g., a second V DD 2) may be provided. When the second gate electrode G2 is turned on, a predetermined electric potential provided to the second portion SP2 is transferred to the first portion SP1. Therefore, the second gate electrode G2 may play a role of periodically resetting the first portion SP1.

[0061] Continuing to refer to FIG. 5 and FIG. 6a, in the image sensor 5, the first gate electrode G1 may be connected to the fourth surface 242b, and the first photoelectric conversion layer 320 may be connected to the third surface 242a.

[0062] For example, a first via 220 connected to the fourth surface 242b and a second via 230 connected to the third surface 242a may be formed in the first interlayer insulating film 200. The vias in the present application may be formed by filling a through-hole with a conductive material as long as they are vertically conductive conduits, and may electrically connect conductive components at different levels vertically of the circuit structure (the vertical direction is the thickness direction of the circuit structure). The first gate electrode G1 may be connected to the first semiconductor layer 242 through the first via 220, and the first photoelectric conversion layer 320 may be connected to the first semiconductor layer 242 through the second via 230 and the third via.

[0063] A first conductive pad 210a and a second conductive pad 210b may be formed on the first semiconductor layer 242. The first conductive pad 210a may be connected to the first portion SP1, and the second conductive pad 210b may be connected to the second portion SP2. The first conductive pad 210a and the second conductive pad 210b may be in contact with the fourth surface 242b. In such a case, the first via 220 may be connected to the first semiconductor layer 242 through the first conductive pad 210a. The second conductive pad 210b may apply a predetermined electrical potential (e.g., a second V DD 2) can be provided.

[0064] The first light-shielding film 250 may be formed on the third surface 242a of the first semiconductor layer 242. For example, a portion of the first light-shielding film 250 may be formed in the first interlayer insulating film 200 directly on the third surface 242a. The first light-shielding film 250 may be separated from the first photoelectric conversion layer 320 by an upper region of the first interlayer insulating film 200. The first light-shielding film 250 may be interposed between the first transistor structure TR1 and the first photoelectric conversion layer 320.

[0065] The first light blocking film 250 can cover at least a part of the third surface 242a from the incident light IL (for example, the entire third surface 242a). That is, the first light blocking film 250 can prevent the incident light IL from penetrating into the first semiconductor layer 242. Therefore, noise generated in the first semiconductor layer 242 by the incident light IL can be reduced, and as a result, an image sensor 5 with improved performance compared to conventional image sensors can be provided.

[0066] The first light-blocking film 250 may include an electrically conductive material and may be electrically connected to the first semiconductor layer 242. For example, the first light-blocking film 250 may be connected to the second via 230. The first light-blocking film 250 may be connected to the first photoelectric conversion layer 320. For example, a third via 260 connecting the first light-blocking film 250 and the first lower electrode 322 may be formed in the first interlayer insulating film 200. Therefore, the first photoelectric conversion layer 320 may be connected to the third surface 242a through the first lower electrode 322, the third via 260, the first light-blocking film 250, and the second via 230. If the first light-blocking film 250 includes a non-conductive material, another via (not shown) may be formed in the light-blocking film 250 to connect the first via 220 and the third via 260.

[0067] The microlens 340 may be formed on the first upper electrode 324. The microlens 340 may have a convex shape and a predetermined radius of curvature. Therefore, the microlens 340 may focus the incident light IL.

[0068] The microlenses 340 may include, but are not limited to, an organic material such as a light-transmitting resin.

[0069] The image sensor 5 may further include a protective layer 330 interposed between the first upper electrode 324 and the microlens 340. The protective layer 330 may include a transparent insulating material. The protective layer 330 may include, for example, but is not limited to, silicon oxide or metal oxide.

[0070] 6b is a diagram illustrating another embodiment of a structure of circuit components in the S1 region of the image sensor 5. In this embodiment, the second gate electrode G2 and the second gate dielectric layer 244 may be formed on the third surface 242a of the first semiconductor layer 242.

[0071] 6c is a diagram illustrating another embodiment of the structure of the circuit components in the S1 region of the image sensor 5. In the embodiment, the second gate electrode G2 and the second gate dielectric film 244 may be both formed on the third surface 242a and the fourth surface 242b. For example, the second gate electrode G2 may include an upper gate electrode G2a and a lower gate electrode G2b, and the second gate dielectric film 244 may include an upper gate dielectric film 244a and a lower gate dielectric film 244b. The upper gate electrode G2a and the upper gate dielectric film 244a may be formed on the third surface 242a, and the lower gate electrode G2b and the lower gate dielectric film 244b may be formed on the fourth surface 242b.

[0072] 6d is a diagram illustrating another embodiment of the structure of the circuit components in the S1 region of the image sensor 5. In this embodiment, the first gate electrode (G1, see FIG. 5) and the first photoelectric conversion layer 320 may be connected to the fourth surface 242b of the first semiconductor layer 242.

[0073] For example, the second via 230 connected to the first photoelectric conversion layer 320 may be connected to the first via 220 connected to the fourth surface 242b. For example, the first wiring 232, the fourth via 234, and the second wiring 236 that connect the bottom surface of the second via 230 and the bottom surface of the first via 220 may be formed in the first interlayer insulating film 200. Therefore, the first portion SP1 of the first semiconductor layer 242 may be connected to the first photoelectric conversion layer 320 via the first via 220, the second wiring 236, the fourth via 234, the first wiring 232, and the second via 230. Therefore, the first portion SP1 may be connected to the first gate electrode G1 via the first via 220, the second wiring 236, and the fifth via 238.

[0074] 6e is a diagram illustrating another embodiment of the structure of the circuit components in the S1 region of the image sensor 5. In this embodiment, the first gate electrode (G1, see FIG. 5) and the first photoelectric conversion layer 320 may be connected to the third surface 242a of the first semiconductor layer 242.

[0075] For example, the first via 220 connected to the first gate electrode G1 may be connected to the second via 230 connected to the third surface 242a of the first semiconductor layer 242. For example, the third wiring 222, the sixth via 224, and the fourth wiring 226 connecting the upper surface of the first via 220 and the upper surface of the second via 230 may be formed in the first interlayer insulating film 200. Therefore, the first portion SP1 of the first semiconductor layer 242 may be connected to the first gate electrode G1 via the second via 230, the fourth wiring 226, the sixth via 224, the third wiring 222, and the first via 220.

[0076] In some embodiments, the first portion SP1 of the first semiconductor layer 242 can be connected to the first gate electrode G1 through the second via 230, the fourth wiring 226, and the seventh via 228.

[0077] 7 is an exemplary timing diagram for explaining the operation of the image sensor 5. For convenience of explanation, parts that overlap with the contents explained in relation to FIGS. 1 to 6 will be briefly explained or omitted.

[0078] Referring to FIG. 7, an image sensor according to some embodiments may perform a global shutter operation. First, electrical signals for all unit pixel regions PU of the active pixel sensor array 10 may be stored for a first time (T1). For example, the first reset transistors RG1 of all unit pixel regions PU may be turned on by a signal (RG), and electrical signals for the first floating diffusion regions FD1 of all unit pixel regions PU may be reset (RG(shutter) applied for a first time (T1)). Then, the first photoelectric conversion elements PD1 of all unit pixel regions PU may generate first photocharges (V PD(shutter)). Then, an electrical signal can be stored in the first floating diffusion region FD1 of every unit pixel area PU.

[0079] Then, during a second time (T2), an electrical signal for the unit pixel region PU of the row unit may be output. For example, the first selection transistor SEL1 may be turned on to select the unit pixel region PU to be read out on a row unit basis (during the pulse of the signal (SEL), i.e., when the signal (SEL) is at a high level). Then, the electrical signal of the selected unit pixel region PU of the row unit may be output to the first output line OL1 ("Signal Reading", which occurs when the signal (SEL) is at a high level). Then, the electrical signal of the selected unit pixel region PU of the row unit may be reset (RG(reading), which occurs when the signal (SEL) is at a high level). Then, the electrical signal of the selected unit pixel region PU of the row unit may be output again to the first output line OL1 ("Reference Reading", which occurs when the RG(reading) signal (SEL) is at a high level). Thus, the correlated double sampler 60 may output a difference level corresponding to the difference between the noise level and the signal level.

[0080] Figure 8 is a schematic layout diagram illustrating another embodiment of a unit pixel region of an image sensor 5 according to another embodiment. Figure 9 is a cross-sectional view taken along line BB in Figure 8. Figures 10a to 10e are enlarged views of various embodiments of the S2 region in Figure 9. For convenience of explanation, parts that overlap with those described in relation to Figures 1 to 7 will be briefly explained or omitted.

[0081] 8 to 10a, incident light IL in the image sensor 5 may be incident on the second surface 100b of the substrate 100. For example, the second surface 100b of the substrate 100 extends in a direction perpendicular to (opposes) the incident light IL incident in the first direction.

[0082] In some embodiments, the first photoelectric conversion layer 320 may be formed on the second surface 100b of the substrate 100. For example, the second interlayer insulating film 300 may be formed on the second surface 100b of the substrate 100, and the first photoelectric conversion layer 320 may be formed on the second interlayer insulating film 300. That is, the first photoelectric conversion layer 320 may be separated from the substrate 100 by the second interlayer insulating film 300.

[0083] 9 and 10a, in the image sensor according to some embodiments, the first gate electrode G1 and the first photoelectric conversion layer 320 may be connected to the third surface 242a of the first semiconductor layer 242.

[0084] For example, a first via 220 connected to the third surface 242a of the first semiconductor layer 242 may be formed in the first interlayer insulating film 200. The first gate electrode G1 may be connected to the first semiconductor layer 242 through the first via 220.

[0085] In some embodiments, a first through via 160 may be formed through the substrate 100 and connected to the third surface 242a of the first semiconductor layer 242. The first photoelectric conversion layer 320 may be connected to the first semiconductor layer 242 through the first through via 160. The first through via 160 may include a first plug pattern 162 including a conductive material and a first spacer 164 including an insulating material. The first plug pattern (162, conductive plug) may be electrically insulated from the substrate 100 through the first spacer 164. The first spacer 164 may be a hollow cylindrical structure.

[0086] In some embodiments, the first light-shielding film 250 may be in contact with the third surface 242a of the first semiconductor layer 242. For example, the first light-shielding film 250 may include a first sub-shielding film 250a in contact with the first portion SP1 of the first semiconductor layer 242 and a second sub-shielding film 250b in contact with the second portion SP2 of the first semiconductor layer 242. The first sub-shielding film 250a may cover a portion of the third surface 242a of the first semiconductor layer 242, and the second sub-shielding film 250b may cover another portion of the third surface 242a of the first semiconductor layer 242.

[0087] The first light-shielding film 250 may include a conductive material and may be electrically connected to the first gate electrode G1 and the first photoelectric conversion layer 320. For example, the first through via 160 and the first via 220 may contact the first sub-shielding film 250a.

[0088] 9 and 10b, in the image sensor 5 using the structure of the alternative embodiment for the S2 region, the second gate electrode G2 and the second gate dielectric film 244 may be formed on the fourth surface 242b of the first semiconductor layer 242. The first light-shielding film 250 may further include a third sub-shielding film 250c. The third sub-shielding film 250c may be interposed between the first sub-shielding film 250a and the second sub-shielding film 250b, and may cover the area of ​​the third surface 242a of the first semiconductor layer 242 that is not covered by the first sub-shielding film 250a and the second sub-shielding film 250b.

[0089] 9 and 10c, in the image sensor 5 using the structure of yet another alternative embodiment for the S2 region, the second gate electrode G2 and the second gate dielectric film 244 may be both formed on the third surface 242a and the fourth surface 242b of the first semiconductor layer 242. For example, the upper gate electrode G2a and the upper gate dielectric film 244a may be formed on the third surface 242a of the first semiconductor layer 242, and the lower gate electrode G2b and the lower gate dielectric film 244b may be formed on the fourth surface 242b of the first semiconductor layer 242.

[0090] Referring to Figures 9 and 10d, in an image sensor 5 using another alternative embodiment structure for the S2 region, the first gate electrode G1 and the first photoelectric conversion layer 320 can be connected to the fourth surface 242b of the first semiconductor layer 242.

[0091] For example, the first light-shielding film 250 connected to the first gate electrode G1 and the first photoelectric conversion layer 320 may be connected to the fourth surface 242b of the first semiconductor layer 242. For example, the fourth via 234, the second wiring 236, and the fifth via 238 connecting the bottom surface of the first light-shielding film 250 and the fourth surface 242b of the first semiconductor layer 242 may be formed in the first interlayer insulating film 200. The first light-shielding film 250 may cover the entire third surface 242a of the first semiconductor layer 242. The first light-shielding film 250 may be connected to the first portion SP1 of the first semiconductor layer 242. The eighth via 212 and the fifth wiring 214 connected to the second portion SP2 of the first semiconductor layer 242 may be formed. In some embodiments, the eighth via 212 and the fifth wiring 214 may be connected to the fourth surface 242b of the first semiconductor layer 242. In some embodiments, the eighth via 212 and the fifth wiring 214 provide a predetermined electrical potential (e.g., a second V DD 2) can be provided.

[0092] 9 and 10e, in the image sensor 5 according to another alternative embodiment, the first light blocking film 250 may include a first sub-blocking film 250a and a second sub-blocking film 250b spaced apart from each other. The first sub-blocking film 250a may cover a portion of the third surface 242a of the first semiconductor layer 242, and the second sub-blocking film 250b may cover another portion of the third surface 242a of the first semiconductor layer 242. The first sub-blocking film 250a may be connected to the first gate electrode G1 and the first photoelectric conversion layer 320. The first sub-blocking film 250a may be connected to the first portion SP1 of the first semiconductor layer 242.

[0093] Figure 11 is a cross-sectional view illustrating a unit pixel region PU in an image sensor 5 according to some embodiments. Figures 12 and 13 are partial perspective views illustrating a structure showing another individual embodiment of the first light blocking layer of Figure 11. For convenience of explanation, parts that overlap with the contents explained in relation to Figures 1 to 7 will be briefly explained or omitted.

[0094] 11 to 13, in the image sensor according to some embodiments, the first light-shielding film 250 may include an upper surface portion 250P and a side surface portion 250V. The upper surface portion 250P may cover at least a part of the third surface 242a of the first semiconductor layer 242. The side surface portion 250V may cover the side surface of the first semiconductor layer 242. For example, the side surface portion 250V may extend from the upper surface portion 250P toward the first semiconductor layer 242. The upper surface portion 250P of the first light-shielding film 250 may cover the entire third surface 242a of the first semiconductor layer 242. As shown in FIG. 12, the side surface portion 250V of the first light-shielding film 250 may include a plurality of vias surrounding the side surface of the first semiconductor layer 242. As shown in FIG. 13, the side surface portion 250V of the first light-shielding film 250 may cover the entire side surface of the first semiconductor layer 242.

[0095] Figure 14 is also an exemplary circuit diagram of a unit pixel region of an image sensor 5 according to some other embodiments. Figures 15 and 16 are cross-sectional views illustrating other embodiments of a unit pixel unit PU in an image sensor 5 according to some embodiments using the circuit arrangement of Figure 14. For convenience of explanation, parts that overlap with the contents explained using Figures 1 to 13 will be briefly explained or omitted.

[0096] Referring to FIG. 14, the unit pixel region PU of the image sensor according to some embodiments may further include a second photoelectric conversion element PD2, a first transfer transistor TG, a second floating diffusion region FD2, a second reset transistor RG2, a second source follower transistor SF2 and a second selection transistor SEL2.

[0097] The second photoelectric conversion element PD2 can absorb light and accumulate a charge corresponding to the amount of light. The second photoelectric conversion element PD2 can include, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode, an organic photodiode, a quantum dot, and a combination thereof.

[0098] The second photoelectric conversion element PD2 may be coupled with a first transfer transistor TG that transfers the accumulated charge to the second floating diffusion region FD2. The first transfer transistor TG may transfer the charge generated from the second photoelectric conversion element PD2 to the second floating diffusion region FD2. The first transfer transistor TG may be driven by a transfer line that applies a predetermined bias. When the first transfer transistor TG is turned on, the charge generated from the second photoelectric conversion element PD2 may be transferred to the second floating diffusion region FD2.

[0099] The second source follower transistor SF2 can amplify the change in the electrical potential of the second floating diffusion region FD2 and provide it to the second output line OL2. For example, a predetermined electrical potential (e.g., a third V DD 3) is controlled by the second floating diffusion region FD2 and provided to the second output line OL2.

[0100] The second selection transistor SEL2 can select a unit pixel area to be read out on a row-by-row basis. When the second selection transistor SEL2 is turned on, a predetermined electrical potential provided to the drain of the second selection transistor SEL2 (e.g., an electrical potential provided from the source of the second source follower transistor SF2) is connected to the second output line (V OUT 2) can be output.

[0101] The second reset transistor RG2 can periodically reset the second floating diffusion region FD2. When the second reset transistor RG2 is turned on, a predetermined electrical potential (e.g., a fourth V DD 4) can be transferred to the second floating diffusion region FD2.

[0102] 14 and 15, an image sensor according to some embodiments may further include a second photoelectric conversion layer 110.

[0103] The second photoelectric conversion layer 110 can generate second photocharges in proportion to the amount of incident light IL incident from the outside. For example, the second photoelectric conversion layer 110 corresponds to the second photoelectric conversion element PD2 in FIG.

[0104] In some embodiments, the second photoelectric conversion layer 110 may be formed in the substrate 100. For example, the second photoelectric conversion layer 110 may be formed by doping impurities in the substrate 100. Also, there may be an impurity concentration difference between the upper and lower parts of the second photoelectric conversion layer 110 so that the second photoelectric conversion layer 110 has a potential gradient. For example, the second photoelectric conversion layer 110 may be formed in a form in which a plurality of impurity regions are stacked.

[0105] For convenience of explanation, various transistors for processing electrical signals connected to the second photoelectric conversion layer 110 are not shown. However, a portion of the substrate 100 may be used to arrange various transistors for processing electrical signals generated from the second photoelectric conversion layer 110. For example, a second transfer transistor (TG in FIG. 14), a second reset transistor (RG2 in FIG. 14), a second source follower transistor (SF2 in FIG. 14), and a second selection transistor (SEL2 in FIG. 14) may be formed on the first surface 100a of the substrate 100.

[0106] In some embodiments, the second photovoltaic layer 110 can include a semiconductor photovoltaic layer.

[0107] In some embodiments, a color filter 310 may be formed in the first interlayer insulating film 200. The color filter 310 may include, for example, one of a red filter or a blue filter. However, this is merely an example, and the color filter 310 may also include one of a green filter, a yellow filter, a magenta filter, a cyan filter, or a white filter.

[0108] In some embodiments, the second photovoltaic conversion layer 110 can sense light of a different wavelength than the first photovoltaic conversion layer 320.

[0109] For example, the first photoelectric conversion layer 320 can sense green light, and the second photoelectric conversion layer 110 can sense red or blue light. Specifically, light of a green wavelength in the incident light IL can be absorbed by the first photoelectric conversion layer 320. Therefore, the first photoelectric conversion layer 320 can provide an electrical signal for the green light. Light of other wavelengths except for the green light can pass through the first photoelectric conversion layer 320. The light that passes through the first photoelectric conversion layer 320 can pass through the color filter 310 to provide red or blue light to the second photoelectric conversion layer 110. Therefore, the second photoelectric conversion layer 110 can provide an electrical signal for the red or blue light.

[0110] 14 and 16, in an image sensor according to some embodiments, incident light IL may be incident on the second surface 100b of the substrate 100. A color filter 310 may be formed in the second interlayer insulating film 300.

[0111] Fig. 17 is an exemplary circuit diagram of a unit pixel region of an image sensor 5 according to some alternative embodiments. Figs. 18 and 19 are cross-sectional views illustrating a unit pixel unit PU according to some embodiments in an image sensor 5 using the circuit diagram of Fig. 17. For convenience of explanation, parts that overlap with the contents explained in relation to Figs. 1 to 16 will be briefly explained or omitted.

[0112] Referring to FIG. 17, the unit pixel region PU of the image sensor according to some embodiments may further include a third photoelectric conversion element PD3, a third floating diffusion region FD3, a third reset transistor RG3, a third source follower transistor, and a third selection transistor SEL3.

[0113] The third photoelectric conversion element PD3 can absorb light and accumulate electric charges corresponding to the amount of light. The first photoelectric conversion element PD1 can include, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode, an organic photodiode, a quantum dot, and combinations thereof.

[0114] The charge accumulated from the third photoelectric conversion element PD3 may be stored in the third floating diffusion region FD3.

[0115] The third source follower transistor SF3 can amplify the change in the electric potential of the third floating diffusion region FD3 and provide it to the third output line OL3. For example, a predetermined electric potential (e.g., 5th V DD 5) is controlled by the third floating diffusion region FD3 and provided to the third output line OL3.

[0116] The third selection transistor SEL3 may select a unit pixel region to be read out on a row-by-row basis. When the third selection transistor SEL3 is turned on, a predetermined electrical potential provided to the drain of the third selection transistor SEL3 (e.g., an electrical potential provided from the source of the third source follower transistor SF3) may be output to the third output line OL3.

[0117] The third reset transistor RG3 can periodically reset the third floating diffusion region FD3. When the third reset transistor RG3 is turned on, a predetermined electrical potential (e.g., a third V DD 3) may be transferred to the third floating diffusion region FD3.

[0118] 17 and 18, an image sensor according to some embodiments may further include a third photoelectric conversion layer 420, a third gate electrode G3, a second transistor structure TR2, and a second light-shielding film 2502.

[0119] The third photoelectric conversion layer 420 can generate third photocharges in proportion to the amount of incident light IL incident from the outside. For example, the third photoelectric conversion layer 420 corresponds to the third photoelectric conversion element PD3 in FIG.

[0120] The third photoelectric conversion layer 420 may be formed outside the substrate 100. For example, the third photoelectric conversion layer 420 may be formed on the third interlayer insulating film 400 on the second photoelectric conversion layer 110. The third photoelectric conversion layer 420 may be formed on the first surface 100a of the substrate 100 and may be separated from the substrate 100 by the first interlayer insulating film 200 and the third interlayer insulating film 400.

[0121] A second lower electrode 422 and a second upper electrode 424 may be formed adjacent to the third photoelectric conversion layer 420. The third photoelectric conversion layer 420 may be interposed between the second lower electrode 422 and the second upper electrode 424.

[0122] Voltages of different levels may be applied to the second lower electrode 422 and the second upper electrode 424 individually. For example, voltages of different levels may be applied to the second lower electrode 422 and the second upper electrode 424 so that an electrical signal generated from the third photoelectric conversion layer 420 is directed to the second lower electrode 422.

[0123] The second lower electrode 422 and the second upper electrode 424 may include a transparent conductive material. The third photoelectric conversion layer 420 may include an organic photoelectric conversion layer.

[0124] The third gate electrode G3 may be formed on the first surface 100a of the substrate 100. In some embodiments, the third gate electrode G3 may constitute a third source follower transistor SF3. For example, the third source follower transistor SF3 may include a third gate dielectric film 1222 and a third gate electrode G3 formed on the active region 120.

[0125] The second transistor structure TR2 may be formed on the first surface 100a of the substrate 100. For example, the second transistor structure TR2 may be formed in the first interlayer insulating film 200.

[0126] The second transistor structure TR2 may include a second semiconductor layer 2422, a fourth gate dielectric film 2442 and a fourth gate electrode G4. The second transistor structure TR2 is similar to the first transistor structure TR1, and therefore will not be described in detail below.

[0127] The second semiconductor layer 2422 may form a third floating diffusion region FD3. For example, one end of the second semiconductor layer 2422 may be connected to the third gate electrode G3 and the third photoelectric conversion layer 420.

[0128] A second through via 2602 may be formed to penetrate the first photoelectric conversion layer 320 and connect to the first semiconductor layer 242. The third photoelectric conversion layer 420 may be connected to the first semiconductor layer 242 through the second through via 2602. The third photoelectric conversion layer 420 may be electrically insulated from the first photoelectric conversion layer 320, the first lower electrode 322, and the first upper electrode 324 through a second spacer 2604.

[0129] The second transistor structure TR2 including the second semiconductor layer 2422 may form the third reset transistor RG3.

[0130] The second light blocking film 2502 may cover at least a portion of the second semiconductor layer 2422 from incident light IL. In some embodiments, the second through via 2602 may connect the second lower electrode 422 and the second light blocking film 2502.

[0131] 17 and 19, in an image sensor according to some embodiments, incident light IL may be incident on the second surface 100b of the substrate 100.

[0132] A third through via 1602 may be formed that penetrates the substrate 100 and the first photoelectric conversion layer 320 and is connected to the second semiconductor layer 2422. The third photoelectric conversion layer 420 may be connected to the second semiconductor layer 2422 through the third through via 1602. The third through via 1602 may include a third plug pattern 1622 including a conductive material and a third spacer 1642 including an insulating material. The third plug pattern 1622 may be electrically insulated from the substrate 100, the first photoelectric conversion layer 320, the first lower electrode 322, and the first upper electrode 324 through the third spacer 1642.

[0133] In some embodiments, the second light blocking film 2502 can be in contact with the second semiconductor layer 2422 .

[0134] Figure 20 is an exemplary circuit diagram of a unit pixel region of an image sensor 5 according to some other embodiments. Figure 21 is a schematic layout diagram illustrating a unit pixel region of an image sensor according to some embodiments. Figure 22 is a cross-sectional view taken along CC in Figure 21. Figures 23a to 23e are various enlarged views of an S3 region in Figure 22. For convenience of explanation, parts that overlap with those described in relation to Figures 1 to 7 will be briefly explained or omitted.

[0135] Referring to FIG. 20, the unit pixel area PU in this embodiment may further include a second transfer transistor TX, a storage element CAP, a control transistor CAL and a fourth source follower transistor SF4.

[0136] The first photoelectric conversion element PD1 may be coupled with a second transfer transistor TX that transfers the accumulated charge to the first floating diffusion region FD1. The second transfer transistor TX may transfer the charge generated from the first photoelectric conversion element PD1 to the first floating diffusion region FD1. The second transfer transistor TX may be driven by a transfer line that applies a predetermined bias. When the second transfer transistor TX is turned on, the charge generated from the first photoelectric conversion element PD1 may be transferred to the first floating diffusion region FD1.

[0137] The first source follower transistor SF1 can amplify the change in the electrical potential of the first floating diffusion region FD1 and provide it to the storage element CAP. For example, a predetermined electrical potential (e.g., the third V DD 1) is provided on one side of the storage element CAP and is controlled by a first floating diffusion region FD1.

[0138] The control transistor CAL can control the electrical potential of the first node Y. The control transistor CAL can be driven by a control line that applies a predetermined bias. For example, when the control transistor CAL is turned on, a predetermined electrical potential (e.g., a second V DD 2) may be communicated to the first node Y.

[0139] The storage element CAP is interposed between the source of the first source follower transistor SF1 and the first node Y, and can store an electrical signal provided from the first source follower transistor SF1. Some embodiments of the storage element CAP may be, for example, a high capacity capacitor (supercapacitor or ultracapacitor) such as an electric double layer capacitor (EDLC), or a metal-insulator-metal (MIM) capacitor, etc.

[0140] The fourth source follower transistor SF4 may act as a source follower buffer amplifier controlled by the first node Y. The fourth source follower transistor SF4 may amplify a change in the electrical potential of the first node Y and provide it to a fourth output line OL4. For example, a predetermined electrical potential (e.g., a first V DD 1) may be controlled by the first floating diffusion region FD1 and provided to the fourth output line OL4.

[0141] 20 to 23a, an image sensor 5 according to some embodiments may include a fifth gate electrode G5, a first source / drain region (FD1; e.g., the first floating diffusion region in FIG. 20), a sixth gate electrode G6, a second source / drain region 105a, a third source / drain region 105b and a capacitor structure 500.

[0142] The fifth gate electrode G5 may be formed on the first surface 100a of the substrate 100. In some embodiments, the fifth gate electrode G5 may constitute a second transfer transistor TX.

[0143] The first source / drain region FD1 may be formed in the active region 120 disposed on one side of the fifth gate electrode G5. For example, the first source / drain region FD1 may be formed by doping impurities in the active region 120. In some embodiments, the first source / drain region FD1 may form the first floating diffusion region FD1 of FIG. 20. Therefore, the second transfer transistor TX may transfer the first photocharges generated from the second photoelectric conversion layer 110 to the first source / drain region (FD1; or the first floating diffusion region FD1 of FIG. 20).

[0144] In some embodiments, the second photoelectric conversion layer 110 corresponds to the first photoelectric conversion element PD1 in FIG.

[0145] The sixth gate electrode G6 may be formed on the first surface 100a of the substrate 100. In some embodiments, the sixth gate electrode G6 may constitute a first source follower transistor SF1. For example, the first source / drain region FD1 may be connected to the sixth gate electrode G6.

[0146] The second source / drain region 105a and the third source / drain region 105b may be formed in the active region 120 disposed on both sides of the sixth gate electrode G6. For example, the second source / drain region 105a and the third source / drain region 105b may be formed by doping impurities into the active region 120.

[0147] In some embodiments, the second source / drain region 105a is provided with a predetermined electrical potential (e.g., a first V DD Therefore, the first source follower transistor SF1 can amplify the electric potential change of the first source / drain region FD1 and provide it to the third source / drain region 105b.

[0148] The capacitor structure 500 may be connected with the first gate electrode G1, the first semiconductor layer 242 and the third source / drain region 105b. For example, the capacitor structure 500 may include a first capacitor electrode 510, a second capacitor electrode 530 and a capacitor dielectric film 520.

[0149] The first capacitor electrode 510 may be connected to the first portion SP1 of the first semiconductor layer 242 by, for example, a ninth via 280 in the first interlayer insulating film 200. The first portion SP1 of the first semiconductor layer 242 may be connected to the first gate electrode G1 by a first via 220.

[0150] In some embodiments, the first gate electrode G1 may constitute a fourth source follower transistor SF4. In some embodiments, the first transistor structure TR1 may constitute a control transistor CAL. That is, the first portion SP1 of the first semiconductor layer 242 corresponds to the first node Y in FIG. 20.

[0151] The second capacitor electrode 530 can be connected to the third source / drain region 105b by, for example, a sixth wiring 290 and a tenth via 292 in the first interlayer insulating film 200.

[0152] The capacitor dielectric layer 520 may be interposed between the first capacitor electrode 510 and the second capacitor electrode 530. In some embodiments, the capacitor structure 500 may form a storage element CAP. For example, the capacitor structure 500 may store charges in the capacitor dielectric layer 520 using a potential difference generated between the first capacitor electrode 510 and the second capacitor electrode 530. Thus, the capacitor structure 500 may store an electrical signal provided from the sixth gate electrode G6.

[0153] Referring to Figures 22 and 23a, in an image sensor according to some embodiments, the first gate electrode G1 may be connected to the third surface 242a of the first semiconductor layer 242, and the first capacitor electrode 510 may be connected to the fourth surface 242b of the first semiconductor layer 242.

[0154] 22 and 23b, in the image sensor according to some embodiments, the second gate electrode G2 and the second gate dielectric film 244 may be formed on the fourth surface 242b of the first semiconductor layer 242.

[0155] 22 and 23c, in an image sensor according to some embodiments, the second gate electrode G2 and the second gate dielectric film 244 may be both formed on the third surface 242a and the fourth surface 242b of the first semiconductor layer 242.

[0156] 22 and 23d, in the image sensor according to some embodiments, the second gate electrode G2 and the first capacitor electrode 510 may be connected to the fourth surface 242b of the first semiconductor layer 242.

[0157] 22 and 23e, in an image sensor according to some embodiments, a first light blocking layer 250 may include a first sub-blocking layer 250a and a second sub-blocking layer 250b spaced apart from each other.

[0158] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, and can be manufactured in various different forms, and a person having ordinary skill in the art to which the present invention belongs can understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0159] 5: Image sensor 10: Active pixel sensor array 20: Row Decoder 30: Row driver 40: Column decoder 50: Timing generator 60: Correlated double sampler 70: Analog-to-digital converter 80: Input / output buffer 100: Substrate 110: second photoelectric conversion layer 130: Element isolation film 200: First interlayer insulating film 250: First light blocking film 2502: Second light shielding film 320: First photoelectric conversion layer 340: Microlens 420: Third photoelectric conversion layer 500 Capacitor Structure TR1: first transistor structure TR2: second transistor structure

Claims

1. a substrate including opposing first and second surfaces; a first transistor including a first gate on the first surface; a photoelectric conversion layer that generates photocharges from incident light incident in a first direction; a second transistor between the first surface and the photoelectric conversion layer and spaced apart from the photoelectric conversion layer, the second transistor including a transistor structure including a semiconductor layer including a metal oxide semiconductor material and including a third surface extending in a direction perpendicular to the first direction and a fourth surface opposite to the third surface, a second gate being disposed on the semiconductor layer, the semiconductor layer being connected to the first gate; a light blocking film between the third surface and the photoelectric conversion layer and spaced apart from the photoelectric conversion layer; The light blocking film is electrically connected to the semiconductor layer.

2. The image sensor of claim 1 , wherein the second gate is disposed on the fourth surface of the semiconductor layer.

3. The image sensor of claim 1 , wherein the second gate is disposed on the third surface of the semiconductor layer.

4. The image sensor of claim 3 , wherein the transistor structure further comprises a third gate disposed on the fourth surface of the semiconductor layer.

5. The image sensor of claim 1 , wherein the light blocking film includes a top surface portion covering at least a portion of the third surface of the semiconductor layer, and a side surface portion covering at least a portion of a side surface of the semiconductor layer.

6. The image sensor of claim 5 , wherein the side portions of the light-shielding film include a plurality of vias each connected to the top portion of the light-shielding film.

7. The light shielding film is a first sub-blocking film covering a portion of the third surface of the semiconductor layer; 2. The image sensor of claim 1, further comprising a second sub-blocking layer spaced apart from the first sub-blocking layer and covering another portion of the third surface of the semiconductor layer.

8. The image sensor of claim 1 , wherein the light blocking film is in contact with the third surface of the semiconductor layer.

9. a first via connecting a first portion of the semiconductor layer disposed on one side of the second gate to the first gate; The image sensor of claim 1 , further comprising a second via connected to the first portion of the semiconductor layer.

10. The image sensor of claim 1 , wherein the semiconductor layer comprises indium gallium zinc oxide (IGZO).

11. a substrate including opposing first and second surfaces; a source follower transistor including a first gate on the first surface of the substrate; a first photoelectric conversion layer separate from the substrate and on the second surface, the first photoelectric conversion layer generating first photocharges from incident light; a transistor structure disposed adjacent the first surface of the substrate, the transistor structure including a semiconductor layer including a metal oxide semiconductor material and a second gate on a central region of the semiconductor layer; a light shielding film between the first photoelectric conversion layer and the transistor structure, the light shielding film being spaced apart from the first photoelectric conversion layer and covering at least a part of the semiconductor layer from the incident light; a through via that penetrates the substrate and connects the first photoelectric conversion layer and the light blocking film; A first portion of the semiconductor layer disposed on one side of the central region is connected to the first gate and the first photoelectric conversion layer.

12. the first photoelectric conversion layer is disposed on the first surface of the substrate; The image sensor of claim 11 , wherein the transistor structure is interposed between the substrate and the first photoelectric conversion layer.

13. The image sensor of claim 11 , wherein the first photoelectric conversion layer is disposed on the second surface of the substrate.

14. The image sensor of claim 13 , further comprising a through via extending through the substrate and connecting the first photoelectric conversion layer and the first portion of the semiconductor layer.

15. the first portion of the semiconductor layer is a floating diffusion region that stores the first photocharges generated from the first photoelectric conversion layer; 12. The image sensor of claim 11, wherein the transistor structure is a reset transistor structure that periodically resets the floating diffusion region.

16. The image sensor of claim 11 , further comprising a second photoelectric conversion layer in the substrate for generating second photocharges from the incident light.

17. The first photoelectric conversion layer includes an organic photoelectric conversion layer, The image sensor of claim 16 , wherein the second photoelectric conversion layer comprises a semiconductor photoelectric conversion layer.

18. a substrate including opposing first and second surfaces; a first transistor including a first gate on the first surface of the substrate; a photoelectric conversion layer within the substrate for generating photocharges from incident light; a second transistor disposed adjacent to the first surface of the substrate, the second transistor including a transistor structure including a semiconductor layer including a metal oxide semiconductor material and a second gate on a central region of the semiconductor layer; a light shielding film disposed adjacent to the first surface of the substrate and covering at least a portion of the semiconductor layer from the incident light; A capacitor structure is included. a first portion of the semiconductor layer located at an end portion of the semiconductor layer is connected to the first gate and the capacitor structure; the light blocking film is electrically connected to the semiconductor layer and the first transistor; Image sensor.

19. a first source / drain region in the substrate for storing the photocharges generated from the photoelectric conversion layer; a first source follower transistor on the first surface of the substrate, the first source follower transistor including a third gate connected to the first source / drain region and a second source / drain region disposed on one side of the third gate; 20. The image sensor of claim 18, wherein the capacitor structure is connected to the second source / drain region.

20. the capacitor structure includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric layer between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the first portion of the semiconductor layer and to the first gate; 20. The image sensor of claim 19, wherein the second capacitor electrode is connected to the second source / drain region.

Images