Vertical Memory Device

Abstract

To provide a vertical memory device in which memory cell density can be increased by vertically stacking memory cells to form a three-dimensional structure, and parasitic capacitance can be reduced.SOLUTION: A memory device according to the present technology includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line. The transistor may include: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a pair of line-shaped word lines that are vertically stacked with the active layer therebetween and extend to intersect with the active layer.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to memory devices. [Background technology]

[0002] In recent years, the size of memory cells has been continuously reduced in order to increase the net die of memory devices.

[0003] As the size of the memory cell is miniaturized, the parasitic capacitance Cb should be reduced and the capacitance should be increased, but due to structural limitations of the memory cell, it is difficult to increase the net die. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE DISCLOSURE The embodiments of the present invention provide a highly integrated vertical memory cell and a memory device having the same. [Means for solving the problem]

[0005] A memory device according to an embodiment of the present invention may include a substrate, a bit line vertically oriented from the substrate, a plate line vertically oriented from the substrate, and a memory cell including a transistor and a capacitor located in a horizontal arrangement between the bit line and the plate line, and the transistor may include an active layer horizontally oriented to be parallel to the substrate between the bit line and the capacitor, and a pair of line-shaped word lines stacked vertically across the active layer and extending to cross the active layer.

[0006] A memory device according to an embodiment of the present invention may include a substrate, a bit line vertically oriented from the substrate, a plate line vertically oriented from the substrate, and a plurality of memory cells stacked between the bit line and the plate line in a vertical direction from the substrate, each of the memory cells including a transistor having an active layer horizontally oriented to be parallel to the substrate between the bit line and the plate line, and a pair of line-shaped word lines vertically stacked on either side of the active layer and extending to cross the active layer, and a capacitor including cylindrical first and second nodes horizontally oriented to be parallel to the substrate between the transistor and the plate line, and a dielectric material between the cylindrical first and second nodes. Effect of the Invention

[0007] This technology increases cell density and reduces parasitic capacitance by vertically stacking memory cells into a three-dimensional structure.

[0008] The present technique can prevent interference between vertically stacked memory cells because the memory cell transistors include double word lines.

[0009] The present technique forms vertical bit lines, thereby reducing bit line resistance.

[0010] This technology vertically stacks memory cells above or below a peripheral circuit section, thereby enabling a highly integrated memory device to be realized in a limited area. [Brief description of the drawings]

[0011] [Figure 1] 1 is an equivalent circuit diagram for explaining a memory device; [Diagram 2] FIG. 2 is a perspective view for explaining a mirror type structure sharing a plate line in FIG. [Diagram 3] FIG. 3 is an equivalent circuit diagram for explaining the mirror type structure of FIG. 2. [Figure 4] FIG. 2 is a perspective view illustrating a mirror structure sharing a bit line in FIG. [Diagram 5] FIG. 2 is a cross-sectional view for explaining the memory device of FIG. [Figure 6] FIG. 2 is a plan view for explaining the memory device of FIG. [Figure 7] FIG. 2 is a perspective view showing the details of a memory cell. [Figure 8] 8 is a cross-sectional view taken along the A1-A1' direction in FIG. 7. [Figure 9] 8 is a plan view taken along the A2-A2' direction in FIG. 7. FIG. [Figure 10] FIG. 2 is a detailed perspective view of a capacitor. [Figure 11A] 13 is a diagram for explaining a first node of a capacitor having a three-dimensional structure according to another embodiment. FIG. [Figure 11B] 13 is a diagram for explaining a first node of a capacitor having a three-dimensional structure according to another embodiment. FIG. [Figure 11C] 13 is a diagram for explaining a first node of a capacitor having a three-dimensional structure according to another embodiment. FIG. [Figure 12A] 11 is a diagram illustrating a memory device according to another embodiment; [Figure 12B] 11 is a diagram illustrating a memory device according to another embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the most preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings in order to enable those skilled in the art to easily implement the technical concept of the present invention.

[0013] The embodiments described below allow memory cells to be stacked vertically to increase cell density and reduce parasitic capacitance.

[0014] In the embodiment described below, the memory device may include a substrate, a bit line oriented vertically from the substrate, a plate line oriented vertically from the substrate, and a memory cell including a transistor and a capacitor arranged in a horizontal arrangement between the bit line and the plate line. The transistor may include an active layer oriented horizontally to be parallel to the substrate between the bit line and the capacitor, and a pair of line-shaped word lines vertically stacked with the active layer sandwiched therebetween and extending to cross the active layer. Here, the pair of word lines may include a line-shaped lower word line and a line-shaped upper word line.

[0015] FIG. 1 is an equivalent circuit diagram for explaining a memory device. FIG. 2 is a perspective view for explaining a mirror type structure 100A sharing a plate line in FIG. 1. FIG. 3 is an equivalent circuit diagram for explaining the mirror type structure in FIG. 2. FIG. 4 is a perspective view for explaining a mirror type structure 100B sharing a bit line in FIG. 1. FIG. 5 is a cross-sectional view for explaining the memory device in FIG. 1. FIG. 6 is a plan view for explaining the memory device in FIG. 1.

[0016] The memory device 100 may include a peripheral structure 110 and a memory cell array stack MCA, and the memory cell array stack MCA may be located above the peripheral structure 110. In another embodiment, the memory cell array stack MCA may be located below the peripheral structure 110. The memory cell array stack MCA may include a plurality of memory cell arrays MCA. L , M.C.A. U In this embodiment, the memory cell array stack MCA may include a DRAM memory cell array.

[0017] The memory device 100 includes two memory cell arrays MCA on a peripheral structure 110. L , M.C.A. UHere, the number of memory cell arrays stacked on the peripheral structure 110 may be n (n=an integer of 2 or more). L , M.C.A. U Alternatively, a plurality of pairs may be stacked vertically on the peripheral structure 110. L , M.C.A. U Alternatively, multiple pairs may be arranged horizontally on the peripheral structure 110.

[0018] The peripheral structure 110 may be a material suitable for semiconductor processing. The peripheral structure 110 may include a substrate. For example, the peripheral structure 110 may include a semiconductor substrate, which may include a silicon substrate, a single crystal silicon substrate, a polysilicon substrate, an amorphous silicon substrate, a silicon germanium substrate, a single crystal silicon germanium substrate, a polycrystalline silicon germanium substrate, a carbon-doped silicon substrate, a combination thereof, or a multi-layer thereof. The peripheral structure 110 may include other semiconductor materials, such as germanium. The peripheral structure 110 may include a compound semiconductor substrate, such as a III / V semiconductor substrate, e.g., GaAs. The peripheral structure 110 may include a silicon on insulator (SOI) substrate. The peripheral structure 110 may be a stacked structure of a semiconductor substrate and an insulating material.

[0019] The surface of the peripheral structure 110 may include a surface of a substrate. The surface of the peripheral structure 110 may include a plane CP. The memory cell array stack MCA may be located perpendicular to the plane CP of the peripheral structure 110. The memory cell array stack MCA may be formed along a first direction D1 perpendicular to the surface of the peripheral structure 110, i.e., the plane CP. The first direction D1 may be perpendicular to the plane CP, and the second direction D2 and the third direction D3 may be parallel to the plane CP. The second direction D2 and the third direction D3 may intersect with each other, and the first direction D1 may intersect with the second direction D2 and the third direction D3. Two memory cell arrays MCA L , M.C.A. U Alternatively, a plurality of pairs may be stacked vertically on the peripheral structure 110 along the first direction D1.

[0020] The plane CP of the peripheral structure 110 may include a first plane CP1 and a second plane CP2. The first plane CP1 and the second plane CP2 may be spaced apart from each other along a second direction D2 perpendicular to the first direction D1. The first plane CP1 and the second plane CP2 may be surfaces of the same material. The first plane CP1 and the second plane CP2 may be surfaces of different materials, etc. The first plane CP1 and the second plane CP2 may be electrically insulated. The plane CP may be provided by an insulating material. The top surface of the peripheral structure 110 may provide the plane CP. The top surface of the peripheral structure 110 may be an insulating material or a conductive material. The first plane CP1 and the second plane CP2 may be an insulating material or a conductive material. The first plane CP1 may be a conductive material, and the second plane CP2 may be an insulating material.

[0021] The peripheral structure 110 may include at least one peripheral circuit unit for controlling the memory cell array stack MCA. The at least one peripheral circuit unit may be formed under the memory cell array stack MCA. The at least one peripheral circuit unit may include at least one circuit selected from among sense amplifiers and sub-wordline drivers.

[0022] Two memory cell arrays MCA L , M.C.A. U may be arranged above the plane CP of the peripheral structure 110. For convenience of explanation, two memory cell arrays MCA L , M.C.A. U The lower memory cell array (MCA) L ) and the upper memory cell array (MCA U ) are abbreviated as MCA. L , M.C.A. U Alternatively, a plurality of pairs may be arranged horizontally along the third direction D3 on the peripheral structure 110. For example, as shown in FIGS. L1 , M.C.A. L2 may be horizontally arranged along a third direction D3, and the upper memory cell array MCA U1 , M.C.A. U2 may be arranged horizontally along a third direction D3.

[0023] The memory cell array stack MCA includes a plurality of word lines WL L1 , W.L. L2 , W.L. U1 , W.L. U2 , W.L. L3 , W.L. U3 , a plurality of bit lines BL1, BL2, BL3, BL4, a plurality of memory cells MC L1 , M.C. L2 , M.C. L3 , M.C. L4 , M.C.L5 , M.C. L6 , M.C. U1 , M.C. U2 , M.C. U3 , M.C. U4 , M.C. U5 , M.C. U6 ) and a plurality of plate lines PL1, PL2. However, the numbers of word lines, bit lines, memory cells, and plate lines are merely examples and are not limited thereto.

[0024] Lower memory cell array MCA L is a plurality of word lines WL L1 , W.L. L2 , W.L. L3 , a plurality of bit lines BL1, BL2, BL3, BL4, a plurality of memory cells MC L1 , M.C. L2 , M.C. L3 , M.C. L4 , M.C. L5 , M.C. L6 , and a plurality of plate lines PL1, PL2. U is a plurality of word lines WL U1 , W.L. U2 , W.L. U3 , a plurality of bit lines BL1, BL2, BL3, BL4, a plurality of memory cells MC U1 , M.C. U2 , M.C. U3 , M.C. U4 , M.C. L5 , M.C. L6 , and a plurality of plate lines PL1, PL2.

[0025] The plurality of bitlines BL1, BL2, BL3, BL4 may extend in a first direction D1 perpendicular to the plane CP of the peripheral structure 110. The bitlines BL1, BL2, BL3, BL4 may directly contact the plane CP of the peripheral structure 110. The bitlines BL1, BL2, BL3, BL4 may be vertically oriented from the plane CP. The bitlines BL1, BL2, BL3, BL4 may be referred to as vertical bitlines (VBL). The bitlines BL1, BL2, BL3, BL4 may be parallel to each other. The bitlines BL1, BL2, BL3, BL4 may be independently arranged horizontally along the second direction D2 and the third direction D3. The bitlines BL1, BL2 may be independently arranged along the second direction D2. The bitlines BL1, BL3 may be independently arranged along the third direction D3. The bit lines BL2 and BL4 may be independently arranged along a third direction D3.

[0026] With respect to the bit line BL1, one memory cell MC L1 A plurality of memory cells MC are arranged vertically along a first direction D1. L1 , M.C. U1 can be connected to one bit line BL1. L and the upper memory cell array MCA U may share one bit line BL1. Another bit line BL3 may be located horizontally spaced apart from the bit line BL1 in a third direction D3, and the other bit line BL3 may be oriented vertically from the plane CP. L3 , M.C. U3 can be stacked vertically from the plane CP between the other bit line BL3 and the plate line PL1. L1 , M.C. U1can share the plate line PL1 and the bit line BL1. L3 , M.C. U3 can share the plate line PL1 and the bit line BL3.

[0027] With respect to the bit line BL2, one memory cell MCL2 may be connected to one bit line BL2. L2 , M.C. U2 can be connected to one bit line BL2. L and the upper memory cell array MCA U may share one bit line BL2. Another bit line BL4 may be located horizontally spaced apart from the bit line BL2 in a third direction D3, and the other bit line BL4 may be oriented vertically from the plane CP. L4 , M.C. U4 can be stacked vertically from the plane CP between the other bit line BL4 and the plate line PL1. L2 , M.C. U2 can share the plate line PL1 and the bit line BL2. L4 , M.C. U4 can share the plate line PL1 and the bit line BL4.

[0028] With respect to the bit line BL3, one memory cell MC L3 A plurality of memory cells MC arranged vertically along a first direction D1 may be connected to each other. L3 , M.C. U3 can be connected to one bit line BL3. L and the upper memory cell array MCA U can share one bit line BL3.

[0029] Referring to the bit line BL4, one memory cell MCL4 may be connected to one bit line BL4. L4 , M.C. U4 can be connected to one bit line BL4. L and the upper memory cell array MCA U can share one bit line BL4.

[0030] As described above, the lower memory cell array MCA L and the upper memory cell array MCA U may include bit lines BL1, BL2, BL3, and BL4, respectively. L and the upper memory cell array MCA U can share bit lines BL1, BL2, BL3, and BL4, respectively.

[0031] Multiple word lines WL L1 , W.L. L2 , W.L. U1 , W.L. U2 , W.L. L3 , W.L. U3 The word lines WL may extend in a third direction D3 that is parallel to the surface of the peripheral structure 110 and intersects with the first direction D1. L1 , W.L. L2 , W.L. U1 , W.L. U2 , W.L. L3 , W.L. U3 The word line WL can be referred to as a lateral word line. L1 , W.L. L2 , W.L. U1 , W.L. U2 , W.L. L3 , W.L. U3 may be arranged in a direction intersecting the bit lines BL1, BL2, BL3, and BL4. L1 , W.L. L2 , W.L. L3may be at the same level along the second direction D2 and the third direction D3, and the lower memory cell array MCA L A plurality of word lines WL U1 , W.L. U2 , W.L. U3 may be at the same level along the second direction D2 and the third direction D3, and the upper memory cell array MCA U can be located at

[0032] Word Line WL L1 Based on this, one word line WL L1 One memory cell MC L1 A plurality of memory cells MC arranged horizontally along a third direction D3 may be connected to the memory cells MC. L1 , M.C. L3 There is one word line WL L1 can be connected to

[0033] Word Line WL L2 Based on this, one word line WL L2 One memory cell MC L2 A plurality of memory cells MC arranged horizontally along a third direction D3 may be connected to the memory cells MC. L2 , M.C. L4 There is one word line WL L2 can be connected to

[0034] Word Line WL L3 Based on this, one word line WL L3 One memory cell MC L5 A plurality of memory cells MC arranged horizontally along a third direction D3 may be connected to the memory cells MC. L5 , M.C. L6 There is one word line WL L3 can be connected to

[0035] Word Line WL U1 Based on this, one word line WL U1 One memory cell MCU1 A plurality of memory cells MC arranged horizontally along a third direction D3 may be connected to the memory cells MC. U1 , M.C. U3 There is one word line WL U1 can be connected to

[0036] Word Line WL U2 Based on this, one word line WL U2 One memory cell MC U2 A plurality of memory cells MC arranged horizontally along a third direction D3 may be connected to the memory cells MC. U2 , M.C. U4 There is one word line WL U2 can be connected to

[0037] Word Line WL U3 Based on this, one word line WL U3 One memory cell MC U5 A plurality of memory cells MC arranged horizontally along a third direction D3 may be connected to the memory cells MC. U5 , M.C. U6 There is one word line WL U3 can be connected to

[0038] As described above, the lower memory cell array MCA L are word lines WL parallel to each other along the second direction D2. L1 , W.L. L2 , W.L. L3 The upper memory cell array MCA U are word lines WL parallel to each other along the second direction D2. U1 , W.L. U2 , W.L. U3 The lower memory cell array MCA L Word Line WL L1 , W.L. L2 , W.L. L3 and the upper memory cell array MCA U Word Line WL U1 , W.L. U2 , W.L. U3and may be arranged vertically along the first direction D1.

[0039] Lower memory cell array MCA L and the upper memory cell array MCA U may share one plate line PL1, PL2. The plate lines PL1, PL2 may extend vertically along a first direction D1 from a plane CP of the peripheral structure 110. The plate lines PL1, PL2 may directly contact the plane CP of the peripheral structure 110. In other embodiments, the plate lines PL1, PL2 may not contact the plane CP of the peripheral structure 110. The plate lines PL1, PL2 may be connected to the word lines WL L1 , W.L. L2 , W.L. L3 , W.L. U1 , W.L. U2 , W.L. U3 and may be parallel to the bit lines BL1, BL2, BL3, and BL4. The plate lines PL1 and PL2 may be set at a fixed potential (e.g., ground potential). In this embodiment, the plate lines PL1 and PL2 may be oriented in a first direction D1 perpendicular to the plane CP of the peripheral structure 110 and may extend long in a third direction D3 intersecting the first direction D1. The plate lines PL1 and PL2 may be vertically oriented from the plane CP. The plate lines PL1 and PL2 may be referred to as vertical plate lines VPL. The plate lines PL1 and PL2 may be linear-shaped pillars that extend vertically along the first direction D1 and horizontally along the third direction D3.

[0040] The bit lines BL1, BL2, BL3, BL4 and the plate lines PL1, PL2 may be spaced apart from each other on a plane CP. The bit lines BL1, BL2, BL3, BL4 and the plate lines PL1, PL2 may be oriented perpendicular to the plane CP in a first direction D1. As shown in FIG. 3, the bit lines BL1, BL2, BL3, BL4 may be connected to a first plane CP1, and the plate lines PL1, PL2 may be connected to a second plane CP2. The bit lines BL1, BL2, BL3, BL4 and the plate lines PL1, PL2 may be electrically insulated.

[0041] Memory cell MC L1 , M.C. L2 , M.C. L3 , M.C. L4 , M.C. U1 , M.C. U2 , M.C. U3 , M.C. U4 Each of the memory cells MC can be located between the bit lines BL1, BL2, BL3, and BL4 and the plate lines PL1 and PL2. L1 , M.C. L2 , M.C. L3 , M.C. L4 , M.C. U1 , M.C. U2 , M.C. U3 , M.C. U4 The memory cells MC may be arranged in a lateral arrangement (LA) along a second direction D2 parallel to the plane CP. L1 , M.C. L2 , M.C. L3 , M.C. L4 , M.C. U1 , M.C. U2 , M.C. U3 , M.C. U4 may be located above the surrounding structure 110, spaced apart from the plane CP.

[0042] Memory cell MC L1 , M.C. L2 , M.C. L3 , M.C. L4 , M.C. U1 , M.C.U2 , M.C. U3 , M.C. U4 each of the bit lines BL1, BL2, BL3, and BL4, and the word line WL L1 , W.L. L2 , W.L. U1 , W.L. U2 The plate lines PL1, PL2 and the bit lines BL1, BL2, BL3, BL4 may be spaced apart from each other, and a memory cell MC may be provided between each of the plate lines PL1, PL2 and the bit lines BL1, BL2, BL3, BL4. L1 , M.C. L2 , M.C. L3 , M.C. L4 , M.C. U1 , M.C. U2 , M.C. U3 , M.C. U4 can be located.

[0043] Memory cell MC L1 Based on this, one memory cell MC is connected to one plate line PL1. L1 A plurality of memory cells MC arranged vertically along a first direction D1 may be connected to each other. L1 , M.C. U1 A plurality of memory cells MC arranged horizontally along a second direction D2 can be connected to one plate line PL1. L1 , M.C. L2 A plurality of memory cells MC arranged horizontally along a third direction D3 may be connected to one plate line PL1. L1 , M.C. L3 can be connected to one plate line PL1.

[0044] Memory cell MC L1 , M.C. L2 , M.C. L3 , M.C. L4 , M.C. U1 , M.C. U2 , M.C. U3 , M.C.U4 are transistors T L1 , T L2 , T L3 , T L4 , T U1 , T U2 , T U3 , T U4 and capacitor C L1 , C L2 , C L3 , C L4 , C U1 , C U2 , C U3 , C U4 The transistor T L1 , T L2 , T L3 , T L4 , T U1 , T U2 , T U3 , T U4 and capacitor C L1 , C L2 , C L3 , C L4 , C U1 , C U2 , C U3 , C U4 can be located between the bit lines BL1, BL2, BL3, BL4 and the plate lines PL1, PL2. L1 , T L2 , T L3 , T L4 , T U1 , T U2 , T U3 , T U4 and capacitor C L1 , C L2 , C L3 , C L4 , C U1 , C U2 , C U3 , C U4 can be positioned in a horizontal array LA extending along a second direction D2 parallel to the plane CP.

[0045] 1, 2 and 3, a plate line sharing mirror structure 100A will be described.

[0046] Memory cell MC L1 , M.C. L2 may be arranged in a mirror structure in which the memory cells MC are connected to different bit lines BL1 and BL2 and share the plate line PL1. L1 , M.C. L2 can be arranged horizontally along a second direction D2 parallel to the plane CP.

[0047] Memory cell MC L3 , M.C. L4 may be arranged in a mirror structure in which the memory cells MC are connected to different bit lines BL3 and BL4 and share the plate line PL1. L3 , M.C. L4 can be arranged horizontally along a second direction D2 parallel to the plane CP.

[0048] Memory cell MC U1 , M.C. U2 may be arranged in a mirror structure in which the memory cells MC are connected to different bit lines BL1 and BL2 and share the plate line PL1. U1 , M.C. U2 can be arranged horizontally along a second direction D2 parallel to the plane CP.

[0049] Memory cell MC U3 , M.C. U4 may be arranged in a mirror structure in which the memory cells MC are connected to different bit lines BL3 and BL4 and share the plate line PL1. U3 , M.C. U4 can be arranged horizontally along a second direction D2 parallel to the plane CP.

[0050] 1 and 4, a bit line sharing mirror structure 100B is described.

[0051] Memory cell MC L2 , M.C. L5may be arranged in a mirror structure in which the memory cells MC are connected to different plate lines PL1 and PL2 and share the bit line BL2. L2 , M.C. L5 can be arranged horizontally along a second direction D2 parallel to the plane CP.

[0052] Memory cell MC L4 , M.C. L6 may be arranged in a mirror structure in which the memory cells MC are connected to different plate lines PL1 and PL2 and share the bit line BL4. L4 , M.C. L6 can be arranged horizontally along a second direction D2 parallel to the plane CP.

[0053] Memory cell MC U2 , M.C. U5 may be arranged in a mirror structure in which the memory cells MC are connected to different plate lines PL1 and PL2 and share the bit line BL2. U2 , M.C. U5 can be arranged horizontally along a second direction D2 parallel to the plane CP.

[0054] Memory cell MC U4 , M.C. U6 may be arranged in a mirror structure in which the memory cells MC are connected to different plate lines PL1 and PL2 and share the bit line BL4. U4 , M.C. U6 can be arranged horizontally along a second direction D2 parallel to the plane CP.

[0055] The memory device 100 shown in FIG. 1 may include both a mirror type structure 100A that shares a plate line and a mirror type structure 100B that shares a bit line.

[0056] FIG. 5 is a cross-sectional view of a portion of the memory device 100 of FIG. 1 illustrating memory cells connected to bit lines BL1, BL2 and plate lines PL1, PL2.

[0057] As shown in FIGS. 1 to 5, the memory device 100 may include a memory cell array stack MCA located above a peripheral structure 110. The memory cell array stack MCA may include a lower memory cell array MCA that is vertically stacked. L and the upper memory cell array MCA U The memory device 100 may include bit lines BL1 and BL2 and plate lines PL1 and PL2 that are spaced apart from a peripheral structure 110 and oriented vertically.

[0058] A transistor T located in a horizontal arrangement between a bit line BL1 and a plate line PL1 L1 , T U1 and capacitor C L1 , C U1 A memory cell MC having L1 , M.C. U1 A transistor T located in a horizontal arrangement between the bit line BL2 and the plate line PL1 may be formed. L2 , T U2 and capacitor C L2 , C U2 A memory cell MC having L2 , M.C. U2 A transistor T located in a horizontal arrangement between the bit line BL2 and the plate line PL2 may be formed. L5 , T U5 and capacitor C L5 , C U5 A memory cell MC having L5 , M.C. U5 can be formed.

[0059] Transistor T L1 , T L2 , T L5 , T U1 , T U2 , T U5Each of the transistors T may have an active layer ACT oriented horizontally with respect to the peripheral structure 110, and the active layer ACT may have a first source / drain region T1, a channel CH, and a second source / drain region T2. ​​The first source / drain region T1, the channel CH, and the second source / drain region T2 may be positioned in a horizontal arrangement parallel to the peripheral structure 110. L1 , T L2 , T L5 , T U1 , T U2 , T U5 are word lines WL L1 , W.L. L2 , W.L. L3 , W.L. U1 , W.L. U2 , W.L. U3 and the word line WL L1 , W.L. L2 , W.L. L3 , W.L. U1 , W.L. U2 , W.L. U3 Each of the word lines WL may have a line shape extending to cross the active layer ACT. L1 , W.L. L2 , W.L. L3 , W.L. U1 , W.L. U2 , W.L. U3 The word lines WL may have a double word line structure in which the word lines WL are vertically stacked with the active layer ACT interposed therebetween. L1 , W.L. L2 , W.L. L3 , W.L. U1 , W.L. U2 , W.L. U3 A gate insulating layer GD may be formed between the active layer ACT and the gate insulating layer GD.

[0060] Capacitor C L1 , C L2 , C L5 , C U1 , C U2 , C U5) may each include a first node N1, a second node N2, and a dielectric material N3 between the first node N1 and the second node N2. The first node N1, the dielectric material N3, and the second node N2 may be positioned in a horizontal arrangement parallel to the peripheral structure 110. The first node N1 may be cylindrical, and the second node N2 may extend from the plate lines PL1 and PL2 into the cylinder interior of the first node N2.

[0061] Vertically stacked lower memory cells MC L1 , M.C. L2 , M.C. L5 and the upper memory cell MC U1 , M.C. U2 , M.C. U5 Therefore, in the memory cell array stack MCA, the lower memory cell array MCA L and the upper memory cell array MCA U When multiple memory cell arrays are stacked, a lower memory cell array MCA may have an insulating material ILD therebetween. L , an insulating material ILD, and an upper memory cell array MCA U can be stacked vertically in an alternating fashion.

[0062] FIG. 6 shows a lower memory cell array MCA of the memory cell array stack MCA. L FIG.

[0063] As shown in FIGS. 1 to 6, the lower memory cell array MCA L 1 and 2. The pixel regions 110 may include vertically oriented bit lines BL1, BL2, BL3, and BL4 and plate lines PL1 and PL2 spaced apart from the peripheral structure 110.

[0064] A memory cell MC includes a transistor TL1 and a capacitor CL1 arranged in a horizontal arrangement LA between a bit line BL1 and a plate line PL1. L1The transistors T are arranged in a horizontal arrangement LA between the bit line BL3 and the plate line PL1. L3 and capacitor C L3 A memory cell MC having L3 The transistors T are arranged in a horizontal arrangement LA between the bit line BL2 and the plate line PL1. L2 and capacitor C L2 A memory cell MC having L2 The transistors T are arranged in a horizontal arrangement LA between the bit line BL4 and the plate line PL1. L4 and capacitor C L4 A memory cell MC having L4 can be formed.

[0065] Transistors T located in a horizontal arrangement LA between the bit line BL2 and the plate line PL2 L5 and capacitor C L5 A memory cell MC having L5 The transistors T are arranged in a horizontal arrangement LA between the bit line BL4 and the plate line PL2. L6 and capacitor C L6 A memory cell MC having L6 can be formed.

[0066] Transistor T L1 , T L2 , T L3 , T L4 , T L5 , T L6 Each of the transistors T may have an active layer ACT oriented horizontally with respect to the peripheral structure 110, and the active layer ACT may have a first source / drain region T1, a channel CH, and a second source / drain region T2. ​​The first source / drain region T1, the channel CH, and the second source / drain region T2 may be positioned in a horizontal arrangement LA parallel to the peripheral structure 110. L1 , T L2 , T L3 , T L4 , T L5 , T L6are word lines WL L1 , W.L. L2 , W.L. L3 and the word line WL L1 , W.L. L2 , W.L. L3 Each of the word lines WL may have a line shape extending to cross the active layer ACT. L1 , W.L. L2 , W.L. L3 The transistors T may have a double word line structure in which the active layer ACT is sandwiched between the transistors T L1 , T L3 is the word line WL L1 The transistor T L2 , T L4 is the word line WL L2 The transistor T L5 , T L6 is the word line WL L3 can be shared.

[0067] Capacitor C L1 , C L2 , C L3 , C L4 , C L5 , C L6 Each of the peripheral structures 110 may include a first node N1, a second node N2, and a dielectric material N3 between the first node N1 and the second node N2. The first node N1, the dielectric material N3, and the second node N2 may be positioned in a horizontal arrangement parallel to the peripheral structure 110. The first node N1 may be cylindrical, and the second node N2 may extend from the plate lines PL1 and PL2 into the cylinder interior of the first node N2.

[0068] FIG. 7 is a perspective view showing the details of a memory cell. FIG. 8 is a cross-sectional view taken along the A1-A1' direction in FIG. 7. FIG. 9 is a plan view taken along the A2-A2' direction in FIG. 7. FIG. 10 is a detailed perspective view of a capacitor. FIGS. 7 to 10 are diagrams showing memory cell MC L1 Explain.

[0069] As shown in FIG. 7 to FIG. 10, a memory cell MC L1 may be positioned in a horizontal array LA along a second direction D2 parallel to the plane CP of the surrounding structure 110.

[0070] Memory cell MC L1 is the transistor T L1 and capacitor C L1 and a transistor T L1 and capacitor C L1 may be positioned in a horizontal array LA extending along a second direction D2 parallel to the plane CP of the surrounding structure 110.

[0071] Transistor T L1 indicates the active layer ACT, the gate insulating layer GD, and the word line WL L1 The word line WL L1 may comprise an upper word line G1 and a lower word line G2.

[0072] The active layer ACT includes a first source / drain region T1 connected to a bit line BL1, a capacitor C L1The active layer ACT may include a second source / drain region T2 connected to the bit line BL1 and a channel CH located between the first source / drain region T1 and the second source / drain region T2. ​​The active layer ACT may be oriented horizontally along a second direction D2 between the bit line BL1 and the capacitor CL1. The active layer ACT may be flat. Thus, the first source / drain region T1, the channel CH, and the second source / drain region T2 may be located in a horizontal array LA oriented along a second direction D2 parallel to the plane CP. The first source / drain region T1, the second source / drain region T2, and the channel CH may be formed in the active layer ACT. The active layer ACT may include a semiconductor material. The active layer ACT may include doped polysilicon, undoped polysilicon, or amorphous silicon. The first source / drain region T1 and the second source / drain region T2 may be doped with N-type impurities or P-type impurities. The first source / drain region T1 and the second source / drain region T2 may be doped with the same conductive impurity. The first source / drain region T1 and the second source / drain region T2 may include at least one impurity selected from the group consisting of arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. In some embodiments, the channel CH may be doped with a conductive impurity. As shown in FIG. 9, the width of the channel CH along the third direction D3 may be greater than the widths of the first and second source / drain regions T1 and T2.

[0073] The upper word line G1 and the lower word line G2 may form a pair. The upper word line G1 and the lower word line G2 may be stacked vertically along a first direction D1 across a channel CH and extend long along a third direction D3. The upper word line G1 and the lower word line G2 may extend along a third direction D3 that is parallel to a plane CP and perpendicular to the second direction D2. The upper word line G1 and the lower word line G2 may have a line shape extending along the third direction D3. The pair of the upper word line G1 and the lower word line G2 may form a vertically stacked double gate. The upper word line G1 and the lower word line G2 may include a silicon-based material, a metal-based material, or a combination thereof. The upper wordline G1 and the lower wordline G2 may include polysilicon, titanium nitride, tungsten, aluminum, copper, tungsten silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof.

[0074] The upper word line G1 and the lower word line G2 may be set to the same potential and may be electrically connected to each other at one end. In another embodiment, the upper word line G1 and the lower word line G2 may be connected to different nodes. For example, the upper word line G1 may be connected to a node that applies a word line signal, and the lower word line G2 may be connected to a node that applies a ground voltage.

[0075] The upper word line G1 and the lower word line G2 may have the same width along the second direction D2 and may have the same length along the third direction D3. The upper word line G1 and the lower word line G2 may have the same thickness. The upper word line G1, the lower word line G2, and the active layer ACT may have the same thickness or different thicknesses. Both edges of the upper word line G1 and both edges of the lower word line G2 may be aligned with each other. In another embodiment, both edges of the upper word line G1 and both edges of the lower word line G2 may not be aligned with each other. The upper word line G1 and the lower word line G2 may vertically overlap the channel CH of the active layer ACT along the first direction D1. The upper word line G1 and the lower word line G2 may partially cover the upper and lower portions of the active layer ACT. The upper word line G1 and the lower word line G2 may be formed of a material different from the active layer ACT. The upper word line G1 and the lower word line G2 can be paired. Since a pair of word lines including the upper word line G1 and the lower word line G2 is formed, the resistance of the word line can be reduced. In addition, since a pair of the upper word line G1 and the lower word line G2 is formed, interference between vertically adjacent memory cells can be prevented. For example, in the memory cell MC U1 The lower word line G2 of the memory cell MC U1 The upper word line G1 and the memory cell MC L1 A lower word line G2 may be provided between the upper word line G1 and the lower word line G2 to prevent coupling between the lower word line G2 and the adjacent upper word line G1.

[0076] The gate insulating layer GD may be formed on the upper and lower surfaces of the active layer ACT. The gate insulating layer GD may include a first insulating portion GD1 and a second insulating portion GD2. The first insulating portion GD1 may be formed between the upper word line G1 and the channel CH, and the second insulating portion GD2 may be formed between the lower word line G2 and the channel CH. The first insulating portion GD1 may be discontinuous from the second insulating portion GD2. The first insulating portion GD1 and the second insulating portion GD2 may have the same thickness and may be formed of the same material. The gate insulating layer GD may include silicon oxide, silicon nitride, or a combination thereof. The gate insulating layer GD may be formed by thermal oxidation of the active layer ACT. In another embodiment, the gate insulating layer GD may include a high-k material, and the high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). In another embodiment, the gate insulating layer GD may include a stack of silicon oxide and a high-k material, and the silicon oxide may directly contact the channel CH, and the high-k material may directly contact the upper and lower word lines G1, G2.

[0077] Capacitor C L1 is the transistor T L1 a first node N1 connected to the plate line PL1, a second node N2 connected to the plate line PL1, and a dielectric material N3 between the first node N1 and the second node N2. The first node N1, the dielectric material N3, and the second node N2 may be positioned in a horizontal arrangement parallel to the plane CP.

[0078] Capacitor C L1Although the first node N1 of the capacitor C1 has a three-dimensional structure, the first node N1 of the three-dimensional structure may be a horizontal three-dimensional structure parallel to the plane CP. L1 The first node N1 may have a cylinder shape, a pillar shape, or a pylinder shape in which the pillar shape and the cylinder shape are merged. The first node N1 may include polysilicon, metal, noble metal, metal nitride, conductive metal oxide, conductive noble metal oxide, metal carbide, metal silicide, or a combination thereof. For example, the first node N1 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack.

[0079] Capacitor C L1 The second node N2 may have a branch shape extending from the plate line PL1 in a second direction D2 parallel to the plane CP. The dielectric material N3 may be shaped to surround the branch-shaped second node N2, and the first node N1 may be shaped to surround the second node N2 with the dielectric material N3 in between. For example, the cylinder-shaped first node N1 may be connected to the transistor T L1 A second node N2 may be located inside the cylinder of the first node N1, and the second node N2 may be electrically connected to the plate line PL1.

[0080] As shown in FIG. L1The second node N2 may further include outer second nodes N21, N22, N23, and N24 connected to the plate line PL1. The outer second nodes N21, N22, N23, and N24 may be located outside the first node N1 with the dielectric material N3 interposed therebetween. The second node N2 may be abbreviated to "inner second node," and the inner second node N2 may be located inside the cylinder of the first node N1.

[0081] The external second nodes N21, N22, N23, and N24 may be located to surround the cylinder outer wall of the first node N1. The external second nodes N21, N22, N23, and N24 may be continuous with each other.

[0082] Capacitor C L1 may comprise a metal-insulator-metal (MIM) capacitor. The first node N1 and the second nodes N2, N21, N22, N23, and N24 may include a metal-base material, and the dielectric material N3 may include silicon oxide, silicon nitride, or a combination thereof. The dielectric material N3 may include a high-k material having a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric material N3 may include a high-k material having a dielectric constant of 4 or greater. The high-k material may have a dielectric constant of about 20 or greater. The high dielectric constant material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). In other embodiments, the dielectric material N3 may be a composite layer including two or more layers of the aforementioned high dielectric constant materials.

[0083] The first node N1 and the second nodes N2, N21, N22, N23, and N24 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first node N1 and the second nodes N2, N21, N22, N23, and N24 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack. The first node N1 and the second nodes N2, N21, N22 may also include a combination of metal-based and silicon-based materials, for example, the second nodes N2, N21, N22, N23, N24 may be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack.

[0084] The dielectric material N3 may be formed of a zirconium-based oxide (Zr-base oxide). The dielectric material N3 may be a stack structure including zirconium oxide (ZrO2). The stack structure including zirconium oxide (ZrO2) may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack is a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2), and the zirconium oxide (ZrO2) may contact the first node N1 and the aluminum oxide (Al2O3) may contact the second node N2. The ZAZ stack may be a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. The ZA stack and the ZAZ stack may be referred to as a zirconium oxide-base layer (ZrO2-base layer). In another embodiment, the dielectric material N3 may be formed of a hafnium-based oxide (Hf-base oxide). The dielectric material N3 may be a stack structure including hafnium oxide (HfO2). The stack structure including hafnium oxide (HfO2) may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack is a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2), and the hafnium oxide (HfO2) may contact the first node N1 and the aluminum oxide (Al2O3) may contact the second node N2. The HAH stack may be a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are sequentially stacked. The HA stack and the HAH stack may be referred to as a hafnium oxide-base layer (HfO2-base layer). In the ZA stack, ZAZ stack, HA stack, and HAH stack, aluminum oxide (Al2O3) can have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2).Aluminum oxide (Al2O3) may have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Thus, the dielectric material N3 may include a stack of a high dielectric constant material and a high band gap material having a larger band gap than the high dielectric constant material. In addition to aluminum oxide (Al2O3), the dielectric material N3 may also include silicon oxide (SiO2) as another high band gap material. The dielectric material N3 may include a high band gap material to suppress leakage current. The high band gap material may be extremely thin. The high band gap material may be thinner than the high dielectric constant material.

[0085] In another embodiment, the dielectric material N3 may include a laminated structure in which a high dielectric constant material and a high band gap material are alternately stacked. For example, it may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2 / HfO2). In such a laminated structure, the aluminum oxide (Al2O3) may be very thin.

[0086] In other embodiments, the dielectric material N3 may include a stack structure, a laminate structure, or an intermixing structure including zirconium oxide, hafnium oxide, and aluminum oxide.

[0087] In another embodiment, an interface control layer for improving leakage current may be further formed between the first node N1 and the dielectric material N3. The interface control layer may include titanium oxide (TiO2). An interface control layer may also be formed between the second node N2 and the dielectric material N3.

[0088] The bit line BL1 and the plate line PL1 may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL1 may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL1 may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The bit line BL1 may include a stack of titanium nitride and tungsten (TiN / W). The bit line BL1 and the transistor T L1 An ohmic contact such as a metal silicide may be further formed between the first source / drain region T1 and the plate line PL1. The plate line PL1 may be formed of the same material as the second nodes N2, N21, N22, N23, and N24. The plate line PL1 may be formed simultaneously with the second nodes N2, N21, N22, N23, and N24.

[0089] The bit line BL1 may be in the shape of a pillar extending perpendicularly from the plane CP in the first direction D1. The cross section of the bit line BL1 along the second direction D2 may be in the shape of a circle or an oval. The pillar-shaped bit line BL1 may reduce resistance.

[0090] The plate line PL1 may be a linear-shape pillar extending perpendicularly from the plane CP in a first direction D1. The cross section of the plate line PL1 along the second direction D2 may be rectangular-shaped. The plate line PL1 along the third direction D3 may be an elongated linear-shape rectangle.

[0091] As described above, the upper word line G1 and the lower word line G2 may be formed horizontally spaced apart from the bit line BL1 and the plate line PL1.L1 and capacitor C L1 The parasitic capacitance between the word line WL L1 This can reduce the parasitic capacitance between the bit line BL1 and the bit line BL2.

[0092] The memory cell MC in FIG. L1 The method for forming a transistor T L1 , forming a bit line BL1, forming a capacitor CL1, and forming a plate line PL1.

[0093] The process of forming the transistor TL1 is as follows. First, an active layer ACT is formed so as to be vertically spaced apart from the plane CP of the peripheral structure 110, and a gate insulating layer GD is formed on each of the upper and lower parts of the active layer ACT. Next, an upper word line G1 and a lower word line G2 are formed on the gate insulating layer GD. Next, a first source / drain region T1 and a second source / drain region T2 are formed in the active layer ACT by ion implantation of impurities.

[0094] The bit line BL1 may be formed to be oriented perpendicularly from the plane CP of the peripheral structure 110. The bit line BL1 may be formed to be connected to the first source / drain region T1.

[0095] The process of forming the capacitor CL1 will be described as follows. First, a first node N1 may be formed to be connected to the second source / drain region T2. ​​Next, a dielectric material N3 may be formed on the first node N1. Next, a second node N2 may be formed on the dielectric material N3. During the formation of the second node N2, a plate line PL1 may be formed. The plate line PL1 may be oriented perpendicular to the plane CP of the peripheral structure 110.

[0096] 11A to 11C are diagrams illustrating a first node of a capacitor having a three-dimensional structure according to another embodiment of the present invention, Fig. 11A shows a pillar-shaped first node LP, and Figs. 11B and 11C show a pillar-shaped first node N1.

[0097] 11A, the first node N1 may be a lateral pillar (LP). The lateral pillar LP may include a metal-based material, a silicon-based material, or a combination thereof. For example, the lateral pillar LP may be formed of titanium nitride alone or a stack of titanium nitride and polysilicon.

[0098] As shown in Figures 11B and 11C, the first node N1 of the Pilinda shape may include a horizontal cylinder LC and a horizontal pillar LP parallel to a plane CP. As shown in Figure 11B, the horizontal pillar LP may be located within the horizontal cylinder LC. The horizontal length of the horizontal cylinder LC may be longer than the horizontal length of the horizontal pillar LP. For example, the inlet of the horizontal cylinder LC may not be filled with the horizontal pillar LP. As shown in Figure 11C, the horizontal cylinder LC may be formed in a horizontal arrangement on the horizontal pillar LP.

[0099] 11B, the horizontal cylinder LC and the horizontal pillar LP may be the same material or different materials. The horizontal cylinder LC and the horizontal pillar LP may include a metal-based material, a silicon-based material, or a combination thereof. For example, the horizontal cylinder LC may be titanium nitride and the horizontal pillar LP may be polysilicon.

[0100] 11C, the horizontal cylinder LC and the horizontal pillar LP may be the same material or different materials. The horizontal cylinder LC and the horizontal pillar LP may include a metal-based material, a silicon-based material, or a combination thereof. For example, the horizontal cylinder LC and the horizontal pillar LP may be titanium nitride. Alternatively, the horizontal cylinder LC may be titanium nitride and the horizontal pillar LP may be polysilicon.

[0101] 12A and 12B are diagrams illustrating memory devices 200 and 200' according to other embodiments.

[0102] 12A and 12B, the memory device 200, 200' may include a peripheral circuit unit 210 and a memory cell array stack MCA. The memory cell array stack MCA may be the same as the memory cell array stack MCA of FIG 1. The memory cell array stack MCA may include a DRAM memory cell array.

[0103] 12A, the memory cell array stack MCA may be located above a peripheral circuit unit 210. The peripheral circuit unit 210 may correspond to the peripheral structure 110 of FIG. 1. Therefore, the memory device 200 may have a PUC (Peri under Cell) structure. The memory cell array stack MCA may be located above a semiconductor substrate 211 of the peripheral circuit unit 210.

[0104] As shown in FIG. 12B, the memory cell array stack MCA may be located below the peripheral circuit section 210. The peripheral circuit section 210 may correspond to the peripheral structure 110 of FIG. 1. For example, in FIG. 1, the peripheral structure 110 may be stacked above the memory cell array stack MCA. Therefore, the memory device 200′ may have a CUP (Cell under Peri) structure. The memory cell array stack MCA may be located below the semiconductor substrate 211 of the peripheral circuit section 210.

[0105] The peripheral circuit unit 210 may refer to a circuit for driving the memory cell array stack MCA during a read / write operation. The peripheral circuit unit 210 may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The peripheral circuit unit 210 may include an address decoder circuit, a read circuit, a write circuit, and the like. The peripheral circuit unit 210 may have a structure in which a semiconductor substrate 211 and a sense amplifier 212 are arranged on a surface of the semiconductor substrate 211. The sense amplifier 212 may include a transistor SA_T having the semiconductor substrate 211 as a channel, and the transistor SA_T may be a planar channel transistor having a channel parallel to the surface of the semiconductor substrate 211. The transistor structure in the sense amplifier 211 may include a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like in addition to the planar channel transistor.

[0106] A bit line BL of the memory cell array stack MCA may be electrically connected to a transistor SA_T of the sense amplifier 211. The bit line BL and the transistor SA_T may be interconnected via a multi-level metal wiring (MLM, 213). The multi-level metal wiring (MLM, 213) may be formed by a damascene process.

[0107] Although not shown, in yet another embodiment, the memory device 200, 200' may include a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate. The memory cell array stack MCA may be formed on the first semiconductor substrate, and the peripheral circuit unit 210 may be formed on the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate may each include a conductive bonding pad, and the first semiconductor substrate and the second semiconductor substrate may be bonded to each other via the conductive bonding pad. As a result, the memory cell array stack MCA and the peripheral circuit unit 210 may be electrically connected to each other.

[0108] The present invention is not limited to the above-described embodiments and the accompanying drawings, and it will be apparent to those skilled in the art to which the present invention pertains that various substitutions, modifications, and alterations are possible within the scope of the technical idea of ​​the present invention. [Explanation of symbols]

[0109] 100 Memory device 110 Surrounding Structures MCA Memory Cell Array Stack MCA L Lower Memory Cell Array MCA U Upper memory cell array W.L. L1 , W.L. L2 , W.L. L3 , W.L. U1 , W.L. U2 , W.L. U3 Word Line BL1, BL2, BL3, BL4 bit lines MC L1 ~MC L6 , M.C. U1 ~MC U6 Memory Cell PL1, PL2 plate line T L1 ~T L6 , T U1~T U6 Transistor C L1 ~C L6 , C U1 ~C U6 Capacitor

Claims

1. A substrate; a bit line oriented vertically from the substrate; a plate line aligned perpendicular to the substrate; a memory cell including a transistor disposed in a horizontal arrangement between the bit line and the plate line and a capacitor connected to the transistor; Equipped with The transistor is an active layer oriented horizontally so as to be parallel to the substrate between the bit line and the capacitor; a pair of word lines vertically stacked with the active layer therebetween and having a line shape extending so as to intersect with the active layer; Equipped with The capacitor is a first node connected to the transistor; a second node connected to the plate line; a dielectric material between the first node and a second node; Equipped with the first node, the dielectric material, and the second node are positioned in a horizontal arrangement between the transistor and a plate line; the first node of the capacitor has a three-dimensional structure, but the three-dimensional structure is horizontally oriented so as to be parallel to the substrate; The capacitor and the pair of word lines are arranged so as not to overlap in the vertical direction.

2. The active layer of the transistor comprises: a first source / drain region connected to the bit line; a second source / drain region connected to the capacitor; a channel between the first source / drain region and a second source / drain region; Equipped with 2. The memory device of claim 1, wherein the first source / drain region, the channel, and the second source / drain region are positioned in a horizontal arrangement between the bit line and a capacitor.

3. 3. The memory device of claim 2, wherein the pair of word lines are stacked vertically across the channel of the transistor.

4. The transistor is The memory device of claim 2 , further comprising a gate insulating layer formed between the pair of word lines and a channel.

5. 2. The memory device of claim 1, wherein different potentials are applied to the pair of word lines.

6. The memory device of claim 1 , wherein the first node of the capacitor has a shape of a horizontal cylinder, a horizontal pillar, or a pillar shape that is a merger of a horizontal pillar and a horizontal cylinder.

7. the first node of the capacitor is in the shape of a horizontal cylinder; The second node of the capacitor is an internal second node oriented horizontally from the plate line and extending into the cylinder interior of the first node; 2. The memory device of claim 1, further comprising: a plurality of outer second nodes oriented horizontally from said plate line and surrounding a cylindrical exterior of said first node.

8. 2. The memory device of claim 1, wherein the pair of word lines are horizontally spaced apart from the bit line, the plate line, and the capacitor.

9. The memory device of claim 1 , wherein the substrate comprises a peripheral circuit portion for controlling the memory cells, the peripheral circuit portion being located below the memory cells.

10. 2. The memory device of claim 1, wherein the substrate comprises a peripheral circuit portion for controlling the memory cells, the peripheral circuit portion being located above the memory cells.

11. another bit line vertically oriented from the substrate and spaced horizontally from the bit line; another memory cell stacked in a direction perpendicular to the substrate between the other bit line and the plate line; Further equipped with 2. The memory device of claim 1, wherein the memory cell and another memory cell are horizontally arranged in a mirror structure sharing the plate line.

12. another plate line spaced horizontally from said plate line and oriented vertically from said substrate; another memory cell stacked in a direction perpendicular to the substrate between the other plate line and the bit line; Further equipped with 2. The memory device of claim 1, wherein the memory cell and other memory cells are arranged horizontally in a mirror structure sharing the bit line.

13. another bit line vertically oriented from the substrate and spaced horizontally from the bit line; another memory cell stacked in a direction perpendicular to the substrate between the other bit line and the plate line; Further equipped with The other memory cell is another transistor having another active layer horizontally oriented parallel to the substrate between the other bit line and the plate line; another capacitor oriented horizontally parallel to the substrate between the other transistor and a plate line; Equipped with 2. The memory device of claim 1, wherein the other transistors share the pair of line-shaped word lines.

14. A substrate; a bit line oriented vertically from the substrate; a plate line aligned perpendicular to the substrate; a plurality of memory cells stacked in a direction perpendicular to the substrate between the bit line and the plate line; Equipped with Each of the memory cells comprises: a transistor including an active layer oriented horizontally between the bit line and the plate line so as to be parallel to the substrate, and a pair of line-shaped word lines vertically stacked on either side of the active layer and extending to intersect the active layer; a capacitor including a cylindrical first node and a second node oriented horizontally parallel to the substrate between the transistor and a plate line, and a dielectric material between the cylindrical first node and the second node; Equipped with The capacitor and the pair of line-shaped word lines are arranged so as not to overlap in the vertical direction.

15. The active layer of the transistor comprises: a first source / drain region connected to the bit line; a second source / drain region connected to the capacitor; a channel between the first source / drain region and a second source / drain region; Equipped with 15. The memory device of claim 14, wherein the first source / drain region, the channel, and the second source / drain region are positioned in a horizontal arrangement parallel to the substrate.

16. 16. The memory device of claim 15, wherein the pair of word lines are stacked vertically across the channel of the transistor.

17. The transistor is The memory device of claim 15 , further comprising a gate insulating layer formed between the pair of word lines and a channel.

18. The memory device of claim 14 , wherein different potentials are applied to the pair of word lines.

19. a cylindrical first node of the capacitor is connected to the transistor; The memory device of claim 14 , wherein a second node of the capacitor is connected to the plate line.

20. The second node of the capacitor is an internal second node oriented horizontally from the plate line and extending into a cylinder interior of the cylindrical first node; a plurality of exterior second nodes oriented horizontally from the plate line and surrounding a cylindrical exterior of the cylindrical first node; 15. The memory device of claim 14, comprising:

21. another bit line vertically oriented from the substrate and spaced horizontally from the bit line; a plurality of other memory cells stacked in a direction perpendicular to the substrate between the other bit lines and the plate lines; Further equipped with 15. The memory device of claim 14, wherein the memory cell and another memory cell are horizontally arranged in a mirror structure sharing the plate line.

22. another plate line spaced horizontally from said plate line and oriented vertically from said substrate; a plurality of other memory cells stacked in a direction perpendicular to the substrate between the other plate lines and the bit lines; Further equipped with 15. The memory device of claim 14, wherein the memory cell and another memory cell are arranged horizontally in a mirror structure sharing the bit line.

23. another bit line vertically oriented from the substrate and spaced horizontally from the bit line; a plurality of other memory cells stacked in a direction perpendicular to the substrate between the other bit lines and the plate lines; Further equipped with Each of the other memory cells another transistor having another active layer horizontally oriented parallel to the substrate between the other bit line and the plate line; another capacitor oriented horizontally parallel to the substrate between the other transistor and a plate line; Equipped with The memory device of claim 14 , wherein the other transistors share the pair of line-shaped word lines.

24. The memory device according to claim 14 , wherein the substrate includes a peripheral circuit portion for controlling the memory cells, the peripheral circuit portion being formed below the memory cells.

25. The memory device according to claim 14 , wherein the substrate includes a peripheral circuit portion for controlling the memory cells, the peripheral circuit portion being formed above the memory cells.

26. 15. The memory device of claim 14, wherein the substrate comprises at least one peripheral circuit portion formed below the memory cells, the at least one peripheral circuit portion comprising a selected one of a sense amplifier and a sub-word line driver.

27. a plurality of insulating materials positioned between the vertically stacked memory cells; The memory device of claim 14 , wherein the memory cells and insulating materials are stacked vertically in an alternating manner.

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