Semiconductor Device

Abstract

To provide a semiconductor device capable of protecting a memory, preventing plasma from damaging a gate dielectric layer or tunnel layer of the memory and improving the retention performance of the memory.SOLUTION: A semiconductor device SD1 includes a substrate 10, a dope ring 38, a plurality of contacts 42 and a plurality of conductive wires 44. The substrate includes a first area AR and a second area PR surrounding the first area; the dope ring positioned in the second area of the substrate and surrounding the first area includes a first doped area and a plurality of second doped areas; the first doped area positioned in the second area of the substrate and surrounding the first area includes an opening; the plurality of second doped areas separated from each other are positioned in the opening of the substrate; the contacts are electrically connected to the plurality of second doped areas; and the conductive wires are connected to the contacts and a plurality of conductive layers in the first area.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] The present invention relates to integrated circuits, and more particularly to semiconductor devices. [Background technology]

[0002] Plasma is often used in deposition and etching processes in semiconductor manufacturing processes. However, plasma discharges can damage semiconductor elements during the process. For example, the use of plasma in semiconductor back-end processes can cause discharges to damage the gate dielectric layer of memory devices on the substrate, thereby reducing the retention performance of the memory devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US10,163,641 B2

[0004] [Patent Document 2] US7,151,302 B1 Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE DISCLOSURE The embodiments of the present invention provide a semiconductor device that can protect a memory, prevent plasma from damaging a gate dielectric layer or a tunnel layer of the memory, and improve the retention performance of the memory. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment of the present invention includes a substrate, a doped ring, a plurality of contacts, and a plurality of conductive lines. The substrate includes a first region and a second region surrounding the first region. The doped ring is located within the substrate in the second region and surrounds the first region. The doped ring includes a first doped region and a plurality of second doped regions. The first doped regions are located within the substrate in the second region and surround the first region. The first doped regions have openings. The second doped regions are spaced apart from each other and located within the substrate in the openings. The contacts are electrically connected to the second doped regions. The conductive lines are connected to the contacts and to the plurality of conductive layers in the first region.

[0007] In accordance with another embodiment of the present invention, a semiconductor device includes a substrate, a plurality of memory devices, a plurality of diodes, a plurality of contacts, and a plurality of conductive lines. The substrate includes a first region and a second region surrounding the first region. The memory devices are located in the first region. The diodes are located in the substrate in the second region. The contacts are electrically connected to the diodes. The conductive lines are connected to the contacts and connected to the memory devices. Effect of the Invention

[0008] As described above, in embodiments of the present invention, by placing a diode (e.g., a doped ring) in the semiconductor structure, the semiconductor structure can protect the memory device, prevent the plasma used in the subsequent metallization process from damaging the gate dielectric layer of the memory device, and improve the retention performance of the memory device. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1 is a top view of a semiconductor device according to one embodiment of the present invention. [Figure 1B] FIG. 1B is a cross-sectional view taken along line II' in FIG. 1A. [Figure 1C] FIG. 1B is another cross-sectional view taken along line II' in FIG. 1A. [Figure 2A] FIG. 2 is a top view of a semiconductor device according to an embodiment of the present invention. [Figure 2B] FIG. 2B is a cross-sectional view taken along line II-II' in FIG. 2A. [Figure 2C] 2B is another cross-sectional view taken along line II-II' in FIG. 2A. [Figure 3A] FIG. 2 is a top view of a semiconductor device according to an embodiment of the present invention. [Figure 3B] FIG. 3B is a cross-sectional view taken along line III-III' in FIG. 3A. [Figure 4A] FIG. 2 is a top view of a semiconductor device according to an embodiment of the present invention. [Figure 4B] FIG. 4B is a cross-sectional view taken along line IV-IV' in FIG. 4A. [Figure 5A] FIG. 2 is a top view of a semiconductor device according to an embodiment of the present invention. [Figure 5B] FIG. 5B is a cross-sectional view taken along line VV' in FIG. 5A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Figure 1A is a top view of a semiconductor device according to an embodiment of the present invention, Figure 1B is a cross-sectional view taken along line II' in Figure 1A, and Figure 1C is another cross-sectional view taken along line II' in Figure 1A.

[0011] 1A and 1B, a semiconductor device SD1 according to an embodiment of the present invention includes a substrate 10, a plurality of memory devices 116A, a guard ring 16, a plurality of diodes 33, a plurality of contacts 42, and a plurality of conductive lines 44. The substrate 10 may include a semiconductor or a semiconductor compound. The semiconductor may include silicon, such as bulk silicon or silicon-on-insulator (SOI). The semiconductor compound may include germanium silicide. An isolation structure 14 is disposed within the substrate 10. The isolation structure 14 may include silicon oxide, silicon nitride, or a combination thereof. The isolation structure 14 defines a first region AR and a second region PR of the substrate 10. The first region AR is, for example, a memory array region. The second region PR is, for example, a peripheral region. The second region PR surrounds the first region AR.

[0012] A plurality of memory devices 116A are disposed in the region 100A of the first region AR. The memory devices 116A may be arranged in rows and columns to form a memory array. The memory devices 116A may be flash memory devices. The flash memory devices may have various structures. For example, the flash memory devices may include a tunnel layer 118, a floating gate layer 120, an inter-gate dielectric layer 125, a control gate layer 128, a cap layer 130, and a spacer 132. The tunnel layer 118, the floating gate layer 120, the inter-gate dielectric layer 125, the control gate layer 128, and the cap layer 130 are stacked from bottom to top to form a gate stack structure SK1. The tunnel layer 118 may include silicon oxide. The floating gate layer 120 may include polysilicon. The inter-gate dielectric layer 125 may include, for example, a silicon oxide layer 122, a silicon nitride layer 124, and a silicon oxide layer 126. The control gate layer 128 may include polysilicon. The cap layer 130 may include silicon nitride. The spacer 132 covers the sidewalls of the gate stack structure SK1 formed by the tunnel layer 118, the floating gate layer 120, the inter-gate dielectric layer 125, the control gate layer 128, and the cap layer 130.

[0013] 1A, the semiconductor element SD1 may further include a plurality of dummy memory devices 116A'. The plurality of dummy memory devices 116A' are disposed in a first region AR outside the region 100A. The dummy memory devices 116A' may have a configuration and components similar to those of the memory devices 116A.

[0014] 1A and 1B, the guard ring 16 is located on the substrate 10 in the second region PR. The guard ring 16 is a closed ring surrounding the boundary of the memory device 116A, which can reduce the impact of the loading effect caused by the density difference between the first region AR and the second region PR in the manufacturing process and protect the memory device 116A. The configuration of the guard ring 16 may be similar to the gate stack structure SK1 of the memory device 116A. In some embodiments, the guard ring 16 may include a dielectric layer 18, a conductive layer 20, dielectric layers 22, 24, and 26, a conductive layer 28, a cap layer 30, and a spacer 32. The materials of the dielectric layer 18, the conductive layer 20, the dielectric layers 22, 24, and 26, the conductive layer 28, the cap layer 30, and the spacer 32 are the same as the materials of the tunnel layer 118, the floating gate layer 120, the inter-gate dielectric layer 125, the control gate layer 128, and the cap layer 130, respectively, and the dielectric layer 18, the conductive layer 20, the dielectric layers 22, 24, and 26, the conductive layer 28, the cap layer 30, and the spacer 32 may be formed simultaneously with the tunnel layer 118, the floating gate layer 120, the inter-gate dielectric layer 125, the control gate layer 128, and the cap layer 130, respectively.

[0015] 1A and 1B, the multiple diodes 33 of the embodiment of the present invention are disposed in the substrate 10 in the second region PR. The multiple diodes 33 include a well region 12 and a doped ring 38. The well region 12 extends from under one isolation structure 14 between the first region AR and the second region PR to the second region PR, and then extends under another isolation structure 14 outside the second region PR, but the present invention is not limited thereto. The well region 12 may include a dopant of a first conductivity type. The dopant of the well region 12 may be a P-type, such as boron or boron trifluoride. The dopant of the well region 12 may be an N-type, such as phosphorus or arsenic.

[0016] 1A and 1B, both doped ring 38 and guard ring 16 are located within the boundary of well region 12. Doped ring 38 is disposed adjacent to guard ring 16. Doped ring 38 and guard ring 16 may partially overlap (as shown in FIG. 1B) or may not overlap (as shown in FIG. 1C) and may be spaced apart from each other by a non-zero distance. Because doped ring 38 is located inside guard ring 16, doped region 38 is closer to first region AR than guard ring 16.

[0017] Referring to FIG. 1A, the doped ring 38 is located in the well region 12 of the second region PR, as shown in FIG. 1B. Referring to FIG. 1A, the doped ring 38 includes a first doped region 38A and a plurality of second doped regions 38B. The first doped region 38A is a non-closed open ring, for example, located in the well region 12 surrounding the first region AR. In other words, the first doped region 38A has an opening 38C. The second doped region 38B is located in the well region 12 of the opening 38C. The second doped regions 38B are, for example, island-like and separated from each other. In other words, the doped ring 38 formed by the first doped region 38A and the plurality of second doped regions 38B is a non-closed ring.

[0018] 1A and 1B, each of the first doped region 38A and the second doped region 38B of the doped ring 38 includes a lightly doped region 36 and a heavily doped region 34. The lightly doped region 36 is located in the well region 12, and the heavily doped region 34 is located in the lightly doped region 36. The conductivity type of the dopants in the lightly doped region and the heavily doped region is different from the conductivity type of the dopants in the well region. The lightly doped region 36 and the heavily doped region 34 may include a dopant of a second conductivity type. The dopants in the lightly doped region 36 and the heavily doped region 34 may be N-type, such as phosphorus or arsenic. The dopants in the lightly doped region 36 and the heavily doped region 34 may be P-type, such as boron or boron trifluoride. The lightly doped region 36 is located in the well region 12 and is adjacent to the guard ring 16. The lightly doped region 36 and the guard ring 16 may be partially overlapping (as shown in FIG. 1B) or non-overlapping (as shown in FIG. 1C) and spaced apart from one another by a non-zero distance. The heavily doped region 34 and the guard ring 16 may be non-overlapping (as shown in FIGS. 1B and 1C) and spaced apart from one another by a non-zero distance.

[0019] 1A and 1B, an interconnect structure 50 is located on a substrate 10. The interconnect structure 50 includes a dielectric layer 160, a plurality of contacts 42, 142, and a plurality of conductive lines 44.

[0020] 1B, the dielectric layer 160 may include silicon oxide. The dielectric layer 160 may have a flat surface through a planarization process. The contacts 42, 142 are formed in the dielectric layer 160. The contact 42 extends through the dielectric layer 160 and is electrically connected to the doped region 34. The contact 142 extends through the dielectric layer 160 and the cap layer 130 and is electrically connected to the control gate 128. As shown in FIG. 1A, the contact 42 is electrically connected to ends E1 and E2 of the second doped region 38B and the first doped region 38A.

[0021] 1A and 1B, a conductive line 44 is formed on the dielectric layer 160 and extends from the first region AR to the second region PR. The conductive line 44 may be connected to the control gate 128 of the first region AR through a contact 142, and may be connected to a decoder. The conductive line 44 is also connected to the heavily doped region 34 of the diode 33 through the contact 42. In other words, the contact 42 and the contact 142 are at the same potential (equipotential) because they are connected to the same conductive line 44.

[0022] In some embodiments, the semiconductor device SD1 further includes metal silicide layers 140 and 40 to reduce contact resistance. The metal silicide layer 140 is located between the contact 142 and the control gate layer 128. The metal silicide 40 is located between the contact 42 and the heavily doped region 34.

[0023] The contact 42 is located outside the first region AR. Therefore, in a subsequent metallization process, before the plasma discharge 46 enters the first region AR, the conductive line 44 and the contact 42 function as a discharge path to guide the plasma discharge to the diode 33. Therefore, such a configuration can prevent the plasma discharge from damaging the tunnel layer (e.g., gate dielectric layer) 118 of the memory device and improve the retention performance of the memory device. The contact 42 and the contact 142 are formed through the same photomask, so no additional photomask is required.

[0024] In the above embodiment, the multiple diodes 33 are disposed between the guard ring 16 and the memory device 116A. In another embodiment, referring to Figures 2A and 2B, the diodes 33 of the semiconductor element SD2 can be located outside the guard ring 16. That is, the guard ring 16 is disposed between the memory device 116A and the diodes 33.

[0025] Figure 2A is a top view of a semiconductor device according to one embodiment of the present invention, Figure 2B is a cross-sectional view taken along line II-II' in Figure 2A, and Figure 2C is another cross-sectional view taken along line II-II' in Figure 2A.

[0026] 2B, the doped ring 38 is disposed adjacent to the guard ring 16. Both the doped ring 38 and the guard ring 16 are located within the boundary of the well region 12. The doped ring 38 and the guard ring 16 may partially overlap (as shown in FIG. 2B) or may not overlap (as shown in FIG. 2C) and may be spaced apart from each other by a non-zero distance. Because the doped ring 38 is located outside the guard ring 16, the doped ring 38 is farther away from the first region AR than the guard ring 16.

[0027] The doped ring 38 is located in the well region 12 of the second region PR, as shown in FIG. 2B. Referring to FIG. 2A, the doped ring 38 includes a first doped region 38A and a plurality of second doped regions 38B. The first doped region 38A is an open ring that is not closed, and is located, for example, in the well region 12 surrounding the first region AR. In other words, the first doped region 38A has an opening 38C. The second doped region 38B is located in the well region 12 of the opening 38C. The second doped regions 38B are, for example, island-like and separated from each other. In other words, the doped ring 38 formed by the first doped region 38A and the plurality of second doped regions 38B is an open ring.

[0028] The lightly doped region 36 and the guard ring 16 may partially overlap (as shown in FIG. 2B) or may not overlap (as shown in FIG. 2C) and may be spaced apart from one another by a non-zero distance. The heavily doped region 34 and the guard ring 16 may not overlap (as shown in FIGS. 2B and 2C) and may be spaced apart from one another by a non-zero distance.

[0029] The above embodiments are described using memory device 116A. However, the embodiments of the present invention can also be applied to various memory devices 116B, 116C, 116D, as shown in Figures 3A and 3B, 4A and 4B, and 5A and 5B, respectively. In Figures 3A, 4A, and 5A, the diode 33 is located inside the guard ring 16 as an illustrative example. However, the embodiments of the present invention are not limited thereto. The diode 33 can also be located outside the guard ring 16, as shown in Figures 2A and 2B. The diode 33 may also have similar components and structures as the semiconductor elements SD1 or SD4. For simplicity, the diode 33 is not shown in Figures 3B, 4B, and 5B.

[0030] FIG. 3A is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line III-III' in FIG. 3A. FIG. 4A is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 4B is a cross-sectional view taken along line IV-IV' in FIG. 4A. FIG. 5A is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 5B is a cross-sectional view taken along line V-V' in FIG. 5A.

[0031] 3A and 3B, the memory device 116B in the region 100B of the semiconductor element SD3 includes a gate stack structure SK2, a select gate structure SG, a word line structure WL, and a doped region 138. The gate stack structure SK2 includes a tunnel layer 118, a floating gate layer 120, an inter-gate dielectric layer 125, a control gate layer 128, a cap layer 130, and a spacer 132. The select gate structure SG is located between two adjacent gate stack structures SK2. The word line structure WL is located outside the two gate stack structures SK2. Each of the select gate structure SG and the word line structure WL includes a gate dielectric layer and a gate conductive layer. The doped region 138 is located in the substrate 10 outside the two word line structures WL and below the select gate structure SG. The semiconductor element SD3 may further include a metal silicide layer on the gate conductive layer of the select gate structure SG and the word line structure WL.

[0032] The guard ring 16 may have similar components and structure as the gate stack structure SK2, however, for simplicity, the detailed components of the guard ring 16 are not shown.

[0033] 4A and 4B, the memory device 116C in the region 100C of the semiconductor element SD4 includes a gate stack structure SK3, a select gate structure SG, and a doped region 138. The gate stack structure SK3 includes a tunnel layer 117, a charge storage layer 119, a blocking layer 121, and a control gate layer 128. The tunnel layer 117 may include silicon oxide. The charge storage layer 119 may include silicon nitride. The blocking layer 121 may include silicon oxide. The control gate layer 128 may include polysilicon. The select gate structure SG includes a gate dielectric layer and a gate conductive layer. The doped region 138 is in the substrate 10 outside the gate stack structure SK3 and the select gate structure SG.

[0034] The guard ring 16 may have similar components and structure as the gate stack structure SK3, however, for simplicity, the detailed components of the guard ring 16 are not shown.

[0035] 5A and 5B, the memory device 116D of the semiconductor element SD5 includes a gate stack structure SK4. The gate stack structure SK4 includes a tunnel layer 118, a floating gate layer 120, an inter-gate dielectric layer 125, a control gate layer 128, and a metal silicide layer 140. The metal silicide layer 140 covers most or all of an upper surface of the control gate layer 128. The metal silicide layer 140 further covers an upper surface of the doped region 138.

[0036] The guard ring 16 may have similar components and structure as the gate stack structure SK4, however, for simplicity, the detailed components of the guard ring 16 are not shown.

[0037] As described above, the embodiment of the present invention protects the memory device by placing a diode, which prevents the plasma discharge used in the subsequent metallization process from damaging the gate dielectric layer or the tunnel layer of the memory device, and accordingly improves the retention performance of the memory device. The diode may or may not overlap the guard ring. The diode may be located between the guard ring and the memory array, or may be located outside the guard ring. [Industrial Applicability]

[0038] The semiconductor element of the present invention can be applied to semiconductor elements including memory devices and diodes. [Explanation of symbols]

[0039] 10 Substrate 12 Well Area 14 Isolation structure 16 Guard Ring 18 Dielectric layer 20 Conductive layer 22 Dielectric layer 24 Dielectric layer 26 Dielectric Layer 28 Conductive Layer 30 Cap Layer 32 Spacer 33 Diode 34 Highly doped region 36 Lightly doped region 38 Dope Ring 38A First doped region 38B Second doped region 38C opening 40 Metal silicide layer 42 Contact 44 Conductive Wire 46 Plasma Discharge 50 Internal connection structure 100A area 100B area 100C area 100D area 116A Memory Device 116A' Dummy Memory Device 116B Memory Device 116C Memory Device 116D Memory Device 117 Tunnel Layer 118 Tunnel Layer 119 Charge storage layer 120 Floating Gate Layer 121 Blocking Layer 122 Silicon oxide layer 124 Silicon nitride layer 125 Inter-gate dielectric layer 126 Silicon oxide layer 128 Control Gate Layer 130 Cap Layer 132 Spacer 138 Doped Region 140 Metal silicide layer 142 Contacts 160 Dielectric layer AR 1st area E1 end E2 end PR area 2 SD1 Semiconductor device SD2 Semiconductor device SD3 Semiconductor Device SD4 Semiconductor Device SD5 Semiconductor Device SG Select gate structure SK1 Gate stack structure SK2 Gate stack structure SK3 Gate Stack Structure SK4 gate stack structure WL Word Line Structure I-I' Line II-II' Line III-III' line IV-IV' line V-V' line

Claims

1. a substrate including a first region and a second region surrounding the first region; a doped ring located within the substrate in the second region and surrounding the first region, a first doped region that is an open ring, the first doped region being located within the substrate of the second region, surrounding the first region and having an opening; a plurality of second doped regions spaced apart from one another and positioned within the substrate in the opening; the doped ring comprising: a plurality of contacts electrically connected to ends of the plurality of second doped regions and the first doped region; a plurality of conductive lines connected to the plurality of contacts and connected to a plurality of conductive layers in the first region; Including, 1. A semiconductor device, comprising: the first doped region having a continuous open ring structure; the plurality of second doped regions having an island shape; and the plurality of second doped regions located in the opening between the two ends of the first doped region.

2. 2. The semiconductor device of claim 1, wherein the plurality of conductive lines are connected to a plurality of control gates and a plurality of decoders for the plurality of control gates.

3. 2. The semiconductor device of claim 1, further comprising a guard ring located on the substrate in the second region and adjacent to the doped ring.

4. 4. The semiconductor device of claim 3, wherein the guard ring partially overlaps the doped ring.

5. 4. The semiconductor device of claim 3, wherein the guard ring does not overlap the doped ring.

6. 4. The semiconductor device of claim 3, wherein the doped ring is closer to the first region than the guard ring.

7. 4. The semiconductor device of claim 3, wherein the doped ring is farther away from the first region than the guard ring.

8. Each of the first doped region and the plurality of second doped regions is a lightly doped region located within a well region, the well region being located within the substrate of at least the second region; a heavily doped region located within the lightly doped region; 4. The semiconductor device of claim 3, wherein a conductivity type of the dopants in the well region is different from a conductivity type of the dopants in the lightly doped region and the heavily doped region.

9. The semiconductor device of claim 8 , wherein the guard ring is located within the well region.

10. The semiconductor device of claim 8 , further comprising a metal silicide layer overlying the highly doped region.

11. The semiconductor device of claim 8 , further comprising an isolation structure located between the first region and the second region.

12. a substrate including a first region and a second region surrounding the first region; a plurality of memory devices located within the first region; a plurality of diodes located in the substrate in the second region, the diodes including doped rings; a plurality of contacts electrically connected to the plurality of diodes; a plurality of conductive lines connected to the plurality of contacts and connected to the plurality of memory devices; Including, The doping ring is a first doped region that is an open ring, the first doped region being located within the substrate of the second region, surrounding the first region and having an opening; a plurality of second doped regions spaced apart from one another and positioned within the substrate in the opening; Including, 1. A semiconductor device, comprising: the first doped region having a continuous open ring structure; the plurality of second doped regions having islands; and the plurality of second doped regions located in the opening between two ends of the first doped region.

13. Each of the diodes is a well region located within the substrate in the second region; a lightly doped region located within the well region; a heavily doped region located within the lightly doped region; 13. The semiconductor device of claim 12, wherein a conductivity type of the dopants in the well region differs from a conductivity type of the dopants in the lightly doped region and the heavily doped region.

14. The semiconductor device of claim 13 , further comprising a metal silicide layer overlying the highly doped region.

15. The semiconductor device of claim 12 , further comprising a guard ring located within the substrate in the second region and adjacent to the plurality of diodes.

16. The semiconductor device of claim 15 , wherein the guard ring overlaps the plurality of diodes.

17. The semiconductor device of claim 15 , wherein the guard ring does not overlap the plurality of diodes.

18. The semiconductor device of claim 15 , wherein the plurality of diodes are closer to the first region than the guard ring.

19. The semiconductor device of claim 15 , wherein the plurality of diodes are farther away from the first region than a guard ring is.

20. 13. The semiconductor device of claim 12, wherein the memory device includes a plurality of flash memory devices, and the plurality of conductive lines are connected to a plurality of control gates of the plurality of flash memory devices and a plurality of decoders for the plurality of control gates.

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