Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device that has a conductive path for charges to reduce arcing effects and prevents various material layers and components on the dielectric substrate from being damaged by plasma bombardment.SOLUTION: A semiconductor device includes a staircase structure SC and an extension EP. The laminated structure is disposed on a dielectric substrate 50. The staircase structure includes a plurality of conductive layers 38 and a plurality of insulating layers 54, which are alternately laminated one on the other. The extension EP is disposed at an end of a lower staircase portion LP of the staircase structure SC. A resistance value of the extension is different from the resistance values of the plurality of conductive layers.SELECTED DRAWING: Figure 1F

Description

[Technical field]

[0001] The present invention relates to integrated circuits and methods of manufacturing integrated circuits, and more particularly to semiconductor devices and methods of manufacturing semiconductor devices. [Background technology]

[0002] 2. Description of Related Art Non-volatile memory has the advantage that the stored data is not lost when the power is turned off, so it has become a widely used memory for personal computers or other electronic devices. Currently, the three-dimensional memories commonly used in industry are NOR (Negative OR) and NAND (Nand) memories. In addition, another kind of three-dimensional memory is AND (And) memory, which can be applied to multi-dimensional memory arrays with high integration and high area utilization, and has the advantage of high operating speed. Therefore, the development of three-dimensional memory devices is gradually becoming a current trend. However, there are still many challenges related to three-dimensional memory devices. Summary of the Invention [Problem to be solved by the invention]

[0003] Technical issues The present invention provides a semiconductor device that has a conductive path for charges to reduce arcing effects and prevent various material layers and components on a dielectric substrate from being damaged by plasma bombardment. [Means for solving the problem]

[0004] Solutions to the challenges According to a preferred embodiment of the present invention, a semiconductor device includes a staircase structure and an extension. The staircase structure is disposed on a dielectric substrate. The staircase structure includes a plurality of conductive layers and a plurality of insulating layers, which are alternately stacked one on top of the other. The extension is disposed at an end of a lower staircase portion of the staircase structure. A resistance value of the extension is different from a resistance value of the plurality of conductive layers.

[0005] According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor device includes the steps of: forming a staircase structure on a dielectric substrate, the staircase structure including a plurality of conductive layers and a plurality of insulating layers alternately stacked one on the other; forming an extension at an end of a lower staircase portion of the staircase structure; and forming a resistance value of the extension at a different value from the resistance value of the plurality of conductive layers. Effect of the Invention

[0006] Based on the above, in an embodiment of the present invention, one or more semiconductor layers located at the bottom of the stacked structure can act as a conductive path for charges to reduce the arcing effect, and prevent various material layers and components on the dielectric substrate from being damaged by plasma bombardment. Thus, the process yield can be improved. In addition, the one or more semiconductor layers can be subjected to a subsequent exchange process to form one or more conductive layers, which can function as gate layers or dummy gate layers. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1A is a circuit diagram of a three-dimensional AND flash memory array according to some embodiments, FIG. 1B is a partial perspective view of a portion of the memory array of FIG. 1A, FIGS. 1C and 1D are cross-sectional views taken along line I-I' of FIG. 1B, FIG. 1E is a top view of line II-II' of FIGS. 1B, 1C, and 1D, and FIGS. 1F-1I are cross-sectional views of various staircase structures. [Diagram 2] 2A to 2I are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 3]3A and 3B are top views of several staircase structures of a memory device according to one embodiment of the present invention. [Figure 4] 4A-4F are schematic cross-sectional views of a method for manufacturing a memory device according to another embodiment of the present invention. [Diagram 5] 5A and 5B are top views of several staircase structures of a memory device according to other embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Description of the embodiments Figure 1A is a circuit diagram of a 3D AND flash memory array according to some embodiments. Figure 1B is a partial perspective view of a portion of the memory array of Figure 1A. Figures 1C and 1D are cross-sectional views taken along line I-I' of Figure 1B. Figure 1E is a top view taken along line II-II' of Figures 1B, 1C, and 1D.

[0009] FIG. 1A shows two blocks BLOCK of a vertical AND memory array 10 arranged in rows and columns. (i) and BLOCK (i+1) 1 is a schematic diagram of a block BLOCK (i) is memory array A (i) Memory Array A (i) One row (e.g., the (m+1)th row) of (i) m+1 ) in the memory array A. (i) The AND memory cells 20 are connected to a common word line (e.g., WL (i) m+1 ) and different source pillars (e.g., SP (i) n and SP (i) n+1 ) and drain pillars (e.g., DP (i) n and D.P. (i) n+1), such that these AND memory cells 20 are logically coupled to a common word line (e.g., WL (i) m+1 ) along the

[0010] Memory Array A (i) One column (e.g., the nth column) of the (i) n ) and common drain pillars (e.g., DP (i) n ) in each column (e.g., the nth column) of the memory array A (i) The AND memory cells 20 are connected to different word lines (e.g., WL (i) m+1 and W.L. (i) m ) and common source pillars (e.g., SP (i) n ) and common drain pillars (e.g., DP (i) n ) are connected to the memory array A. (i) The AND memory cells 20 are logically connected to a common source pillar (e.g., SP (i) n ) and common drain pillars (e.g., DP (i) n In the physical layout, depending on the manufacturing method being applied, these columns or rows may be intertwined and arranged in a honeycomb pattern or other pattern for densification or other reasons.

[0011] In Figure 1A, the block BLOCK (i) In the memory array A (i) The AND memory cells 20 in the n-th column of (i) n ) and common drain pillars (e.g., DP (i) n The AND memory cells 20 in the (n+1)th column share a common source pillar (e.g., SP (i) n+1) and common drain pillars (e.g., DP (i) n+1 ) to share.

[0012] Common source pillars (e.g., SP (i) n ) is a common source line (e.g., SL n ) and connected to a common drain pillar (e.g., DP (i) n ) is a common bit line (e.g., BL n ) are connected to a common source pillar (e.g., SP (i) n+1 ) is a common source line (e.g., SL n+1 ) and connected to a common drain pillar (e.g., DP (i) n+1 ) is a common bit line (e.g., BL n+1 )

[0013] Similarly, BLOCK (i+1) is memory array A (i+1) memory array A (i+1) is a block (i) Memory array A in (i) The same as in memory array A. (i+1) One row (e.g., the (m+1)th row) of (i+1) m+1 ) in the memory array A. (i+1) The AND memory cells 20 are connected to a common word line (e.g., WL (i+1) m+1 ) and different source pillars (e.g., SP (i+1) n and SP (i+1) n+1 ) and different drain pillars (e.g., DP (i+1) n and D.P. (i+1) n+1 ) is connected to memory array A. (i+1) One column (e.g., the nth column) of the (i+1)n ) and common drain pillars (e.g., DP (i+1) n ) in each column (e.g., the nth column) of the memory array A. (i+1) The AND memory cells 20 are connected to different word lines (e.g., WL (i+1) m+1 and W.L. (i+1) m ) and common source pillars (e.g., SP (i+1) n ) and common drain pillars (e.g., DP (i+1) m ) are connected to the memory array A. (i+1) The AND memory cells 20 are logically connected to a common source pillar (e.g., SP (i+1) n ) and common drain pillars (e.g., DP (i+1) n ) along the

[0014] BLOCK (i+1) and block BLOCK (i) means the source line (e.g., SL n and S.L. n+1 ) and bit lines (e.g., BL n and B.L. n+1 ) are shared. Therefore, the source line SL n and bit line BL n BLOCK (i) AND memory array A (i) , which is coupled to the n-th column of AND memory cells 20 in the block BLOCK (i+1) AND memory array A (i+1) Similarly, the source line SL n+1 and bit line BL n+1 BLOCK (i) AND memory array A (i) , coupled to the (n+1)th column of AND memory cells 20 in block BLOCK (i+1) AND memory array A (i+1)2. The (n+1)th column of AND memory cells 20 in the row 11 is coupled to the (n+1)th column of AND memory cells 20 in the row 11.

[0015] 1B-1D, the memory array 10 may be disposed, for example, above an interconnect structure of a semiconductor die, for example, above one or more active devices (e.g., transistors) formed on a semiconductor substrate. Thus, the dielectric substrate (also referred to as a dielectric layer) 50 may be a dielectric layer (e.g., a silicon oxide layer) above a metal interconnect structure formed on a silicon substrate. The memory array 10 may include a stacked structure GSK, a plurality of channel pillars 16, a plurality of first conductive pillars (also referred to as source pillars) 32a, a plurality of second conductive pillars (also referred to as drain pillars) 32b, and a plurality of charge storage structures 40.

[0016] 1B, a stack structure GSK is formed on a dielectric substrate 50. The stack structure GSK includes a number of gate layers (also called word lines or conductive layers) 38 and a number of insulating layers 54 stacked vertically on a surface 50s of the dielectric substrate 50. In the Z direction, the gate layers 38 are electrically insulated from each other by the insulating layers 54 arranged between them. The gate layers 38 extend in a direction parallel to the surface of the dielectric substrate 50. As shown in FIGS. 1F-1I, the gate layers 38 in the stepped region SR may have a stepped structure SC. Thus, the lower gate layers 38 are longer than the upper gate layers 38, and the ends of the lower gate layers 38 extend laterally beyond the ends of the upper gate layers 38. Contacts (not shown) for connecting to the gate layers 38 may be placed on the ends of the gate layers 38 to connect each gate layer 38 to a respective conductive line.

[0017] 1B-1D, the memory array 10 further includes a plurality of channel pillars 16. In some embodiments, each channel pillar 16 has a ring shape when viewed from above. The material of the channel pillars 16 may include a semiconductor such as undoped polysilicon.

[0018] 1B to 1D, the memory array 10 further includes a plurality of insulating pillars 28, a plurality of first conductive pillars 32a, and a plurality of second conductive pillars 32b. In this example, the first conductive pillar 32a functions as a source pillar. The second conductive pillar 32b functions as a drain pillar. Each of the first conductive pillar 32a, the second conductive pillar 32b, and the insulating pillar 28 extends in a direction (i.e., Z direction) perpendicular to the surface of the gate layer 38 (i.e., XY plane). The first conductive pillar 32a and the second conductive pillar 32b are separated by the insulating pillar 28 and surrounded by the insulating fill layer 24. The first conductive pillar 32a and the second conductive pillar 32b are electrically connected to the channel pillar 16. The first conductive pillar 32a and the second conductive pillar 32b may include doped polysilicon or a metal material. The insulating pillars 28 may comprise silicon nitride or silicon oxide, and the insulating fill layer 24 may comprise silicon oxide.

[0019] 1C and 1D, a charge storage structure 40 is disposed between the channel pillar 16 and a gate layer (also referred to as a conductive layer) 38. The charge storage structure 40 may include a tunnel layer (also referred to as a band gap engineered tunnel oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is disposed between the tunnel layer 14 and the blocking layer 36. In some embodiments, the tunnel layer 14 and the blocking layer 36 include silicon oxide. The charge storage layer 12 includes silicon nitride or other materials capable of trapping charges. In some embodiments, as shown in FIG. 1C, a portion of the charge storage structure 40 (e.g., the tunnel layer 14 and the charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), and another portion of the charge storage structure 40 (e.g., the blocking layer 36) surrounds the gate layer 38. In another embodiment, a charge storage structure 40 (eg, tunnel layer 14, charge storage layer 12, and blocking layer 36) surrounds a corresponding gate layer 38, as shown in FIG. 1D.

[0020] Referring to FIG. 1E, the charge storage structure 40, the channel pillar 16, the source pillar 32a, and the drain pillar 32b are surrounded by a gate layer 38 to define the memory cell 20. According to different operation methods, one-bit or two-bit operations can be performed on the memory cell 20. For example, when a voltage is applied to the source pillar 32a and the drain pillar 32b, since the source pillar 32a and the drain pillar 32b are connected to the channel pillar 16, electrons move along the channel pillar 16 and are stored in the entire charge storage structure 40. Thus, one-bit operations can be performed on the memory cell 20. In addition, for operations involving Fowler-Nordheim tunneling (tunnel injection), electrons or holes can be trapped in the charge storage structure 40 between the source pillar 32a and the drain pillar 32b. For operations including source-side injection, channel hot electron injection, and band-to-band tunneling hot carrier injection, electrons or holes can be trapped locally in the charge storage structure 40 adjacent to one of the source pillar 32a and drain pillar 32b. Thus, single level cell (SLC, 1 bit) or multi-level cell (MLC, 2 bits or more) operations can be performed on the memory cell 20.

[0021] In operation, a voltage is applied to a selected word line (gate layer) 38; for example, a corresponding threshold voltage (V th ), the channel region where the channel pillar 16 intersects the selected word line 38 is turned on, causing a current to flow through the bit line BL n Or BL n+1 1B), into drain pillar 32b, through the on-state channel region (e.g., in the direction indicated by arrow 60) to source pillar 32a, and finally to source line SL n or SL n+1 Allows the flow to

[0022] 1F to 1I are schematic cross-sectional views of various staircase structures.

[0023] 1F-1I, in some embodiments of the present invention, the conductive layer 38 of the upper staircase portion TP of the staircase structure SC can function as a word line. The conductive layer 38 of the lower staircase portion LP of the staircase structure SC can be used to close a leakage path. An end of the lower staircase portion LP is connected to an extension of the staircase structure SC. The resistance of the extension EP is different from the resistance of the adjacent conductive layer 38g. The conductive layer 38g includes, for example, tungsten. The extension EP includes a semiconductor such as polysilicon.

[0024] 1F and 1G, in some embodiments, the extension EP and the adjacent conductive layer 38g can be electrically insulated from each other by the blocking layer 36 of the charge storage structure 40. With reference to FIGS. 1H and 1I, in some embodiments, the extension EP and the adjacent conductive layer 38g can be electrically insulated from each other by the blocking layer 36, the charge storage layer 12, and the tunnel layer 14 of the charge storage structure 40.

[0025] With reference to Figures 1F and 1H, the extension EP can include multiple layers. With reference to Figures 1G and 1I, the extension EP can also be a single layer. Each layer of the extension EP is connected to one of the lower step portions LP. conductive In addition, the conductive layers 38g of the lower staircase portion LP are electrically connected to each other through connections 38v. conductive A barrier layer 37 may also be included between layers 38g. The barrier layer 37 may include: conductive It may be disposed between layer 38g and blocking layer 36. The material of barrier layer 37 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.

[0026] 2A to 2I are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0027] Referring to FIG. 2A, a dielectric substrate 100 is provided. The dielectric substrate 100 is, for example, a dielectric layer of an interconnect structure formed on a silicon substrate. The material of the dielectric substrate 100 includes silicon oxide. A plurality of insulating layers 92 and a plurality of semiconductor layers 94 are alternately stacked on the dielectric substrate 100 one by one. Each insulating layer 92 includes a silicon oxide layer. Each semiconductor layer 94 includes a doped polysilicon layer. In this embodiment, there are three insulating layers 92 and two semiconductor layers 94, but the present invention is not limited thereto. In other embodiments, more or fewer insulating layers 92 and more or fewer semiconductor layers 94 can be formed according to actual needs.

[0028] Referring to FIG. 2B, a mask layer 95 is formed on a dielectric substrate 100. The mask layer 95 has an opening. The opening can have various shapes, such as a circle, an ellipse, a square, a rectangle, etc. Then, an etching process is performed to transfer the opening to the underlying insulating layer 92 and the semiconductor layer 94 to form an opening OP1. The opening OP1 can be a contact opening or a contact trench. The opening OP1 can expose the bottom semiconductor layer 94.

[0029] 2B and 2C, the mask layer 95 is removed. Next, another semiconductor layer 94T is formed on the insulating layer 92. The semiconductor layer 94T further fills the opening OP1 to form the connection 96. In addition, the semiconductor layer 94T can be grounded to act as a discharge path. The insulating layer 92 and the semiconductor layers 94 and 94T together form the lower part BP of the stacked structure SK1.

[0030] Referring to FIG. 2C, the upper part UP of the laminated structure SK1 is formed on the lower part BP of the laminated structure SK1. In this embodiment, the upper part UP of the laminated structure SK1 includes a plurality of insulating layers 104 and a plurality of intermediate layers 106, which are alternately stacked one by one on the lower part BP of the laminated structure SK1. Each insulating layer 104 includes a silicon oxide layer. Each intermediate layer 106 includes a silicon nitride layer. The intermediate layer 106 can function as a sacrificial layer, which can be completely or partially removed in a subsequent process. In this embodiment, the laminated structure SK1 has seven insulating layers 104 and six intermediate layers 106, but the present invention is not limited thereto. In other embodiments, more insulating layers 104 and more intermediate layers 106 can be formed according to actual needs.

[0031] Referring to FIG. 2D, the upper part of the stacked structure SK1 is patterned, whereas the lower part BP of the stacked structure SK1 is not patterned to form a staircase structure SC. The lengths of the intermediate layers 106 are gradually increased from the top to the bottom, and the lengths of the semiconductor layers 94 are approximately the same. Then, a dielectric layer 107 is formed on the dielectric substrate 100. The dielectric layer 107 covers the staircase structure SC. The dielectric layer 107 can have a flat surface by a chemical mechanical polishing process. The bottom insulating layer 104 on the upper part UP of the stacked structure SK1 covers the lower part BP of the stacked structure SK1.

[0032] Referring to FIG. 2E, lithography and etching processes are performed to form a plurality of openings 108 in the stack structure SK1 in the array region (not shown). Each opening 108 extends from an upper portion UP to a lower portion BP of the stack structure SK1. The openings 108 have a circular outline, but the invention is not limited thereto. In other embodiments, the openings 108 can have an outline of other shapes, such as a polygon (not shown). The etching process can include a dry etching process. During the dry etching process, the semiconductor layer 94T can function as a conductive path for charges.

[0033] Referring to FIG. 2E, a protective layer 110 is formed on the sidewalls of the semiconductor layer 94 and the intermediate layer 106. Each protective layer 110 includes a silicon oxide layer. A method for forming the protective layer 110 includes a dry thermal oxidation process, a wet thermal oxidation process, or a combination thereof. Then, a channel pillar 116 is formed in each opening 108. A material of the channel pillar 116 includes a semiconductor, such as undoped polysilicon. A method for forming the channel pillar 116 includes forming a channel material on the stack structure SK1 and in the opening 108. Then, an etch-back process is performed to partially remove the channel material to form the channel pillar 116.

[0034] Referring to FIG. 2E, an insulating fill layer 124 and an insulating pillar 128 are formed in each opening 108. The material of the insulating fill layer 124 includes silicon oxide, and the method of forming the insulating pillar 128 includes silicon nitride, and the method of forming the insulating pillar 128 includes chemical vapor deposition. The insulating fill layer 124 is filled in the opening 108, and before the insulating fill layer 124 completely fills the opening 108, a filling material different from the insulating fill layer 124 is filled in the opening 108 to seal the opening 108. The insulating material is etched back by dry etching or wet etching until the surface of the insulating fill layer 124 is exposed, and thus the insulating material remaining in the center of the opening 108 forms the insulating pillar 128.

[0035] Referring to FIG. 2E, a patterning process (e.g., lithography and etching process) is performed to form holes (not shown) in the insulating fill layer 124. Then, conductive pillars 132a and 132b are formed in the holes. The conductive pillars 132a and 132b can function as source pillars and drain pillars, respectively, and are each electrically connected to the channel pillar 116. The conductive pillars 132a and 132b can be formed by forming a conductive layer on the insulating fill layer 124 and in the holes, followed by an etch-back process. The conductive pillars 132a and 132b include doped polysilicon. The conductive pillars 132a and 132b, the channel pillar 116, the insulating pillar 128, and the insulating fill layer 124 are collectively referred to as a vertical pillar VC.

[0036] 2E-2H, an exchange process is performed to exchange the intermediate layers 106 and a portion of the semiconductor layer 94 with the conductive layers 138 and the charge storage structures 140. First, referring to FIG. 2E, a patterning process (e.g., lithography and etching process) is performed on the stack structure SK1 to form an isolation trench 133 (or slit in some examples). The isolation trench 133 extends from the upper portion UP to the lower portion BP of the stack structure SK1. Then, a multi-stage etching process is performed. First, a first-stage etching process is performed to remove a portion of the semiconductor layer 94 to form the horizontal openings 119 and the connection openings 117. The first-stage etching process can include a wet etching process. The etchant (etching solution) that can be used in this wet etching process includes ammonium hydroxide and hydrogen peroxide, such as the chemical etchant SC1. The horizontal openings 119 can have approximately the same length or different lengths. The length of the horizontal openings 119 is greater than the length of the bottom intermediate layer 106. Portions of the semiconductor layer 94 are left at the ends of the horizontal openings 119 to form a plurality of extensions EP.

[0037] 2G, a second-stage etching process of the multi-stage etching process is performed to remove parts of the intermediate layers 106 to form the horizontal openings 121. The second-stage etching process can include a wet etching process. The etchant used in the wet etching process includes hot phosphoric acid. During the etching process, the protective layer 110 can function as a stop layer because the materials of the insulating layer 104 and the protective layer 110 are different from the material of the intermediate layer 106.

[0038] Referring to FIG. 2H, a plurality of charge storage structures 140 (each including a tunnel layer 114, an accumulation layer 112, and a blocking layer 136), a plurality of barrier layers 137, and a plurality of conductive layers 138 are formed in the plurality of horizontal openings 121 and 119. The tunnel layer 114 includes silicon oxide. The accumulation layer 112 includes silicon oxynitride, silicon nitride, or a combination thereof. The blocking layer 136 includes silicon oxide, a material having a high dielectric constant of 7 or more, or a combination thereof. The material having a high dielectric constant of 7 or more includes aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), a transition metal oxide, a lanthanide oxide, or a combination thereof. The material of each barrier layer 137 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The material of each conductive layer 138 includes tungsten.

[0039] The method of forming the tunnel layer 114, the accumulation layer 112, the blocking layer 136, the barrier layer 137, and the conductive layer 138 includes the steps of forming a tunneling material, an accumulation material, a blocking material, a barrier material, and a conductive material in sequence. The thicknesses of the tunneling material, the accumulation material, the blocking material, the barrier material, and the conductive material are thick enough to completely fill the horizontal openings 121, 119, and the connection openings 117. The height H1 of the horizontal openings 119 is equal to or smaller than the height H2 of the horizontal openings 121. The diameter (or width) W of the connection openings 117 is equal to or smaller than the heights H2, H1 of the horizontal openings 121, 119. Then, an etch-back process is performed to remove the accumulation material, the blocking material, the barrier material, and the conductive material in the isolation trenches 133, and form the tunnel layer 114, the accumulation layer 112, the blocking layer 136, the barrier layer 137, and the conductive layer 138 in the horizontal openings 121, 119, and the connection openings 117. Thus, the laminated structure SK2 and the staircase structure SC are formed. The length of the conductive layer 138 of the upper staircase portion TP of the staircase structure SC gradually increases from the top to the bottom. The lower staircase portion LP of the staircase structure SC is adjacent to the extension portion EP, and the conductive layer 138g is separated from the extension portion EP by the charge storage structure 140.

[0040] Referring to FIG. 2H, a separation wall SLT is formed in the separation trench 133. The stack structure SK2 is divided into a plurality of zones by the separation wall SLT. In some embodiments, the separation wall SLT may include an insulating layer 142. The method of forming the separation wall SLT includes forming an insulating material on the stack structure SK2 to fill in the separation trench 133, and then removing the excess insulating material by an etch-back process or a planarization process. In other embodiments, the separation wall SLT further includes a fill layer (not shown) surrounded by the insulating layer 142. The fill layer may provide sufficient support to avoid bending of the separation wall SLT. The insulating layer 142 includes silicon oxide, and the fill layer includes polysilicon.

[0041] 2I, a number of contacts COA1 and COA2 are formed above the dielectric substrate 100. The contact COA2 is placed on and electrically connected to the conductive layer 138 of the upper staircase portion TP of the staircase structure SC. The contact COA1 is placed on and electrically connected to the top conductive layer 138g of the lower staircase portion LP of the staircase structure SC.

[0042] In the present invention, Lamination The barrier layer 137 and the conductive layer 138 of the upper part UP of the structure SK2 function as a number of word lines of the memory array. The stack structure SK2 in the array area includes a number of memory cells. These memory cells are connected in parallel to each other through the conductive pillars 132a and 132b to form a memory string. The conductive layer 138 of the upper part UP of the stack structure SK2 is electrically connected to a subsequently formed upper interconnect structure through the contact COA2. The conductive layers 138g of the lower part BP of the stack structure SK2 are connected to each other through the connection 138v and are electrically connected to a subsequently formed upper interconnect structure through the contact COA1. The conductive layer 138g can function as a gate or a dummy gate. In some embodiments, as shown in Figures 3A and 3B, stairs No contacts are placed or electrically connected onto the extension EP at the end of the lower stepped portion LP of the structure SC.

[0043] 3A and 3B are top views of several staircase structures of a memory device according to one embodiment of the present invention.

[0044] 3A and 3B, the connection portion 138v can be a connection hole (as shown in FIG. 3A) or a connection wall (as shown in FIG. 3B). The shape of the connection portion 138v can be a circle (as shown in FIG. 3A), a strip (as shown in FIG. 3B), or an oval (not shown), but the present invention is not limited thereto. With reference to FIG. 3B, in an embodiment in which the connection portion 138v is a strip-shaped connection wall, the extension direction of the connection wall can be perpendicular to the extension direction of the separation wall SLT, but the present invention is not limited thereto.

[0045] As shown in Figures 3A and 3B, the connection 138v can be oriented in any suitable manner. The connection 138v can be located in the conductive layer 138 of the upper step portion TP (not shown) or can be located in the conductive layer 138g and in the insulating layer 92 of the lower step portion LP (as shown in Figure 2I).

[0046] Contact COA2 is disposed on the upper surface of conductive layer 138 in upper staircase portion TP. Contact COA1 is disposed on the upper surface of top conductive layer 138g in lower staircase portion LP. Connection portion 138v is disposed between the lower surface of top conductive layer 138g and the upper surface of bottom conductive layer 138g. The position of connection portion 138v does not affect the position of contact COA1. Therefore, the position of connection portion 138v can be shifted in a direction perpendicular to dielectric substrate 100 to partially or completely overlap the position of contact COA1 or COA2.

[0047] 3A and 3B, in some embodiments, a support pillar DV (shown in FIGS. 2E-2I) is further provided in the staircase structure SC to prevent the staircase structure SC from collapsing during the exchange of the gate. For simplicity, FIG. 2E shows only a single support pillar DV, but the present invention is not limited thereto. As shown in FIGS. 3A and 3B, the staircase structure SC can include multiple support pillars DV. The support pillar DV can be formed simultaneously during the formation of the vertical pillar VC (shown in FIGS. 2E-2I), and thus the support pillar DV and the vertical pillar VC can have approximately the same height, i.e., can extend from the top surface of the dielectric layer 107 to the insulating layer 92. Alternatively, the support pillar DV can be formed simultaneously during the formation of the through via, which connects the lower interconnect structure to the upper interconnect structure. In other words, the support pillar DV extends from at least the top layer to the bottom layer of the staircase structure SC. Therefore, in order to avoid affecting the arrangement of the support pillar DV, the positions of the connection portions 138v and the support pillars DV are shifted so as not to overlap, as shown in FIGS. 3A and 3B.

[0048] 4A-4F are cross-sectional views illustrating a method for fabricating a memory device according to another embodiment of the present invention.

[0049] Referring to FIG. 4A, a laminated structure SK1 is formed on a dielectric substrate 100. The laminated structure SK1 of FIG. 4A is similar to the laminated structure SK1 of the above embodiment, but does not include a connection portion 96. The method of forming the laminated structure SK1 includes the steps of sequentially forming a lower portion BP and an upper portion UP. The lower portion BP includes a plurality of insulating layers 92 and a plurality of semiconductor layers 94, which are alternately stacked one by one. The bottom semiconductor layer 94 can be grounded to function as a conductive path for charges. The upper portion UP includes a plurality of insulating layers 104 and a plurality of intermediate layers 106, which are alternately stacked one by one. The insulating layers 92, the semiconductor layers 94, the insulating layers 104, and the intermediate layers 106 are similar to those described in the above embodiment.

[0050] 4B, the upper portion UP and the lower portion BP of the stacked structure SK1 are patterned to form a staircase structure SC. In this embodiment, the length of the intermediate layer 106 of the staircase structure SC gradually increases from the top to the bottom, and the length of the semiconductor layer 94 gradually increases from the top to the bottom. Then, a dielectric layer 107 is formed on the dielectric substrate 100. The dielectric layer 107 covers the staircase structure SC.

[0051] Referring to FIG. 4C, vertical pillars VC are formed in stack structure SK1 in the array region by the methods described above.

[0052] 4C to 4F, an exchange process is performed to exchange the intermediate layers 106 and the semiconductor layers 94 with the conductive layers 138 and the charge storage structures 140. First, referring to FIG. 4C, a patterning process (e.g., lithography and etching process) is performed on the stacked structure SK1 to form an isolation trench 133. Next, referring to FIG. 4D, an etching process (e.g., wet etching process) is performed to simultaneously remove a portion of the intermediate layers 106 and a portion of the semiconductor layers 94 to form a plurality of horizontal openings 121 and 119. A portion of the semiconductor layer 94 is left at the end of the bottom horizontal opening 119 to form an extension EP.

[0053] 4E, by the above method, a plurality of charge storage layers 140 (each of which includes a tunnel layer 114, a storage layer 112, and a blocking layer 136), a plurality of barrier layers 137, and a plurality of conductive layers 138 are formed in the horizontal openings 121 and 119. A stacked structure SK2 and a staircase structure SC are thus formed. The length of the conductive layer 138 of the upper staircase portion TP of the staircase structure SC and the conductive layer 138g of the lower staircase portion LP gradually increase from the top to the bottom. The conductive layer 138g of the lower staircase portion LP of the staircase structure SC is adjacent to the extension portion EP, and the conductive layer 138g and the extension portion EP are separated from each other by the charge storage structure 140. Next, a separation wall SLT is formed in the separation trench 133.

[0054] 4F, by the above-mentioned method, a number of contacts COA1 and COA2 are formed on the dielectric substrate 100. The contact COA2 is placed on the conductive layer 138 of the upper staircase portion TP of the staircase structure SC and is electrically connected to this conductive layer 138. The contact COA1 is placed on the conductive layer 138g of the lower staircase portion LP of the staircase structure SC and is electrically connected to this conductive layer 138g.

[0055] In the present invention, the barrier layer 137 and the conductive layer 138 of the upper part UP of the stack structure SK2 function as a number of word lines of the memory array. The stack structure SK2 includes a number of memory cells, which are connected in parallel to each other through the conductive pillars 132a and 132b to form a memory string. The conductive layer 138 of the upper part UP is electrically connected to a subsequently formed upper connection structure through the contact COA2. The lower part BP has a single conductive layer 138g, which is electrically connected to a subsequently formed upper interconnect structure through the contact COA1. The conductive layer 138g can function as a gate or a dummy gate. In some embodiments, no contact is placed on or electrically connected to the extension EP at the end of the staircase structure LP at the bottom of the staircase structure SC, as shown in Figures 5A and 5B.

[0056] 5A and 5B are top views of several staircase structures of a memory device according to other embodiments of the present invention.

[0057] The top views of Figures 5A and 5B are similar to those of Figures 3A and 3B, but the staircase structure SC of Figures 5A and 5B is not provided with any connections. The upper staircase part TP has a larger number of steps and the lower staircase part LP adjacent to the extension EP has a smaller number of steps, even a single step.

[0058] The above embodiment is described by taking AND flash memory as an example. The present invention can also be applied to 3D NOR flash memory and 3D NAND flash memory. The embodiment of the present invention can not only be applied in flash memory, but also be applied to various devices with staircase structure.

[0059] In the embodiment of the present invention, one or more semiconductor layers disposed at the bottom of the stack structure can act as a conductive path for charges to reduce arcing effects and prevent various material layers and components on the dielectric substrate from being damaged by plasma bombardment, thus improving the process yield. In addition, the one or more semiconductor layers can be subjected to a subsequent exchange process to form one or more conductive layers, which can function as gate layers or dummy gate layers. [Industrial Applicability]

[0060] The semiconductor device and the method for manufacturing the semiconductor device of the present invention can be applied to a semiconductor device having a staircase structure and to a method for manufacturing such a semiconductor device. [Explanation of symbols]

[0061] 10. A (i) , A (i+1) :Memory array 12: Charge storage layer 14: Tunnel layer 16: Channel pillar 20: Memory cell 24: Insulating filling layer 28: Insulating pillar 32a: First conductive pillar / source pillar 32b: second conductive pillar / drain pillar 36: Blocking layer 38: Gate layer / conductive layer / word line 38g: Conductive layer 38v: Connection 40: Charge storage structure 50: Dielectric substrate 50s: surface 54: Insulating layer 60: Arrow 92: Insulating layer 94: Semiconductor layer 94T: Semiconductor layer 95: Mask layer 96: Connection 100: Dielectric substrate 104: Insulating layer 106: Middle class 107: Dielectric layer 108: Opening 110: Protective layer 112: Accumulation layer 114: Tunnel layer 116: Channel pillar 117: Connection opening 119:Horizontal opening 121:Horizontal opening 124: Insulating filling layer 128: Insulating pillar 132a: Conductive pillar 132b: Conductive pillar 133: Isolation trench 136: Blocking layer 137: Barrier layer 138: Gate layer / conductive layer / word line 138g: Conductive layer 138v: Connection 140: Charge storage structure 142: Insulating layer BP: Lower COA1: Contact COA2: Contact DV: Support pillar EP: Extension part GSK:Laminated structure H1:Height H2:Height LP: Lower staircase OP1: Opening SC: Stair structure SK1:Laminated structure SK2:Laminated structure SLT: Separation wall TP: Upper staircase UP: Top VC: Vertical pillar W: Distance I-I': Straight line II-II': Straight line BLOCK, BLOCK (i) , BLOCK (i+1) :block BL n , B.L. n+1:Bit line SP (i) n , S.P. (i) n+1 , S.P. (i+1) n , S.P. (i+1) n+1 :Source pillar DP (i) n , D.P. (i) n+1 , D.P. (i+1) n , D.P. (i+1) n+1 :Drain pillar W.L. (i) m , W.L. (i) m+1 , W.L. (i+1) m , W.L. (i+1) m+1 : Word line

Claims

1. a staircase structure disposed on a dielectric substrate, the staircase structure comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked one on top of the other; an extension portion disposed at an end of a lower step portion of the staircase structure and being a polysilicon layer; a plurality of contacts disposed on the plurality of conductive layers and not disposed on the extension; A semiconductor device comprising: A semiconductor device in which the extension has a resistance different from a resistance of the plurality of conductive layers.

2. The semiconductor device of claim 1 , wherein the extension has a higher resistance than a resistance of the plurality of conductive layers.

3. The semiconductor device of claim 1, wherein the plurality of conductive layers comprises a metallic material.

4. 2. The semiconductor device of claim 1, further comprising a connection portion disposed within the lower step portion and connected to the conductive layer of the lower step portion.

5. The semiconductor device of claim 4 , wherein the width of the connection is less than the thickness of the conductive layer.

6. The semiconductor device of claim 4 , further comprising a support pillar extending through the conductive layer and the insulating layer of the staircase structure.

7. The semiconductor device of claim 6 , wherein the connection portion is offset relative to the support pillar.

8. The semiconductor device of claim 4 , wherein the connection comprises a connection via or a connection wall.

9. 9. The semiconductor device of claim 8, further comprising a separation wall extending through the staircase structure, the direction in which the connecting walls extend being different than the direction in which the separation walls extend.

10. a channel pillar extending through the staircase structure; a plurality of conductive pillars disposed within and electrically connected to the channel pillars; a charge storage layer disposed between the conductive layer and the channel pillar; The semiconductor device of claim 1 further comprising:

11. The semiconductor device of claim 10 , wherein the charge storage layer is further disposed between the extension and the lower step portion of the step structure.

12. 2. The semiconductor device of claim 1, wherein in said plurality of conductive layers, a thickness of said conductive layer connected to said extension is no greater than a thickness of said conductive layer not connected to said extension.

13. 1. A method for manufacturing a semiconductor device, comprising: forming a staircase structure on a dielectric substrate, the staircase structure comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked one on top of the other; forming an extension portion, which is a polysilicon layer, at an end of a lower step portion of the staircase structure; forming a plurality of contacts disposed on the plurality of conductive layers of the staircase structure and not disposed on the extension; The extension has a resistance different from a resistance of the plurality of conductive layers.

14. The step of forming the staircase structure includes: forming a plurality of semiconductor layers and a plurality of insulating layers, which are alternately stacked one on the other, on the dielectric substrate; patterning the semiconductor layers and the insulating layers to form the staircase structure; replacing a portion of the semiconductor layers with the conductive layers, leaving a portion of the semiconductor layers at an edge of the lower horizontal opening to form the extension; The method of claim 13, comprising:

15. forming a first connection portion connecting the plurality of semiconductor layers; removing the first connection portion to form a connection opening; forming a conductive material in the contact opening to form a second contact; The method of claim 14 further comprising:

16. 16. The method according to claim 15, wherein the connection opening comprises a connection opening or a connection trench and the second connection comprises a connection via or a connection wall.

17. forming a channel pillar, the channel pillar penetrating the stair structure; forming a plurality of conductive pillars within the channel pillar, the plurality of conductive pillars being electrically connected to the channel pillar; forming a charge storage layer between the conductive layer and the channel pillar and between the conductive layer and the extension; 20. The method of claim 16, further comprising:

18. forming a separation wall, the separation wall extending through the staircase structure; The method of claim 16 , wherein the direction in which the connecting walls extend is different than the direction in which the separating walls extend.

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