Substrate, recording device and manufacturing method

Abstract

To provide a technique that can increase a writing power of an anti-fuse element as necessary.SOLUTION: A substrate comprises: a plurality of storage units each including an anti-fuse element and a switching element switching application of a predetermined voltage to the anti-fuse element; wiring to which the plurality of storage units are connected; a first electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied; and a second electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a substrate having an anti-fuse element. [Background technology]

[0002] After a product is completed, an OTP (One Time Programmable) memory is used to record product-specific information such as a chip ID, setting parameters, etc. A memory using an anti-fuse element is known as an OTP memory (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-47215 A Summary of the Invention [Problem to be solved by the invention]

[0004] The power for writing to the anti-fuse elements is supplied by the built-in power supply of the product in which the memory is embedded. In products with many anti-fuse elements, the number of simultaneous writes to the anti-fuse elements is limited by the output of the built-in power supply. In terms of production efficiency, it is advantageous to have a large number of simultaneous writes during the writing process before the product is shipped. However, increasing the output of the built-in power supply just for that purpose would be wasteful in terms of product use after shipment.

[0005] The present invention provides a technique that makes it possible to increase the write power of an anti-fuse element as needed. [Means for solving the problem]

[0006] According to the present invention, a plurality of memory units each including an anti-fuse element and a switching element for switching application of a predetermined voltage to the anti-fuse element; Wiring to which the plurality of storage units are respectively connected; a first electrode pad to which a voltage is applied for supplying the predetermined voltage to the wiring; a second electrode pad to which a voltage is applied for supplying the predetermined voltage to the wiring; picture, the memory unit includes a resistive element connected between the anti-fuse element and the wiring; A substrate is provided. Effect of the Invention

[0007] According to the present invention, it is possible to provide a technique that enables the write power of an anti-fuse element to be increased as necessary. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a circuit diagram of a substrate according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit diagram showing a modified example of the substrate in FIG. [Diagram 3] FIG. 3 is a diagram illustrating the structure of the board in FIG. 2. [Figure 4] 1 is an external view of a recording apparatus according to an embodiment of the present invention. [Diagram 5] (A) is a perspective view of the recording head and its periphery, and (B) is a cutaway view of the ink ejection orifices and their periphery. [Figure 6] FIG. 11 is a circuit diagram of a substrate according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0010] First Embodiment FIG. 1 is a circuit diagram of a substrate 1 according to one embodiment of the present invention. The substrate 1 is a storage device having a plurality of storage units 2-1 to 2-N. In this embodiment, the substrate 1 has N storage units 2-1 to 2-N, which are referred to collectively as storage unit 2 when there is no need to distinguish between the individual storage units. Each storage unit 2 is a storage circuit that includes an anti-fuse element 3 and is capable of holding 1 bit of information. 1 Although only the circuit of storage unit 2-1 is illustrated, other storage units 2-2 to 2-N also have the same circuit.

[0011] The anti-fuse element 3 has, for example, a MOS (Metal Oxide Semiconductor) structure, and is an element whose resistance value changes before and after information is written. In the case of this embodiment, the anti-fuse element 3 functions as a capacitive element before information is written, and functions as a resistive element after information is written. In other words, the resistance value of the anti-fuse element 3 changes due to the information writing operation, and this makes it possible to express 1 bit of information.

[0012] The N memory units 2 are connected in parallel between a wiring 7 and a wiring 8. The anti-fuse element 3 of each memory unit 2 is connected to the wiring 7 via a connection point 2a. The anti-fuse element 3 of each memory unit 2 is connected to the wiring 8 via a switching element 4 and a connection point 2b. In this embodiment, a write voltage for the anti-fuse element 3 is applied to the wiring 7, and the wiring 8 is at a ground potential (GND potential). The write voltage is, for example, 32V.

[0013] The switching element 4 is an element that switches the application of a write voltage to the anti-fuse element 3, and in this embodiment, is a high-voltage N-type MOS transistor. A high-voltage transistor (DMOS transistor (Double-diffused MOSFET)) is a transistor that has a higher withstand voltage than transistors (such as switching elements 5 and 6 described later) used in logic circuits. A higher voltage can be applied to a high-voltage transistor. The drain D of the switching element 4 is connected to the anti-fuse element 3, and the source S and back gate B are connected to the wiring 8 via the connection point 2b. When the switching element 4 is turned on, the voltage applied to the wiring 7 can be applied to the anti-fuse element 3.

[0014] The gate G of the switching element 4 is connected to the transistors 5 and 6. In this embodiment, the transistors 5 and 6 form a logic circuit (an inverter in this embodiment). In this embodiment, the transistor 5 is a P-type MOS transistor, and the transistor 6 is an N-type MOS transistor. A voltage VDD is supplied to the source S and back gate B of the transistor 5. The drain D of the transistor 5 is connected to the drain D of the transistor 6 and the gate G of the switching element 4. The source S and back gate B of the transistor 6 are grounded. By making the transistors 5 and 6 forming the logic circuit transistors with a lower withstand voltage than the switching element 4, the logic circuit can be operated at high speed.

[0015] The substrate 1 includes a signal control circuit 10, and each gate G of the transistors 5 and 6 is connected to the signal control circuit 10. The signal control circuit 10 outputs corresponding control signals (selection signals) S1 to SN to the storage units 2-1 to 2-N via a connection point 2c.

[0016] The substrate 1 includes an electrode pad group 11 that serves as an electrical contact with an external device of the substrate 1. The electrode pad group 11 includes electrode pads 12 and 13. A power supply voltage is applied to the electrode pad 12 from an internal power supply 201 of a device (not shown) including the substrate 1. The electrode pad 13 is connected to the GND of the internal power supply 201. The substrate 1 includes a voltage application circuit 9 connected between the electrode pad 12 and the wiring 7.

[0017] The voltage application circuit 9 outputs a write voltage to the wiring 7 based on the power supply voltage applied to the electrode pad 12. The voltage application circuit 9 may include a switching circuit that switches the application of the write voltage to the wiring 7. The electrode pad group 11 may include an electrode pad to which a control signal for the switching circuit is input. Furthermore, the voltage application circuit 9 may include a boost circuit that boosts the power supply voltage to the write voltage when the power supply voltage applied to the electrode pad 12 is lower than the write voltage. Furthermore, the voltage application circuit 9 may include a step-down circuit that steps down the power supply voltage to the write voltage when the power supply voltage applied to the electrode pad 12 is higher than the write voltage.

[0018] The electrode pad group 11 includes a plurality of electrode pads 14. A control signal for controlling the signal control circuit 10 is input to the electrode pad 14 from a control circuit (not shown) of an apparatus (not shown) including the substrate 1. The electrode pad group 11 also includes electrode pads 15 and 16. The electrode pad 15 is connected to a wiring 7, and the electrode pad 16 is connected to a wiring 8. An external power source 202 outside the apparatus including the substrate 1 can be selectively connected to the electrode pad 15 to apply a write voltage from the external power source 202. Note that, in this embodiment, the electrode pad 13 and the electrode pad 16 are provided as electrode pads connected to the wiring 8, but either one of them may be used.

[0019] Next, a description will be given of the operation of writing information to the anti-fuse element 3. Writing information to the anti-fuse element 3 can be performed during the manufacturing process of the substrate 1 before shipment of the substrate 1 or a product incorporating the substrate 1, or during operation of the product after shipment.

[0020] First, with a write voltage applied to the wiring 7, the signal control circuit 10 outputs a low-level control signal (a signal at ground potential) to the memory unit 2 to which information is to be written. For example, when information is to be written to the anti-fuse element 3 of the memory unit 2-2, the signal control circuit 10 outputs a control signal S2 to the connection point 2c of the memory unit 2-2.

[0021] In the memory unit 2 that receives a low-level control signal from the signal control circuit 10, the transistor 5 is turned on and the transistor 6 is turned off, the VDD voltage is supplied to the gate G of the switching element 4, and the switching element 4 is turned on. As a result, a write voltage is applied to the anti-fuse element 3, and the anti-fuse element 3 changes from a capacitive element to a resistive element. A detailed configuration example of the anti-fuse element 3 having such characteristics will be described later with reference to FIG. 3.

[0022] The write voltage applied to the wiring 7 can be supplied by a voltage supply circuit 9. However, when information is simultaneously written to each of the anti-fuse elements 3 of a large number of memory units 2, the write current increases in proportion to the number of anti-fuse elements 3 to which information is simultaneously written. As a result, the power provided by the voltage supply circuit 9 may be insufficient, which may result in restrictions on the number of anti-fuse elements 3 to which information can be simultaneously written. At production sites and the like where substrates 1 are manufactured before shipment, it is necessary to shorten the time required to write information and improve tact time, and therefore a circuit configuration capable of simultaneously writing to a larger number of anti-fuse elements 3 is required.

[0023] In this embodiment, in addition to the electrode pad 12 to which a power supply voltage for supplying a write voltage to the wiring 7 is applied, an electrode pad 15 to which a power supply voltage of an external power supply 202 for supplying a write voltage to the wiring 7 is applied is provided. When writing information to a large number of anti-fuse elements 3 during the manufacturing process of the substrate 1, the external power supply 202 is connected to the electrode pad 15 and a write voltage is supplied from the external power supply 202 to the wiring 7. By using the internal power supply 201 and the external power supply 202 in combination, it is possible to supply the wiring 7 with power required for writing information to a large number of anti-fuse elements 3. Furthermore, the power required for writing information to a large number of anti-fuse elements 3 may be supplied to the wiring 7 only from the external power supply 202 without using the internal power supply 201.

[0024] In this manner, in this embodiment, the write power of the anti-fuse elements 3 can be increased as necessary. Therefore, when product-specific information or the like is written to the storage unit 2 at the production site before the product is shipped, a write voltage can be supplied to the wiring 7 using the internal power supply 201 and the external power supply 202, or only the external power supply 202. This allows information to be written to a large number of anti-fuse elements 3 at the same time. Furthermore, when information is written to the storage unit 2 after the product is shipped, a write voltage can be supplied to the wiring 7 using the internal power supply 201. This also allows information such as the operation history of the device including the substrate 1 to be stored in the storage unit 2.

[0025] To read out information written in the memory unit 2, for example, a current of a predetermined current value is supplied from the wiring 7 to the anti-fuse element 3 of the memory unit 2 to be read out. This makes it possible to measure the voltage (potential difference between the connection point 2a and the connection point 2b) generated in the anti-fuse element 3 and read out this voltage as information.

[0026] <Modification> Fig. 2 shows a modified example of the substrate 1. In the substrate 1 of Fig. 2, the memory unit 2 includes resistive elements 17 and 18. The resistive element 17 is a resistive element for preventing static electricity, connected between the wiring 7 and the anti-fuse element 3. For example, when a surge voltage is applied to the electrode pad 15, the resistive element 17 absorbs the electrical energy of the surge voltage to prevent the anti-fuse element 3 from being destroyed by the electrical energy.

[0027] When the anti-fuse element 3 is in the state of a capacitive element before writing, the resistive element 18 can fix the voltage applied to the drain D of the switching element 4 when the switching element 4 is off to the voltage of the wiring 7 (write voltage).

[0028] <Board structure> Fig. 3 shows a specific example of a cross-sectional structure of the anti-fuse element 3, the resistance element 18, and the switching element 4 in the substrate 1 of Fig. 2. The substrate 1 includes a semiconductor substrate 310.

[0029] In a semiconductor substrate 310, a P-well region 301 and N-well regions 302a, 302b, and 302c are formed on a P-type silicon substrate 300. The P-well region 301 can be formed in the same process as the P-well of an N-type MOS transistor 6 constituting a logic circuit. The N-well regions 302a, 302b, and 302c can be formed in the same process as the N-well of a P-type MOS transistor 5 constituting a logic circuit.

[0030] The impurity concentration of the N-well region with respect to the P-type silicon substrate 300 is set so that the breakdown voltage between the N-well regions 302a, 302b, and 302c and the P-type silicon substrate 300 is higher than the write voltage. Also, the impurity concentrations of the P-well region 301 and the N-well regions 302a, 302b, and 302c are set so that the breakdown voltage between the P-well region 301 and the N-well regions 302a and 302b is higher than the write voltage.

[0031] A field oxide film 303, high concentration N-type diffusion regions 306a to 306e, and a high concentration P-type diffusion region 307 are formed in the P-well region 301 and the N-well regions 302a, 302b, and 302c. The field oxide film 303 can be formed by, for example, a LOCOS (Local Oxidation of Silicon) method.

[0032] The configuration of the switching element 4, which is a high-voltage N-type MOS transistor, will be described. A gate electrode 305a constituting the gate G is disposed on the adjacent P-well region 301 and N-well region 302a via a gate insulating film 304. The region where the P-well region 301 and the gate electrode 305a overlap becomes a channel formation region.

[0033] The high-concentration N-type diffusion region 306a is the source S of the switching element 4, and the high-concentration P-type diffusion region 307 is an electrode that constitutes the back gate B. The N-well region 302a has a portion that extends to the bottom of the gate electrode 305a as an electric field relaxation region for the drain D. The high-concentration N-type diffusion region 306b formed in the N-well region 302a becomes the electrode for the drain D of the switching element 4.

[0034] Furthermore, the drain side of the gate electrode 305a has a so-called LOCOS offset structure, which is a structure in which the gate electrode 305a rides up on the field oxide film 303 formed in the N-well region 302. This ensures a gate-drain breakdown voltage even when the switching element 4 is in an off state, that is, when the voltage of the gate electrode 305a is the ground voltage (GND) and the voltage of the drain D electrode rises to the write voltage.

[0035] Next, the structure of the anti-fuse element 3 will be described. The anti-fuse element 3 has an upper electrode, a lower electrode, and an insulating layer (gate insulating film 304) therebetween. For example, an electrode 305b provided on the N-well region 302b via the gate insulating film 304 functions as the upper electrode of the anti-fuse element 3. In addition, in the N-well region 302b, a portion that is connected to the high concentration N-type diffusion region 306c and overlaps with the upper electrode in a plan view of the surface of the semiconductor substrate 310 on which elements such as the switching element 4 are arranged functions as a lower electrode. By applying a predetermined voltage between the upper electrode and the lower electrode, the gate insulating film 304 is broken down, and the resistance value of the anti-fuse element 3 can be reduced.

[0036] Note that the plan view with respect to the surface on which elements such as the switching element 4, the anti-fuse element 3, and the resistance element 18 are arranged is, for example, a plan view with respect to the surface of the channel formation region of the switching element 4.

[0037] 3, the high-concentration N-type diffusion region 306c is formed only in the region of the N-well region 302b that does not overlap with the upper electrode in a plan view, but the high-concentration N-type diffusion region 306c is not limited to this. For example, the high-concentration N-type diffusion region 306b may be formed in a part of the portion that overlaps with the upper electrode or in the entire overlapping region. When the high-concentration N-type diffusion region 306c is also formed in the region that overlaps with the upper electrode in a plan view, the overlapping portion of the high-concentration N-type diffusion region 306c also functions as the lower electrode of the anti-fuse element 3.

[0038] Furthermore, although the lower electrode of the anti-fuse element 3 is connected to the drain D of the switching element 4 in FIG. 2, the upper electrode may be connected to the drain D of the switching element 4, and the lower electrode may be connected to the wiring .

[0039] The gate insulating film 304 can be formed in the process of forming the gate insulating films of the transistors 5 and 6 constituting the logic circuit, and can be formed of, for example, an oxide film. The electrodes 305a and 305b can be, for example, a polysilicon layer. The polysilicon layer, the high concentration N-type diffusion regions 306a to 306c, and the high concentration P-type diffusion region 307 can be formed in the same process as the process of forming each element of the transistors 5 and 6 constituting the low voltage logic circuit.

[0040] In this way, the anti-fuse element 3 is an anti-fuse element having a MOS structure, and the switching element 4 that controls writing to the anti-fuse element 3 is a MOS transistor. Therefore, the anti-fuse element 3 and the switching element 4 can be formed in the same process. This makes it possible to form a semiconductor element inexpensively with a small number of processes.

[0041] An insulating film having a plurality of contact portions 308 is provided on the high concentration P-type diffusion region 307, the N-type diffusion regions 306a to 306e, and the field oxide film 303. Conductive layers 309a to 309b are provided on the insulating film. g The conductive layers 309a to 309 g The conductive layers 309a to 309b can be made of a metal such as aluminum. g As long as the electrodes and wiring are electrically connected, there are no limitations on the manufacturing method, materials, and structure.

[0042] 3, a capacitive element in which the lower electrode and the upper electrode are formed of an N-well region and polysilicon is shown as an example of the anti-fuse element 3, but the anti-fuse element 3 is not limited to this structure and may be, for example, a capacitive element using a P-type MOS transistor. One of the lower electrode and the upper electrode of the anti-fuse element 3 functions as one terminal, and the other functions as the other terminal.

[0043] The resistor element 18 has an N-well region 302c, which is a semiconductor region in a semiconductor substrate 310. e and 309 fvia high concentration N-type diffusion regions 306d and 306e, respectively. The resistance element 18 is not limited to this structure. For example, a resistor made of a conductive layer or a resistor made of polysilicon may be used as the resistance element 18.

[0044] The insulating film is an insulator layer formed on the semiconductor substrate 310 so as to cover the switching element 4, the resistance element 18, etc., and is made of, for example, silicon oxide. The insulator layer is not limited to this, and may be made of silicon nitride or silicon carbide, or may be a laminate or mixture layer of these.

[0045] The conductive layer 309a is connected to the source S and back gate B of the switching element 4 via the contact portion 308, and is supplied with a ground potential. The conductive layer 309b is connected to the electrode of the drain D of the switching element 4 and the lower electrode of the anti-fuse element 3 via the contact portion 308. The conductive layer 309c is connected to the upper electrode of the anti-fuse element 3 via the contact portion 308, and is connected to the wiring 7 at a portion not shown. A write voltage is applied to the conductive layer 309c from the voltage supply circuit 9 when writing information. The conductive layer 309d is connected to the conductive layer 309c (not shown), and the conductive layer 309e is connected to the conductive layer 309b (not shown).

[0046] Second Embodiment 4 is an external view of a recording apparatus 30 according to an embodiment of the present invention. The recording apparatus 30 is an inkjet recording apparatus that ejects ink to perform recording on a recording medium.

[0047] In addition, "recording" includes not only the formation of meaningful information such as characters and figures, but also the formation of images, patterns, and the like on a recording medium, whether meaningful or insignificant, or the processing of the medium, regardless of whether it is manifested in a way that can be visually perceived by humans. In addition, although a sheet of paper is assumed as the "recording medium" in this embodiment, it may also be cloth, plastic film, etc.

[0048] In addition, the recording device to which the present invention can be applied is not limited to an inkjet recording device, and can also be applied to, for example, a thermal transfer type recording device such as a melting type or a dye sublimation type. The recording device may also be, for example, a manufacturing device for manufacturing a color filter, an electronic device, an optical device, a microstructure, etc. by a predetermined recording method. The recording device may also be a device that forms a three-dimensional image from 3D data.

[0049] The recording device 30 includes an ink tank 31 and a recording head 32, which are assembled into one unit, and are mounted on a carriage 34. The recording head 32 ejects ink contained in the ink tank 31 onto a recording medium P to perform recording. The carriage 34 can be reciprocated in the direction of the arrow by a drive unit 35. The drive unit 35 includes a lead screw 35a and a guide shaft 35b that extend in the moving direction of the carriage 34. The lead screw 35a engages with a screw hole (not shown) of the carriage 34, and the carriage 34 moves due to its rotation. A motor 35c and a gear train 35d are a rotation mechanism for the lead screw 35a. The guide shaft 35b guides the movement of the carriage 34. An optical sensor 34b that detects a detection target piece 34a of the carriage 34 is disposed at one end of the moving range of the carriage 34, and the detection result is used to control the movement of the carriage 34.

[0050] The transport unit 33 transports the recording medium P. The transport unit 33 includes a motor (not shown) that is a drive source, and a transport roller (not shown) that rotates by the driving force of the motor, and the recording medium P is transported by the rotation of the transport roller.

[0051] The recording device 30 includes an internal power source 36 that supplies power consumed by the recording device 30, and a control circuit 37 that controls the recording device 30. The control circuit 37 records an image on the recording medium P by alternately moving the recording head 32 and ejecting ink by moving the carriage 34, and transporting the recording medium P.

[0052] Fig. 5(A) is a perspective view of an ink tank 31 and a recording head 32 which are made into one unit. The ink tank 31 and the recording head 32 can be separated at the positions indicated by the dashed lines. The recording head 32 has a plurality of ink ejection orifices 32a which eject ink. Fig. 5(B) is a cutaway view of the recording head 32 showing the structure around the ink ejection orifices 32a.

[0053] The recording head 32 has a flow path forming member 32b and an element substrate 1A. The flow path forming member 32b forms ink ejection ports 32a, flow paths 32c for supplying ink to each ink ejection port 32a, and a common liquid chamber 32d. The element substrate 1A is provided with ejection elements 24 corresponding to each ink ejection port 32a. The ejection elements 24 of this embodiment are elements that eject liquid (ink) when power is supplied, and are particularly electrothermal conversion elements (heaters). The electrothermal conversion elements heat the ink when current is applied, causing it to bubble, and the resulting bubble-generating energy causes the ink to be ejected from the ink ejection ports 32a. The ejection elements 24 may be piezoelectric elements instead of electrothermal conversion elements.

[0054] Fig. 6 is a circuit diagram of the element substrate 1A. The element substrate 1A is configured by mounting the ejection elements 24 and their drive circuits on the substrate 1 described in the first embodiment, and functions not only as a substrate for ejecting ink but also as a memory device. In the element substrate 1A shown in Fig. 6, the same reference numerals are used for the components common to the substrate 1 described in the first embodiment, and the description is omitted or is given only briefly.

[0055] Each electrode pad of the electrode pad group 11 comes into contact with and is electrically connected to a contact (not shown) provided on the carriage 34. The carriage 34 is connected to a control circuit 37 via a cable (not shown), and an electrical signal from the control circuit 37 and a power supply voltage of the internal power supply 36 via the control circuit 37 are applied to the electrode pad group 11 via the cable and the carriage 34.

[0056] The electrode pad group 11 includes electrode pads 12A and 12B to which a power supply voltage is input from an internal power supply 36. A writing voltage for the memory unit 2 is applied to the electrode pad 12A, and the writing voltage is supplied to the wiring 7 via a voltage supply circuit 9. A drive voltage for the ejection elements 24 is applied to the electrode pad 12B. In this embodiment, two electrode pads 12A and 12B are provided. However, if the writing voltage for the memory unit 2 and the drive voltage for the ejection elements 24 are the same or if the voltage supply circuit 9 has a step-up or step-down circuit, the electrode pads corresponding to the electrode pads 12A and 12B may be a single electrode pad.

[0057] The substrate 1A has a plurality of driving units 23-1 to 23-K. In this embodiment, the substrate 1A has K driving units 23-1 to 23-K corresponding to the K ink ejection ports 32a. When the driving units 23-1 to 23-K are collectively referred to or when there is no need to distinguish between the individual driving units, they are referred to as driving unit 23. Each driving unit 23 is an ink ejection driving circuit including an ejection element 24. In FIG. 6, only the circuit of driving unit 23-1 is shown, but the other driving units 23-2 to 23-K also have the same circuit.

[0058] The K driving units 23 are connected in parallel between a wiring 27 and a wiring 28. The ejection elements 24 of each driving unit 23 are connected to the wiring 27 via a connection point 23a. The ejection elements 24 of each driving unit 23 are connected to the wiring 28 via a switching element 25 and a connection point 23b. In this embodiment, a drive voltage for the ejection elements 27 is applied to the wiring 27, and the wiring 28 is at a ground potential (GND potential). The drive voltage is, for example, 24V.

[0059] The switching element 25 is an element that switches the application of a drive voltage to the ejection element 24, and in this embodiment, is an N-type MOS transistor. The drain D of the switching element 25 is connected to the ejection element 24, and the source S and back gate B are connected to the wiring 28 via the connection point 23b. When the switching element 25 is turned on, the voltage applied to the wiring 27 can be applied to the ejection element 24. The gate G of the switching element 25 is connected to the AND circuit 26, and when a high-level signal is input from the AND circuit 26 to the gate G, the switching element 25 is turned on. One input of the AND circuit 26 is connected to one of the signal line groups 20, and the other input is connected to one of the signal line groups 21.

[0060] A NAND circuit 19 is connected to the connection point 2c of each memory unit 2. When a low-level signal is input from the NAND circuit 19 to the connection point 2c, the switching element 4 is turned on. One input of the NAND circuit 19 is connected to one of the signal line group 20, and the other input is connected to a signal line 22.

[0061] The substrate 1A includes a signal control circuit 10A. The signal control circuit 10A outputs corresponding control signals (selection signals) to the driving units 23 and the storage unit 2. The signal control circuit 10A is configured with, for example, a shift register and a latch circuit. A clock signal CLK, a data signal DATA, a latch signal LT, a heater control signal HE, and the like are input from a control circuit 37 to the signal control circuit 10A, thereby selecting the drive of each driving unit 23.

[0062] The driving units 23 can be driven by time division. The K driving units 23 are divided into a plurality of groups and driven for each group. In the time division driving, the signal control circuit 10A outputs a group selection signal for selecting a group to the signal line group 52, and further outputs a block selection signal for selecting a driving unit 23 to be driven within the group to the signal line group 53.

[0063] A corresponding group selection signal and block selection signal are input to the AND circuit 26, and when both signals are on, the switching element 25 is turned on. When the switching element 25 is on, the ejection elements 24 connected in series are driven.

[0064] A corresponding block selection signal and a control signal from a signal line 22 are input to the NAND circuit 19, and the switching element 4 is switched on / off accordingly (when both signals are on, the switching element 4 is on).

[0065] In this manner, in this embodiment, the element substrate 1A can function not only as a substrate for ejecting ink, but also as a storage device.

[0066] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0067] 1 substrate, 1A element substrate, 2 memory section, 3 anti-fuse element, 4 switching element, 12 electrode pad, 15 electrode pad

Claims

1. a plurality of memory units each including an anti-fuse element and a switching element for switching application of a predetermined voltage to the anti-fuse element; Wiring to which the plurality of storage units are respectively connected; a first electrode pad to which a voltage is applied for supplying the predetermined voltage to the wiring; a second electrode pad to which a voltage is applied for supplying the predetermined voltage to the wiring; the memory unit includes a resistive element connected between the anti-fuse element and the wiring; A substrate comprising:

2. 2. The substrate of claim 1 , a voltage application means connected between the first electrode pad and the wiring and applying the predetermined voltage to the wiring based on a voltage applied to the first electrode pad; A substrate comprising:

3. The substrate according to claim 1 or 2, The second electrode pad is connected to the wiring. A substrate comprising:

4. The substrate according to any one of claims 1 to 3, the first electrode pad is an electrode pad to which an internal power supply of a device in which the substrate is provided is connected; The second electrode pad is an electrode pad to which an external power source outside the device is connected. A substrate comprising:

5. The substrate according to any one of claims 1 to 4, the memory unit includes a resistive element connected in parallel with the anti-fuse element; A substrate comprising:

6. The substrate according to any one of claims 1 to 5, The anti-fuse element has a MOS structure, When the predetermined voltage is applied, a gate insulating film of the MOS structure is broken down, and the resistance value of the anti-fuse element is reduced. The switching element is a DMOS transistor. A substrate comprising:

7. The substrate according to any one of claims 1 to 6, The liquid ejection device includes a plurality of ejection elements that eject liquid when supplied with electric power. A substrate comprising:

8. 8. The substrate of claim 7, the ejection element is a heater; A substrate comprising:

9. A recording head that ejects ink onto a recording medium; Power supply, A recording device comprising: The recording head includes: A substrate having a plurality of ejection elements for ejecting ink is provided, The substrate is a plurality of memory units each including an anti-fuse element and a switching element for switching application of a predetermined voltage to the anti-fuse element; Wiring to which the plurality of storage units are respectively connected; a first electrode pad to which a voltage is applied by the power source to supply the predetermined voltage to the wiring; a second electrode pad to which a voltage is applied by an external power source of the recording device to supply the predetermined voltage to the wiring, the memory unit includes a resistive element connected between the anti-fuse element and the wiring; A recording apparatus comprising:

10. A method for manufacturing a substrate, comprising the steps of: The substrate is a plurality of memory units each including an anti-fuse element and a switching element for switching application of a predetermined voltage to the anti-fuse element; wiring to which the plurality of storage units are respectively connected; the memory unit includes a resistive element connected between the anti-fuse element and the wiring, The manufacturing method includes: applying the predetermined voltage to the wiring by a first power source and a second power source; applying the predetermined voltage to the anti-fuse elements of a plurality of memory units among the plurality of memory units by the corresponding switching elements; A manufacturing method comprising the steps of:

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